/*
 * Copyright (C) 2017 MediaTek Inc.

 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.

 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See http://www.gnu.org/licenses/gpl-2.0.html for more details.
 */

#ifndef _MT_PMIC_UPMU_HW_MT6358_H_
#define _MT_PMIC_UPMU_HW_MT6358_H_

#define PMU_FLAG_TABLE_ENTRY struct pmu_flag_table_entry_t
#define PMU_FLAGS_LIST_ENUM enum PMU_FLAGS_LIST

#define PMIC_BASE (0x0)

#define MT6358_TOP0_ID ((unsigned int)(PMIC_BASE+0x0))
#define MT6358_TOP0_REV0 ((unsigned int)(PMIC_BASE+0x2))
#define MT6358_TOP0_DSN_DBI  ((unsigned int)(PMIC_BASE+0x4))
#define MT6358_TOP0_DSN_DXI  ((unsigned int)(PMIC_BASE+0x6))
#define MT6358_HWCID   ((unsigned int)(PMIC_BASE+0x8))
#define MT6358_SWCID   ((unsigned int)(PMIC_BASE+0xa))
#define MT6358_PONSTS  ((unsigned int)(PMIC_BASE+0xc))
#define MT6358_POFFSTS ((unsigned int)(PMIC_BASE+0xe))
#define MT6358_PSTSCTL ((unsigned int)(PMIC_BASE+0x10))
#define MT6358_PG_DEB_STS0   ((unsigned int)(PMIC_BASE+0x12))
#define MT6358_PG_DEB_STS1   ((unsigned int)(PMIC_BASE+0x14))
#define MT6358_PG_SDN_STS0   ((unsigned int)(PMIC_BASE+0x16))
#define MT6358_PG_SDN_STS1   ((unsigned int)(PMIC_BASE+0x18))
#define MT6358_OC_SDN_STS0   ((unsigned int)(PMIC_BASE+0x1a))
#define MT6358_THERMALSTATUS ((unsigned int)(PMIC_BASE+0x1c))
#define MT6358_TOP_CON ((unsigned int)(PMIC_BASE+0x1e))
#define MT6358_TEST_OUT  ((unsigned int)(PMIC_BASE+0x20))
#define MT6358_TEST_CON0 ((unsigned int)(PMIC_BASE+0x22))
#define MT6358_TEST_CON1 ((unsigned int)(PMIC_BASE+0x24))
#define MT6358_TESTMODE_SW   ((unsigned int)(PMIC_BASE+0x26))
#define MT6358_TOPSTATUS ((unsigned int)(PMIC_BASE+0x28))
#define MT6358_TDSEL_CON ((unsigned int)(PMIC_BASE+0x2a))
#define MT6358_RDSEL_CON ((unsigned int)(PMIC_BASE+0x2c))
#define MT6358_SMT_CON0  ((unsigned int)(PMIC_BASE+0x2e))
#define MT6358_SMT_CON1  ((unsigned int)(PMIC_BASE+0x30))
#define MT6358_TOP_RSV0  ((unsigned int)(PMIC_BASE+0x32))
#define MT6358_TOP_RSV1  ((unsigned int)(PMIC_BASE+0x34))
#define MT6358_DRV_CON0  ((unsigned int)(PMIC_BASE+0x36))
#define MT6358_DRV_CON1  ((unsigned int)(PMIC_BASE+0x38))
#define MT6358_DRV_CON2  ((unsigned int)(PMIC_BASE+0x3a))
#define MT6358_DRV_CON3  ((unsigned int)(PMIC_BASE+0x3c))
#define MT6358_DRV_CON4  ((unsigned int)(PMIC_BASE+0x3e))
#define MT6358_FILTER_CON0   ((unsigned int)(PMIC_BASE+0x40))
#define MT6358_FILTER_CON1   ((unsigned int)(PMIC_BASE+0x42))
#define MT6358_FILTER_CON2   ((unsigned int)(PMIC_BASE+0x44))
#define MT6358_FILTER_CON3   ((unsigned int)(PMIC_BASE+0x46))
#define MT6358_TOP_STATUS   ((unsigned int)(PMIC_BASE+0x48))
#define MT6358_TOP_STATUS_SET  ((unsigned int)(PMIC_BASE+0x4a))
#define MT6358_TOP_STATUS_CLR  ((unsigned int)(PMIC_BASE+0x4c))
#define MT6358_TOP_TRAP  ((unsigned int)(PMIC_BASE+0x4e))
#define MT6358_TOP1_ID ((unsigned int)(PMIC_BASE+0x80))
#define MT6358_TOP1_REV0 ((unsigned int)(PMIC_BASE+0x82))
#define MT6358_TOP1_DSN_DBI  ((unsigned int)(PMIC_BASE+0x84))
#define MT6358_TOP1_DSN_DXI  ((unsigned int)(PMIC_BASE+0x86))
#define MT6358_GPIO_DIR0 ((unsigned int)(PMIC_BASE+0x88))
#define MT6358_GPIO_DIR0_SET ((unsigned int)(PMIC_BASE+0x8a))
#define MT6358_GPIO_DIR0_CLR ((unsigned int)(PMIC_BASE+0x8c))
#define MT6358_GPIO_DIR1 ((unsigned int)(PMIC_BASE+0x8e))
#define MT6358_GPIO_DIR1_SET ((unsigned int)(PMIC_BASE+0x90))
#define MT6358_GPIO_DIR1_CLR ((unsigned int)(PMIC_BASE+0x92))
#define MT6358_GPIO_PULLEN0  ((unsigned int)(PMIC_BASE+0x94))
#define MT6358_GPIO_PULLEN0_SET   ((unsigned int)(PMIC_BASE+0x96))
#define MT6358_GPIO_PULLEN0_CLR   ((unsigned int)(PMIC_BASE+0x98))
#define MT6358_GPIO_PULLEN1  ((unsigned int)(PMIC_BASE+0x9a))
#define MT6358_GPIO_PULLEN1_SET   ((unsigned int)(PMIC_BASE+0x9c))
#define MT6358_GPIO_PULLEN1_CLR   ((unsigned int)(PMIC_BASE+0x9e))
#define MT6358_GPIO_PULLSEL0 ((unsigned int)(PMIC_BASE+0xa0))
#define MT6358_GPIO_PULLSEL0_SET  ((unsigned int)(PMIC_BASE+0xa2))
#define MT6358_GPIO_PULLSEL0_CLR  ((unsigned int)(PMIC_BASE+0xa4))
#define MT6358_GPIO_PULLSEL1 ((unsigned int)(PMIC_BASE+0xa6))
#define MT6358_GPIO_PULLSEL1_SET  ((unsigned int)(PMIC_BASE+0xa8))
#define MT6358_GPIO_PULLSEL1_CLR  ((unsigned int)(PMIC_BASE+0xaa))
#define MT6358_GPIO_DINV0   ((unsigned int)(PMIC_BASE+0xac))
#define MT6358_GPIO_DINV0_SET  ((unsigned int)(PMIC_BASE+0xae))
#define MT6358_GPIO_DINV0_CLR  ((unsigned int)(PMIC_BASE+0xb0))
#define MT6358_GPIO_DINV1   ((unsigned int)(PMIC_BASE+0xb2))
#define MT6358_GPIO_DINV1_SET  ((unsigned int)(PMIC_BASE+0xb4))
#define MT6358_GPIO_DINV1_CLR  ((unsigned int)(PMIC_BASE+0xb6))
#define MT6358_GPIO_DOUT0   ((unsigned int)(PMIC_BASE+0xb8))
#define MT6358_GPIO_DOUT0_SET  ((unsigned int)(PMIC_BASE+0xba))
#define MT6358_GPIO_DOUT0_CLR  ((unsigned int)(PMIC_BASE+0xbc))
#define MT6358_GPIO_DOUT1   ((unsigned int)(PMIC_BASE+0xbe))
#define MT6358_GPIO_DOUT1_SET  ((unsigned int)(PMIC_BASE+0xc0))
#define MT6358_GPIO_DOUT1_CLR  ((unsigned int)(PMIC_BASE+0xc2))
#define MT6358_GPIO_PI0  ((unsigned int)(PMIC_BASE+0xc4))
#define MT6358_GPIO_PI1  ((unsigned int)(PMIC_BASE+0xc6))
#define MT6358_GPIO_POE0 ((unsigned int)(PMIC_BASE+0xc8))
#define MT6358_GPIO_POE1 ((unsigned int)(PMIC_BASE+0xca))
#define MT6358_GPIO_MODE0   ((unsigned int)(PMIC_BASE+0xcc))
#define MT6358_GPIO_MODE0_SET  ((unsigned int)(PMIC_BASE+0xce))
#define MT6358_GPIO_MODE0_CLR  ((unsigned int)(PMIC_BASE+0xd0))
#define MT6358_GPIO_MODE1   ((unsigned int)(PMIC_BASE+0xd2))
#define MT6358_GPIO_MODE1_SET  ((unsigned int)(PMIC_BASE+0xd4))
#define MT6358_GPIO_MODE1_CLR  ((unsigned int)(PMIC_BASE+0xd6))
#define MT6358_GPIO_MODE2   ((unsigned int)(PMIC_BASE+0xd8))
#define MT6358_GPIO_MODE2_SET  ((unsigned int)(PMIC_BASE+0xda))
#define MT6358_GPIO_MODE2_CLR  ((unsigned int)(PMIC_BASE+0xdc))
#define MT6358_GPIO_MODE3   ((unsigned int)(PMIC_BASE+0xde))
#define MT6358_GPIO_MODE3_SET  ((unsigned int)(PMIC_BASE+0xe0))
#define MT6358_GPIO_MODE3_CLR  ((unsigned int)(PMIC_BASE+0xe2))
#define MT6358_GPIO_MODE4   ((unsigned int)(PMIC_BASE+0xe4))
#define MT6358_GPIO_MODE4_SET  ((unsigned int)(PMIC_BASE+0xe6))
#define MT6358_GPIO_MODE4_CLR  ((unsigned int)(PMIC_BASE+0xe8))
#define MT6358_GPIO_RSV  ((unsigned int)(PMIC_BASE+0xea))
#define MT6358_TOP2_ID ((unsigned int)(PMIC_BASE+0x100))
#define MT6358_TOP2_REV0 ((unsigned int)(PMIC_BASE+0x102))
#define MT6358_TOP2_DSN_DBI  ((unsigned int)(PMIC_BASE+0x104))
#define MT6358_TOP2_DSN_DXI  ((unsigned int)(PMIC_BASE+0x106))
#define MT6358_TOP_PAM0  ((unsigned int)(PMIC_BASE+0x108))
#define MT6358_TOP_PAM1  ((unsigned int)(PMIC_BASE+0x10a))
#define MT6358_TOP_CKPDN_CON0  ((unsigned int)(PMIC_BASE+0x10c))
#define MT6358_TOP_CKPDN_CON0_SET  ((unsigned int)(PMIC_BASE+0x10e))
#define MT6358_TOP_CKPDN_CON0_CLR  ((unsigned int)(PMIC_BASE+0x110))
#define MT6358_TOP_CKPDN_CON1  ((unsigned int)(PMIC_BASE+0x112))
#define MT6358_TOP_CKPDN_CON1_SET  ((unsigned int)(PMIC_BASE+0x114))
#define MT6358_TOP_CKPDN_CON1_CLR  ((unsigned int)(PMIC_BASE+0x116))
#define MT6358_TOP_CKSEL_CON0  ((unsigned int)(PMIC_BASE+0x118))
#define MT6358_TOP_CKSEL_CON0_SET  ((unsigned int)(PMIC_BASE+0x11a))
#define MT6358_TOP_CKSEL_CON0_CLR  ((unsigned int)(PMIC_BASE+0x11c))
#define MT6358_TOP_CKSEL_CON1  ((unsigned int)(PMIC_BASE+0x11e))
#define MT6358_TOP_CKSEL_CON1_SET  ((unsigned int)(PMIC_BASE+0x120))
#define MT6358_TOP_CKSEL_CON1_CLR  ((unsigned int)(PMIC_BASE+0x122))
#define MT6358_TOP_CKDIVSEL_CON0  ((unsigned int)(PMIC_BASE+0x124))
#define MT6358_TOP_CKDIVSEL_CON0_SET ((unsigned int)(PMIC_BASE+0x126))
#define MT6358_TOP_CKDIVSEL_CON0_CLR ((unsigned int)(PMIC_BASE+0x128))
#define MT6358_TOP_CKHWEN_CON0 ((unsigned int)(PMIC_BASE+0x12a))
#define MT6358_TOP_CKHWEN_CON0_SET ((unsigned int)(PMIC_BASE+0x12c))
#define MT6358_TOP_CKHWEN_CON0_CLR ((unsigned int)(PMIC_BASE+0x12e))
#define MT6358_TOP_CKTST_CON0  ((unsigned int)(PMIC_BASE+0x130))
#define MT6358_TOP_CKTST_CON1  ((unsigned int)(PMIC_BASE+0x132))
#define MT6358_TOP_CLK_CON0  ((unsigned int)(PMIC_BASE+0x134))
#define MT6358_TOP_CLK_CON0_SET   ((unsigned int)(PMIC_BASE+0x136))
#define MT6358_TOP_CLK_CON0_CLR   ((unsigned int)(PMIC_BASE+0x138))
#define MT6358_TOP_DCM_CON0  ((unsigned int)(PMIC_BASE+0x13a))
#define MT6358_TOP_HANDOVER_DEBUG0 ((unsigned int)(PMIC_BASE+0x13c))
#define MT6358_TOP_RST_CON0  ((unsigned int)(PMIC_BASE+0x13e))
#define MT6358_TOP_RST_CON0_SET   ((unsigned int)(PMIC_BASE+0x140))
#define MT6358_TOP_RST_CON0_CLR   ((unsigned int)(PMIC_BASE+0x142))
#define MT6358_TOP_RST_CON1  ((unsigned int)(PMIC_BASE+0x144))
#define MT6358_TOP_RST_CON1_SET   ((unsigned int)(PMIC_BASE+0x146))
#define MT6358_TOP_RST_CON1_CLR   ((unsigned int)(PMIC_BASE+0x148))
#define MT6358_TOP_RST_CON2  ((unsigned int)(PMIC_BASE+0x14a))
#define MT6358_TOP_RST_MISC  ((unsigned int)(PMIC_BASE+0x14c))
#define MT6358_TOP_RST_MISC_SET   ((unsigned int)(PMIC_BASE+0x14e))
#define MT6358_TOP_RST_MISC_CLR   ((unsigned int)(PMIC_BASE+0x150))
#define MT6358_TOP_RST_STATUS  ((unsigned int)(PMIC_BASE+0x152))
#define MT6358_TOP_RST_STATUS_SET  ((unsigned int)(PMIC_BASE+0x154))
#define MT6358_TOP_RST_STATUS_CLR  ((unsigned int)(PMIC_BASE+0x156))
#define MT6358_TOP2_ELR_NUM  ((unsigned int)(PMIC_BASE+0x158))
#define MT6358_TOP2_ELR0 ((unsigned int)(PMIC_BASE+0x15a))
#define MT6358_TOP2_ELR1 ((unsigned int)(PMIC_BASE+0x15c))
#define MT6358_TOP3_ID ((unsigned int)(PMIC_BASE+0x180))
#define MT6358_TOP3_REV0 ((unsigned int)(PMIC_BASE+0x182))
#define MT6358_TOP3_DSN_DBI  ((unsigned int)(PMIC_BASE+0x184))
#define MT6358_TOP3_DSN_DXI  ((unsigned int)(PMIC_BASE+0x186))
#define MT6358_MISC_TOP_INT_CON0  ((unsigned int)(PMIC_BASE+0x188))
#define MT6358_MISC_TOP_INT_CON0_SET ((unsigned int)(PMIC_BASE+0x18a))
#define MT6358_MISC_TOP_INT_CON0_CLR ((unsigned int)(PMIC_BASE+0x18c))
#define MT6358_MISC_TOP_INT_MASK_CON0   ((unsigned int)(PMIC_BASE+0x18e))
#define MT6358_MISC_TOP_INT_MASK_CON0_SET  ((unsigned int)(PMIC_BASE+0x190))
#define MT6358_MISC_TOP_INT_MASK_CON0_CLR  ((unsigned int)(PMIC_BASE+0x192))
#define MT6358_MISC_TOP_INT_STATUS0  ((unsigned int)(PMIC_BASE+0x194))
#define MT6358_MISC_TOP_INT_RAW_STATUS0 ((unsigned int)(PMIC_BASE+0x196))
#define MT6358_TOP_INT_MASK_CON0  ((unsigned int)(PMIC_BASE+0x198))
#define MT6358_TOP_INT_MASK_CON0_SET ((unsigned int)(PMIC_BASE+0x19a))
#define MT6358_TOP_INT_MASK_CON0_CLR ((unsigned int)(PMIC_BASE+0x19c))
#define MT6358_TOP_INT_STATUS0 ((unsigned int)(PMIC_BASE+0x19e))
#define MT6358_TOP_INT_RAW_STATUS0 ((unsigned int)(PMIC_BASE+0x1a0))
#define MT6358_TOP_INT_CON0  ((unsigned int)(PMIC_BASE+0x1a2))
#define MT6358_PLT0_ID ((unsigned int)(PMIC_BASE+0x380))
#define MT6358_PLT0_REV0 ((unsigned int)(PMIC_BASE+0x382))
#define MT6358_PLT0_REV1 ((unsigned int)(PMIC_BASE+0x384))
#define MT6358_PLT0_DSN_DXI  ((unsigned int)(PMIC_BASE+0x386))
#define MT6358_TOP_CLK_TRIM  ((unsigned int)(PMIC_BASE+0x388))
#define MT6358_OTP_CON0  ((unsigned int)(PMIC_BASE+0x38a))
#define MT6358_OTP_CON1  ((unsigned int)(PMIC_BASE+0x38c))
#define MT6358_OTP_CON2  ((unsigned int)(PMIC_BASE+0x38e))
#define MT6358_OTP_CON3  ((unsigned int)(PMIC_BASE+0x390))
#define MT6358_OTP_CON4  ((unsigned int)(PMIC_BASE+0x392))
#define MT6358_OTP_CON5  ((unsigned int)(PMIC_BASE+0x394))
#define MT6358_OTP_CON6  ((unsigned int)(PMIC_BASE+0x396))
#define MT6358_OTP_CON7  ((unsigned int)(PMIC_BASE+0x398))
#define MT6358_OTP_CON8  ((unsigned int)(PMIC_BASE+0x39a))
#define MT6358_OTP_CON9  ((unsigned int)(PMIC_BASE+0x39c))
#define MT6358_OTP_CON10 ((unsigned int)(PMIC_BASE+0x39e))
#define MT6358_OTP_CON11 ((unsigned int)(PMIC_BASE+0x3a0))
#define MT6358_OTP_CON12 ((unsigned int)(PMIC_BASE+0x3a2))
#define MT6358_OTP_CON13 ((unsigned int)(PMIC_BASE+0x3a4))
#define MT6358_OTP_CON14 ((unsigned int)(PMIC_BASE+0x3a6))
#define MT6358_TOP_TMA_KEY   ((unsigned int)(PMIC_BASE+0x3a8))
#define MT6358_TOP_MDB_CONF0 ((unsigned int)(PMIC_BASE+0x3aa))
#define MT6358_TOP_MDB_CONF1 ((unsigned int)(PMIC_BASE+0x3ac))
#define MT6358_TOP_MDB_CONF2 ((unsigned int)(PMIC_BASE+0x3ae))
#define MT6358_PLT0_ELR_NUM  ((unsigned int)(PMIC_BASE+0x3b0))
#define MT6358_PLT0_ELR0 ((unsigned int)(PMIC_BASE+0x3b2))
#define MT6358_PLT0_ELR1 ((unsigned int)(PMIC_BASE+0x3b4))
#define MT6358_SPISLV_ID ((unsigned int)(PMIC_BASE+0x400))
#define MT6358_SPISLV_REV0   ((unsigned int)(PMIC_BASE+0x402))
#define MT6358_SPISLV_REV1   ((unsigned int)(PMIC_BASE+0x404))
#define MT6358_SPISLV_DSN_DXI  ((unsigned int)(PMIC_BASE+0x406))
#define MT6358_RG_SPI_CON0   ((unsigned int)(PMIC_BASE+0x408))
#define MT6358_RG_SPI_RECORD0  ((unsigned int)(PMIC_BASE+0x40a))
#define MT6358_DEW_DIO_EN   ((unsigned int)(PMIC_BASE+0x40c))
#define MT6358_DEW_READ_TEST ((unsigned int)(PMIC_BASE+0x40e))
#define MT6358_DEW_WRITE_TEST  ((unsigned int)(PMIC_BASE+0x410))
#define MT6358_DEW_CRC_SWRST ((unsigned int)(PMIC_BASE+0x412))
#define MT6358_DEW_CRC_EN   ((unsigned int)(PMIC_BASE+0x414))
#define MT6358_DEW_CRC_VAL   ((unsigned int)(PMIC_BASE+0x416))
#define MT6358_DEW_DBG_MON_SEL ((unsigned int)(PMIC_BASE+0x418))
#define MT6358_DEW_CIPHER_KEY_SEL  ((unsigned int)(PMIC_BASE+0x41a))
#define MT6358_DEW_CIPHER_IV_SEL  ((unsigned int)(PMIC_BASE+0x41c))
#define MT6358_DEW_CIPHER_EN ((unsigned int)(PMIC_BASE+0x41e))
#define MT6358_DEW_CIPHER_RDY  ((unsigned int)(PMIC_BASE+0x420))
#define MT6358_DEW_CIPHER_MODE ((unsigned int)(PMIC_BASE+0x422))
#define MT6358_DEW_CIPHER_SWRST   ((unsigned int)(PMIC_BASE+0x424))
#define MT6358_DEW_RDDMY_NO  ((unsigned int)(PMIC_BASE+0x426))
#define MT6358_INT_TYPE_CON0 ((unsigned int)(PMIC_BASE+0x428))
#define MT6358_INT_TYPE_CON0_SET  ((unsigned int)(PMIC_BASE+0x42a))
#define MT6358_INT_TYPE_CON0_CLR  ((unsigned int)(PMIC_BASE+0x42c))
#define MT6358_INT_STA ((unsigned int)(PMIC_BASE+0x42e))
#define MT6358_RG_SPI_CON1   ((unsigned int)(PMIC_BASE+0x430))
#define MT6358_RG_SPI_CON2   ((unsigned int)(PMIC_BASE+0x432))
#define MT6358_RG_SPI_CON3   ((unsigned int)(PMIC_BASE+0x434))
#define MT6358_RG_SPI_CON4   ((unsigned int)(PMIC_BASE+0x436))
#define MT6358_RG_SPI_CON5   ((unsigned int)(PMIC_BASE+0x438))
#define MT6358_RG_SPI_CON6   ((unsigned int)(PMIC_BASE+0x43a))
#define MT6358_RG_SPI_CON7   ((unsigned int)(PMIC_BASE+0x43c))
#define MT6358_RG_SPI_CON8   ((unsigned int)(PMIC_BASE+0x43e))
#define MT6358_RG_SPI_CON9   ((unsigned int)(PMIC_BASE+0x440))
#define MT6358_RG_SPI_CON10  ((unsigned int)(PMIC_BASE+0x442))
#define MT6358_RG_SPI_CON11  ((unsigned int)(PMIC_BASE+0x444))
#define MT6358_RG_SPI_CON12  ((unsigned int)(PMIC_BASE+0x446))
#define MT6358_RG_SPI_CON13  ((unsigned int)(PMIC_BASE+0x448))
#define MT6358_SPISLV_KEY   ((unsigned int)(PMIC_BASE+0x44a))
#define MT6358_TOP_SPI_CON0  ((unsigned int)(PMIC_BASE+0x44c))
#define MT6358_TOP_SPI_CON1  ((unsigned int)(PMIC_BASE+0x44e))
#define MT6358_SCK_TOP_DSN_ID  ((unsigned int)(PMIC_BASE+0x500))
#define MT6358_SCK_TOP_DSN_REV0   ((unsigned int)(PMIC_BASE+0x502))
#define MT6358_SCK_TOP_DBI   ((unsigned int)(PMIC_BASE+0x504))
#define MT6358_SCK_TOP_DXI   ((unsigned int)(PMIC_BASE+0x506))
#define MT6358_SCK_TOP_TPM0  ((unsigned int)(PMIC_BASE+0x508))
#define MT6358_SCK_TOP_TPM1  ((unsigned int)(PMIC_BASE+0x50a))
#define MT6358_SCK_TOP_CON0  ((unsigned int)(PMIC_BASE+0x50c))
#define MT6358_SCK_TOP_CON1  ((unsigned int)(PMIC_BASE+0x50e))
#define MT6358_SCK_TOP_TEST_OUT   ((unsigned int)(PMIC_BASE+0x510))
#define MT6358_SCK_TOP_TEST_CON0  ((unsigned int)(PMIC_BASE+0x512))
#define MT6358_FQMTR_CON0   ((unsigned int)(PMIC_BASE+0x514))
#define MT6358_FQMTR_CON1   ((unsigned int)(PMIC_BASE+0x516))
#define MT6358_FQMTR_CON2   ((unsigned int)(PMIC_BASE+0x518))
#define MT6358_SCK_TOP_CKPDN_CON0  ((unsigned int)(PMIC_BASE+0x51a))
#define MT6358_SCK_TOP_CKPDN_CON0_SET   ((unsigned int)(PMIC_BASE+0x51c))
#define MT6358_SCK_TOP_CKPDN_CON0_CLR   ((unsigned int)(PMIC_BASE+0x51e))
#define MT6358_SCK_TOP_CKHWEN_CON0 ((unsigned int)(PMIC_BASE+0x520))
#define MT6358_SCK_TOP_CKHWEN_CON0_SET  ((unsigned int)(PMIC_BASE+0x522))
#define MT6358_SCK_TOP_CKHWEN_CON0_CLR  ((unsigned int)(PMIC_BASE+0x524))
#define MT6358_SCK_TOP_CKTST_CON  ((unsigned int)(PMIC_BASE+0x526))
#define MT6358_SCK_TOP_RST_CON0   ((unsigned int)(PMIC_BASE+0x528))
#define MT6358_SCK_TOP_RST_CON0_SET  ((unsigned int)(PMIC_BASE+0x52a))
#define MT6358_SCK_TOP_RST_CON0_CLR  ((unsigned int)(PMIC_BASE+0x52c))
#define MT6358_SCK_TOP_INT_CON0   ((unsigned int)(PMIC_BASE+0x52e))
#define MT6358_SCK_TOP_INT_CON0_SET  ((unsigned int)(PMIC_BASE+0x530))
#define MT6358_SCK_TOP_INT_CON0_CLR  ((unsigned int)(PMIC_BASE+0x532))
#define MT6358_SCK_TOP_INT_MASK_CON0 ((unsigned int)(PMIC_BASE+0x534))
#define MT6358_SCK_TOP_INT_MASK_CON0_SET ((unsigned int)(PMIC_BASE+0x536))
#define MT6358_SCK_TOP_INT_MASK_CON0_CLR ((unsigned int)(PMIC_BASE+0x538))
#define MT6358_SCK_TOP_INT_STATUS0 ((unsigned int)(PMIC_BASE+0x53a))
#define MT6358_SCK_TOP_INT_RAW_STATUS0  ((unsigned int)(PMIC_BASE+0x53c))
#define MT6358_SCK_TOP_INT_MISC_CON  ((unsigned int)(PMIC_BASE+0x53e))
#define MT6358_EOSC_CALI_CON0  ((unsigned int)(PMIC_BASE+0x540))
#define MT6358_EOSC_CALI_CON1  ((unsigned int)(PMIC_BASE+0x542))
#define MT6358_RTC_MIX_CON0  ((unsigned int)(PMIC_BASE+0x544))
#define MT6358_RTC_MIX_CON1  ((unsigned int)(PMIC_BASE+0x546))
#define MT6358_RTC_MIX_CON2  ((unsigned int)(PMIC_BASE+0x548))
#define MT6358_RTC_DSN_ID   ((unsigned int)(PMIC_BASE+0x580))
#define MT6358_RTC_DSN_REV0  ((unsigned int)(PMIC_BASE+0x582))
#define MT6358_RTC_DBI ((unsigned int)(PMIC_BASE+0x584))
#define MT6358_RTC_DXI ((unsigned int)(PMIC_BASE+0x586))
#define MT6358_RTC_BBPU  ((unsigned int)(PMIC_BASE+0x588))
#define MT6358_RTC_IRQ_STA   ((unsigned int)(PMIC_BASE+0x58a))
#define MT6358_RTC_IRQ_EN   ((unsigned int)(PMIC_BASE+0x58c))
#define MT6358_RTC_CII_EN   ((unsigned int)(PMIC_BASE+0x58e))
#define MT6358_RTC_AL_MASK   ((unsigned int)(PMIC_BASE+0x590))
#define MT6358_RTC_TC_SEC   ((unsigned int)(PMIC_BASE+0x592))
#define MT6358_RTC_TC_MIN   ((unsigned int)(PMIC_BASE+0x594))
#define MT6358_RTC_TC_HOU   ((unsigned int)(PMIC_BASE+0x596))
#define MT6358_RTC_TC_DOM   ((unsigned int)(PMIC_BASE+0x598))
#define MT6358_RTC_TC_DOW   ((unsigned int)(PMIC_BASE+0x59a))
#define MT6358_RTC_TC_MTH   ((unsigned int)(PMIC_BASE+0x59c))
#define MT6358_RTC_TC_YEA   ((unsigned int)(PMIC_BASE+0x59e))
#define MT6358_RTC_AL_SEC   ((unsigned int)(PMIC_BASE+0x5a0))
#define MT6358_RTC_AL_MIN   ((unsigned int)(PMIC_BASE+0x5a2))
#define MT6358_RTC_AL_HOU   ((unsigned int)(PMIC_BASE+0x5a4))
#define MT6358_RTC_AL_DOM   ((unsigned int)(PMIC_BASE+0x5a6))
#define MT6358_RTC_AL_DOW   ((unsigned int)(PMIC_BASE+0x5a8))
#define MT6358_RTC_AL_MTH   ((unsigned int)(PMIC_BASE+0x5aa))
#define MT6358_RTC_AL_YEA   ((unsigned int)(PMIC_BASE+0x5ac))
#define MT6358_RTC_OSC32CON  ((unsigned int)(PMIC_BASE+0x5ae))
#define MT6358_RTC_POWERKEY1 ((unsigned int)(PMIC_BASE+0x5b0))
#define MT6358_RTC_POWERKEY2 ((unsigned int)(PMIC_BASE+0x5b2))
#define MT6358_RTC_PDN1  ((unsigned int)(PMIC_BASE+0x5b4))
#define MT6358_RTC_PDN2  ((unsigned int)(PMIC_BASE+0x5b6))
#define MT6358_RTC_SPAR0 ((unsigned int)(PMIC_BASE+0x5b8))
#define MT6358_RTC_SPAR1 ((unsigned int)(PMIC_BASE+0x5ba))
#define MT6358_RTC_PROT  ((unsigned int)(PMIC_BASE+0x5bc))
#define MT6358_RTC_DIFF  ((unsigned int)(PMIC_BASE+0x5be))
#define MT6358_RTC_CALI  ((unsigned int)(PMIC_BASE+0x5c0))
#define MT6358_RTC_WRTGR ((unsigned int)(PMIC_BASE+0x5c2))
#define MT6358_RTC_CON ((unsigned int)(PMIC_BASE+0x5c4))
#define MT6358_RTC_SEC_CTRL  ((unsigned int)(PMIC_BASE+0x5c6))
#define MT6358_RTC_INT_CNT   ((unsigned int)(PMIC_BASE+0x5c8))
#define MT6358_RTC_SEC_DAT0  ((unsigned int)(PMIC_BASE+0x5ca))
#define MT6358_RTC_SEC_DAT1  ((unsigned int)(PMIC_BASE+0x5cc))
#define MT6358_RTC_SEC_DAT2  ((unsigned int)(PMIC_BASE+0x5ce))
#define MT6358_RTC_SEC_DSN_ID  ((unsigned int)(PMIC_BASE+0x600))
#define MT6358_RTC_SEC_DSN_REV0   ((unsigned int)(PMIC_BASE+0x602))
#define MT6358_RTC_SEC_DBI   ((unsigned int)(PMIC_BASE+0x604))
#define MT6358_RTC_SEC_DXI   ((unsigned int)(PMIC_BASE+0x606))
#define MT6358_RTC_TC_SEC_SEC  ((unsigned int)(PMIC_BASE+0x608))
#define MT6358_RTC_TC_MIN_SEC  ((unsigned int)(PMIC_BASE+0x60a))
#define MT6358_RTC_TC_HOU_SEC  ((unsigned int)(PMIC_BASE+0x60c))
#define MT6358_RTC_TC_DOM_SEC  ((unsigned int)(PMIC_BASE+0x60e))
#define MT6358_RTC_TC_DOW_SEC  ((unsigned int)(PMIC_BASE+0x610))
#define MT6358_RTC_TC_MTH_SEC  ((unsigned int)(PMIC_BASE+0x612))
#define MT6358_RTC_TC_YEA_SEC  ((unsigned int)(PMIC_BASE+0x614))
#define MT6358_RTC_SEC_CK_PDN  ((unsigned int)(PMIC_BASE+0x616))
#define MT6358_RTC_SEC_WRTGR ((unsigned int)(PMIC_BASE+0x618))
#define MT6358_DCXO_DSN_ID   ((unsigned int)(PMIC_BASE+0x780))
#define MT6358_DCXO_DSN_REV0 ((unsigned int)(PMIC_BASE+0x782))
#define MT6358_DCXO_DSN_DBI  ((unsigned int)(PMIC_BASE+0x784))
#define MT6358_DCXO_DSN_DXI  ((unsigned int)(PMIC_BASE+0x786))
#define MT6358_DCXO_CW00 ((unsigned int)(PMIC_BASE+0x788))
#define MT6358_DCXO_CW00_SET ((unsigned int)(PMIC_BASE+0x78a))
#define MT6358_DCXO_CW00_CLR ((unsigned int)(PMIC_BASE+0x78c))
#define MT6358_DCXO_CW01 ((unsigned int)(PMIC_BASE+0x78e))
#define MT6358_DCXO_CW02 ((unsigned int)(PMIC_BASE+0x790))
#define MT6358_DCXO_CW03 ((unsigned int)(PMIC_BASE+0x792))
#define MT6358_DCXO_CW04 ((unsigned int)(PMIC_BASE+0x794))
#define MT6358_DCXO_CW05 ((unsigned int)(PMIC_BASE+0x796))
#define MT6358_DCXO_CW06 ((unsigned int)(PMIC_BASE+0x798))
#define MT6358_DCXO_CW07 ((unsigned int)(PMIC_BASE+0x79a))
#define MT6358_DCXO_CW08 ((unsigned int)(PMIC_BASE+0x79c))
#define MT6358_DCXO_CW09 ((unsigned int)(PMIC_BASE+0x79e))
#define MT6358_DCXO_CW10 ((unsigned int)(PMIC_BASE+0x7a0))
#define MT6358_DCXO_CW11 ((unsigned int)(PMIC_BASE+0x7a2))
#define MT6358_DCXO_CW11_SET ((unsigned int)(PMIC_BASE+0x7a4))
#define MT6358_DCXO_CW11_CLR ((unsigned int)(PMIC_BASE+0x7a6))
#define MT6358_DCXO_CW12 ((unsigned int)(PMIC_BASE+0x7a8))
#define MT6358_DCXO_CW13 ((unsigned int)(PMIC_BASE+0x7aa))
#define MT6358_DCXO_CW14 ((unsigned int)(PMIC_BASE+0x7ac))
#define MT6358_DCXO_CW15 ((unsigned int)(PMIC_BASE+0x7ae))
#define MT6358_DCXO_CW16 ((unsigned int)(PMIC_BASE+0x7b0))
#define MT6358_DCXO_CW17 ((unsigned int)(PMIC_BASE+0x7b2))
#define MT6358_DCXO_CW18 ((unsigned int)(PMIC_BASE+0x7b4))
#define MT6358_DCXO_CW19 ((unsigned int)(PMIC_BASE+0x7b6))
#define MT6358_DCXO_CW20 ((unsigned int)(PMIC_BASE+0x7b8))
#define MT6358_DCXO_CW21 ((unsigned int)(PMIC_BASE+0x7ba))
#define MT6358_DCXO_CW22 ((unsigned int)(PMIC_BASE+0x7bc))
#define MT6358_DCXO_CW23 ((unsigned int)(PMIC_BASE+0x7be))
#define MT6358_DCXO_CW24 ((unsigned int)(PMIC_BASE+0x7c0))
#define MT6358_DCXO_ELR_NUM  ((unsigned int)(PMIC_BASE+0x7c2))
#define MT6358_DCXO_ELR0 ((unsigned int)(PMIC_BASE+0x7c4))
#define MT6358_PSC_TOP_ID   ((unsigned int)(PMIC_BASE+0x900))
#define MT6358_PSC_TOP_REV0  ((unsigned int)(PMIC_BASE+0x902))
#define MT6358_PSC_TOP_DBI   ((unsigned int)(PMIC_BASE+0x904))
#define MT6358_PSC_TOP_DXI   ((unsigned int)(PMIC_BASE+0x906))
#define MT6358_PSC_TPM0  ((unsigned int)(PMIC_BASE+0x908))
#define MT6358_PSC_TPM1  ((unsigned int)(PMIC_BASE+0x90a))
#define MT6358_PSC_TOP_CLKCTL_0   ((unsigned int)(PMIC_BASE+0x90c))
#define MT6358_PSC_TOP_RSTCTL_0   ((unsigned int)(PMIC_BASE+0x90e))
#define MT6358_PSC_TOP_INT_CON0   ((unsigned int)(PMIC_BASE+0x910))
#define MT6358_PSC_TOP_INT_CON0_SET  ((unsigned int)(PMIC_BASE+0x912))
#define MT6358_PSC_TOP_INT_CON0_CLR  ((unsigned int)(PMIC_BASE+0x914))
#define MT6358_PSC_TOP_INT_MASK_CON0 ((unsigned int)(PMIC_BASE+0x916))
#define MT6358_PSC_TOP_INT_MASK_CON0_SET ((unsigned int)(PMIC_BASE+0x918))
#define MT6358_PSC_TOP_INT_MASK_CON0_CLR ((unsigned int)(PMIC_BASE+0x91a))
#define MT6358_PSC_TOP_INT_STATUS0 ((unsigned int)(PMIC_BASE+0x91c))
#define MT6358_PSC_TOP_INT_RAW_STATUS0  ((unsigned int)(PMIC_BASE+0x91e))
#define MT6358_PSC_TOP_INT_MISC_CON  ((unsigned int)(PMIC_BASE+0x920))
#define MT6358_PSC_TOP_INT_MISC_CON_SET ((unsigned int)(PMIC_BASE+0x922))
#define MT6358_PSC_TOP_INT_MISC_CON_CLR ((unsigned int)(PMIC_BASE+0x924))
#define MT6358_PSC_TOP_MON_CTL ((unsigned int)(PMIC_BASE+0x926))
#define MT6358_STRUP_ID  ((unsigned int)(PMIC_BASE+0x980))
#define MT6358_STRUP_REV0   ((unsigned int)(PMIC_BASE+0x982))
#define MT6358_STRUP_DBI ((unsigned int)(PMIC_BASE+0x984))
#define MT6358_STRUP_DSN_FPI ((unsigned int)(PMIC_BASE+0x986))
#define MT6358_STRUP_ANA_CON0  ((unsigned int)(PMIC_BASE+0x988))
#define MT6358_STRUP_ANA_CON1  ((unsigned int)(PMIC_BASE+0x98a))
#define MT6358_STRUP_ELR_NUM ((unsigned int)(PMIC_BASE+0x98c))
#define MT6358_STRUP_ELR_0   ((unsigned int)(PMIC_BASE+0x98e))
#define MT6358_STRUP_ELR_1   ((unsigned int)(PMIC_BASE+0x990))
#define MT6358_PSEQ_ID ((unsigned int)(PMIC_BASE+0xa00))
#define MT6358_PSEQ_REV0 ((unsigned int)(PMIC_BASE+0xa02))
#define MT6358_PSEQ_DBI  ((unsigned int)(PMIC_BASE+0xa04))
#define MT6358_PSEQ_DXI  ((unsigned int)(PMIC_BASE+0xa06))
#define MT6358_PPCCTL0 ((unsigned int)(PMIC_BASE+0xa08))
#define MT6358_PPCCTL1 ((unsigned int)(PMIC_BASE+0xa0a))
#define MT6358_PPCCTL2 ((unsigned int)(PMIC_BASE+0xa0c))
#define MT6358_PPCCFG0 ((unsigned int)(PMIC_BASE+0xa0e))
#define MT6358_PPCTST0 ((unsigned int)(PMIC_BASE+0xa10))
#define MT6358_PORFLAG ((unsigned int)(PMIC_BASE+0xa12))
#define MT6358_STRUP_CON0   ((unsigned int)(PMIC_BASE+0xa14))
#define MT6358_STRUP_CON1   ((unsigned int)(PMIC_BASE+0xa16))
#define MT6358_STRUP_CON2   ((unsigned int)(PMIC_BASE+0xa18))
#define MT6358_STRUP_CON3   ((unsigned int)(PMIC_BASE+0xa1a))
#define MT6358_STRUP_CON4   ((unsigned int)(PMIC_BASE+0xa1c))
#define MT6358_STRUP_CON5   ((unsigned int)(PMIC_BASE+0xa1e))
#define MT6358_STRUP_CON6   ((unsigned int)(PMIC_BASE+0xa20))
#define MT6358_STRUP_CON7   ((unsigned int)(PMIC_BASE+0xa22))
#define MT6358_CPSCFG0 ((unsigned int)(PMIC_BASE+0xa24))
#define MT6358_CPSDSA0 ((unsigned int)(PMIC_BASE+0xa26))
#define MT6358_CPSDSA1 ((unsigned int)(PMIC_BASE+0xa28))
#define MT6358_CPSDSA2 ((unsigned int)(PMIC_BASE+0xa2a))
#define MT6358_CPSDSA3 ((unsigned int)(PMIC_BASE+0xa2c))
#define MT6358_CPSDSA4 ((unsigned int)(PMIC_BASE+0xa2e))
#define MT6358_CPSDSA5 ((unsigned int)(PMIC_BASE+0xa30))
#define MT6358_CPSDSA6 ((unsigned int)(PMIC_BASE+0xa32))
#define MT6358_CPSDSA7 ((unsigned int)(PMIC_BASE+0xa34))
#define MT6358_STRUP_CON9   ((unsigned int)(PMIC_BASE+0xa36))
#define MT6358_STRUP_CON10   ((unsigned int)(PMIC_BASE+0xa38))
#define MT6358_STRUP_CON11   ((unsigned int)(PMIC_BASE+0xa3a))
#define MT6358_STRUP_CON12   ((unsigned int)(PMIC_BASE+0xa3c))
#define MT6358_STRUP_CON13   ((unsigned int)(PMIC_BASE+0xa3e))
#define MT6358_PWRKEY_PRESS_STS   ((unsigned int)(PMIC_BASE+0xa40))
#define MT6358_STRUP_CON19   ((unsigned int)(PMIC_BASE+0xa42))
#define MT6358_STRUP_CON14   ((unsigned int)(PMIC_BASE+0xa44))
#define MT6358_STRUP_CON15   ((unsigned int)(PMIC_BASE+0xa46))
#define MT6358_STRUP_CON16   ((unsigned int)(PMIC_BASE+0xa48))
#define MT6358_STRUP_CON17   ((unsigned int)(PMIC_BASE+0xa4a))
#define MT6358_STRUP_CON18   ((unsigned int)(PMIC_BASE+0xa4c))
#define MT6358_PSEQ_ELR_NUM  ((unsigned int)(PMIC_BASE+0xa4e))
#define MT6358_PSEQ_ELR0 ((unsigned int)(PMIC_BASE+0xa50))
#define MT6358_PSEQ_ELR1 ((unsigned int)(PMIC_BASE+0xa52))
#define MT6358_PSEQ_ELR2 ((unsigned int)(PMIC_BASE+0xa54))
#define MT6358_PSEQ_ELR3 ((unsigned int)(PMIC_BASE+0xa56))
#define MT6358_PSEQ_ELR4 ((unsigned int)(PMIC_BASE+0xa58))
#define MT6358_PSEQ_ELR5 ((unsigned int)(PMIC_BASE+0xa5a))
#define MT6358_PSEQ_ELR6 ((unsigned int)(PMIC_BASE+0xa5c))
#define MT6358_PSEQ_ELR7 ((unsigned int)(PMIC_BASE+0xa5e))
#define MT6358_PSEQ_ELR10   ((unsigned int)(PMIC_BASE+0xa60))
#define MT6358_PSEQ_ELR11   ((unsigned int)(PMIC_BASE+0xa62))
#define MT6358_CHRDET_ID ((unsigned int)(PMIC_BASE+0xa80))
#define MT6358_CHRDET_REV0   ((unsigned int)(PMIC_BASE+0xa82))
#define MT6358_CHRDET_DBI   ((unsigned int)(PMIC_BASE+0xa84))
#define MT6358_CHRDET_DXI   ((unsigned int)(PMIC_BASE+0xa86))
#define MT6358_CHR_CON0  ((unsigned int)(PMIC_BASE+0xa88))
#define MT6358_CHR_CON1  ((unsigned int)(PMIC_BASE+0xa8a))
#define MT6358_CHR_CON2  ((unsigned int)(PMIC_BASE+0xa8c))
#define MT6358_CHR_CON3  ((unsigned int)(PMIC_BASE+0xa8e))
#define MT6358_CHR_CON4  ((unsigned int)(PMIC_BASE+0xa90))
#define MT6358_PCHR_VREF_ANA_DA0  ((unsigned int)(PMIC_BASE+0xa92))
#define MT6358_PCHR_VREF_ANA_CON0  ((unsigned int)(PMIC_BASE+0xa94))
#define MT6358_PCHR_VREF_ANA_CON1  ((unsigned int)(PMIC_BASE+0xa96))
#define MT6358_PCHR_VREF_ANA_CON2  ((unsigned int)(PMIC_BASE+0xa98))
#define MT6358_PCHR_VREF_ANA_CON3  ((unsigned int)(PMIC_BASE+0xa9a))
#define MT6358_PCHR_VREF_ELR_NUM  ((unsigned int)(PMIC_BASE+0xa9c))
#define MT6358_PCHR_VREF_ELR_0 ((unsigned int)(PMIC_BASE+0xa9e))
#define MT6358_PCHR_VREF_ELR_1 ((unsigned int)(PMIC_BASE+0xaa0))
#define MT6358_BM_TOP_DSN_ID ((unsigned int)(PMIC_BASE+0xc00))
#define MT6358_BM_TOP_DSN_REV0 ((unsigned int)(PMIC_BASE+0xc02))
#define MT6358_BM_TOP_DBI   ((unsigned int)(PMIC_BASE+0xc04))
#define MT6358_BM_TOP_DXI   ((unsigned int)(PMIC_BASE+0xc06))
#define MT6358_BM_TPM0 ((unsigned int)(PMIC_BASE+0xc08))
#define MT6358_BM_TPM1 ((unsigned int)(PMIC_BASE+0xc0a))
#define MT6358_BM_TOP_CKPDN_CON0  ((unsigned int)(PMIC_BASE+0xc0c))
#define MT6358_BM_TOP_CKPDN_CON0_SET ((unsigned int)(PMIC_BASE+0xc0e))
#define MT6358_BM_TOP_CKPDN_CON0_CLR ((unsigned int)(PMIC_BASE+0xc10))
#define MT6358_BM_TOP_CKSEL_CON0  ((unsigned int)(PMIC_BASE+0xc12))
#define MT6358_BM_TOP_CKSEL_CON0_SET ((unsigned int)(PMIC_BASE+0xc14))
#define MT6358_BM_TOP_CKSEL_CON0_CLR ((unsigned int)(PMIC_BASE+0xc16))
#define MT6358_BM_TOP_CKDIVSEL_CON0  ((unsigned int)(PMIC_BASE+0xc18))
#define MT6358_BM_TOP_CKDIVSEL_CON0_SET ((unsigned int)(PMIC_BASE+0xc1a))
#define MT6358_BM_TOP_CKDIVSEL_CON0_CLR ((unsigned int)(PMIC_BASE+0xc1c))
#define MT6358_BM_TOP_CKHWEN_CON0  ((unsigned int)(PMIC_BASE+0xc1e))
#define MT6358_BM_TOP_CKHWEN_CON0_SET   ((unsigned int)(PMIC_BASE+0xc20))
#define MT6358_BM_TOP_CKHWEN_CON0_CLR   ((unsigned int)(PMIC_BASE+0xc22))
#define MT6358_BM_TOP_CKTST_CON0  ((unsigned int)(PMIC_BASE+0xc24))
#define MT6358_BM_TOP_RST_CON0 ((unsigned int)(PMIC_BASE+0xc26))
#define MT6358_BM_TOP_RST_CON0_SET ((unsigned int)(PMIC_BASE+0xc28))
#define MT6358_BM_TOP_RST_CON0_CLR ((unsigned int)(PMIC_BASE+0xc2a))
#define MT6358_BM_TOP_RST_CON1 ((unsigned int)(PMIC_BASE+0xc2c))
#define MT6358_BM_TOP_RST_CON1_SET ((unsigned int)(PMIC_BASE+0xc2e))
#define MT6358_BM_TOP_RST_CON1_CLR ((unsigned int)(PMIC_BASE+0xc30))
#define MT6358_BM_TOP_INT_CON0 ((unsigned int)(PMIC_BASE+0xc32))
#define MT6358_BM_TOP_INT_CON0_SET ((unsigned int)(PMIC_BASE+0xc34))
#define MT6358_BM_TOP_INT_CON0_CLR ((unsigned int)(PMIC_BASE+0xc36))
#define MT6358_BM_TOP_INT_CON1 ((unsigned int)(PMIC_BASE+0xc38))
#define MT6358_BM_TOP_INT_CON1_SET ((unsigned int)(PMIC_BASE+0xc3a))
#define MT6358_BM_TOP_INT_CON1_CLR ((unsigned int)(PMIC_BASE+0xc3c))
#define MT6358_BM_TOP_INT_MASK_CON0  ((unsigned int)(PMIC_BASE+0xc3e))
#define MT6358_BM_TOP_INT_MASK_CON0_SET ((unsigned int)(PMIC_BASE+0xc40))
#define MT6358_BM_TOP_INT_MASK_CON0_CLR ((unsigned int)(PMIC_BASE+0xc42))
#define MT6358_BM_TOP_INT_MASK_CON1  ((unsigned int)(PMIC_BASE+0xc44))
#define MT6358_BM_TOP_INT_MASK_CON1_SET ((unsigned int)(PMIC_BASE+0xc46))
#define MT6358_BM_TOP_INT_MASK_CON1_CLR ((unsigned int)(PMIC_BASE+0xc48))
#define MT6358_BM_TOP_INT_STATUS0  ((unsigned int)(PMIC_BASE+0xc4a))
#define MT6358_BM_TOP_INT_STATUS1  ((unsigned int)(PMIC_BASE+0xc4c))
#define MT6358_BM_TOP_INT_RAW_STATUS0   ((unsigned int)(PMIC_BASE+0xc4e))
#define MT6358_BM_TOP_INT_RAW_STATUS1   ((unsigned int)(PMIC_BASE+0xc50))
#define MT6358_BM_TOP_INT_MISC_CON ((unsigned int)(PMIC_BASE+0xc52))
#define MT6358_BM_TOP_DBG_CON  ((unsigned int)(PMIC_BASE+0xc54))
#define MT6358_BM_TOP_RSV0   ((unsigned int)(PMIC_BASE+0xc56))
#define MT6358_FGADC_ANA_DSN_ID   ((unsigned int)(PMIC_BASE+0xc80))
#define MT6358_FGADC_ANA_DSN_REV0  ((unsigned int)(PMIC_BASE+0xc82))
#define MT6358_FGADC_ANA_DSN_DBI  ((unsigned int)(PMIC_BASE+0xc84))
#define MT6358_FGADC_ANA_DSN_DXI  ((unsigned int)(PMIC_BASE+0xc86))
#define MT6358_FGADC_ANA_CON0  ((unsigned int)(PMIC_BASE+0xc88))
#define MT6358_FGADC_ANA_TEST_CON0 ((unsigned int)(PMIC_BASE+0xc8a))
#define MT6358_FGADC_ANA_ELR_NUM  ((unsigned int)(PMIC_BASE+0xc8c))
#define MT6358_FGADC_ANA_ELR0  ((unsigned int)(PMIC_BASE+0xc8e))
#define MT6358_FGADC_ANA_ELR1  ((unsigned int)(PMIC_BASE+0xc90))
#define MT6358_FGADC0_DSN_ID ((unsigned int)(PMIC_BASE+0xd00))
#define MT6358_FGADC0_DSN_REV0 ((unsigned int)(PMIC_BASE+0xd02))
#define MT6358_FGADC0_DSN_DBI  ((unsigned int)(PMIC_BASE+0xd04))
#define MT6358_FGADC0_DSN_DXI  ((unsigned int)(PMIC_BASE+0xd06))
#define MT6358_FGADC_CON0   ((unsigned int)(PMIC_BASE+0xd08))
#define MT6358_FGADC_CON1   ((unsigned int)(PMIC_BASE+0xd0a))
#define MT6358_FGADC_CON2   ((unsigned int)(PMIC_BASE+0xd0c))
#define MT6358_FGADC_CON3   ((unsigned int)(PMIC_BASE+0xd0e))
#define MT6358_FGADC_CON4   ((unsigned int)(PMIC_BASE+0xd10))
#define MT6358_FGADC_RST_CON0  ((unsigned int)(PMIC_BASE+0xd12))
#define MT6358_FGADC_CAR_CON0  ((unsigned int)(PMIC_BASE+0xd14))
#define MT6358_FGADC_CAR_CON1  ((unsigned int)(PMIC_BASE+0xd16))
#define MT6358_FGADC_CARTH_CON0   ((unsigned int)(PMIC_BASE+0xd18))
#define MT6358_FGADC_CARTH_CON1   ((unsigned int)(PMIC_BASE+0xd1a))
#define MT6358_FGADC_CARTH_CON2   ((unsigned int)(PMIC_BASE+0xd1c))
#define MT6358_FGADC_CARTH_CON3   ((unsigned int)(PMIC_BASE+0xd1e))
#define MT6358_FGADC_CARTH_CON4   ((unsigned int)(PMIC_BASE+0xd20))
#define MT6358_FGADC_CARTH_CON5   ((unsigned int)(PMIC_BASE+0xd22))
#define MT6358_FGADC_CARTH_CON6   ((unsigned int)(PMIC_BASE+0xd24))
#define MT6358_FGADC_CARTH_CON7   ((unsigned int)(PMIC_BASE+0xd26))
#define MT6358_FGADC_NCAR_CON0 ((unsigned int)(PMIC_BASE+0xd28))
#define MT6358_FGADC_NCAR_CON1 ((unsigned int)(PMIC_BASE+0xd2a))
#define MT6358_FGADC_NCAR_CON2 ((unsigned int)(PMIC_BASE+0xd2c))
#define MT6358_FGADC_NCAR_CON3 ((unsigned int)(PMIC_BASE+0xd2e))
#define MT6358_FGADC_IAVG_CON0 ((unsigned int)(PMIC_BASE+0xd30))
#define MT6358_FGADC_IAVG_CON1 ((unsigned int)(PMIC_BASE+0xd32))
#define MT6358_FGADC_IAVG_CON2 ((unsigned int)(PMIC_BASE+0xd34))
#define MT6358_FGADC_IAVG_CON3 ((unsigned int)(PMIC_BASE+0xd36))
#define MT6358_FGADC_IAVG_CON4 ((unsigned int)(PMIC_BASE+0xd38))
#define MT6358_FGADC_IAVG_CON5 ((unsigned int)(PMIC_BASE+0xd3a))
#define MT6358_FGADC_NTER_CON0 ((unsigned int)(PMIC_BASE+0xd3c))
#define MT6358_FGADC_NTER_CON1 ((unsigned int)(PMIC_BASE+0xd3e))
#define MT6358_FGADC_NTERTH_CON0  ((unsigned int)(PMIC_BASE+0xd40))
#define MT6358_FGADC_NTERTH_CON1  ((unsigned int)(PMIC_BASE+0xd42))
#define MT6358_FGADC_SON_CON0  ((unsigned int)(PMIC_BASE+0xd44))
#define MT6358_FGADC_SON_CON1  ((unsigned int)(PMIC_BASE+0xd46))
#define MT6358_FGADC_SON_CON2  ((unsigned int)(PMIC_BASE+0xd48))
#define MT6358_FGADC_SON_CON3  ((unsigned int)(PMIC_BASE+0xd4a))
#define MT6358_FGADC_SOFF_CON0 ((unsigned int)(PMIC_BASE+0xd4c))
#define MT6358_FGADC_SOFF_CON1 ((unsigned int)(PMIC_BASE+0xd4e))
#define MT6358_FGADC_SOFF_CON2 ((unsigned int)(PMIC_BASE+0xd50))
#define MT6358_FGADC_SOFF_CON3 ((unsigned int)(PMIC_BASE+0xd52))
#define MT6358_FGADC_SOFF_CON4 ((unsigned int)(PMIC_BASE+0xd54))
#define MT6358_FGADC_PWR_CON0  ((unsigned int)(PMIC_BASE+0xd56))
#define MT6358_FGADC_PWR_CON1  ((unsigned int)(PMIC_BASE+0xd58))
#define MT6358_FGADC_ZCV_CON0  ((unsigned int)(PMIC_BASE+0xd5a))
#define MT6358_FGADC_ZCV_CON1  ((unsigned int)(PMIC_BASE+0xd5c))
#define MT6358_FGADC_ZCV_CON2  ((unsigned int)(PMIC_BASE+0xd5e))
#define MT6358_FGADC_ZCV_CON3  ((unsigned int)(PMIC_BASE+0xd60))
#define MT6358_FGADC_ZCVTH_CON0   ((unsigned int)(PMIC_BASE+0xd62))
#define MT6358_FGADC_ZCVTH_CON1   ((unsigned int)(PMIC_BASE+0xd64))
#define MT6358_FGADC1_DSN_ID ((unsigned int)(PMIC_BASE+0xd80))
#define MT6358_FGADC1_DSN_REV0 ((unsigned int)(PMIC_BASE+0xd82))
#define MT6358_FGADC1_DSN_DBI  ((unsigned int)(PMIC_BASE+0xd84))
#define MT6358_FGADC1_DSN_DXI  ((unsigned int)(PMIC_BASE+0xd86))
#define MT6358_FGADC_R_CON0  ((unsigned int)(PMIC_BASE+0xd88))
#define MT6358_FGADC_CUR_CON0  ((unsigned int)(PMIC_BASE+0xd8a))
#define MT6358_FGADC_CUR_CON1  ((unsigned int)(PMIC_BASE+0xd8c))
#define MT6358_FGADC_CUR_CON2  ((unsigned int)(PMIC_BASE+0xd8e))
#define MT6358_FGADC_CUR_CON3  ((unsigned int)(PMIC_BASE+0xd90))
#define MT6358_FGADC_OFFSET_CON0  ((unsigned int)(PMIC_BASE+0xd92))
#define MT6358_FGADC_OFFSET_CON1  ((unsigned int)(PMIC_BASE+0xd94))
#define MT6358_FGADC_GAIN_CON0 ((unsigned int)(PMIC_BASE+0xd96))
#define MT6358_FGADC_TEST_CON0 ((unsigned int)(PMIC_BASE+0xd98))
#define MT6358_SYSTEM_INFO_CON0   ((unsigned int)(PMIC_BASE+0xd9a))
#define MT6358_BATON_ANA_DSN_ID   ((unsigned int)(PMIC_BASE+0xe00))
#define MT6358_BATON_ANA_DSN_REV0  ((unsigned int)(PMIC_BASE+0xe02))
#define MT6358_BATON_ANA_DSN_DBI  ((unsigned int)(PMIC_BASE+0xe04))
#define MT6358_BATON_ANA_DSN_DXI  ((unsigned int)(PMIC_BASE+0xe06))
#define MT6358_BATON_ANA_CON0  ((unsigned int)(PMIC_BASE+0xe08))
#define MT6358_BATON_ANA_MON0  ((unsigned int)(PMIC_BASE+0xe0a))
#define MT6358_BIF_ANA_MON0  ((unsigned int)(PMIC_BASE+0xe0c))
#define MT6358_BATON_ANA_ELR_NUM  ((unsigned int)(PMIC_BASE+0xe0e))
#define MT6358_BATON_ANA_ELR0  ((unsigned int)(PMIC_BASE+0xe10))
#define MT6358_BATON_DSN_ID  ((unsigned int)(PMIC_BASE+0xe80))
#define MT6358_BATON_DSN_REV0  ((unsigned int)(PMIC_BASE+0xe82))
#define MT6358_BATON_DSN_DBI ((unsigned int)(PMIC_BASE+0xe84))
#define MT6358_BATON_DSN_DXI ((unsigned int)(PMIC_BASE+0xe86))
#define MT6358_BATON_CON0   ((unsigned int)(PMIC_BASE+0xe88))
#define MT6358_BATON_CON1   ((unsigned int)(PMIC_BASE+0xe8a))
#define MT6358_BATON_CON2   ((unsigned int)(PMIC_BASE+0xe8c))
#define MT6358_BATON_CON3   ((unsigned int)(PMIC_BASE+0xe8e))
#define MT6358_BATON_ELR_NUM ((unsigned int)(PMIC_BASE+0xe90))
#define MT6358_BATON_ELR0   ((unsigned int)(PMIC_BASE+0xe92))
#define MT6358_BIF_DSN_ID   ((unsigned int)(PMIC_BASE+0xf00))
#define MT6358_BIF_DSN_REV0  ((unsigned int)(PMIC_BASE+0xf02))
#define MT6358_BIF_DSN_DBI   ((unsigned int)(PMIC_BASE+0xf04))
#define MT6358_BIF_DSN_DXI   ((unsigned int)(PMIC_BASE+0xf06))
#define MT6358_BIF_CON0  ((unsigned int)(PMIC_BASE+0xf08))
#define MT6358_BIF_CON1  ((unsigned int)(PMIC_BASE+0xf0a))
#define MT6358_BIF_CON2  ((unsigned int)(PMIC_BASE+0xf0c))
#define MT6358_BIF_CON3  ((unsigned int)(PMIC_BASE+0xf0e))
#define MT6358_BIF_CON4  ((unsigned int)(PMIC_BASE+0xf10))
#define MT6358_BIF_CON5  ((unsigned int)(PMIC_BASE+0xf12))
#define MT6358_BIF_CON6  ((unsigned int)(PMIC_BASE+0xf14))
#define MT6358_BIF_CON7  ((unsigned int)(PMIC_BASE+0xf16))
#define MT6358_BIF_CON8  ((unsigned int)(PMIC_BASE+0xf18))
#define MT6358_BIF_CON9  ((unsigned int)(PMIC_BASE+0xf1a))
#define MT6358_BIF_CON10 ((unsigned int)(PMIC_BASE+0xf1c))
#define MT6358_BIF_CON11 ((unsigned int)(PMIC_BASE+0xf1e))
#define MT6358_BIF_CON12 ((unsigned int)(PMIC_BASE+0xf20))
#define MT6358_BIF_CON13 ((unsigned int)(PMIC_BASE+0xf22))
#define MT6358_BIF_CON14 ((unsigned int)(PMIC_BASE+0xf24))
#define MT6358_BIF_CON15 ((unsigned int)(PMIC_BASE+0xf26))
#define MT6358_BIF_CON16 ((unsigned int)(PMIC_BASE+0xf28))
#define MT6358_BIF_CON17 ((unsigned int)(PMIC_BASE+0xf2a))
#define MT6358_BIF_CON18 ((unsigned int)(PMIC_BASE+0xf2c))
#define MT6358_BIF_CON19 ((unsigned int)(PMIC_BASE+0xf2e))
#define MT6358_BIF_CON20 ((unsigned int)(PMIC_BASE+0xf30))
#define MT6358_BIF_CON21 ((unsigned int)(PMIC_BASE+0xf32))
#define MT6358_BIF_CON22 ((unsigned int)(PMIC_BASE+0xf34))
#define MT6358_BIF_CON23 ((unsigned int)(PMIC_BASE+0xf36))
#define MT6358_BIF_CON24 ((unsigned int)(PMIC_BASE+0xf38))
#define MT6358_BIF_CON25 ((unsigned int)(PMIC_BASE+0xf3a))
#define MT6358_BIF_CON26 ((unsigned int)(PMIC_BASE+0xf3c))
#define MT6358_BIF_CON27 ((unsigned int)(PMIC_BASE+0xf3e))
#define MT6358_BIF_CON28 ((unsigned int)(PMIC_BASE+0xf40))
#define MT6358_BIF_CON29 ((unsigned int)(PMIC_BASE+0xf42))
#define MT6358_BIF_CON30 ((unsigned int)(PMIC_BASE+0xf44))
#define MT6358_BIF_CON31 ((unsigned int)(PMIC_BASE+0xf46))
#define MT6358_BIF_CON32 ((unsigned int)(PMIC_BASE+0xf48))
#define MT6358_BIF_CON33 ((unsigned int)(PMIC_BASE+0xf4a))
#define MT6358_BIF_CON34 ((unsigned int)(PMIC_BASE+0xf4c))
#define MT6358_BIF_CON35 ((unsigned int)(PMIC_BASE+0xf4e))
#define MT6358_BIF_CON36 ((unsigned int)(PMIC_BASE+0xf50))
#define MT6358_BIF_CON37 ((unsigned int)(PMIC_BASE+0xf52))
#define MT6358_BIF_CON38 ((unsigned int)(PMIC_BASE+0xf54))
#define MT6358_BIF_CON39 ((unsigned int)(PMIC_BASE+0xf56))
#define MT6358_HK_TOP_ID ((unsigned int)(PMIC_BASE+0xf80))
#define MT6358_HK_TOP_REV0   ((unsigned int)(PMIC_BASE+0xf82))
#define MT6358_HK_TOP_DBI   ((unsigned int)(PMIC_BASE+0xf84))
#define MT6358_HK_TOP_DXI   ((unsigned int)(PMIC_BASE+0xf86))
#define MT6358_HK_TPM0 ((unsigned int)(PMIC_BASE+0xf88))
#define MT6358_HK_TPM1 ((unsigned int)(PMIC_BASE+0xf8a))
#define MT6358_HK_TOP_CLK_CON0 ((unsigned int)(PMIC_BASE+0xf8c))
#define MT6358_HK_TOP_CLK_CON1 ((unsigned int)(PMIC_BASE+0xf8e))
#define MT6358_HK_TOP_RST_CON0 ((unsigned int)(PMIC_BASE+0xf90))
#define MT6358_HK_TOP_INT_CON0 ((unsigned int)(PMIC_BASE+0xf92))
#define MT6358_HK_TOP_INT_CON0_SET ((unsigned int)(PMIC_BASE+0xf94))
#define MT6358_HK_TOP_INT_CON0_CLR ((unsigned int)(PMIC_BASE+0xf96))
#define MT6358_HK_TOP_INT_MASK_CON0  ((unsigned int)(PMIC_BASE+0xf98))
#define MT6358_HK_TOP_INT_MASK_CON0_SET ((unsigned int)(PMIC_BASE+0xf9a))
#define MT6358_HK_TOP_INT_MASK_CON0_CLR ((unsigned int)(PMIC_BASE+0xf9c))
#define MT6358_HK_TOP_INT_STATUS0  ((unsigned int)(PMIC_BASE+0xf9e))
#define MT6358_HK_TOP_INT_RAW_STATUS0   ((unsigned int)(PMIC_BASE+0xfa0))
#define MT6358_HK_TOP_MON_CON0 ((unsigned int)(PMIC_BASE+0xfa2))
#define MT6358_HK_TOP_MON_CON1 ((unsigned int)(PMIC_BASE+0xfa4))
#define MT6358_HK_TOP_MON_CON2 ((unsigned int)(PMIC_BASE+0xfa6))
#define MT6358_HK_TOP_CHR_CON  ((unsigned int)(PMIC_BASE+0xfa8))
#define MT6358_HK_TOP_AUXADC_ANA  ((unsigned int)(PMIC_BASE+0xfaa))
#define MT6358_AUXADC_DSN_ID ((unsigned int)(PMIC_BASE+0x1000))
#define MT6358_AUXADC_DSN_REV0 ((unsigned int)(PMIC_BASE+0x1002))
#define MT6358_AUXADC_DSN_DBI  ((unsigned int)(PMIC_BASE+0x1004))
#define MT6358_AUXADC_DSN_FPI  ((unsigned int)(PMIC_BASE+0x1006))
#define MT6358_AUXADC_ANA_CON0 ((unsigned int)(PMIC_BASE+0x1008))
#define MT6358_AUXADC_DIG_1_DSN_ID ((unsigned int)(PMIC_BASE+0x1080))
#define MT6358_AUXADC_DIG_1_DSN_REV0 ((unsigned int)(PMIC_BASE+0x1082))
#define MT6358_AUXADC_DIG_1_DSN_DBI  ((unsigned int)(PMIC_BASE+0x1084))
#define MT6358_AUXADC_DIG_1_DSN_DXI  ((unsigned int)(PMIC_BASE+0x1086))
#define MT6358_AUXADC_ADC0   ((unsigned int)(PMIC_BASE+0x1088))
#define MT6358_AUXADC_ADC1   ((unsigned int)(PMIC_BASE+0x108a))
#define MT6358_AUXADC_ADC2   ((unsigned int)(PMIC_BASE+0x108c))
#define MT6358_AUXADC_ADC3   ((unsigned int)(PMIC_BASE+0x108e))
#define MT6358_AUXADC_ADC4   ((unsigned int)(PMIC_BASE+0x1090))
#define MT6358_AUXADC_ADC5   ((unsigned int)(PMIC_BASE+0x1092))
#define MT6358_AUXADC_ADC6   ((unsigned int)(PMIC_BASE+0x1094))
#define MT6358_AUXADC_ADC7   ((unsigned int)(PMIC_BASE+0x1096))
#define MT6358_AUXADC_ADC8   ((unsigned int)(PMIC_BASE+0x1098))
#define MT6358_AUXADC_ADC9   ((unsigned int)(PMIC_BASE+0x109a))
#define MT6358_AUXADC_ADC10  ((unsigned int)(PMIC_BASE+0x109c))
#define MT6358_AUXADC_ADC11  ((unsigned int)(PMIC_BASE+0x109e))
#define MT6358_AUXADC_ADC12  ((unsigned int)(PMIC_BASE+0x10a0))
#define MT6358_AUXADC_ADC13  ((unsigned int)(PMIC_BASE+0x10a2))
#define MT6358_AUXADC_ADC14  ((unsigned int)(PMIC_BASE+0x10a4))
#define MT6358_AUXADC_ADC15  ((unsigned int)(PMIC_BASE+0x10a6))
#define MT6358_AUXADC_ADC16  ((unsigned int)(PMIC_BASE+0x10a8))
#define MT6358_AUXADC_ADC17  ((unsigned int)(PMIC_BASE+0x10aa))
#define MT6358_AUXADC_ADC18  ((unsigned int)(PMIC_BASE+0x10ac))
#define MT6358_AUXADC_ADC19  ((unsigned int)(PMIC_BASE+0x10ae))
#define MT6358_AUXADC_ADC20  ((unsigned int)(PMIC_BASE+0x10b0))
#define MT6358_AUXADC_ADC21  ((unsigned int)(PMIC_BASE+0x10b2))
#define MT6358_AUXADC_ADC22  ((unsigned int)(PMIC_BASE+0x10b4))
#define MT6358_AUXADC_ADC23  ((unsigned int)(PMIC_BASE+0x10b6))
#define MT6358_AUXADC_ADC24  ((unsigned int)(PMIC_BASE+0x10b8))
#define MT6358_AUXADC_ADC25  ((unsigned int)(PMIC_BASE+0x10ba))
#define MT6358_AUXADC_ADC26  ((unsigned int)(PMIC_BASE+0x10bc))
#define MT6358_AUXADC_ADC27  ((unsigned int)(PMIC_BASE+0x10be))
#define MT6358_AUXADC_ADC28  ((unsigned int)(PMIC_BASE+0x10c0))
#define MT6358_AUXADC_ADC29  ((unsigned int)(PMIC_BASE+0x10c2))
#define MT6358_AUXADC_ADC30  ((unsigned int)(PMIC_BASE+0x10c4))
#define MT6358_AUXADC_ADC31  ((unsigned int)(PMIC_BASE+0x10c6))
#define MT6358_AUXADC_ADC32  ((unsigned int)(PMIC_BASE+0x10c8))
#define MT6358_AUXADC_ADC33  ((unsigned int)(PMIC_BASE+0x10ca))
#define MT6358_AUXADC_ADC34  ((unsigned int)(PMIC_BASE+0x10cc))
#define MT6358_AUXADC_ADC35  ((unsigned int)(PMIC_BASE+0x10ce))
#define MT6358_AUXADC_ADC36  ((unsigned int)(PMIC_BASE+0x10d0))
#define MT6358_AUXADC_ADC37  ((unsigned int)(PMIC_BASE+0x10d2))
#define MT6358_AUXADC_ADC38  ((unsigned int)(PMIC_BASE+0x10d4))
#define MT6358_AUXADC_ADC39  ((unsigned int)(PMIC_BASE+0x10d6))
#define MT6358_AUXADC_ADC40  ((unsigned int)(PMIC_BASE+0x10d8))
#define MT6358_AUXADC_STA0   ((unsigned int)(PMIC_BASE+0x10da))
#define MT6358_AUXADC_STA1   ((unsigned int)(PMIC_BASE+0x10dc))
#define MT6358_AUXADC_STA2   ((unsigned int)(PMIC_BASE+0x10de))
#define MT6358_AUXADC_DIG_2_DSN_ID ((unsigned int)(PMIC_BASE+0x1100))
#define MT6358_AUXADC_DIG_2_DSN_REV0 ((unsigned int)(PMIC_BASE+0x1102))
#define MT6358_AUXADC_DIG_2_DSN_DBI  ((unsigned int)(PMIC_BASE+0x1104))
#define MT6358_AUXADC_DIG_2_DSN_DXI  ((unsigned int)(PMIC_BASE+0x1106))
#define MT6358_AUXADC_RQST0  ((unsigned int)(PMIC_BASE+0x1108))
#define MT6358_AUXADC_RQST1  ((unsigned int)(PMIC_BASE+0x110a))
#define MT6358_AUXADC_DIG_3_DSN_ID ((unsigned int)(PMIC_BASE+0x1180))
#define MT6358_AUXADC_DIG_3_DSN_REV0 ((unsigned int)(PMIC_BASE+0x1182))
#define MT6358_AUXADC_DIG_3_DSN_DBI  ((unsigned int)(PMIC_BASE+0x1184))
#define MT6358_AUXADC_DIG_3_DSN_DXI  ((unsigned int)(PMIC_BASE+0x1186))
#define MT6358_AUXADC_CON0   ((unsigned int)(PMIC_BASE+0x1188))
#define MT6358_AUXADC_CON0_SET ((unsigned int)(PMIC_BASE+0x118a))
#define MT6358_AUXADC_CON0_CLR ((unsigned int)(PMIC_BASE+0x118c))
#define MT6358_AUXADC_CON1   ((unsigned int)(PMIC_BASE+0x118e))
#define MT6358_AUXADC_CON2   ((unsigned int)(PMIC_BASE+0x1190))
#define MT6358_AUXADC_CON3   ((unsigned int)(PMIC_BASE+0x1192))
#define MT6358_AUXADC_CON4   ((unsigned int)(PMIC_BASE+0x1194))
#define MT6358_AUXADC_CON5   ((unsigned int)(PMIC_BASE+0x1196))
#define MT6358_AUXADC_CON6   ((unsigned int)(PMIC_BASE+0x1198))
#define MT6358_AUXADC_CON7   ((unsigned int)(PMIC_BASE+0x119a))
#define MT6358_AUXADC_CON8   ((unsigned int)(PMIC_BASE+0x119c))
#define MT6358_AUXADC_CON9   ((unsigned int)(PMIC_BASE+0x119e))
#define MT6358_AUXADC_CON10  ((unsigned int)(PMIC_BASE+0x11a0))
#define MT6358_AUXADC_CON11  ((unsigned int)(PMIC_BASE+0x11a2))
#define MT6358_AUXADC_CON12  ((unsigned int)(PMIC_BASE+0x11a4))
#define MT6358_AUXADC_CON13  ((unsigned int)(PMIC_BASE+0x11a6))
#define MT6358_AUXADC_CON14  ((unsigned int)(PMIC_BASE+0x11a8))
#define MT6358_AUXADC_CON15  ((unsigned int)(PMIC_BASE+0x11aa))
#define MT6358_AUXADC_CON16  ((unsigned int)(PMIC_BASE+0x11ac))
#define MT6358_AUXADC_CON17  ((unsigned int)(PMIC_BASE+0x11ae))
#define MT6358_AUXADC_CON18  ((unsigned int)(PMIC_BASE+0x11b0))
#define MT6358_AUXADC_CON19  ((unsigned int)(PMIC_BASE+0x11b2))
#define MT6358_AUXADC_CON20  ((unsigned int)(PMIC_BASE+0x11b4))
#define MT6358_AUXADC_AUTORPT0 ((unsigned int)(PMIC_BASE+0x11b6))
#define MT6358_AUXADC_ACCDET ((unsigned int)(PMIC_BASE+0x11b8))
#define MT6358_AUXADC_DBG0   ((unsigned int)(PMIC_BASE+0x11ba))
#define MT6358_AUXADC_DIG_3_ELR_NUM  ((unsigned int)(PMIC_BASE+0x11bc))
#define MT6358_AUXADC_DIG_3_ELR0  ((unsigned int)(PMIC_BASE+0x11be))
#define MT6358_AUXADC_DIG_3_ELR1  ((unsigned int)(PMIC_BASE+0x11c0))
#define MT6358_AUXADC_DIG_3_ELR2  ((unsigned int)(PMIC_BASE+0x11c2))
#define MT6358_AUXADC_DIG_3_ELR3  ((unsigned int)(PMIC_BASE+0x11c4))
#define MT6358_AUXADC_DIG_3_ELR4  ((unsigned int)(PMIC_BASE+0x11c6))
#define MT6358_AUXADC_DIG_3_ELR5  ((unsigned int)(PMIC_BASE+0x11c8))
#define MT6358_AUXADC_DIG_3_ELR6  ((unsigned int)(PMIC_BASE+0x11ca))
#define MT6358_AUXADC_DIG_3_ELR7  ((unsigned int)(PMIC_BASE+0x11cc))
#define MT6358_AUXADC_DIG_3_ELR8  ((unsigned int)(PMIC_BASE+0x11ce))
#define MT6358_AUXADC_DIG_3_ELR9  ((unsigned int)(PMIC_BASE+0x11d0))
#define MT6358_AUXADC_DIG_3_ELR10  ((unsigned int)(PMIC_BASE+0x11d2))
#define MT6358_AUXADC_DIG_3_ELR11  ((unsigned int)(PMIC_BASE+0x11d4))
#define MT6358_AUXADC_DIG_3_ELR12  ((unsigned int)(PMIC_BASE+0x11d6))
#define MT6358_AUXADC_DIG_3_ELR13  ((unsigned int)(PMIC_BASE+0x11d8))
#define MT6358_AUXADC_DIG_4_DSN_ID ((unsigned int)(PMIC_BASE+0x1200))
#define MT6358_AUXADC_DIG_4_DSN_REV0 ((unsigned int)(PMIC_BASE+0x1202))
#define MT6358_AUXADC_DIG_4_DSN_DBI  ((unsigned int)(PMIC_BASE+0x1204))
#define MT6358_AUXADC_DIG_4_DSN_DXI  ((unsigned int)(PMIC_BASE+0x1206))
#define MT6358_AUXADC_IMP0   ((unsigned int)(PMIC_BASE+0x1208))
#define MT6358_AUXADC_IMP1   ((unsigned int)(PMIC_BASE+0x120a))
#define MT6358_AUXADC_IMP2   ((unsigned int)(PMIC_BASE+0x120c))
#define MT6358_AUXADC_LBAT0  ((unsigned int)(PMIC_BASE+0x120e))
#define MT6358_AUXADC_LBAT1  ((unsigned int)(PMIC_BASE+0x1210))
#define MT6358_AUXADC_LBAT2  ((unsigned int)(PMIC_BASE+0x1212))
#define MT6358_AUXADC_LBAT3  ((unsigned int)(PMIC_BASE+0x1214))
#define MT6358_AUXADC_LBAT4  ((unsigned int)(PMIC_BASE+0x1216))
#define MT6358_AUXADC_LBAT5  ((unsigned int)(PMIC_BASE+0x1218))
#define MT6358_AUXADC_LBAT6  ((unsigned int)(PMIC_BASE+0x121a))
#define MT6358_AUXADC_BAT_TEMP_0  ((unsigned int)(PMIC_BASE+0x121c))
#define MT6358_AUXADC_BAT_TEMP_1  ((unsigned int)(PMIC_BASE+0x121e))
#define MT6358_AUXADC_BAT_TEMP_2  ((unsigned int)(PMIC_BASE+0x1220))
#define MT6358_AUXADC_BAT_TEMP_3  ((unsigned int)(PMIC_BASE+0x1222))
#define MT6358_AUXADC_BAT_TEMP_4  ((unsigned int)(PMIC_BASE+0x1224))
#define MT6358_AUXADC_BAT_TEMP_5  ((unsigned int)(PMIC_BASE+0x1226))
#define MT6358_AUXADC_BAT_TEMP_6  ((unsigned int)(PMIC_BASE+0x1228))
#define MT6358_AUXADC_BAT_TEMP_7  ((unsigned int)(PMIC_BASE+0x122a))
#define MT6358_AUXADC_LBAT2_1  ((unsigned int)(PMIC_BASE+0x122c))
#define MT6358_AUXADC_LBAT2_2  ((unsigned int)(PMIC_BASE+0x122e))
#define MT6358_AUXADC_LBAT2_3  ((unsigned int)(PMIC_BASE+0x1230))
#define MT6358_AUXADC_LBAT2_4  ((unsigned int)(PMIC_BASE+0x1232))
#define MT6358_AUXADC_LBAT2_5  ((unsigned int)(PMIC_BASE+0x1234))
#define MT6358_AUXADC_LBAT2_6  ((unsigned int)(PMIC_BASE+0x1236))
#define MT6358_AUXADC_LBAT2_7  ((unsigned int)(PMIC_BASE+0x1238))
#define MT6358_AUXADC_MDRT_0 ((unsigned int)(PMIC_BASE+0x123a))
#define MT6358_AUXADC_MDRT_1 ((unsigned int)(PMIC_BASE+0x123c))
#define MT6358_AUXADC_MDRT_2 ((unsigned int)(PMIC_BASE+0x123e))
#define MT6358_AUXADC_MDRT_3 ((unsigned int)(PMIC_BASE+0x1240))
#define MT6358_AUXADC_MDRT_4 ((unsigned int)(PMIC_BASE+0x1242))
#define MT6358_AUXADC_DCXO_MDRT_1  ((unsigned int)(PMIC_BASE+0x1244))
#define MT6358_AUXADC_DCXO_MDRT_2  ((unsigned int)(PMIC_BASE+0x1246))
#define MT6358_AUXADC_NAG_0  ((unsigned int)(PMIC_BASE+0x1248))
#define MT6358_AUXADC_NAG_1  ((unsigned int)(PMIC_BASE+0x124a))
#define MT6358_AUXADC_NAG_2  ((unsigned int)(PMIC_BASE+0x124c))
#define MT6358_AUXADC_NAG_3  ((unsigned int)(PMIC_BASE+0x124e))
#define MT6358_AUXADC_NAG_4  ((unsigned int)(PMIC_BASE+0x1250))
#define MT6358_AUXADC_NAG_5  ((unsigned int)(PMIC_BASE+0x1252))
#define MT6358_AUXADC_NAG_6  ((unsigned int)(PMIC_BASE+0x1254))
#define MT6358_AUXADC_NAG_7  ((unsigned int)(PMIC_BASE+0x1256))
#define MT6358_AUXADC_NAG_8  ((unsigned int)(PMIC_BASE+0x1258))
#define MT6358_AUXADC_NAG_9  ((unsigned int)(PMIC_BASE+0x125a))
#define MT6358_AUXADC_RSV_1  ((unsigned int)(PMIC_BASE+0x125c))
#define MT6358_AUXADC_PRI_NEW  ((unsigned int)(PMIC_BASE+0x125e))
#define MT6358_AUXADC_DCM_CON  ((unsigned int)(PMIC_BASE+0x1260))
#define MT6358_AUXADC_SPL_LIST_0  ((unsigned int)(PMIC_BASE+0x1262))
#define MT6358_AUXADC_SPL_LIST_1  ((unsigned int)(PMIC_BASE+0x1264))
#define MT6358_AUXADC_SPL_LIST_2  ((unsigned int)(PMIC_BASE+0x1266))
#define MT6358_BUCK_TOP_DSN_ID ((unsigned int)(PMIC_BASE+0x1300))
#define MT6358_BUCK_TOP_DSN_REV0  ((unsigned int)(PMIC_BASE+0x1302))
#define MT6358_BUCK_TOP_DBI  ((unsigned int)(PMIC_BASE+0x1304))
#define MT6358_BUCK_TOP_DXI  ((unsigned int)(PMIC_BASE+0x1306))
#define MT6358_BUCK_TOP_PAM0 ((unsigned int)(PMIC_BASE+0x1308))
#define MT6358_BUCK_TOP_PAM1 ((unsigned int)(PMIC_BASE+0x130a))
#define MT6358_BUCK_TOP_CLK_CON0  ((unsigned int)(PMIC_BASE+0x130c))
#define MT6358_BUCK_TOP_CLK_CON0_SET ((unsigned int)(PMIC_BASE+0x130e))
#define MT6358_BUCK_TOP_CLK_CON0_CLR ((unsigned int)(PMIC_BASE+0x1310))
#define MT6358_BUCK_TOP_CLK_HWEN_CON0   ((unsigned int)(PMIC_BASE+0x1312))
#define MT6358_BUCK_TOP_CLK_HWEN_CON0_SET  ((unsigned int)(PMIC_BASE+0x1314))
#define MT6358_BUCK_TOP_CLK_HWEN_CON0_CLR  ((unsigned int)(PMIC_BASE+0x1316))
#define MT6358_BUCK_TOP_INT_CON0  ((unsigned int)(PMIC_BASE+0x1318))
#define MT6358_BUCK_TOP_INT_CON0_SET ((unsigned int)(PMIC_BASE+0x131a))
#define MT6358_BUCK_TOP_INT_CON0_CLR ((unsigned int)(PMIC_BASE+0x131c))
#define MT6358_BUCK_TOP_INT_MASK_CON0   ((unsigned int)(PMIC_BASE+0x131e))
#define MT6358_BUCK_TOP_INT_MASK_CON0_SET  ((unsigned int)(PMIC_BASE+0x1320))
#define MT6358_BUCK_TOP_INT_MASK_CON0_CLR  ((unsigned int)(PMIC_BASE+0x1322))
#define MT6358_BUCK_TOP_INT_STATUS0  ((unsigned int)(PMIC_BASE+0x1324))
#define MT6358_BUCK_TOP_INT_RAW_STATUS0 ((unsigned int)(PMIC_BASE+0x1326))
#define MT6358_BUCK_TOP_STB_CON   ((unsigned int)(PMIC_BASE+0x1328))
#define MT6358_BUCK_TOP_SLP_CON0  ((unsigned int)(PMIC_BASE+0x132a))
#define MT6358_BUCK_TOP_SLP_CON1  ((unsigned int)(PMIC_BASE+0x132c))
#define MT6358_BUCK_TOP_SLP_CON2  ((unsigned int)(PMIC_BASE+0x132e))
#define MT6358_BUCK_TOP_MINFREQ_CON  ((unsigned int)(PMIC_BASE+0x1330))
#define MT6358_BUCK_TOP_OC_CON0   ((unsigned int)(PMIC_BASE+0x1332))
#define MT6358_BUCK_TOP_K_CON0 ((unsigned int)(PMIC_BASE+0x1334))
#define MT6358_BUCK_TOP_K_CON1 ((unsigned int)(PMIC_BASE+0x1336))
#define MT6358_BUCK_TOP_K_CON2 ((unsigned int)(PMIC_BASE+0x1338))
#define MT6358_BUCK_TOP_WDTDBG0   ((unsigned int)(PMIC_BASE+0x133a))
#define MT6358_BUCK_TOP_WDTDBG1   ((unsigned int)(PMIC_BASE+0x133c))
#define MT6358_BUCK_TOP_WDTDBG2   ((unsigned int)(PMIC_BASE+0x133e))
#define MT6358_BUCK_TOP_WDTDBG3   ((unsigned int)(PMIC_BASE+0x1340))
#define MT6358_BUCK_TOP_WDTDBG4   ((unsigned int)(PMIC_BASE+0x1342))
#define MT6358_BUCK_TOP_ELR_NUM   ((unsigned int)(PMIC_BASE+0x1344))
#define MT6358_BUCK_TOP_ELR0 ((unsigned int)(PMIC_BASE+0x1346))
#define MT6358_BUCK_TOP_ELR1 ((unsigned int)(PMIC_BASE+0x1348))
#define MT6358_BUCK_TOP_ELR2 ((unsigned int)(PMIC_BASE+0x134a))
#define MT6358_BUCK_TOP_ELR3 ((unsigned int)(PMIC_BASE+0x134c))
#define MT6358_BUCK_VPROC11_DSN_ID ((unsigned int)(PMIC_BASE+0x1380))
#define MT6358_BUCK_VPROC11_DSN_REV0 ((unsigned int)(PMIC_BASE+0x1382))
#define MT6358_BUCK_VPROC11_DSN_DBI  ((unsigned int)(PMIC_BASE+0x1384))
#define MT6358_BUCK_VPROC11_DSN_DXI  ((unsigned int)(PMIC_BASE+0x1386))
#define MT6358_BUCK_VPROC11_CON0  ((unsigned int)(PMIC_BASE+0x1388))
#define MT6358_BUCK_VPROC11_CON1  ((unsigned int)(PMIC_BASE+0x138a))
#define MT6358_BUCK_VPROC11_CFG0  ((unsigned int)(PMIC_BASE+0x138c))
#define MT6358_BUCK_VPROC11_CFG1  ((unsigned int)(PMIC_BASE+0x138e))
#define MT6358_BUCK_VPROC11_OP_EN  ((unsigned int)(PMIC_BASE+0x1390))
#define MT6358_BUCK_VPROC11_OP_EN_SET   ((unsigned int)(PMIC_BASE+0x1392))
#define MT6358_BUCK_VPROC11_OP_EN_CLR   ((unsigned int)(PMIC_BASE+0x1394))
#define MT6358_BUCK_VPROC11_OP_CFG ((unsigned int)(PMIC_BASE+0x1396))
#define MT6358_BUCK_VPROC11_OP_CFG_SET  ((unsigned int)(PMIC_BASE+0x1398))
#define MT6358_BUCK_VPROC11_OP_CFG_CLR  ((unsigned int)(PMIC_BASE+0x139a))
#define MT6358_BUCK_VPROC11_OC_CFG ((unsigned int)(PMIC_BASE+0x139c))
#define MT6358_BUCK_VPROC11_DBG0  ((unsigned int)(PMIC_BASE+0x139e))
#define MT6358_BUCK_VPROC11_DBG1  ((unsigned int)(PMIC_BASE+0x13a0))
#define MT6358_BUCK_VPROC11_DBG2  ((unsigned int)(PMIC_BASE+0x13a2))
#define MT6358_BUCK_VPROC11_ELR_NUM  ((unsigned int)(PMIC_BASE+0x13a4))
#define MT6358_BUCK_VPROC11_ELR0  ((unsigned int)(PMIC_BASE+0x13a6))
#define MT6358_BUCK_VPROC12_DSN_ID ((unsigned int)(PMIC_BASE+0x1400))
#define MT6358_BUCK_VPROC12_DSN_REV0 ((unsigned int)(PMIC_BASE+0x1402))
#define MT6358_BUCK_VPROC12_DSN_DBI  ((unsigned int)(PMIC_BASE+0x1404))
#define MT6358_BUCK_VPROC12_DSN_DXI  ((unsigned int)(PMIC_BASE+0x1406))
#define MT6358_BUCK_VPROC12_CON0  ((unsigned int)(PMIC_BASE+0x1408))
#define MT6358_BUCK_VPROC12_CON1  ((unsigned int)(PMIC_BASE+0x140a))
#define MT6358_BUCK_VPROC12_CFG0  ((unsigned int)(PMIC_BASE+0x140c))
#define MT6358_BUCK_VPROC12_CFG1  ((unsigned int)(PMIC_BASE+0x140e))
#define MT6358_BUCK_VPROC12_OP_EN  ((unsigned int)(PMIC_BASE+0x1410))
#define MT6358_BUCK_VPROC12_OP_EN_SET   ((unsigned int)(PMIC_BASE+0x1412))
#define MT6358_BUCK_VPROC12_OP_EN_CLR   ((unsigned int)(PMIC_BASE+0x1414))
#define MT6358_BUCK_VPROC12_OP_CFG ((unsigned int)(PMIC_BASE+0x1416))
#define MT6358_BUCK_VPROC12_OP_CFG_SET  ((unsigned int)(PMIC_BASE+0x1418))
#define MT6358_BUCK_VPROC12_OP_CFG_CLR  ((unsigned int)(PMIC_BASE+0x141a))
#define MT6358_BUCK_VPROC12_OC_CFG ((unsigned int)(PMIC_BASE+0x141c))
#define MT6358_BUCK_VPROC12_DBG0  ((unsigned int)(PMIC_BASE+0x141e))
#define MT6358_BUCK_VPROC12_DBG1  ((unsigned int)(PMIC_BASE+0x1420))
#define MT6358_BUCK_VPROC12_DBG2  ((unsigned int)(PMIC_BASE+0x1422))
#define MT6358_BUCK_VPROC12_ELR_NUM  ((unsigned int)(PMIC_BASE+0x1424))
#define MT6358_BUCK_VPROC12_ELR0  ((unsigned int)(PMIC_BASE+0x1426))
#define MT6358_BUCK_VCORE_DSN_ID  ((unsigned int)(PMIC_BASE+0x1480))
#define MT6358_BUCK_VCORE_DSN_REV0 ((unsigned int)(PMIC_BASE+0x1482))
#define MT6358_BUCK_VCORE_DSN_DBI  ((unsigned int)(PMIC_BASE+0x1484))
#define MT6358_BUCK_VCORE_DSN_DXI  ((unsigned int)(PMIC_BASE+0x1486))
#define MT6358_BUCK_VCORE_CON0 ((unsigned int)(PMIC_BASE+0x1488))
#define MT6358_BUCK_VCORE_CON1 ((unsigned int)(PMIC_BASE+0x148a))
#define MT6358_BUCK_VCORE_CFG0 ((unsigned int)(PMIC_BASE+0x148c))
#define MT6358_BUCK_VCORE_CFG1 ((unsigned int)(PMIC_BASE+0x148e))
#define MT6358_BUCK_VCORE_OP_EN   ((unsigned int)(PMIC_BASE+0x1490))
#define MT6358_BUCK_VCORE_OP_EN_SET  ((unsigned int)(PMIC_BASE+0x1492))
#define MT6358_BUCK_VCORE_OP_EN_CLR  ((unsigned int)(PMIC_BASE+0x1494))
#define MT6358_BUCK_VCORE_OP_CFG  ((unsigned int)(PMIC_BASE+0x1496))
#define MT6358_BUCK_VCORE_OP_CFG_SET ((unsigned int)(PMIC_BASE+0x1498))
#define MT6358_BUCK_VCORE_OP_CFG_CLR ((unsigned int)(PMIC_BASE+0x149a))
#define MT6358_BUCK_VCORE_OC_CFG  ((unsigned int)(PMIC_BASE+0x149c))
#define MT6358_BUCK_VCORE_DBG0 ((unsigned int)(PMIC_BASE+0x149e))
#define MT6358_BUCK_VCORE_DBG1 ((unsigned int)(PMIC_BASE+0x14a0))
#define MT6358_BUCK_VCORE_DBG2 ((unsigned int)(PMIC_BASE+0x14a2))
#define MT6358_BUCK_VCORE_SSHUB_CON0 ((unsigned int)(PMIC_BASE+0x14a4))
#define MT6358_BUCK_VCORE_SSHUB_CON1 ((unsigned int)(PMIC_BASE+0x14a6))
#define MT6358_BUCK_VCORE_ELR_NUM  ((unsigned int)(PMIC_BASE+0x14a8))
#define MT6358_BUCK_VCORE_ELR0 ((unsigned int)(PMIC_BASE+0x14aa))
#define MT6358_BUCK_VGPU_DSN_ID   ((unsigned int)(PMIC_BASE+0x1500))
#define MT6358_BUCK_VGPU_DSN_REV0  ((unsigned int)(PMIC_BASE+0x1502))
#define MT6358_BUCK_VGPU_DSN_DBI  ((unsigned int)(PMIC_BASE+0x1504))
#define MT6358_BUCK_VGPU_DSN_DXI  ((unsigned int)(PMIC_BASE+0x1506))
#define MT6358_BUCK_VGPU_CON0  ((unsigned int)(PMIC_BASE+0x1508))
#define MT6358_BUCK_VGPU_CON1  ((unsigned int)(PMIC_BASE+0x150a))
#define MT6358_BUCK_VGPU_CFG0  ((unsigned int)(PMIC_BASE+0x150c))
#define MT6358_BUCK_VGPU_CFG1  ((unsigned int)(PMIC_BASE+0x150e))
#define MT6358_BUCK_VGPU_OP_EN ((unsigned int)(PMIC_BASE+0x1510))
#define MT6358_BUCK_VGPU_OP_EN_SET ((unsigned int)(PMIC_BASE+0x1512))
#define MT6358_BUCK_VGPU_OP_EN_CLR ((unsigned int)(PMIC_BASE+0x1514))
#define MT6358_BUCK_VGPU_OP_CFG   ((unsigned int)(PMIC_BASE+0x1516))
#define MT6358_BUCK_VGPU_OP_CFG_SET  ((unsigned int)(PMIC_BASE+0x1518))
#define MT6358_BUCK_VGPU_OP_CFG_CLR  ((unsigned int)(PMIC_BASE+0x151a))
#define MT6358_BUCK_VGPU_OC_CFG   ((unsigned int)(PMIC_BASE+0x151c))
#define MT6358_BUCK_VGPU_DBG0  ((unsigned int)(PMIC_BASE+0x151e))
#define MT6358_BUCK_VGPU_DBG1  ((unsigned int)(PMIC_BASE+0x1520))
#define MT6358_BUCK_VGPU_DBG2  ((unsigned int)(PMIC_BASE+0x1522))
#define MT6358_BUCK_VGPU_ELR_NUM  ((unsigned int)(PMIC_BASE+0x1524))
#define MT6358_BUCK_VGPU_ELR0  ((unsigned int)(PMIC_BASE+0x1526))
#define MT6358_BUCK_VMODEM_DSN_ID  ((unsigned int)(PMIC_BASE+0x1580))
#define MT6358_BUCK_VMODEM_DSN_REV0  ((unsigned int)(PMIC_BASE+0x1582))
#define MT6358_BUCK_VMODEM_DSN_DBI ((unsigned int)(PMIC_BASE+0x1584))
#define MT6358_BUCK_VMODEM_DSN_DXI ((unsigned int)(PMIC_BASE+0x1586))
#define MT6358_BUCK_VMODEM_CON0   ((unsigned int)(PMIC_BASE+0x1588))
#define MT6358_BUCK_VMODEM_CON1   ((unsigned int)(PMIC_BASE+0x158a))
#define MT6358_BUCK_VMODEM_CFG0   ((unsigned int)(PMIC_BASE+0x158c))
#define MT6358_BUCK_VMODEM_CFG1   ((unsigned int)(PMIC_BASE+0x158e))
#define MT6358_BUCK_VMODEM_OP_EN  ((unsigned int)(PMIC_BASE+0x1590))
#define MT6358_BUCK_VMODEM_OP_EN_SET ((unsigned int)(PMIC_BASE+0x1592))
#define MT6358_BUCK_VMODEM_OP_EN_CLR ((unsigned int)(PMIC_BASE+0x1594))
#define MT6358_BUCK_VMODEM_OP_CFG  ((unsigned int)(PMIC_BASE+0x1596))
#define MT6358_BUCK_VMODEM_OP_CFG_SET   ((unsigned int)(PMIC_BASE+0x1598))
#define MT6358_BUCK_VMODEM_OP_CFG_CLR   ((unsigned int)(PMIC_BASE+0x159a))
#define MT6358_BUCK_VMODEM_OC_CFG  ((unsigned int)(PMIC_BASE+0x159c))
#define MT6358_BUCK_VMODEM_DBG0   ((unsigned int)(PMIC_BASE+0x159e))
#define MT6358_BUCK_VMODEM_DBG1   ((unsigned int)(PMIC_BASE+0x15a0))
#define MT6358_BUCK_VMODEM_DBG2   ((unsigned int)(PMIC_BASE+0x15a2))
#define MT6358_BUCK_VMODEM_ELR_NUM ((unsigned int)(PMIC_BASE+0x15a4))
#define MT6358_BUCK_VMODEM_ELR0   ((unsigned int)(PMIC_BASE+0x15a6))
#define MT6358_BUCK_VDRAM1_DSN_ID  ((unsigned int)(PMIC_BASE+0x1600))
#define MT6358_BUCK_VDRAM1_DSN_REV0  ((unsigned int)(PMIC_BASE+0x1602))
#define MT6358_BUCK_VDRAM1_DSN_DBI ((unsigned int)(PMIC_BASE+0x1604))
#define MT6358_BUCK_VDRAM1_DSN_DXI ((unsigned int)(PMIC_BASE+0x1606))
#define MT6358_BUCK_VDRAM1_CON0   ((unsigned int)(PMIC_BASE+0x1608))
#define MT6358_BUCK_VDRAM1_CON1   ((unsigned int)(PMIC_BASE+0x160a))
#define MT6358_BUCK_VDRAM1_CFG0   ((unsigned int)(PMIC_BASE+0x160c))
#define MT6358_BUCK_VDRAM1_CFG1   ((unsigned int)(PMIC_BASE+0x160e))
#define MT6358_BUCK_VDRAM1_OP_EN  ((unsigned int)(PMIC_BASE+0x1610))
#define MT6358_BUCK_VDRAM1_OP_EN_SET ((unsigned int)(PMIC_BASE+0x1612))
#define MT6358_BUCK_VDRAM1_OP_EN_CLR ((unsigned int)(PMIC_BASE+0x1614))
#define MT6358_BUCK_VDRAM1_OP_CFG  ((unsigned int)(PMIC_BASE+0x1616))
#define MT6358_BUCK_VDRAM1_OP_CFG_SET   ((unsigned int)(PMIC_BASE+0x1618))
#define MT6358_BUCK_VDRAM1_OP_CFG_CLR   ((unsigned int)(PMIC_BASE+0x161a))
#define MT6358_BUCK_VDRAM1_OC_CFG  ((unsigned int)(PMIC_BASE+0x161c))
#define MT6358_BUCK_VDRAM1_DBG0   ((unsigned int)(PMIC_BASE+0x161e))
#define MT6358_BUCK_VDRAM1_DBG1   ((unsigned int)(PMIC_BASE+0x1620))
#define MT6358_BUCK_VDRAM1_DBG2   ((unsigned int)(PMIC_BASE+0x1622))
#define MT6358_BUCK_VDRAM1_ELR_NUM ((unsigned int)(PMIC_BASE+0x1624))
#define MT6358_BUCK_VDRAM1_ELR0   ((unsigned int)(PMIC_BASE+0x1626))
#define MT6358_BUCK_VS1_DSN_ID ((unsigned int)(PMIC_BASE+0x1680))
#define MT6358_BUCK_VS1_DSN_REV0  ((unsigned int)(PMIC_BASE+0x1682))
#define MT6358_BUCK_VS1_DSN_DBI   ((unsigned int)(PMIC_BASE+0x1684))
#define MT6358_BUCK_VS1_DSN_DXI   ((unsigned int)(PMIC_BASE+0x1686))
#define MT6358_BUCK_VS1_CON0 ((unsigned int)(PMIC_BASE+0x1688))
#define MT6358_BUCK_VS1_CON1 ((unsigned int)(PMIC_BASE+0x168a))
#define MT6358_BUCK_VS1_CFG0 ((unsigned int)(PMIC_BASE+0x168c))
#define MT6358_BUCK_VS1_CFG1 ((unsigned int)(PMIC_BASE+0x168e))
#define MT6358_BUCK_VS1_OP_EN  ((unsigned int)(PMIC_BASE+0x1690))
#define MT6358_BUCK_VS1_OP_EN_SET  ((unsigned int)(PMIC_BASE+0x1692))
#define MT6358_BUCK_VS1_OP_EN_CLR  ((unsigned int)(PMIC_BASE+0x1694))
#define MT6358_BUCK_VS1_OP_CFG ((unsigned int)(PMIC_BASE+0x1696))
#define MT6358_BUCK_VS1_OP_CFG_SET ((unsigned int)(PMIC_BASE+0x1698))
#define MT6358_BUCK_VS1_OP_CFG_CLR ((unsigned int)(PMIC_BASE+0x169a))
#define MT6358_BUCK_VS1_OC_CFG ((unsigned int)(PMIC_BASE+0x169c))
#define MT6358_BUCK_VS1_DBG0 ((unsigned int)(PMIC_BASE+0x169e))
#define MT6358_BUCK_VS1_DBG1 ((unsigned int)(PMIC_BASE+0x16a0))
#define MT6358_BUCK_VS1_DBG2 ((unsigned int)(PMIC_BASE+0x16a2))
#define MT6358_BUCK_VS1_VOTER  ((unsigned int)(PMIC_BASE+0x16a4))
#define MT6358_BUCK_VS1_VOTER_SET  ((unsigned int)(PMIC_BASE+0x16a6))
#define MT6358_BUCK_VS1_VOTER_CLR  ((unsigned int)(PMIC_BASE+0x16a8))
#define MT6358_BUCK_VS1_VOTER_CFG  ((unsigned int)(PMIC_BASE+0x16aa))
#define MT6358_BUCK_VS1_ELR_NUM   ((unsigned int)(PMIC_BASE+0x16ac))
#define MT6358_BUCK_VS1_ELR0 ((unsigned int)(PMIC_BASE+0x16ae))
#define MT6358_BUCK_VS2_DSN_ID ((unsigned int)(PMIC_BASE+0x1700))
#define MT6358_BUCK_VS2_DSN_REV0  ((unsigned int)(PMIC_BASE+0x1702))
#define MT6358_BUCK_VS2_DSN_DBI   ((unsigned int)(PMIC_BASE+0x1704))
#define MT6358_BUCK_VS2_DSN_DXI   ((unsigned int)(PMIC_BASE+0x1706))
#define MT6358_BUCK_VS2_CON0 ((unsigned int)(PMIC_BASE+0x1708))
#define MT6358_BUCK_VS2_CON1 ((unsigned int)(PMIC_BASE+0x170a))
#define MT6358_BUCK_VS2_CFG0 ((unsigned int)(PMIC_BASE+0x170c))
#define MT6358_BUCK_VS2_CFG1 ((unsigned int)(PMIC_BASE+0x170e))
#define MT6358_BUCK_VS2_OP_EN  ((unsigned int)(PMIC_BASE+0x1710))
#define MT6358_BUCK_VS2_OP_EN_SET  ((unsigned int)(PMIC_BASE+0x1712))
#define MT6358_BUCK_VS2_OP_EN_CLR  ((unsigned int)(PMIC_BASE+0x1714))
#define MT6358_BUCK_VS2_OP_CFG ((unsigned int)(PMIC_BASE+0x1716))
#define MT6358_BUCK_VS2_OP_CFG_SET ((unsigned int)(PMIC_BASE+0x1718))
#define MT6358_BUCK_VS2_OP_CFG_CLR ((unsigned int)(PMIC_BASE+0x171a))
#define MT6358_BUCK_VS2_OC_CFG ((unsigned int)(PMIC_BASE+0x171c))
#define MT6358_BUCK_VS2_DBG0 ((unsigned int)(PMIC_BASE+0x171e))
#define MT6358_BUCK_VS2_DBG1 ((unsigned int)(PMIC_BASE+0x1720))
#define MT6358_BUCK_VS2_DBG2 ((unsigned int)(PMIC_BASE+0x1722))
#define MT6358_BUCK_VS2_VOTER  ((unsigned int)(PMIC_BASE+0x1724))
#define MT6358_BUCK_VS2_VOTER_SET  ((unsigned int)(PMIC_BASE+0x1726))
#define MT6358_BUCK_VS2_VOTER_CLR  ((unsigned int)(PMIC_BASE+0x1728))
#define MT6358_BUCK_VS2_VOTER_CFG  ((unsigned int)(PMIC_BASE+0x172a))
#define MT6358_BUCK_VS2_ELR_NUM   ((unsigned int)(PMIC_BASE+0x172c))
#define MT6358_BUCK_VS2_ELR0 ((unsigned int)(PMIC_BASE+0x172e))
#define MT6358_BUCK_VPA_DSN_ID ((unsigned int)(PMIC_BASE+0x1780))
#define MT6358_BUCK_VPA_DSN_REV0  ((unsigned int)(PMIC_BASE+0x1782))
#define MT6358_BUCK_VPA_DSN_DBI   ((unsigned int)(PMIC_BASE+0x1784))
#define MT6358_BUCK_VPA_DSN_DXI   ((unsigned int)(PMIC_BASE+0x1786))
#define MT6358_BUCK_VPA_CON0 ((unsigned int)(PMIC_BASE+0x1788))
#define MT6358_BUCK_VPA_CON1 ((unsigned int)(PMIC_BASE+0x178a))
#define MT6358_BUCK_VPA_CFG0 ((unsigned int)(PMIC_BASE+0x178c))
#define MT6358_BUCK_VPA_CFG1 ((unsigned int)(PMIC_BASE+0x178e))
#define MT6358_BUCK_VPA_OC_CFG ((unsigned int)(PMIC_BASE+0x1790))
#define MT6358_BUCK_VPA_DBG0 ((unsigned int)(PMIC_BASE+0x1792))
#define MT6358_BUCK_VPA_DBG1 ((unsigned int)(PMIC_BASE+0x1794))
#define MT6358_BUCK_VPA_DBG2 ((unsigned int)(PMIC_BASE+0x1796))
#define MT6358_BUCK_VPA_DLC_CON0  ((unsigned int)(PMIC_BASE+0x1798))
#define MT6358_BUCK_VPA_DLC_CON1  ((unsigned int)(PMIC_BASE+0x179a))
#define MT6358_BUCK_VPA_DLC_CON2  ((unsigned int)(PMIC_BASE+0x179c))
#define MT6358_BUCK_VPA_MSFG_CON0  ((unsigned int)(PMIC_BASE+0x179e))
#define MT6358_BUCK_VPA_MSFG_CON1  ((unsigned int)(PMIC_BASE+0x17a0))
#define MT6358_BUCK_VPA_MSFG_RRATE0  ((unsigned int)(PMIC_BASE+0x17a2))
#define MT6358_BUCK_VPA_MSFG_RRATE1  ((unsigned int)(PMIC_BASE+0x17a4))
#define MT6358_BUCK_VPA_MSFG_RRATE2  ((unsigned int)(PMIC_BASE+0x17a6))
#define MT6358_BUCK_VPA_MSFG_RTHD0 ((unsigned int)(PMIC_BASE+0x17a8))
#define MT6358_BUCK_VPA_MSFG_RTHD1 ((unsigned int)(PMIC_BASE+0x17aa))
#define MT6358_BUCK_VPA_MSFG_RTHD2 ((unsigned int)(PMIC_BASE+0x17ac))
#define MT6358_BUCK_VPA_MSFG_FRATE0  ((unsigned int)(PMIC_BASE+0x17ae))
#define MT6358_BUCK_VPA_MSFG_FRATE1  ((unsigned int)(PMIC_BASE+0x17b0))
#define MT6358_BUCK_VPA_MSFG_FRATE2  ((unsigned int)(PMIC_BASE+0x17b2))
#define MT6358_BUCK_VPA_MSFG_FTHD0 ((unsigned int)(PMIC_BASE+0x17b4))
#define MT6358_BUCK_VPA_MSFG_FTHD1 ((unsigned int)(PMIC_BASE+0x17b6))
#define MT6358_BUCK_VPA_MSFG_FTHD2 ((unsigned int)(PMIC_BASE+0x17b8))
#define MT6358_BUCK_ANA0_DSN_ID   ((unsigned int)(PMIC_BASE+0x1800))
#define MT6358_BUCK_ANA0_DSN_REV0  ((unsigned int)(PMIC_BASE+0x1802))
#define MT6358_BUCK_ANA0_DSN_DBI  ((unsigned int)(PMIC_BASE+0x1804))
#define MT6358_BUCK_ANA0_DSN_FPI  ((unsigned int)(PMIC_BASE+0x1806))
#define MT6358_SMPS_ANA_CON0 ((unsigned int)(PMIC_BASE+0x1808))
#define MT6358_SMPS_ANA_CON1 ((unsigned int)(PMIC_BASE+0x180a))
#define MT6358_VPROC_ANA_CON0  ((unsigned int)(PMIC_BASE+0x180c))
#define MT6358_VPROC_ANA_CON1  ((unsigned int)(PMIC_BASE+0x180e))
#define MT6358_VPROC_ANA_CON2  ((unsigned int)(PMIC_BASE+0x1810))
#define MT6358_VPROC_ANA_CON3  ((unsigned int)(PMIC_BASE+0x1812))
#define MT6358_VPROC_ANA_CON4  ((unsigned int)(PMIC_BASE+0x1814))
#define MT6358_VPROC_ANA_CON5  ((unsigned int)(PMIC_BASE+0x1816))
#define MT6358_VPROC_ANA_CON6  ((unsigned int)(PMIC_BASE+0x1818))
#define MT6358_VPROC_ANA_CON7  ((unsigned int)(PMIC_BASE+0x181a))
#define MT6358_VPROC_ANA_CON8  ((unsigned int)(PMIC_BASE+0x181c))
#define MT6358_VPROC_ANA_CON9  ((unsigned int)(PMIC_BASE+0x181e))
#define MT6358_VPROC_ANA_CON10 ((unsigned int)(PMIC_BASE+0x1820))
#define MT6358_VPROC_ANA_CON11 ((unsigned int)(PMIC_BASE+0x1822))
#define MT6358_VPROC_ANA_CON12 ((unsigned int)(PMIC_BASE+0x1824))
#define MT6358_VPROC_ANA_CON13 ((unsigned int)(PMIC_BASE+0x1826))
#define MT6358_VCORE_VGPU_ANA_CON0 ((unsigned int)(PMIC_BASE+0x1828))
#define MT6358_VCORE_VGPU_ANA_CON1 ((unsigned int)(PMIC_BASE+0x182a))
#define MT6358_VCORE_VGPU_ANA_CON2 ((unsigned int)(PMIC_BASE+0x182c))
#define MT6358_VCORE_VGPU_ANA_CON3 ((unsigned int)(PMIC_BASE+0x182e))
#define MT6358_VCORE_VGPU_ANA_CON4 ((unsigned int)(PMIC_BASE+0x1830))
#define MT6358_VCORE_VGPU_ANA_CON5 ((unsigned int)(PMIC_BASE+0x1832))
#define MT6358_VCORE_VGPU_ANA_CON6 ((unsigned int)(PMIC_BASE+0x1834))
#define MT6358_VCORE_VGPU_ANA_CON7 ((unsigned int)(PMIC_BASE+0x1836))
#define MT6358_VCORE_VGPU_ANA_CON8 ((unsigned int)(PMIC_BASE+0x1838))
#define MT6358_VCORE_VGPU_ANA_CON9 ((unsigned int)(PMIC_BASE+0x183a))
#define MT6358_VCORE_VGPU_ANA_CON10  ((unsigned int)(PMIC_BASE+0x183c))
#define MT6358_VCORE_VGPU_ANA_CON11  ((unsigned int)(PMIC_BASE+0x183e))
#define MT6358_VCORE_VGPU_ANA_CON12  ((unsigned int)(PMIC_BASE+0x1840))
#define MT6358_VCORE_VGPU_ANA_CON13  ((unsigned int)(PMIC_BASE+0x1842))
#define MT6358_BUCK_ANA0_ELR_NUM  ((unsigned int)(PMIC_BASE+0x1844))
#define MT6358_SMPS_ELR_0   ((unsigned int)(PMIC_BASE+0x1846))
#define MT6358_SMPS_ELR_1   ((unsigned int)(PMIC_BASE+0x1848))
#define MT6358_SMPS_ELR_2   ((unsigned int)(PMIC_BASE+0x184a))
#define MT6358_SMPS_ELR_3   ((unsigned int)(PMIC_BASE+0x184c))
#define MT6358_SMPS_ELR_4   ((unsigned int)(PMIC_BASE+0x184e))
#define MT6358_SMPS_ELR_5   ((unsigned int)(PMIC_BASE+0x1850))
#define MT6358_VPROC_ELR_0   ((unsigned int)(PMIC_BASE+0x1852))
#define MT6358_VPROC_ELR_1   ((unsigned int)(PMIC_BASE+0x1854))
#define MT6358_VPROC_ELR_2   ((unsigned int)(PMIC_BASE+0x1856))
#define MT6358_VPROC_ELR_3   ((unsigned int)(PMIC_BASE+0x1858))
#define MT6358_VCORE_VGPU_ELR_0   ((unsigned int)(PMIC_BASE+0x185a))
#define MT6358_VCORE_VGPU_ELR_1   ((unsigned int)(PMIC_BASE+0x185c))
#define MT6358_VCORE_VGPU_ELR_2   ((unsigned int)(PMIC_BASE+0x185e))
#define MT6358_VCORE_VGPU_ELR_3   ((unsigned int)(PMIC_BASE+0x1860))
#define MT6358_BUCK_ANA1_DSN_ID   ((unsigned int)(PMIC_BASE+0x1880))
#define MT6358_BUCK_ANA1_DSN_REV0  ((unsigned int)(PMIC_BASE+0x1882))
#define MT6358_BUCK_ANA1_DSN_DBI  ((unsigned int)(PMIC_BASE+0x1884))
#define MT6358_BUCK_ANA1_DSN_FPI  ((unsigned int)(PMIC_BASE+0x1886))
#define MT6358_VMODEM_ANA_CON0 ((unsigned int)(PMIC_BASE+0x1888))
#define MT6358_VMODEM_ANA_CON1 ((unsigned int)(PMIC_BASE+0x188a))
#define MT6358_VMODEM_ANA_CON2 ((unsigned int)(PMIC_BASE+0x188c))
#define MT6358_VMODEM_ANA_CON3 ((unsigned int)(PMIC_BASE+0x188e))
#define MT6358_VMODEM_ANA_CON4 ((unsigned int)(PMIC_BASE+0x1890))
#define MT6358_VMODEM_ANA_CON5 ((unsigned int)(PMIC_BASE+0x1892))
#define MT6358_VMODEM_ANA_CON6 ((unsigned int)(PMIC_BASE+0x1894))
#define MT6358_VDRAM1_ANA_CON0 ((unsigned int)(PMIC_BASE+0x1896))
#define MT6358_VDRAM1_ANA_CON1 ((unsigned int)(PMIC_BASE+0x1898))
#define MT6358_VDRAM1_ANA_CON2 ((unsigned int)(PMIC_BASE+0x189a))
#define MT6358_VDRAM1_ANA_CON3 ((unsigned int)(PMIC_BASE+0x189c))
#define MT6358_VDRAM1_ANA_CON4 ((unsigned int)(PMIC_BASE+0x189e))
#define MT6358_VDRAM1_ANA_CON5 ((unsigned int)(PMIC_BASE+0x18a0))
#define MT6358_VS1_ANA_CON0  ((unsigned int)(PMIC_BASE+0x18a2))
#define MT6358_VS1_ANA_CON1  ((unsigned int)(PMIC_BASE+0x18a4))
#define MT6358_VS1_ANA_CON2  ((unsigned int)(PMIC_BASE+0x18a6))
#define MT6358_VS1_ANA_CON3  ((unsigned int)(PMIC_BASE+0x18a8))
#define MT6358_VS1_ANA_CON4  ((unsigned int)(PMIC_BASE+0x18aa))
#define MT6358_VS1_ANA_CON5  ((unsigned int)(PMIC_BASE+0x18ac))
#define MT6358_VS2_ANA_CON0  ((unsigned int)(PMIC_BASE+0x18ae))
#define MT6358_VS2_ANA_CON1  ((unsigned int)(PMIC_BASE+0x18b0))
#define MT6358_VS2_ANA_CON2  ((unsigned int)(PMIC_BASE+0x18b2))
#define MT6358_VS2_ANA_CON3  ((unsigned int)(PMIC_BASE+0x18b4))
#define MT6358_VS2_ANA_CON4  ((unsigned int)(PMIC_BASE+0x18b6))
#define MT6358_VS2_ANA_CON5  ((unsigned int)(PMIC_BASE+0x18b8))
#define MT6358_VPA_ANA_CON0  ((unsigned int)(PMIC_BASE+0x18ba))
#define MT6358_VPA_ANA_CON1  ((unsigned int)(PMIC_BASE+0x18bc))
#define MT6358_VPA_ANA_CON2  ((unsigned int)(PMIC_BASE+0x18be))
#define MT6358_VPA_ANA_CON3  ((unsigned int)(PMIC_BASE+0x18c0))
#define MT6358_VPA_ANA_CON4  ((unsigned int)(PMIC_BASE+0x18c2))
#define MT6358_VPA_ANA_CON5  ((unsigned int)(PMIC_BASE+0x18c4))
#define MT6358_BUCK_ANA1_ELR_NUM  ((unsigned int)(PMIC_BASE+0x18c6))
#define MT6358_VMODEM_ELR_0  ((unsigned int)(PMIC_BASE+0x18c8))
#define MT6358_VMODEM_ELR_1  ((unsigned int)(PMIC_BASE+0x18ca))
#define MT6358_VDRAM1_ELR_0  ((unsigned int)(PMIC_BASE+0x18cc))
#define MT6358_VDRAM1_ELR_1  ((unsigned int)(PMIC_BASE+0x18ce))
#define MT6358_VS1_ELR_0 ((unsigned int)(PMIC_BASE+0x18d0))
#define MT6358_VS1_ELR_1 ((unsigned int)(PMIC_BASE+0x18d2))
#define MT6358_VS2_ELR_0 ((unsigned int)(PMIC_BASE+0x18d4))
#define MT6358_VS2_ELR_1 ((unsigned int)(PMIC_BASE+0x18d6))
#define MT6358_VPA_ELR_0 ((unsigned int)(PMIC_BASE+0x18d8))
#define MT6358_LDO_TOP_ID   ((unsigned int)(PMIC_BASE+0x1a00))
#define MT6358_LDO_TOP_REV0  ((unsigned int)(PMIC_BASE+0x1a02))
#define MT6358_LDO_TOP_DBI   ((unsigned int)(PMIC_BASE+0x1a04))
#define MT6358_LDO_TOP_DXI   ((unsigned int)(PMIC_BASE+0x1a06))
#define MT6358_LDO_TPM0  ((unsigned int)(PMIC_BASE+0x1a08))
#define MT6358_LDO_TPM1  ((unsigned int)(PMIC_BASE+0x1a0a))
#define MT6358_LDO_TOP_CKPDN_CON0  ((unsigned int)(PMIC_BASE+0x1a0c))
#define MT6358_TOP_TOP_CKHWEN_CON0 ((unsigned int)(PMIC_BASE+0x1a0e))
#define MT6358_LDO_TOP_CLK_DCM_CON0  ((unsigned int)(PMIC_BASE+0x1a10))
#define MT6358_LDO_TOP_CLK_VFE28_CON0   ((unsigned int)(PMIC_BASE+0x1a12))
#define MT6358_LDO_TOP_CLK_VXO22_CON0   ((unsigned int)(PMIC_BASE+0x1a14))
#define MT6358_LDO_TOP_CLK_VRF18_CON0   ((unsigned int)(PMIC_BASE+0x1a16))
#define MT6358_LDO_TOP_CLK_VRF12_CON0   ((unsigned int)(PMIC_BASE+0x1a18))
#define MT6358_LDO_TOP_CLK_VEFUSE_CON0  ((unsigned int)(PMIC_BASE+0x1a1a))
#define MT6358_LDO_TOP_CLK_VCN33_CON0   ((unsigned int)(PMIC_BASE+0x1a1c))
#define MT6358_LDO_TOP_CLK_VCN28_CON0   ((unsigned int)(PMIC_BASE+0x1a1e))
#define MT6358_LDO_TOP_CLK_VCN18_CON0   ((unsigned int)(PMIC_BASE+0x1a20))
#define MT6358_LDO_TOP_CLK_VCAMA1_CON0  ((unsigned int)(PMIC_BASE+0x1a22))
#define MT6358_LDO_TOP_CLK_VCAMA2_CON0  ((unsigned int)(PMIC_BASE+0x1a24))
#define MT6358_LDO_TOP_CLK_VCAMD_CON0   ((unsigned int)(PMIC_BASE+0x1a26))
#define MT6358_LDO_TOP_CLK_VCAMIO_CON0  ((unsigned int)(PMIC_BASE+0x1a28))
#define MT6358_LDO_TOP_CLK_VLDO28_CON0  ((unsigned int)(PMIC_BASE+0x1a2a))
#define MT6358_LDO_TOP_CLK_VA12_CON0 ((unsigned int)(PMIC_BASE+0x1a2c))
#define MT6358_LDO_TOP_CLK_VAUX18_CON0  ((unsigned int)(PMIC_BASE+0x1a2e))
#define MT6358_LDO_TOP_CLK_VAUD28_CON0  ((unsigned int)(PMIC_BASE+0x1a30))
#define MT6358_LDO_TOP_CLK_VIO28_CON0   ((unsigned int)(PMIC_BASE+0x1a32))
#define MT6358_LDO_TOP_CLK_VIO18_CON0   ((unsigned int)(PMIC_BASE+0x1a34))
#define MT6358_LDO_TOP_CLK_VSRAM_PROC11_CON0  ((unsigned int)(PMIC_BASE+0x1a36))
#define MT6358_LDO_TOP_CLK_VSRAM_PROC12_CON0  ((unsigned int)(PMIC_BASE+0x1a38))
#define MT6358_LDO_TOP_CLK_VSRAM_OTHERS_CON0  ((unsigned int)(PMIC_BASE+0x1a3a))
#define MT6358_LDO_TOP_CLK_VSRAM_GPU_CON0  ((unsigned int)(PMIC_BASE+0x1a3c))
#define MT6358_LDO_TOP_CLK_VDRAM2_CON0  ((unsigned int)(PMIC_BASE+0x1a3e))
#define MT6358_LDO_TOP_CLK_VMC_CON0  ((unsigned int)(PMIC_BASE+0x1a40))
#define MT6358_LDO_TOP_CLK_VMCH_CON0 ((unsigned int)(PMIC_BASE+0x1a42))
#define MT6358_LDO_TOP_CLK_VEMC_CON0 ((unsigned int)(PMIC_BASE+0x1a44))
#define MT6358_LDO_TOP_CLK_VSIM1_CON0   ((unsigned int)(PMIC_BASE+0x1a46))
#define MT6358_LDO_TOP_CLK_VSIM2_CON0   ((unsigned int)(PMIC_BASE+0x1a48))
#define MT6358_LDO_TOP_CLK_VIBR_CON0 ((unsigned int)(PMIC_BASE+0x1a4a))
#define MT6358_LDO_TOP_CLK_VUSB_CON0 ((unsigned int)(PMIC_BASE+0x1a4c))
#define MT6358_LDO_TOP_CLK_VBIF28_CON0  ((unsigned int)(PMIC_BASE+0x1a4e))
#define MT6358_LDO_TOP_INT_CON0   ((unsigned int)(PMIC_BASE+0x1a50))
#define MT6358_LDO_TOP_INT_CON0_SET  ((unsigned int)(PMIC_BASE+0x1a52))
#define MT6358_LDO_TOP_INT_CON0_CLR  ((unsigned int)(PMIC_BASE+0x1a54))
#define MT6358_LDO_TOP_INT_CON1   ((unsigned int)(PMIC_BASE+0x1a56))
#define MT6358_LDO_TOP_INT_CON1_SET  ((unsigned int)(PMIC_BASE+0x1a58))
#define MT6358_LDO_TOP_INT_CON1_CLR  ((unsigned int)(PMIC_BASE+0x1a5a))
#define MT6358_LDO_TOP_INT_MASK_CON0 ((unsigned int)(PMIC_BASE+0x1a5c))
#define MT6358_LDO_TOP_INT_MASK_CON0_SET ((unsigned int)(PMIC_BASE+0x1a5e))
#define MT6358_LDO_TOP_INT_MASK_CON0_CLR ((unsigned int)(PMIC_BASE+0x1a60))
#define MT6358_LDO_TOP_INT_MASK_CON1 ((unsigned int)(PMIC_BASE+0x1a62))
#define MT6358_LDO_TOP_INT_MASK_CON1_SET ((unsigned int)(PMIC_BASE+0x1a64))
#define MT6358_LDO_TOP_INT_MASK_CON1_CLR ((unsigned int)(PMIC_BASE+0x1a66))
#define MT6358_LDO_TOP_INT_STATUS0 ((unsigned int)(PMIC_BASE+0x1a68))
#define MT6358_LDO_TOP_INT_STATUS1 ((unsigned int)(PMIC_BASE+0x1a6a))
#define MT6358_LDO_TOP_INT_RAW_STATUS0  ((unsigned int)(PMIC_BASE+0x1a6c))
#define MT6358_LDO_TOP_INT_RAW_STATUS1  ((unsigned int)(PMIC_BASE+0x1a6e))
#define MT6358_LDO_TEST_CON0 ((unsigned int)(PMIC_BASE+0x1a70))
#define MT6358_LDO_TOP_WDT_CON0   ((unsigned int)(PMIC_BASE+0x1a72))
#define MT6358_LDO_TOP_RSV_CON0   ((unsigned int)(PMIC_BASE+0x1a74))
#define MT6358_LDO_TOP_RSV_CON1   ((unsigned int)(PMIC_BASE+0x1a76))
#define MT6358_LDO_OCFB0 ((unsigned int)(PMIC_BASE+0x1a78))
#define MT6358_LDO_LP_PROTECTION  ((unsigned int)(PMIC_BASE+0x1a7a))
#define MT6358_LDO_DUMMY_LOAD_GATED  ((unsigned int)(PMIC_BASE+0x1a7c))
#define MT6358_LDO_GON0_DSN_ID ((unsigned int)(PMIC_BASE+0x1a80))
#define MT6358_LDO_GON0_DSN_REV0  ((unsigned int)(PMIC_BASE+0x1a82))
#define MT6358_LDO_GON0_DSN_DBI   ((unsigned int)(PMIC_BASE+0x1a84))
#define MT6358_LDO_GON0_DSN_DXI   ((unsigned int)(PMIC_BASE+0x1a86))
#define MT6358_LDO_VXO22_CON0  ((unsigned int)(PMIC_BASE+0x1a88))
#define MT6358_LDO_VXO22_OP_EN ((unsigned int)(PMIC_BASE+0x1a8a))
#define MT6358_LDO_VXO22_OP_EN_SET ((unsigned int)(PMIC_BASE+0x1a8c))
#define MT6358_LDO_VXO22_OP_EN_CLR ((unsigned int)(PMIC_BASE+0x1a8e))
#define MT6358_LDO_VXO22_OP_CFG   ((unsigned int)(PMIC_BASE+0x1a90))
#define MT6358_LDO_VXO22_OP_CFG_SET  ((unsigned int)(PMIC_BASE+0x1a92))
#define MT6358_LDO_VXO22_OP_CFG_CLR  ((unsigned int)(PMIC_BASE+0x1a94))
#define MT6358_LDO_VXO22_CON1  ((unsigned int)(PMIC_BASE+0x1a96))
#define MT6358_LDO_VXO22_CON2  ((unsigned int)(PMIC_BASE+0x1a98))
#define MT6358_LDO_VXO22_CON3  ((unsigned int)(PMIC_BASE+0x1a9a))
#define MT6358_LDO_VA12_CON0 ((unsigned int)(PMIC_BASE+0x1a9c))
#define MT6358_LDO_VA12_OP_EN  ((unsigned int)(PMIC_BASE+0x1a9e))
#define MT6358_LDO_VA12_OP_EN_SET  ((unsigned int)(PMIC_BASE+0x1aa0))
#define MT6358_LDO_VA12_OP_EN_CLR  ((unsigned int)(PMIC_BASE+0x1aa2))
#define MT6358_LDO_VA12_OP_CFG ((unsigned int)(PMIC_BASE+0x1aa4))
#define MT6358_LDO_VA12_OP_CFG_SET ((unsigned int)(PMIC_BASE+0x1aa6))
#define MT6358_LDO_VA12_OP_CFG_CLR ((unsigned int)(PMIC_BASE+0x1aa8))
#define MT6358_LDO_VA12_CON1 ((unsigned int)(PMIC_BASE+0x1aaa))
#define MT6358_LDO_VA12_CON2 ((unsigned int)(PMIC_BASE+0x1aac))
#define MT6358_LDO_VA12_CON3 ((unsigned int)(PMIC_BASE+0x1aae))
#define MT6358_LDO_VAUX18_CON0 ((unsigned int)(PMIC_BASE+0x1ab0))
#define MT6358_LDO_VAUX18_OP_EN   ((unsigned int)(PMIC_BASE+0x1ab2))
#define MT6358_LDO_VAUX18_OP_EN_SET  ((unsigned int)(PMIC_BASE+0x1ab4))
#define MT6358_LDO_VAUX18_OP_EN_CLR  ((unsigned int)(PMIC_BASE+0x1ab6))
#define MT6358_LDO_VAUX18_OP_CFG  ((unsigned int)(PMIC_BASE+0x1ab8))
#define MT6358_LDO_VAUX18_OP_CFG_SET ((unsigned int)(PMIC_BASE+0x1aba))
#define MT6358_LDO_VAUX18_OP_CFG_CLR ((unsigned int)(PMIC_BASE+0x1abc))
#define MT6358_LDO_VAUX18_CON1 ((unsigned int)(PMIC_BASE+0x1abe))
#define MT6358_LDO_VAUX18_CON2 ((unsigned int)(PMIC_BASE+0x1ac0))
#define MT6358_LDO_VAUX18_CON3 ((unsigned int)(PMIC_BASE+0x1ac2))
#define MT6358_LDO_VAUD28_CON0 ((unsigned int)(PMIC_BASE+0x1ac4))
#define MT6358_LDO_VAUD28_OP_EN   ((unsigned int)(PMIC_BASE+0x1ac6))
#define MT6358_LDO_VAUD28_OP_EN_SET  ((unsigned int)(PMIC_BASE+0x1ac8))
#define MT6358_LDO_VAUD28_OP_EN_CLR  ((unsigned int)(PMIC_BASE+0x1aca))
#define MT6358_LDO_VAUD28_OP_CFG  ((unsigned int)(PMIC_BASE+0x1acc))
#define MT6358_LDO_VAUD28_OP_CFG_SET ((unsigned int)(PMIC_BASE+0x1ace))
#define MT6358_LDO_VAUD28_OP_CFG_CLR ((unsigned int)(PMIC_BASE+0x1ad0))
#define MT6358_LDO_VAUD28_CON1 ((unsigned int)(PMIC_BASE+0x1ad2))
#define MT6358_LDO_VAUD28_CON2 ((unsigned int)(PMIC_BASE+0x1ad4))
#define MT6358_LDO_VAUD28_CON3 ((unsigned int)(PMIC_BASE+0x1ad6))
#define MT6358_LDO_VIO28_CON0  ((unsigned int)(PMIC_BASE+0x1ad8))
#define MT6358_LDO_VIO28_OP_EN ((unsigned int)(PMIC_BASE+0x1ada))
#define MT6358_LDO_VIO28_OP_EN_SET ((unsigned int)(PMIC_BASE+0x1adc))
#define MT6358_LDO_VIO28_OP_EN_CLR ((unsigned int)(PMIC_BASE+0x1ade))
#define MT6358_LDO_VIO28_OP_CFG   ((unsigned int)(PMIC_BASE+0x1ae0))
#define MT6358_LDO_VIO28_OP_CFG_SET  ((unsigned int)(PMIC_BASE+0x1ae2))
#define MT6358_LDO_VIO28_OP_CFG_CLR  ((unsigned int)(PMIC_BASE+0x1ae4))
#define MT6358_LDO_VIO28_CON1  ((unsigned int)(PMIC_BASE+0x1ae6))
#define MT6358_LDO_VIO28_CON2  ((unsigned int)(PMIC_BASE+0x1ae8))
#define MT6358_LDO_VIO28_CON3  ((unsigned int)(PMIC_BASE+0x1aea))
#define MT6358_LDO_VIO18_CON0  ((unsigned int)(PMIC_BASE+0x1aec))
#define MT6358_LDO_VIO18_OP_EN ((unsigned int)(PMIC_BASE+0x1aee))
#define MT6358_LDO_VIO18_OP_EN_SET ((unsigned int)(PMIC_BASE+0x1af0))
#define MT6358_LDO_VIO18_OP_EN_CLR ((unsigned int)(PMIC_BASE+0x1af2))
#define MT6358_LDO_VIO18_OP_CFG   ((unsigned int)(PMIC_BASE+0x1af4))
#define MT6358_LDO_VIO18_OP_CFG_SET  ((unsigned int)(PMIC_BASE+0x1af6))
#define MT6358_LDO_VIO18_OP_CFG_CLR  ((unsigned int)(PMIC_BASE+0x1af8))
#define MT6358_LDO_VIO18_CON1  ((unsigned int)(PMIC_BASE+0x1afa))
#define MT6358_LDO_VIO18_CON2  ((unsigned int)(PMIC_BASE+0x1afc))
#define MT6358_LDO_VIO18_CON3  ((unsigned int)(PMIC_BASE+0x1afe))
#define MT6358_LDO_GON1_DSN_ID ((unsigned int)(PMIC_BASE+0x1b00))
#define MT6358_LDO_GON1_DSN_REV0  ((unsigned int)(PMIC_BASE+0x1b02))
#define MT6358_LDO_GON1_DSN_DBI   ((unsigned int)(PMIC_BASE+0x1b04))
#define MT6358_LDO_GON1_DSN_DXI   ((unsigned int)(PMIC_BASE+0x1b06))
#define MT6358_LDO_VDRAM2_CON0 ((unsigned int)(PMIC_BASE+0x1b08))
#define MT6358_LDO_VDRAM2_OP_EN   ((unsigned int)(PMIC_BASE+0x1b0a))
#define MT6358_LDO_VDRAM2_OP_EN_SET  ((unsigned int)(PMIC_BASE+0x1b0c))
#define MT6358_LDO_VDRAM2_OP_EN_CLR  ((unsigned int)(PMIC_BASE+0x1b0e))
#define MT6358_LDO_VDRAM2_OP_CFG  ((unsigned int)(PMIC_BASE+0x1b10))
#define MT6358_LDO_VDRAM2_OP_CFG_SET ((unsigned int)(PMIC_BASE+0x1b12))
#define MT6358_LDO_VDRAM2_OP_CFG_CLR ((unsigned int)(PMIC_BASE+0x1b14))
#define MT6358_LDO_VDRAM2_CON1 ((unsigned int)(PMIC_BASE+0x1b16))
#define MT6358_LDO_VDRAM2_CON2 ((unsigned int)(PMIC_BASE+0x1b18))
#define MT6358_LDO_VDRAM2_CON3 ((unsigned int)(PMIC_BASE+0x1b1a))
#define MT6358_LDO_VEMC_CON0 ((unsigned int)(PMIC_BASE+0x1b1c))
#define MT6358_LDO_VEMC_OP_EN  ((unsigned int)(PMIC_BASE+0x1b1e))
#define MT6358_LDO_VEMC_OP_EN_SET  ((unsigned int)(PMIC_BASE+0x1b20))
#define MT6358_LDO_VEMC_OP_EN_CLR  ((unsigned int)(PMIC_BASE+0x1b22))
#define MT6358_LDO_VEMC_OP_CFG ((unsigned int)(PMIC_BASE+0x1b24))
#define MT6358_LDO_VEMC_OP_CFG_SET ((unsigned int)(PMIC_BASE+0x1b26))
#define MT6358_LDO_VEMC_OP_CFG_CLR ((unsigned int)(PMIC_BASE+0x1b28))
#define MT6358_LDO_VEMC_CON1 ((unsigned int)(PMIC_BASE+0x1b2a))
#define MT6358_LDO_VEMC_CON2 ((unsigned int)(PMIC_BASE+0x1b2c))
#define MT6358_LDO_VEMC_CON3 ((unsigned int)(PMIC_BASE+0x1b2e))
#define MT6358_LDO_VUSB_CON0_0 ((unsigned int)(PMIC_BASE+0x1b30))
#define MT6358_LDO_VUSB_OP_EN  ((unsigned int)(PMIC_BASE+0x1b32))
#define MT6358_LDO_VUSB_OP_EN_SET  ((unsigned int)(PMIC_BASE+0x1b34))
#define MT6358_LDO_VUSB_OP_EN_CLR  ((unsigned int)(PMIC_BASE+0x1b36))
#define MT6358_LDO_VUSB_OP_CFG ((unsigned int)(PMIC_BASE+0x1b38))
#define MT6358_LDO_VUSB_OP_CFG_SET ((unsigned int)(PMIC_BASE+0x1b3a))
#define MT6358_LDO_VUSB_OP_CFG_CLR ((unsigned int)(PMIC_BASE+0x1b3c))
#define MT6358_LDO_VUSB_CON0_1 ((unsigned int)(PMIC_BASE+0x1b3e))
#define MT6358_LDO_VUSB_CON1 ((unsigned int)(PMIC_BASE+0x1b40))
#define MT6358_LDO_VUSB_CON2 ((unsigned int)(PMIC_BASE+0x1b42))
#define MT6358_LDO_VUSB_CON3 ((unsigned int)(PMIC_BASE+0x1b44))
#define MT6358_LDO_VSRAM_PROC11_CON0 ((unsigned int)(PMIC_BASE+0x1b46))
#define MT6358_LDO_VSRAM_PROC11_CON2 ((unsigned int)(PMIC_BASE+0x1b48))
#define MT6358_LDO_VSRAM_PROC11_CFG0 ((unsigned int)(PMIC_BASE+0x1b4a))
#define MT6358_LDO_VSRAM_PROC11_CFG1 ((unsigned int)(PMIC_BASE+0x1b4c))
#define MT6358_LDO_VSRAM_PROC11_OP_EN   ((unsigned int)(PMIC_BASE+0x1b4e))
#define MT6358_LDO_VSRAM_PROC11_OP_EN_SET  ((unsigned int)(PMIC_BASE+0x1b50))
#define MT6358_LDO_VSRAM_PROC11_OP_EN_CLR  ((unsigned int)(PMIC_BASE+0x1b52))
#define MT6358_LDO_VSRAM_PROC11_OP_CFG  ((unsigned int)(PMIC_BASE+0x1b54))
#define MT6358_LDO_VSRAM_PROC11_OP_CFG_SET ((unsigned int)(PMIC_BASE+0x1b56))
#define MT6358_LDO_VSRAM_PROC11_OP_CFG_CLR ((unsigned int)(PMIC_BASE+0x1b58))
#define MT6358_LDO_VSRAM_PROC11_CON3 ((unsigned int)(PMIC_BASE+0x1b5a))
#define MT6358_LDO_VSRAM_PROC11_CON4 ((unsigned int)(PMIC_BASE+0x1b5c))
#define MT6358_LDO_VSRAM_PROC11_CON5 ((unsigned int)(PMIC_BASE+0x1b5e))
#define MT6358_LDO_VSRAM_PROC11_DBG0 ((unsigned int)(PMIC_BASE+0x1b60))
#define MT6358_LDO_VSRAM_PROC11_DBG1 ((unsigned int)(PMIC_BASE+0x1b62))
#define MT6358_LDO_VSRAM_PROC11_TRACKING_CON0 ((unsigned int)(PMIC_BASE+0x1b64))
#define MT6358_LDO_VSRAM_PROC11_TRACKING_CON1 ((unsigned int)(PMIC_BASE+0x1b66))
#define MT6358_LDO_VSRAM_PROC11_TRACKING_CON2 ((unsigned int)(PMIC_BASE+0x1b68))
#define MT6358_LDO_VSRAM_PROC11_TRACKING_CON3 ((unsigned int)(PMIC_BASE+0x1b6a))
#define MT6358_LDO_VSRAM_PROC12_TRACKING_CON0 ((unsigned int)(PMIC_BASE+0x1b6c))
#define MT6358_LDO_VSRAM_PROC12_TRACKING_CON1 ((unsigned int)(PMIC_BASE+0x1b6e))
#define MT6358_LDO_VSRAM_PROC12_TRACKING_CON2 ((unsigned int)(PMIC_BASE+0x1b70))
#define MT6358_LDO_VSRAM_PROC12_TRACKING_CON3 ((unsigned int)(PMIC_BASE+0x1b72))
#define MT6358_LDO_VSRAM_WAKEUP_CON0 ((unsigned int)(PMIC_BASE+0x1b74))
#define MT6358_LDO_GON1_ELR_NUM   ((unsigned int)(PMIC_BASE+0x1b76))
#define MT6358_LDO_VDRAM2_ELR0 ((unsigned int)(PMIC_BASE+0x1b78))
#define MT6358_LDO_VDRAM2_ELR1 ((unsigned int)(PMIC_BASE+0x1b7a))
#define MT6358_LDO_STRUP_ELR0  ((unsigned int)(PMIC_BASE+0x1b7c))
#define MT6358_LDO_GON2_DSN_ID ((unsigned int)(PMIC_BASE+0x1b80))
#define MT6358_LDO_GON2_DSN_REV0  ((unsigned int)(PMIC_BASE+0x1b82))
#define MT6358_LDO_GON2_DSN_DBI   ((unsigned int)(PMIC_BASE+0x1b84))
#define MT6358_LDO_GON2_DSN_DXI   ((unsigned int)(PMIC_BASE+0x1b86))
#define MT6358_LDO_VSRAM_PROC12_CON0 ((unsigned int)(PMIC_BASE+0x1b88))
#define MT6358_LDO_VSRAM_PROC12_CON2 ((unsigned int)(PMIC_BASE+0x1b8a))
#define MT6358_LDO_VSRAM_PROC12_CFG0 ((unsigned int)(PMIC_BASE+0x1b8c))
#define MT6358_LDO_VSRAM_PROC12_CFG1 ((unsigned int)(PMIC_BASE+0x1b8e))
#define MT6358_LDO_VSRAM_PROC12_OP_EN   ((unsigned int)(PMIC_BASE+0x1b90))
#define MT6358_LDO_VSRAM_PROC12_OP_EN_SET  ((unsigned int)(PMIC_BASE+0x1b92))
#define MT6358_LDO_VSRAM_PROC12_OP_EN_CLR  ((unsigned int)(PMIC_BASE+0x1b94))
#define MT6358_LDO_VSRAM_PROC12_OP_CFG  ((unsigned int)(PMIC_BASE+0x1b96))
#define MT6358_LDO_VSRAM_PROC12_OP_CFG_SET ((unsigned int)(PMIC_BASE+0x1b98))
#define MT6358_LDO_VSRAM_PROC12_OP_CFG_CLR ((unsigned int)(PMIC_BASE+0x1b9a))
#define MT6358_LDO_VSRAM_PROC12_CON3 ((unsigned int)(PMIC_BASE+0x1b9c))
#define MT6358_LDO_VSRAM_PROC12_CON4 ((unsigned int)(PMIC_BASE+0x1b9e))
#define MT6358_LDO_VSRAM_PROC12_CON5 ((unsigned int)(PMIC_BASE+0x1ba0))
#define MT6358_LDO_VSRAM_PROC12_DBG0 ((unsigned int)(PMIC_BASE+0x1ba2))
#define MT6358_LDO_VSRAM_PROC12_DBG1 ((unsigned int)(PMIC_BASE+0x1ba4))
#define MT6358_LDO_VSRAM_OTHERS_CON0 ((unsigned int)(PMIC_BASE+0x1ba6))
#define MT6358_LDO_VSRAM_OTHERS_CON2 ((unsigned int)(PMIC_BASE+0x1ba8))
#define MT6358_LDO_VSRAM_OTHERS_CFG0 ((unsigned int)(PMIC_BASE+0x1baa))
#define MT6358_LDO_VSRAM_OTHERS_CFG1 ((unsigned int)(PMIC_BASE+0x1bac))
#define MT6358_LDO_VSRAM_OTHERS_OP_EN   ((unsigned int)(PMIC_BASE+0x1bae))
#define MT6358_LDO_VSRAM_OTHERS_OP_EN_SET  ((unsigned int)(PMIC_BASE+0x1bb0))
#define MT6358_LDO_VSRAM_OTHERS_OP_EN_CLR  ((unsigned int)(PMIC_BASE+0x1bb2))
#define MT6358_LDO_VSRAM_OTHERS_OP_CFG  ((unsigned int)(PMIC_BASE+0x1bb4))
#define MT6358_LDO_VSRAM_OTHERS_OP_CFG_SET ((unsigned int)(PMIC_BASE+0x1bb6))
#define MT6358_LDO_VSRAM_OTHERS_OP_CFG_CLR ((unsigned int)(PMIC_BASE+0x1bb8))
#define MT6358_LDO_VSRAM_OTHERS_CON3 ((unsigned int)(PMIC_BASE+0x1bba))
#define MT6358_LDO_VSRAM_OTHERS_CON4 ((unsigned int)(PMIC_BASE+0x1bbc))
#define MT6358_LDO_VSRAM_OTHERS_CON5 ((unsigned int)(PMIC_BASE+0x1bbe))
#define MT6358_LDO_VSRAM_OTHERS_DBG0 ((unsigned int)(PMIC_BASE+0x1bc0))
#define MT6358_LDO_VSRAM_OTHERS_DBG1 ((unsigned int)(PMIC_BASE+0x1bc2))
#define MT6358_LDO_VSRAM_OTHERS_SSHUB_CON0 ((unsigned int)(PMIC_BASE+0x1bc4))
#define MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1 ((unsigned int)(PMIC_BASE+0x1bc6))
#define MT6358_LDO_VSRAM_GPU_CON0  ((unsigned int)(PMIC_BASE+0x1bc8))
#define MT6358_LDO_VSRAM_GPU_CON2  ((unsigned int)(PMIC_BASE+0x1bca))
#define MT6358_LDO_VSRAM_GPU_CFG0  ((unsigned int)(PMIC_BASE+0x1bcc))
#define MT6358_LDO_VSRAM_GPU_CFG1  ((unsigned int)(PMIC_BASE+0x1bce))
#define MT6358_LDO_VSRAM_GPU_OP_EN ((unsigned int)(PMIC_BASE+0x1bd0))
#define MT6358_LDO_VSRAM_GPU_OP_EN_SET  ((unsigned int)(PMIC_BASE+0x1bd2))
#define MT6358_LDO_VSRAM_GPU_OP_EN_CLR  ((unsigned int)(PMIC_BASE+0x1bd4))
#define MT6358_LDO_VSRAM_GPU_OP_CFG  ((unsigned int)(PMIC_BASE+0x1bd6))
#define MT6358_LDO_VSRAM_GPU_OP_CFG_SET ((unsigned int)(PMIC_BASE+0x1bd8))
#define MT6358_LDO_VSRAM_GPU_OP_CFG_CLR ((unsigned int)(PMIC_BASE+0x1bda))
#define MT6358_LDO_VSRAM_GPU_CON3  ((unsigned int)(PMIC_BASE+0x1bdc))
#define MT6358_LDO_VSRAM_GPU_CON4  ((unsigned int)(PMIC_BASE+0x1bde))
#define MT6358_LDO_VSRAM_GPU_CON5  ((unsigned int)(PMIC_BASE+0x1be0))
#define MT6358_LDO_VSRAM_GPU_DBG0  ((unsigned int)(PMIC_BASE+0x1be2))
#define MT6358_LDO_VSRAM_GPU_DBG1  ((unsigned int)(PMIC_BASE+0x1be4))
#define MT6358_LDO_VSRAM_R2R_PDN_DIS ((unsigned int)(PMIC_BASE+0x1be6))
#define MT6358_LDO_VSRAM_WDT_DBG0  ((unsigned int)(PMIC_BASE+0x1be8))
#define MT6358_LDO_VSRAM_WDT_DBG1  ((unsigned int)(PMIC_BASE+0x1bea))
#define MT6358_LDO_GON2_ELR_NUM   ((unsigned int)(PMIC_BASE+0x1bec))
#define MT6358_LDO_VSRAM_CON0  ((unsigned int)(PMIC_BASE+0x1bee))
#define MT6358_LDO_VSRAM_CON1  ((unsigned int)(PMIC_BASE+0x1bf0))
#define MT6358_LDO_VSRAM_CON2  ((unsigned int)(PMIC_BASE+0x1bf2))
#define MT6358_LDO_VSRAM_CON3  ((unsigned int)(PMIC_BASE+0x1bf4))
#define MT6358_LDO_VSRAM_CON4  ((unsigned int)(PMIC_BASE+0x1bf6))
#define MT6358_LDO_GOFF0_DSN_ID   ((unsigned int)(PMIC_BASE+0x1c00))
#define MT6358_LDO_GOFF0_DSN_REV0  ((unsigned int)(PMIC_BASE+0x1c02))
#define MT6358_LDO_GOFF0_DSN_DBI  ((unsigned int)(PMIC_BASE+0x1c04))
#define MT6358_LDO_GOFF0_DSN_DXI  ((unsigned int)(PMIC_BASE+0x1c06))
#define MT6358_LDO_VFE28_CON0  ((unsigned int)(PMIC_BASE+0x1c08))
#define MT6358_LDO_VFE28_OP_EN ((unsigned int)(PMIC_BASE+0x1c0a))
#define MT6358_LDO_VFE28_OP_EN_SET ((unsigned int)(PMIC_BASE+0x1c0c))
#define MT6358_LDO_VFE28_OP_EN_CLR ((unsigned int)(PMIC_BASE+0x1c0e))
#define MT6358_LDO_VFE28_OP_CFG   ((unsigned int)(PMIC_BASE+0x1c10))
#define MT6358_LDO_VFE28_OP_CFG_SET  ((unsigned int)(PMIC_BASE+0x1c12))
#define MT6358_LDO_VFE28_OP_CFG_CLR  ((unsigned int)(PMIC_BASE+0x1c14))
#define MT6358_LDO_VFE28_CON1  ((unsigned int)(PMIC_BASE+0x1c16))
#define MT6358_LDO_VFE28_CON2  ((unsigned int)(PMIC_BASE+0x1c18))
#define MT6358_LDO_VFE28_CON3  ((unsigned int)(PMIC_BASE+0x1c1a))
#define MT6358_LDO_VRF18_CON0  ((unsigned int)(PMIC_BASE+0x1c1c))
#define MT6358_LDO_VRF18_OP_EN ((unsigned int)(PMIC_BASE+0x1c1e))
#define MT6358_LDO_VRF18_OP_EN_SET ((unsigned int)(PMIC_BASE+0x1c20))
#define MT6358_LDO_VRF18_OP_EN_CLR ((unsigned int)(PMIC_BASE+0x1c22))
#define MT6358_LDO_VRF18_OP_CFG   ((unsigned int)(PMIC_BASE+0x1c24))
#define MT6358_LDO_VRF18_OP_CFG_SET  ((unsigned int)(PMIC_BASE+0x1c26))
#define MT6358_LDO_VRF18_OP_CFG_CLR  ((unsigned int)(PMIC_BASE+0x1c28))
#define MT6358_LDO_VRF18_CON1  ((unsigned int)(PMIC_BASE+0x1c2a))
#define MT6358_LDO_VRF18_CON2  ((unsigned int)(PMIC_BASE+0x1c2c))
#define MT6358_LDO_VRF18_CON3  ((unsigned int)(PMIC_BASE+0x1c2e))
#define MT6358_LDO_VRF12_CON0  ((unsigned int)(PMIC_BASE+0x1c30))
#define MT6358_LDO_VRF12_OP_EN ((unsigned int)(PMIC_BASE+0x1c32))
#define MT6358_LDO_VRF12_OP_EN_SET ((unsigned int)(PMIC_BASE+0x1c34))
#define MT6358_LDO_VRF12_OP_EN_CLR ((unsigned int)(PMIC_BASE+0x1c36))
#define MT6358_LDO_VRF12_OP_CFG   ((unsigned int)(PMIC_BASE+0x1c38))
#define MT6358_LDO_VRF12_OP_CFG_SET  ((unsigned int)(PMIC_BASE+0x1c3a))
#define MT6358_LDO_VRF12_OP_CFG_CLR  ((unsigned int)(PMIC_BASE+0x1c3c))
#define MT6358_LDO_VRF12_CON1  ((unsigned int)(PMIC_BASE+0x1c3e))
#define MT6358_LDO_VRF12_CON2  ((unsigned int)(PMIC_BASE+0x1c40))
#define MT6358_LDO_VRF12_CON3  ((unsigned int)(PMIC_BASE+0x1c42))
#define MT6358_LDO_VEFUSE_CON0 ((unsigned int)(PMIC_BASE+0x1c44))
#define MT6358_LDO_VEFUSE_OP_EN   ((unsigned int)(PMIC_BASE+0x1c46))
#define MT6358_LDO_VEFUSE_OP_EN_SET  ((unsigned int)(PMIC_BASE+0x1c48))
#define MT6358_LDO_VEFUSE_OP_EN_CLR  ((unsigned int)(PMIC_BASE+0x1c4a))
#define MT6358_LDO_VEFUSE_OP_CFG  ((unsigned int)(PMIC_BASE+0x1c4c))
#define MT6358_LDO_VEFUSE_OP_CFG_SET ((unsigned int)(PMIC_BASE+0x1c4e))
#define MT6358_LDO_VEFUSE_OP_CFG_CLR ((unsigned int)(PMIC_BASE+0x1c50))
#define MT6358_LDO_VEFUSE_CON1 ((unsigned int)(PMIC_BASE+0x1c52))
#define MT6358_LDO_VEFUSE_CON2 ((unsigned int)(PMIC_BASE+0x1c54))
#define MT6358_LDO_VEFUSE_CON3 ((unsigned int)(PMIC_BASE+0x1c56))
#define MT6358_LDO_VCN18_CON0  ((unsigned int)(PMIC_BASE+0x1c58))
#define MT6358_LDO_VCN18_OP_EN ((unsigned int)(PMIC_BASE+0x1c5a))
#define MT6358_LDO_VCN18_OP_EN_SET ((unsigned int)(PMIC_BASE+0x1c5c))
#define MT6358_LDO_VCN18_OP_EN_CLR ((unsigned int)(PMIC_BASE+0x1c5e))
#define MT6358_LDO_VCN18_OP_CFG   ((unsigned int)(PMIC_BASE+0x1c60))
#define MT6358_LDO_VCN18_OP_CFG_SET  ((unsigned int)(PMIC_BASE+0x1c62))
#define MT6358_LDO_VCN18_OP_CFG_CLR  ((unsigned int)(PMIC_BASE+0x1c64))
#define MT6358_LDO_VCN18_CON1  ((unsigned int)(PMIC_BASE+0x1c66))
#define MT6358_LDO_VCN18_CON2  ((unsigned int)(PMIC_BASE+0x1c68))
#define MT6358_LDO_VCN18_CON3  ((unsigned int)(PMIC_BASE+0x1c6a))
#define MT6358_LDO_VCAMA1_CON0 ((unsigned int)(PMIC_BASE+0x1c6c))
#define MT6358_LDO_VCAMA1_OP_EN   ((unsigned int)(PMIC_BASE+0x1c6e))
#define MT6358_LDO_VCAMA1_OP_EN_SET  ((unsigned int)(PMIC_BASE+0x1c70))
#define MT6358_LDO_VCAMA1_OP_EN_CLR  ((unsigned int)(PMIC_BASE+0x1c72))
#define MT6358_LDO_VCAMA1_OP_CFG  ((unsigned int)(PMIC_BASE+0x1c74))
#define MT6358_LDO_VCAMA1_OP_CFG_SET ((unsigned int)(PMIC_BASE+0x1c76))
#define MT6358_LDO_VCAMA1_OP_CFG_CLR ((unsigned int)(PMIC_BASE+0x1c78))
#define MT6358_LDO_VCAMA1_CON1 ((unsigned int)(PMIC_BASE+0x1c7a))
#define MT6358_LDO_VCAMA1_CON2 ((unsigned int)(PMIC_BASE+0x1c7c))
#define MT6358_LDO_VCAMA1_CON3 ((unsigned int)(PMIC_BASE+0x1c7e))
#define MT6358_LDO_GOFF1_DSN_ID   ((unsigned int)(PMIC_BASE+0x1c80))
#define MT6358_LDO_GOFF1_DSN_REV0  ((unsigned int)(PMIC_BASE+0x1c82))
#define MT6358_LDO_GOFF1_DSN_DBI  ((unsigned int)(PMIC_BASE+0x1c84))
#define MT6358_LDO_GOFF1_DSN_DXI  ((unsigned int)(PMIC_BASE+0x1c86))
#define MT6358_LDO_VCAMA2_CON0 ((unsigned int)(PMIC_BASE+0x1c88))
#define MT6358_LDO_VCAMA2_OP_EN   ((unsigned int)(PMIC_BASE+0x1c8a))
#define MT6358_LDO_VCAMA2_OP_EN_SET  ((unsigned int)(PMIC_BASE+0x1c8c))
#define MT6358_LDO_VCAMA2_OP_EN_CLR  ((unsigned int)(PMIC_BASE+0x1c8e))
#define MT6358_LDO_VCAMA2_OP_CFG  ((unsigned int)(PMIC_BASE+0x1c90))
#define MT6358_LDO_VCAMA2_OP_CFG_SET ((unsigned int)(PMIC_BASE+0x1c92))
#define MT6358_LDO_VCAMA2_OP_CFG_CLR ((unsigned int)(PMIC_BASE+0x1c94))
#define MT6358_LDO_VCAMA2_CON1 ((unsigned int)(PMIC_BASE+0x1c96))
#define MT6358_LDO_VCAMA2_CON2 ((unsigned int)(PMIC_BASE+0x1c98))
#define MT6358_LDO_VCAMA2_CON3 ((unsigned int)(PMIC_BASE+0x1c9a))
#define MT6358_LDO_VCAMD_CON0  ((unsigned int)(PMIC_BASE+0x1c9c))
#define MT6358_LDO_VCAMD_OP_EN ((unsigned int)(PMIC_BASE+0x1c9e))
#define MT6358_LDO_VCAMD_OP_EN_SET ((unsigned int)(PMIC_BASE+0x1ca0))
#define MT6358_LDO_VCAMD_OP_EN_CLR ((unsigned int)(PMIC_BASE+0x1ca2))
#define MT6358_LDO_VCAMD_OP_CFG   ((unsigned int)(PMIC_BASE+0x1ca4))
#define MT6358_LDO_VCAMD_OP_CFG_SET  ((unsigned int)(PMIC_BASE+0x1ca6))
#define MT6358_LDO_VCAMD_OP_CFG_CLR  ((unsigned int)(PMIC_BASE+0x1ca8))
#define MT6358_LDO_VCAMD_CON1  ((unsigned int)(PMIC_BASE+0x1caa))
#define MT6358_LDO_VCAMD_CON2  ((unsigned int)(PMIC_BASE+0x1cac))
#define MT6358_LDO_VCAMD_CON3  ((unsigned int)(PMIC_BASE+0x1cae))
#define MT6358_LDO_VCAMIO_CON0 ((unsigned int)(PMIC_BASE+0x1cb0))
#define MT6358_LDO_VCAMIO_OP_EN   ((unsigned int)(PMIC_BASE+0x1cb2))
#define MT6358_LDO_VCAMIO_OP_EN_SET  ((unsigned int)(PMIC_BASE+0x1cb4))
#define MT6358_LDO_VCAMIO_OP_EN_CLR  ((unsigned int)(PMIC_BASE+0x1cb6))
#define MT6358_LDO_VCAMIO_OP_CFG  ((unsigned int)(PMIC_BASE+0x1cb8))
#define MT6358_LDO_VCAMIO_OP_CFG_SET ((unsigned int)(PMIC_BASE+0x1cba))
#define MT6358_LDO_VCAMIO_OP_CFG_CLR ((unsigned int)(PMIC_BASE+0x1cbc))
#define MT6358_LDO_VCAMIO_CON1 ((unsigned int)(PMIC_BASE+0x1cbe))
#define MT6358_LDO_VCAMIO_CON2 ((unsigned int)(PMIC_BASE+0x1cc0))
#define MT6358_LDO_VCAMIO_CON3 ((unsigned int)(PMIC_BASE+0x1cc2))
#define MT6358_LDO_VMC_CON0  ((unsigned int)(PMIC_BASE+0x1cc4))
#define MT6358_LDO_VMC_OP_EN ((unsigned int)(PMIC_BASE+0x1cc6))
#define MT6358_LDO_VMC_OP_EN_SET  ((unsigned int)(PMIC_BASE+0x1cc8))
#define MT6358_LDO_VMC_OP_EN_CLR  ((unsigned int)(PMIC_BASE+0x1cca))
#define MT6358_LDO_VMC_OP_CFG  ((unsigned int)(PMIC_BASE+0x1ccc))
#define MT6358_LDO_VMC_OP_CFG_SET  ((unsigned int)(PMIC_BASE+0x1cce))
#define MT6358_LDO_VMC_OP_CFG_CLR  ((unsigned int)(PMIC_BASE+0x1cd0))
#define MT6358_LDO_VMC_CON1  ((unsigned int)(PMIC_BASE+0x1cd2))
#define MT6358_LDO_VMC_CON2  ((unsigned int)(PMIC_BASE+0x1cd4))
#define MT6358_LDO_VMC_CON3  ((unsigned int)(PMIC_BASE+0x1cd6))
#define MT6358_LDO_VMCH_CON0 ((unsigned int)(PMIC_BASE+0x1cd8))
#define MT6358_LDO_VMCH_OP_EN  ((unsigned int)(PMIC_BASE+0x1cda))
#define MT6358_LDO_VMCH_OP_EN_SET  ((unsigned int)(PMIC_BASE+0x1cdc))
#define MT6358_LDO_VMCH_OP_EN_CLR  ((unsigned int)(PMIC_BASE+0x1cde))
#define MT6358_LDO_VMCH_OP_CFG ((unsigned int)(PMIC_BASE+0x1ce0))
#define MT6358_LDO_VMCH_OP_CFG_SET ((unsigned int)(PMIC_BASE+0x1ce2))
#define MT6358_LDO_VMCH_OP_CFG_CLR ((unsigned int)(PMIC_BASE+0x1ce4))
#define MT6358_LDO_VMCH_CON1 ((unsigned int)(PMIC_BASE+0x1ce6))
#define MT6358_LDO_VMCH_CON2 ((unsigned int)(PMIC_BASE+0x1ce8))
#define MT6358_LDO_VMCH_CON3 ((unsigned int)(PMIC_BASE+0x1cea))
#define MT6358_LDO_GOFF2_DSN_ID   ((unsigned int)(PMIC_BASE+0x1d00))
#define MT6358_LDO_GOFF2_DSN_REV0  ((unsigned int)(PMIC_BASE+0x1d02))
#define MT6358_LDO_GOFF2_DSN_DBI  ((unsigned int)(PMIC_BASE+0x1d04))
#define MT6358_LDO_GOFF2_DSN_DXI  ((unsigned int)(PMIC_BASE+0x1d06))
#define MT6358_LDO_VIBR_CON0 ((unsigned int)(PMIC_BASE+0x1d08))
#define MT6358_LDO_VIBR_OP_EN  ((unsigned int)(PMIC_BASE+0x1d0a))
#define MT6358_LDO_VIBR_OP_EN_SET  ((unsigned int)(PMIC_BASE+0x1d0c))
#define MT6358_LDO_VIBR_OP_EN_CLR  ((unsigned int)(PMIC_BASE+0x1d0e))
#define MT6358_LDO_VIBR_OP_CFG ((unsigned int)(PMIC_BASE+0x1d10))
#define MT6358_LDO_VIBR_OP_CFG_SET ((unsigned int)(PMIC_BASE+0x1d12))
#define MT6358_LDO_VIBR_OP_CFG_CLR ((unsigned int)(PMIC_BASE+0x1d14))
#define MT6358_LDO_VIBR_CON1 ((unsigned int)(PMIC_BASE+0x1d16))
#define MT6358_LDO_VIBR_CON2 ((unsigned int)(PMIC_BASE+0x1d18))
#define MT6358_LDO_VIBR_CON3 ((unsigned int)(PMIC_BASE+0x1d1a))
#define MT6358_LDO_VCN33_CON0_0   ((unsigned int)(PMIC_BASE+0x1d1c))
#define MT6358_LDO_VCN33_OP_EN ((unsigned int)(PMIC_BASE+0x1d1e))
#define MT6358_LDO_VCN33_OP_EN_SET ((unsigned int)(PMIC_BASE+0x1d20))
#define MT6358_LDO_VCN33_OP_EN_CLR ((unsigned int)(PMIC_BASE+0x1d22))
#define MT6358_LDO_VCN33_OP_CFG   ((unsigned int)(PMIC_BASE+0x1d24))
#define MT6358_LDO_VCN33_OP_CFG_SET  ((unsigned int)(PMIC_BASE+0x1d26))
#define MT6358_LDO_VCN33_OP_CFG_CLR  ((unsigned int)(PMIC_BASE+0x1d28))
#define MT6358_LDO_VCN33_CON0_1   ((unsigned int)(PMIC_BASE+0x1d2a))
#define MT6358_LDO_VCN33_CON1  ((unsigned int)(PMIC_BASE+0x1d2c))
#define MT6358_LDO_VCN33_CON2  ((unsigned int)(PMIC_BASE+0x1d2e))
#define MT6358_LDO_VCN33_CON3  ((unsigned int)(PMIC_BASE+0x1d30))
#define MT6358_LDO_VLDO28_CON0_0  ((unsigned int)(PMIC_BASE+0x1d32))
#define MT6358_LDO_VLDO28_OP_EN   ((unsigned int)(PMIC_BASE+0x1d34))
#define MT6358_LDO_VLDO28_OP_EN_SET  ((unsigned int)(PMIC_BASE+0x1d36))
#define MT6358_LDO_VLDO28_OP_EN_CLR  ((unsigned int)(PMIC_BASE+0x1d38))
#define MT6358_LDO_VLDO28_OP_CFG  ((unsigned int)(PMIC_BASE+0x1d3a))
#define MT6358_LDO_VLDO28_OP_CFG_SET ((unsigned int)(PMIC_BASE+0x1d3c))
#define MT6358_LDO_VLDO28_OP_CFG_CLR ((unsigned int)(PMIC_BASE+0x1d3e))
#define MT6358_LDO_VLDO28_CON0_1  ((unsigned int)(PMIC_BASE+0x1d40))
#define MT6358_LDO_VLDO28_CON1 ((unsigned int)(PMIC_BASE+0x1d42))
#define MT6358_LDO_VLDO28_CON2 ((unsigned int)(PMIC_BASE+0x1d44))
#define MT6358_LDO_VLDO28_CON3 ((unsigned int)(PMIC_BASE+0x1d46))
#define MT6358_LDO_VSIM1_CON0  ((unsigned int)(PMIC_BASE+0x1d48))
#define MT6358_LDO_VSIM1_OP_EN ((unsigned int)(PMIC_BASE+0x1d4a))
#define MT6358_LDO_VSIM1_OP_EN_SET ((unsigned int)(PMIC_BASE+0x1d4c))
#define MT6358_LDO_VSIM1_OP_EN_CLR ((unsigned int)(PMIC_BASE+0x1d4e))
#define MT6358_LDO_VSIM1_OP_CFG   ((unsigned int)(PMIC_BASE+0x1d50))
#define MT6358_LDO_VSIM1_OP_CFG_SET  ((unsigned int)(PMIC_BASE+0x1d52))
#define MT6358_LDO_VSIM1_OP_CFG_CLR  ((unsigned int)(PMIC_BASE+0x1d54))
#define MT6358_LDO_VSIM1_CON1  ((unsigned int)(PMIC_BASE+0x1d56))
#define MT6358_LDO_VSIM1_CON2  ((unsigned int)(PMIC_BASE+0x1d58))
#define MT6358_LDO_VSIM1_CON3  ((unsigned int)(PMIC_BASE+0x1d5a))
#define MT6358_LDO_VSIM2_CON0  ((unsigned int)(PMIC_BASE+0x1d5c))
#define MT6358_LDO_VSIM2_OP_EN ((unsigned int)(PMIC_BASE+0x1d5e))
#define MT6358_LDO_VSIM2_OP_EN_SET ((unsigned int)(PMIC_BASE+0x1d60))
#define MT6358_LDO_VSIM2_OP_EN_CLR ((unsigned int)(PMIC_BASE+0x1d62))
#define MT6358_LDO_VSIM2_OP_CFG   ((unsigned int)(PMIC_BASE+0x1d64))
#define MT6358_LDO_VSIM2_OP_CFG_SET  ((unsigned int)(PMIC_BASE+0x1d66))
#define MT6358_LDO_VSIM2_OP_CFG_CLR  ((unsigned int)(PMIC_BASE+0x1d68))
#define MT6358_LDO_VSIM2_CON1  ((unsigned int)(PMIC_BASE+0x1d6a))
#define MT6358_LDO_VSIM2_CON2  ((unsigned int)(PMIC_BASE+0x1d6c))
#define MT6358_LDO_VSIM2_CON3  ((unsigned int)(PMIC_BASE+0x1d6e))
#define MT6358_LDO_VMCH_EINT_SD_CFG  ((unsigned int)(PMIC_BASE+0x1d70))
#define MT6358_LDO_VSIM1_EINT_SD_CFG ((unsigned int)(PMIC_BASE+0x1d72))
#define MT6358_LDO_VSIM2_EINT_SD_CFG ((unsigned int)(PMIC_BASE+0x1d74))
#define MT6358_LDO_GOFF2_RSV_CON0  ((unsigned int)(PMIC_BASE+0x1d76))
#define MT6358_LDO_GOFF2_RSV_CON1  ((unsigned int)(PMIC_BASE+0x1d78))
#define MT6358_LDO_GOFF3_DSN_ID   ((unsigned int)(PMIC_BASE+0x1d80))
#define MT6358_LDO_GOFF3_DSN_REV0  ((unsigned int)(PMIC_BASE+0x1d82))
#define MT6358_LDO_GOFF3_DSN_DBI  ((unsigned int)(PMIC_BASE+0x1d84))
#define MT6358_LDO_GOFF3_DSN_DXI  ((unsigned int)(PMIC_BASE+0x1d86))
#define MT6358_LDO_VCN28_CON0  ((unsigned int)(PMIC_BASE+0x1d88))
#define MT6358_LDO_VCN28_OP_EN ((unsigned int)(PMIC_BASE+0x1d8a))
#define MT6358_LDO_VCN28_OP_EN_SET ((unsigned int)(PMIC_BASE+0x1d8c))
#define MT6358_LDO_VCN28_OP_EN_CLR ((unsigned int)(PMIC_BASE+0x1d8e))
#define MT6358_LDO_VCN28_OP_CFG   ((unsigned int)(PMIC_BASE+0x1d90))
#define MT6358_LDO_VCN28_OP_CFG_SET  ((unsigned int)(PMIC_BASE+0x1d92))
#define MT6358_LDO_VCN28_OP_CFG_CLR  ((unsigned int)(PMIC_BASE+0x1d94))
#define MT6358_LDO_VCN28_CON1  ((unsigned int)(PMIC_BASE+0x1d96))
#define MT6358_LDO_VCN28_CON2  ((unsigned int)(PMIC_BASE+0x1d98))
#define MT6358_LDO_VCN28_CON3  ((unsigned int)(PMIC_BASE+0x1d9a))
#define MT6358_VRTC28_CON0   ((unsigned int)(PMIC_BASE+0x1d9c))
#define MT6358_LDO_VBIF28_CON0 ((unsigned int)(PMIC_BASE+0x1d9e))
#define MT6358_LDO_VBIF28_OP_EN   ((unsigned int)(PMIC_BASE+0x1da0))
#define MT6358_LDO_VBIF28_OP_EN_SET  ((unsigned int)(PMIC_BASE+0x1da2))
#define MT6358_LDO_VBIF28_OP_EN_CLR  ((unsigned int)(PMIC_BASE+0x1da4))
#define MT6358_LDO_VBIF28_OP_CFG  ((unsigned int)(PMIC_BASE+0x1da6))
#define MT6358_LDO_VBIF28_OP_CFG_SET ((unsigned int)(PMIC_BASE+0x1da8))
#define MT6358_LDO_VBIF28_OP_CFG_CLR ((unsigned int)(PMIC_BASE+0x1daa))
#define MT6358_LDO_VBIF28_CON1 ((unsigned int)(PMIC_BASE+0x1dac))
#define MT6358_LDO_VBIF28_CON2 ((unsigned int)(PMIC_BASE+0x1dae))
#define MT6358_LDO_VBIF28_CON3 ((unsigned int)(PMIC_BASE+0x1db0))
#define MT6358_LDO_GOFF3_RSV_CON0  ((unsigned int)(PMIC_BASE+0x1db2))
#define MT6358_LDO_GOFF3_RSV_CON1  ((unsigned int)(PMIC_BASE+0x1db4))
#define MT6358_LDO_ANA0_DSN_ID ((unsigned int)(PMIC_BASE+0x1e00))
#define MT6358_LDO_ANA0_DSN_REV0  ((unsigned int)(PMIC_BASE+0x1e02))
#define MT6358_LDO_ANA0_DSN_DBI   ((unsigned int)(PMIC_BASE+0x1e04))
#define MT6358_LDO_ANA0_DSN_FPI   ((unsigned int)(PMIC_BASE+0x1e06))
#define MT6358_VCAMA1_ANA_CON0 ((unsigned int)(PMIC_BASE+0x1e08))
#define MT6358_VCAMA1_ANA_CON1 ((unsigned int)(PMIC_BASE+0x1e0a))
#define MT6358_VCAMA2_ANA_CON0 ((unsigned int)(PMIC_BASE+0x1e0c))
#define MT6358_VCAMA2_ANA_CON1 ((unsigned int)(PMIC_BASE+0x1e0e))
#define MT6358_VFE28_ANA_CON0  ((unsigned int)(PMIC_BASE+0x1e10))
#define MT6358_VFE28_ANA_CON1  ((unsigned int)(PMIC_BASE+0x1e12))
#define MT6358_VCN28_ANA_CON0  ((unsigned int)(PMIC_BASE+0x1e14))
#define MT6358_VCN28_ANA_CON1  ((unsigned int)(PMIC_BASE+0x1e16))
#define MT6358_VBIF28_ANA_CON0 ((unsigned int)(PMIC_BASE+0x1e18))
#define MT6358_VBIF28_ANA_CON1 ((unsigned int)(PMIC_BASE+0x1e1a))
#define MT6358_VAUD28_ANA_CON0 ((unsigned int)(PMIC_BASE+0x1e1c))
#define MT6358_VAUD28_ANA_CON1 ((unsigned int)(PMIC_BASE+0x1e1e))
#define MT6358_VAUX18_ANA_CON0 ((unsigned int)(PMIC_BASE+0x1e20))
#define MT6358_VAUX18_ANA_CON1 ((unsigned int)(PMIC_BASE+0x1e22))
#define MT6358_VXO22_ANA_CON0  ((unsigned int)(PMIC_BASE+0x1e24))
#define MT6358_VXO22_ANA_CON1  ((unsigned int)(PMIC_BASE+0x1e26))
#define MT6358_VCN33_ANA_CON0  ((unsigned int)(PMIC_BASE+0x1e28))
#define MT6358_VCN33_ANA_CON1  ((unsigned int)(PMIC_BASE+0x1e2a))
#define MT6358_VSIM1_ANA_CON0  ((unsigned int)(PMIC_BASE+0x1e2c))
#define MT6358_VSIM1_ANA_CON1  ((unsigned int)(PMIC_BASE+0x1e2e))
#define MT6358_VSIM2_ANA_CON0  ((unsigned int)(PMIC_BASE+0x1e30))
#define MT6358_VSIM2_ANA_CON1  ((unsigned int)(PMIC_BASE+0x1e32))
#define MT6358_VUSB_ANA_CON0 ((unsigned int)(PMIC_BASE+0x1e34))
#define MT6358_VUSB_ANA_CON1 ((unsigned int)(PMIC_BASE+0x1e36))
#define MT6358_VEMC_ANA_CON0 ((unsigned int)(PMIC_BASE+0x1e38))
#define MT6358_VEMC_ANA_CON1 ((unsigned int)(PMIC_BASE+0x1e3a))
#define MT6358_VLDO28_ANA_CON0 ((unsigned int)(PMIC_BASE+0x1e3c))
#define MT6358_VLDO28_ANA_CON1 ((unsigned int)(PMIC_BASE+0x1e3e))
#define MT6358_VIO28_ANA_CON0  ((unsigned int)(PMIC_BASE+0x1e40))
#define MT6358_VIO28_ANA_CON1  ((unsigned int)(PMIC_BASE+0x1e42))
#define MT6358_VIBR_ANA_CON0 ((unsigned int)(PMIC_BASE+0x1e44))
#define MT6358_VIBR_ANA_CON1 ((unsigned int)(PMIC_BASE+0x1e46))
#define MT6358_VMCH_ANA_CON0 ((unsigned int)(PMIC_BASE+0x1e48))
#define MT6358_VMCH_ANA_CON1 ((unsigned int)(PMIC_BASE+0x1e4a))
#define MT6358_VMC_ANA_CON0  ((unsigned int)(PMIC_BASE+0x1e4c))
#define MT6358_VMC_ANA_CON1  ((unsigned int)(PMIC_BASE+0x1e4e))
#define MT6358_LDO_ANA0_ELR_NUM   ((unsigned int)(PMIC_BASE+0x1e50))
#define MT6358_VCAMA1_ELR_0  ((unsigned int)(PMIC_BASE+0x1e52))
#define MT6358_VCAMA2_ELR_0  ((unsigned int)(PMIC_BASE+0x1e54))
#define MT6358_VFE28_ELR_0   ((unsigned int)(PMIC_BASE+0x1e56))
#define MT6358_VCN28_ELR_0   ((unsigned int)(PMIC_BASE+0x1e58))
#define MT6358_VBIF28_ELR_0  ((unsigned int)(PMIC_BASE+0x1e5a))
#define MT6358_VAUD28_ELR_0  ((unsigned int)(PMIC_BASE+0x1e5c))
#define MT6358_VAUX18_ELR_0  ((unsigned int)(PMIC_BASE+0x1e5e))
#define MT6358_VXO22_ELR_0   ((unsigned int)(PMIC_BASE+0x1e60))
#define MT6358_VCN33_ELR_0   ((unsigned int)(PMIC_BASE+0x1e62))
#define MT6358_VSIM1_ELR_0   ((unsigned int)(PMIC_BASE+0x1e64))
#define MT6358_VSIM2_ELR_0   ((unsigned int)(PMIC_BASE+0x1e66))
#define MT6358_VUSB_ELR_0   ((unsigned int)(PMIC_BASE+0x1e68))
#define MT6358_VEMC_ELR_0   ((unsigned int)(PMIC_BASE+0x1e6a))
#define MT6358_VLDO28_ELR_0  ((unsigned int)(PMIC_BASE+0x1e6c))
#define MT6358_VIO28_ELR_0   ((unsigned int)(PMIC_BASE+0x1e6e))
#define MT6358_VIBR_ELR_0   ((unsigned int)(PMIC_BASE+0x1e70))
#define MT6358_VMCH_ELR_0   ((unsigned int)(PMIC_BASE+0x1e72))
#define MT6358_VMC_ELR_0 ((unsigned int)(PMIC_BASE+0x1e74))
#define MT6358_LDO_ANA1_DSN_ID ((unsigned int)(PMIC_BASE+0x1e80))
#define MT6358_LDO_ANA1_DSN_REV0  ((unsigned int)(PMIC_BASE+0x1e82))
#define MT6358_LDO_ANA1_DSN_DBI   ((unsigned int)(PMIC_BASE+0x1e84))
#define MT6358_LDO_ANA1_DSN_FPI   ((unsigned int)(PMIC_BASE+0x1e86))
#define MT6358_VRF18_ANA_CON0  ((unsigned int)(PMIC_BASE+0x1e88))
#define MT6358_VRF18_ANA_CON1  ((unsigned int)(PMIC_BASE+0x1e8a))
#define MT6358_VCN18_ANA_CON0  ((unsigned int)(PMIC_BASE+0x1e8c))
#define MT6358_VCN18_ANA_CON1  ((unsigned int)(PMIC_BASE+0x1e8e))
#define MT6358_VCAMIO_ANA_CON0 ((unsigned int)(PMIC_BASE+0x1e90))
#define MT6358_VCAMIO_ANA_CON1 ((unsigned int)(PMIC_BASE+0x1e92))
#define MT6358_VIO18_ANA_CON0  ((unsigned int)(PMIC_BASE+0x1e94))
#define MT6358_VIO18_ANA_CON1  ((unsigned int)(PMIC_BASE+0x1e96))
#define MT6358_VEFUSE_ANA_CON0 ((unsigned int)(PMIC_BASE+0x1e98))
#define MT6358_VEFUSE_ANA_CON1 ((unsigned int)(PMIC_BASE+0x1e9a))
#define MT6358_VRF12_ANA_CON0  ((unsigned int)(PMIC_BASE+0x1e9c))
#define MT6358_VRF12_ANA_CON1  ((unsigned int)(PMIC_BASE+0x1e9e))
#define MT6358_VSRAM_PROC11_ANA_CON0 ((unsigned int)(PMIC_BASE+0x1ea0))
#define MT6358_VSRAM_PROC11_ANA_CON1 ((unsigned int)(PMIC_BASE+0x1ea2))
#define MT6358_VSRAM_PROC12_ANA_CON0 ((unsigned int)(PMIC_BASE+0x1ea4))
#define MT6358_VSRAM_OTHERS_ANA_CON0 ((unsigned int)(PMIC_BASE+0x1ea6))
#define MT6358_VSRAM_GPU_ANA_CON0  ((unsigned int)(PMIC_BASE+0x1ea8))
#define MT6358_VDRAM2_ANA_CON0 ((unsigned int)(PMIC_BASE+0x1eaa))
#define MT6358_VDRAM2_ANA_CON1 ((unsigned int)(PMIC_BASE+0x1eac))
#define MT6358_VCAMD_ANA_CON0  ((unsigned int)(PMIC_BASE+0x1eae))
#define MT6358_VCAMD_ANA_CON1  ((unsigned int)(PMIC_BASE+0x1eb0))
#define MT6358_VA12_ANA_CON0 ((unsigned int)(PMIC_BASE+0x1eb2))
#define MT6358_VA12_ANA_CON1 ((unsigned int)(PMIC_BASE+0x1eb4))
#define MT6358_LDO_ANA1_ELR_NUM   ((unsigned int)(PMIC_BASE+0x1eb6))
#define MT6358_VRF18_ELR_0   ((unsigned int)(PMIC_BASE+0x1eb8))
#define MT6358_VCN18_ELR_0   ((unsigned int)(PMIC_BASE+0x1eba))
#define MT6358_VCAMIO_ELR_0  ((unsigned int)(PMIC_BASE+0x1ebc))
#define MT6358_VIO18_ELR_0   ((unsigned int)(PMIC_BASE+0x1ebe))
#define MT6358_VEFUSE_ELR_0  ((unsigned int)(PMIC_BASE+0x1ec0))
#define MT6358_VRF12_ELR_0   ((unsigned int)(PMIC_BASE+0x1ec2))
#define MT6358_VDRAM2_ELR_0  ((unsigned int)(PMIC_BASE+0x1ec4))
#define MT6358_VCAMD_ELR_0   ((unsigned int)(PMIC_BASE+0x1ec6))
#define MT6358_VA12_ELR_0   ((unsigned int)(PMIC_BASE+0x1ec8))
#define MT6358_VRTC28_ELR_0  ((unsigned int)(PMIC_BASE+0x1eca))
#define MT6358_DUMMYLOAD_DSN_ID   ((unsigned int)(PMIC_BASE+0x1f00))
#define MT6358_DUMMYLOAD_DSN_REV0  ((unsigned int)(PMIC_BASE+0x1f02))
#define MT6358_DUMMYLOAD_DSN_DBI  ((unsigned int)(PMIC_BASE+0x1f04))
#define MT6358_DUMMYLOAD_DSN_FPI  ((unsigned int)(PMIC_BASE+0x1f06))
#define MT6358_DUMMYLOAD_ANA_CON0  ((unsigned int)(PMIC_BASE+0x1f08))
#define MT6358_ISINK0_CON1   ((unsigned int)(PMIC_BASE+0x1f0a))
#define MT6358_ISINK1_CON1   ((unsigned int)(PMIC_BASE+0x1f0c))
#define MT6358_ISINK_ANA1_SMPL ((unsigned int)(PMIC_BASE+0x1f0e))
#define MT6358_ISINK_EN_CTRL_SMPL  ((unsigned int)(PMIC_BASE+0x1f10))
#define MT6358_DUMMYLOAD_ELR_NUM  ((unsigned int)(PMIC_BASE+0x1f12))
#define MT6358_DUMMYLOAD_ELR_0 ((unsigned int)(PMIC_BASE+0x1f14))
#define MT6358_AUD_TOP_ID   ((unsigned int)(PMIC_BASE+0x2200))
#define MT6358_AUD_TOP_REV0  ((unsigned int)(PMIC_BASE+0x2202))
#define MT6358_AUD_TOP_DBI   ((unsigned int)(PMIC_BASE+0x2204))
#define MT6358_AUD_TOP_DXI   ((unsigned int)(PMIC_BASE+0x2206))
#define MT6358_AUD_TOP_CKPDN_TPM0  ((unsigned int)(PMIC_BASE+0x2208))
#define MT6358_AUD_TOP_CKPDN_TPM1  ((unsigned int)(PMIC_BASE+0x220a))
#define MT6358_AUD_TOP_CKPDN_CON0  ((unsigned int)(PMIC_BASE+0x220c))
#define MT6358_AUD_TOP_CKPDN_CON0_SET   ((unsigned int)(PMIC_BASE+0x220e))
#define MT6358_AUD_TOP_CKPDN_CON0_CLR   ((unsigned int)(PMIC_BASE+0x2210))
#define MT6358_AUD_TOP_CKSEL_CON0  ((unsigned int)(PMIC_BASE+0x2212))
#define MT6358_AUD_TOP_CKSEL_CON0_SET   ((unsigned int)(PMIC_BASE+0x2214))
#define MT6358_AUD_TOP_CKSEL_CON0_CLR   ((unsigned int)(PMIC_BASE+0x2216))
#define MT6358_AUD_TOP_CKTST_CON0  ((unsigned int)(PMIC_BASE+0x2218))
#define MT6358_AUD_TOP_CLK_HWEN_CON0 ((unsigned int)(PMIC_BASE+0x221a))
#define MT6358_AUD_TOP_CLK_HWEN_CON0_SET ((unsigned int)(PMIC_BASE+0x221c))
#define MT6358_AUD_TOP_CLK_HWEN_CON0_CLR ((unsigned int)(PMIC_BASE+0x221e))
#define MT6358_AUD_TOP_RST_CON0   ((unsigned int)(PMIC_BASE+0x2220))
#define MT6358_AUD_TOP_RST_CON0_SET  ((unsigned int)(PMIC_BASE+0x2222))
#define MT6358_AUD_TOP_RST_CON0_CLR  ((unsigned int)(PMIC_BASE+0x2224))
#define MT6358_AUD_TOP_RST_BANK_CON0 ((unsigned int)(PMIC_BASE+0x2226))
#define MT6358_AUD_TOP_INT_CON0   ((unsigned int)(PMIC_BASE+0x2228))
#define MT6358_AUD_TOP_INT_CON0_SET  ((unsigned int)(PMIC_BASE+0x222a))
#define MT6358_AUD_TOP_INT_CON0_CLR  ((unsigned int)(PMIC_BASE+0x222c))
#define MT6358_AUD_TOP_INT_MASK_CON0 ((unsigned int)(PMIC_BASE+0x222e))
#define MT6358_AUD_TOP_INT_MASK_CON0_SET ((unsigned int)(PMIC_BASE+0x2230))
#define MT6358_AUD_TOP_INT_MASK_CON0_CLR ((unsigned int)(PMIC_BASE+0x2232))
#define MT6358_AUD_TOP_INT_STATUS0 ((unsigned int)(PMIC_BASE+0x2234))
#define MT6358_AUD_TOP_INT_RAW_STATUS0  ((unsigned int)(PMIC_BASE+0x2236))
#define MT6358_AUD_TOP_INT_MISC_CON0 ((unsigned int)(PMIC_BASE+0x2238))
#define MT6358_AUDNCP_CLKDIV_CON0  ((unsigned int)(PMIC_BASE+0x223a))
#define MT6358_AUDNCP_CLKDIV_CON1  ((unsigned int)(PMIC_BASE+0x223c))
#define MT6358_AUDNCP_CLKDIV_CON2  ((unsigned int)(PMIC_BASE+0x223e))
#define MT6358_AUDNCP_CLKDIV_CON3  ((unsigned int)(PMIC_BASE+0x2240))
#define MT6358_AUDNCP_CLKDIV_CON4  ((unsigned int)(PMIC_BASE+0x2242))
#define MT6358_AUD_TOP_MON_CON0   ((unsigned int)(PMIC_BASE+0x2244))
#define MT6358_AUDIO_DIG_DSN_ID   ((unsigned int)(PMIC_BASE+0x2280))
#define MT6358_AUDIO_DIG_DSN_REV0  ((unsigned int)(PMIC_BASE+0x2282))
#define MT6358_AUDIO_DIG_DSN_DBI  ((unsigned int)(PMIC_BASE+0x2284))
#define MT6358_AUDIO_DIG_DSN_DXI  ((unsigned int)(PMIC_BASE+0x2286))
#define MT6358_AFE_UL_DL_CON0  ((unsigned int)(PMIC_BASE+0x2288))
#define MT6358_AFE_DL_SRC2_CON0_L  ((unsigned int)(PMIC_BASE+0x228a))
#define MT6358_AFE_UL_SRC_CON0_H  ((unsigned int)(PMIC_BASE+0x228c))
#define MT6358_AFE_UL_SRC_CON0_L  ((unsigned int)(PMIC_BASE+0x228e))
#define MT6358_AFE_TOP_CON0  ((unsigned int)(PMIC_BASE+0x2290))
#define MT6358_AUDIO_TOP_CON0  ((unsigned int)(PMIC_BASE+0x2292))
#define MT6358_AFE_MON_DEBUG0  ((unsigned int)(PMIC_BASE+0x2294))
#define MT6358_AFUNC_AUD_CON0  ((unsigned int)(PMIC_BASE+0x2296))
#define MT6358_AFUNC_AUD_CON1  ((unsigned int)(PMIC_BASE+0x2298))
#define MT6358_AFUNC_AUD_CON2  ((unsigned int)(PMIC_BASE+0x229a))
#define MT6358_AFUNC_AUD_CON3  ((unsigned int)(PMIC_BASE+0x229c))
#define MT6358_AFUNC_AUD_CON4  ((unsigned int)(PMIC_BASE+0x229e))
#define MT6358_AFUNC_AUD_CON5  ((unsigned int)(PMIC_BASE+0x22a0))
#define MT6358_AFUNC_AUD_CON6  ((unsigned int)(PMIC_BASE+0x22a2))
#define MT6358_AFUNC_AUD_MON0  ((unsigned int)(PMIC_BASE+0x22a4))
#define MT6358_AUDRC_TUNE_MON0 ((unsigned int)(PMIC_BASE+0x22a6))
#define MT6358_AFE_ADDA_MTKAIF_FIFO_CFG0 ((unsigned int)(PMIC_BASE+0x22a8))
#define MT6358_AFE_ADDA_MTKAIF_FIFO_LOG_MON1  ((unsigned int)(PMIC_BASE+0x22aa))
#define MT6358_AFE_ADDA_MTKAIF_MON0  ((unsigned int)(PMIC_BASE+0x22ac))
#define MT6358_AFE_ADDA_MTKAIF_MON1  ((unsigned int)(PMIC_BASE+0x22ae))
#define MT6358_AFE_ADDA_MTKAIF_MON2  ((unsigned int)(PMIC_BASE+0x22b0))
#define MT6358_AFE_ADDA_MTKAIF_MON3  ((unsigned int)(PMIC_BASE+0x22b2))
#define MT6358_AFE_ADDA_MTKAIF_CFG0  ((unsigned int)(PMIC_BASE+0x22b4))
#define MT6358_AFE_ADDA_MTKAIF_RX_CFG0  ((unsigned int)(PMIC_BASE+0x22b6))
#define MT6358_AFE_ADDA_MTKAIF_RX_CFG1  ((unsigned int)(PMIC_BASE+0x22b8))
#define MT6358_AFE_ADDA_MTKAIF_RX_CFG2  ((unsigned int)(PMIC_BASE+0x22ba))
#define MT6358_AFE_ADDA_MTKAIF_RX_CFG3  ((unsigned int)(PMIC_BASE+0x22bc))
#define MT6358_AFE_ADDA_MTKAIF_TX_CFG1  ((unsigned int)(PMIC_BASE+0x22be))
#define MT6358_AFE_SGEN_CFG0 ((unsigned int)(PMIC_BASE+0x22c0))
#define MT6358_AFE_SGEN_CFG1 ((unsigned int)(PMIC_BASE+0x22c2))
#define MT6358_AFE_ADC_ASYNC_FIFO_CFG   ((unsigned int)(PMIC_BASE+0x22c4))
#define MT6358_AFE_DCCLK_CFG0  ((unsigned int)(PMIC_BASE+0x22c6))
#define MT6358_AFE_DCCLK_CFG1  ((unsigned int)(PMIC_BASE+0x22c8))
#define MT6358_AUDIO_DIG_CFG ((unsigned int)(PMIC_BASE+0x22ca))
#define MT6358_AFE_AUD_PAD_TOP ((unsigned int)(PMIC_BASE+0x22cc))
#define MT6358_AFE_AUD_PAD_TOP_MON ((unsigned int)(PMIC_BASE+0x22ce))
#define MT6358_AFE_AUD_PAD_TOP_MON1  ((unsigned int)(PMIC_BASE+0x22d0))
#define MT6358_AFE_DL_NLE_CFG  ((unsigned int)(PMIC_BASE+0x22d2))
#define MT6358_AFE_DL_NLE_MON  ((unsigned int)(PMIC_BASE+0x22d4))
#define MT6358_AFE_CG_EN_MON ((unsigned int)(PMIC_BASE+0x22d6))
#define MT6358_AUDIO_DIG_2ND_DSN_ID  ((unsigned int)(PMIC_BASE+0x2300))
#define MT6358_AUDIO_DIG_2ND_DSN_REV0   ((unsigned int)(PMIC_BASE+0x2302))
#define MT6358_AUDIO_DIG_2ND_DSN_DBI ((unsigned int)(PMIC_BASE+0x2304))
#define MT6358_AUDIO_DIG_2ND_DSN_DXI ((unsigned int)(PMIC_BASE+0x2306))
#define MT6358_AFE_PMIC_NEWIF_CFG3 ((unsigned int)(PMIC_BASE+0x2308))
#define MT6358_AFE_VOW_TOP   ((unsigned int)(PMIC_BASE+0x230a))
#define MT6358_AFE_VOW_CFG0  ((unsigned int)(PMIC_BASE+0x230c))
#define MT6358_AFE_VOW_CFG1  ((unsigned int)(PMIC_BASE+0x230e))
#define MT6358_AFE_VOW_CFG2  ((unsigned int)(PMIC_BASE+0x2310))
#define MT6358_AFE_VOW_CFG3  ((unsigned int)(PMIC_BASE+0x2312))
#define MT6358_AFE_VOW_CFG4  ((unsigned int)(PMIC_BASE+0x2314))
#define MT6358_AFE_VOW_CFG5  ((unsigned int)(PMIC_BASE+0x2316))
#define MT6358_AFE_VOW_CFG6  ((unsigned int)(PMIC_BASE+0x2318))
#define MT6358_AFE_VOW_MON0  ((unsigned int)(PMIC_BASE+0x231a))
#define MT6358_AFE_VOW_MON1  ((unsigned int)(PMIC_BASE+0x231c))
#define MT6358_AFE_VOW_MON2  ((unsigned int)(PMIC_BASE+0x231e))
#define MT6358_AFE_VOW_MON3  ((unsigned int)(PMIC_BASE+0x2320))
#define MT6358_AFE_VOW_MON4  ((unsigned int)(PMIC_BASE+0x2322))
#define MT6358_AFE_VOW_MON5  ((unsigned int)(PMIC_BASE+0x2324))
#define MT6358_AFE_VOW_SN_INI_CFG  ((unsigned int)(PMIC_BASE+0x2326))
#define MT6358_AFE_VOW_TGEN_CFG0  ((unsigned int)(PMIC_BASE+0x2328))
#define MT6358_AFE_VOW_POSDIV_CFG0 ((unsigned int)(PMIC_BASE+0x232a))
#define MT6358_AFE_VOW_HPF_CFG0   ((unsigned int)(PMIC_BASE+0x232c))
#define MT6358_AFE_VOW_PERIODIC_CFG0 ((unsigned int)(PMIC_BASE+0x232e))
#define MT6358_AFE_VOW_PERIODIC_CFG1 ((unsigned int)(PMIC_BASE+0x2330))
#define MT6358_AFE_VOW_PERIODIC_CFG2 ((unsigned int)(PMIC_BASE+0x2332))
#define MT6358_AFE_VOW_PERIODIC_CFG3 ((unsigned int)(PMIC_BASE+0x2334))
#define MT6358_AFE_VOW_PERIODIC_CFG4 ((unsigned int)(PMIC_BASE+0x2336))
#define MT6358_AFE_VOW_PERIODIC_CFG5 ((unsigned int)(PMIC_BASE+0x2338))
#define MT6358_AFE_VOW_PERIODIC_CFG6 ((unsigned int)(PMIC_BASE+0x233a))
#define MT6358_AFE_VOW_PERIODIC_CFG7 ((unsigned int)(PMIC_BASE+0x233c))
#define MT6358_AFE_VOW_PERIODIC_CFG8 ((unsigned int)(PMIC_BASE+0x233e))
#define MT6358_AFE_VOW_PERIODIC_CFG9 ((unsigned int)(PMIC_BASE+0x2340))
#define MT6358_AFE_VOW_PERIODIC_CFG10   ((unsigned int)(PMIC_BASE+0x2342))
#define MT6358_AFE_VOW_PERIODIC_CFG11   ((unsigned int)(PMIC_BASE+0x2344))
#define MT6358_AFE_VOW_PERIODIC_CFG12   ((unsigned int)(PMIC_BASE+0x2346))
#define MT6358_AFE_VOW_PERIODIC_CFG13   ((unsigned int)(PMIC_BASE+0x2348))
#define MT6358_AFE_VOW_PERIODIC_CFG14   ((unsigned int)(PMIC_BASE+0x234a))
#define MT6358_AFE_VOW_PERIODIC_CFG15   ((unsigned int)(PMIC_BASE+0x234c))
#define MT6358_AFE_VOW_PERIODIC_CFG16   ((unsigned int)(PMIC_BASE+0x234e))
#define MT6358_AFE_VOW_PERIODIC_CFG17   ((unsigned int)(PMIC_BASE+0x2350))
#define MT6358_AFE_VOW_PERIODIC_CFG18   ((unsigned int)(PMIC_BASE+0x2352))
#define MT6358_AFE_VOW_PERIODIC_CFG19   ((unsigned int)(PMIC_BASE+0x2354))
#define MT6358_AFE_VOW_PERIODIC_CFG20   ((unsigned int)(PMIC_BASE+0x2356))
#define MT6358_AFE_VOW_PERIODIC_CFG21   ((unsigned int)(PMIC_BASE+0x2358))
#define MT6358_AFE_VOW_PERIODIC_CFG22   ((unsigned int)(PMIC_BASE+0x235a))
#define MT6358_AFE_VOW_PERIODIC_CFG23   ((unsigned int)(PMIC_BASE+0x235c))
#define MT6358_AFE_VOW_PERIODIC_MON0 ((unsigned int)(PMIC_BASE+0x235e))
#define MT6358_AFE_VOW_PERIODIC_MON1 ((unsigned int)(PMIC_BASE+0x2360))
#define MT6358_AUDENC_DSN_ID ((unsigned int)(PMIC_BASE+0x2380))
#define MT6358_AUDENC_DSN_REV0 ((unsigned int)(PMIC_BASE+0x2382))
#define MT6358_AUDENC_DSN_DBI  ((unsigned int)(PMIC_BASE+0x2384))
#define MT6358_AUDENC_DSN_FPI  ((unsigned int)(PMIC_BASE+0x2386))
#define MT6358_AUDENC_ANA_CON0 ((unsigned int)(PMIC_BASE+0x2388))
#define MT6358_AUDENC_ANA_CON1 ((unsigned int)(PMIC_BASE+0x238a))
#define MT6358_AUDENC_ANA_CON2 ((unsigned int)(PMIC_BASE+0x238c))
#define MT6358_AUDENC_ANA_CON3 ((unsigned int)(PMIC_BASE+0x238e))
#define MT6358_AUDENC_ANA_CON4 ((unsigned int)(PMIC_BASE+0x2390))
#define MT6358_AUDENC_ANA_CON5 ((unsigned int)(PMIC_BASE+0x2392))
#define MT6358_AUDENC_ANA_CON6 ((unsigned int)(PMIC_BASE+0x2394))
#define MT6358_AUDENC_ANA_CON7 ((unsigned int)(PMIC_BASE+0x2396))
#define MT6358_AUDENC_ANA_CON8 ((unsigned int)(PMIC_BASE+0x2398))
#define MT6358_AUDENC_ANA_CON9 ((unsigned int)(PMIC_BASE+0x239a))
#define MT6358_AUDENC_ANA_CON10   ((unsigned int)(PMIC_BASE+0x239c))
#define MT6358_AUDENC_ANA_CON11   ((unsigned int)(PMIC_BASE+0x239e))
#define MT6358_AUDENC_ANA_CON12   ((unsigned int)(PMIC_BASE+0x23a0))
#define MT6358_AUDDEC_DSN_ID ((unsigned int)(PMIC_BASE+0x2400))
#define MT6358_AUDDEC_DSN_REV0 ((unsigned int)(PMIC_BASE+0x2402))
#define MT6358_AUDDEC_DSN_DBI  ((unsigned int)(PMIC_BASE+0x2404))
#define MT6358_AUDDEC_DSN_FPI  ((unsigned int)(PMIC_BASE+0x2406))
#define MT6358_AUDDEC_ANA_CON0 ((unsigned int)(PMIC_BASE+0x2408))
#define MT6358_AUDDEC_ANA_CON1 ((unsigned int)(PMIC_BASE+0x240a))
#define MT6358_AUDDEC_ANA_CON2 ((unsigned int)(PMIC_BASE+0x240c))
#define MT6358_AUDDEC_ANA_CON3 ((unsigned int)(PMIC_BASE+0x240e))
#define MT6358_AUDDEC_ANA_CON4 ((unsigned int)(PMIC_BASE+0x2410))
#define MT6358_AUDDEC_ANA_CON5 ((unsigned int)(PMIC_BASE+0x2412))
#define MT6358_AUDDEC_ANA_CON6 ((unsigned int)(PMIC_BASE+0x2414))
#define MT6358_AUDDEC_ANA_CON7 ((unsigned int)(PMIC_BASE+0x2416))
#define MT6358_AUDDEC_ANA_CON8 ((unsigned int)(PMIC_BASE+0x2418))
#define MT6358_AUDDEC_ANA_CON9 ((unsigned int)(PMIC_BASE+0x241a))
#define MT6358_AUDDEC_ANA_CON10   ((unsigned int)(PMIC_BASE+0x241c))
#define MT6358_AUDDEC_ANA_CON11   ((unsigned int)(PMIC_BASE+0x241e))
#define MT6358_AUDDEC_ANA_CON12   ((unsigned int)(PMIC_BASE+0x2420))
#define MT6358_AUDDEC_ANA_CON13   ((unsigned int)(PMIC_BASE+0x2422))
#define MT6358_AUDDEC_ANA_CON14   ((unsigned int)(PMIC_BASE+0x2424))
#define MT6358_AUDDEC_ANA_CON15   ((unsigned int)(PMIC_BASE+0x2426))
#define MT6358_AUDDEC_ELR_NUM  ((unsigned int)(PMIC_BASE+0x2428))
#define MT6358_AUDDEC_ELR_0  ((unsigned int)(PMIC_BASE+0x242a))
#define MT6358_AUDZCD_DSN_ID ((unsigned int)(PMIC_BASE+0x2480))
#define MT6358_AUDZCD_DSN_REV0 ((unsigned int)(PMIC_BASE+0x2482))
#define MT6358_AUDZCD_DSN_DBI  ((unsigned int)(PMIC_BASE+0x2484))
#define MT6358_AUDZCD_DSN_FPI  ((unsigned int)(PMIC_BASE+0x2486))
#define MT6358_ZCD_CON0  ((unsigned int)(PMIC_BASE+0x2488))
#define MT6358_ZCD_CON1  ((unsigned int)(PMIC_BASE+0x248a))
#define MT6358_ZCD_CON2  ((unsigned int)(PMIC_BASE+0x248c))
#define MT6358_ZCD_CON3  ((unsigned int)(PMIC_BASE+0x248e))
#define MT6358_ZCD_CON4  ((unsigned int)(PMIC_BASE+0x2490))
#define MT6358_ZCD_CON5  ((unsigned int)(PMIC_BASE+0x2492))
#define MT6358_ACCDET_DSN_DIG_ID  ((unsigned int)(PMIC_BASE+0x2500))
#define MT6358_ACCDET_DSN_DIG_REV0 ((unsigned int)(PMIC_BASE+0x2502))
#define MT6358_ACCDET_DSN_DBI  ((unsigned int)(PMIC_BASE+0x2504))
#define MT6358_ACCDET_DSN_FPI  ((unsigned int)(PMIC_BASE+0x2506))
#define MT6358_ACCDET_CON0   ((unsigned int)(PMIC_BASE+0x2508))
#define MT6358_ACCDET_CON1   ((unsigned int)(PMIC_BASE+0x250a))
#define MT6358_ACCDET_CON2   ((unsigned int)(PMIC_BASE+0x250c))
#define MT6358_ACCDET_CON3   ((unsigned int)(PMIC_BASE+0x250e))
#define MT6358_ACCDET_CON4   ((unsigned int)(PMIC_BASE+0x2510))
#define MT6358_ACCDET_CON5   ((unsigned int)(PMIC_BASE+0x2512))
#define MT6358_ACCDET_CON6   ((unsigned int)(PMIC_BASE+0x2514))
#define MT6358_ACCDET_CON7   ((unsigned int)(PMIC_BASE+0x2516))
#define MT6358_ACCDET_CON8   ((unsigned int)(PMIC_BASE+0x2518))
#define MT6358_ACCDET_CON9   ((unsigned int)(PMIC_BASE+0x251a))
#define MT6358_ACCDET_CON10  ((unsigned int)(PMIC_BASE+0x251c))
#define MT6358_ACCDET_CON11  ((unsigned int)(PMIC_BASE+0x251e))
#define MT6358_ACCDET_CON12  ((unsigned int)(PMIC_BASE+0x2520))
#define MT6358_ACCDET_CON13  ((unsigned int)(PMIC_BASE+0x2522))
#define MT6358_ACCDET_CON14  ((unsigned int)(PMIC_BASE+0x2524))
#define MT6358_ACCDET_CON15  ((unsigned int)(PMIC_BASE+0x2526))
#define MT6358_ACCDET_CON16  ((unsigned int)(PMIC_BASE+0x2528))
#define MT6358_ACCDET_CON17  ((unsigned int)(PMIC_BASE+0x252a))
#define MT6358_ACCDET_CON18  ((unsigned int)(PMIC_BASE+0x252c))
#define MT6358_ACCDET_CON19  ((unsigned int)(PMIC_BASE+0x252e))
#define MT6358_ACCDET_CON20  ((unsigned int)(PMIC_BASE+0x2530))
#define MT6358_ACCDET_CON21  ((unsigned int)(PMIC_BASE+0x2532))
#define MT6358_ACCDET_CON22  ((unsigned int)(PMIC_BASE+0x2534))
#define MT6358_ACCDET_CON23  ((unsigned int)(PMIC_BASE+0x2536))
#define MT6358_ACCDET_CON24  ((unsigned int)(PMIC_BASE+0x2538))
#define MT6358_ACCDET_CON25  ((unsigned int)(PMIC_BASE+0x253a))
#define MT6358_ACCDET_CON26  ((unsigned int)(PMIC_BASE+0x253c))
#define MT6358_ACCDET_CON27  ((unsigned int)(PMIC_BASE+0x253e))
#define MT6358_ACCDET_CON28  ((unsigned int)(PMIC_BASE+0x2540))
/* mask is HEX;  shift is Integer */
#define PMIC_TOP0_ANA_ID_ADDR   MT6358_TOP0_ID
#define PMIC_TOP0_ANA_ID_MASK   0xFF
#define PMIC_TOP0_ANA_ID_SHIFT  0
#define PMIC_TOP0_DIG_ID_ADDR   MT6358_TOP0_ID
#define PMIC_TOP0_DIG_ID_MASK   0xFF
#define PMIC_TOP0_DIG_ID_SHIFT  8
#define PMIC_TOP0_ANA_MINOR_REV_ADDR  MT6358_TOP0_REV0
#define PMIC_TOP0_ANA_MINOR_REV_MASK  0xF
#define PMIC_TOP0_ANA_MINOR_REV_SHIFT 0
#define PMIC_TOP0_ANA_MAJOR_REV_ADDR  MT6358_TOP0_REV0
#define PMIC_TOP0_ANA_MAJOR_REV_MASK  0xF
#define PMIC_TOP0_ANA_MAJOR_REV_SHIFT 4
#define PMIC_TOP0_DIG_MINOR_REV_ADDR  MT6358_TOP0_REV0
#define PMIC_TOP0_DIG_MINOR_REV_MASK  0xF
#define PMIC_TOP0_DIG_MINOR_REV_SHIFT 8
#define PMIC_TOP0_DIG_MAJOR_REV_ADDR  MT6358_TOP0_REV0
#define PMIC_TOP0_DIG_MAJOR_REV_MASK  0xF
#define PMIC_TOP0_DIG_MAJOR_REV_SHIFT 12
#define PMIC_TOP0_DSN_CBS_ADDR  MT6358_TOP0_DSN_DBI
#define PMIC_TOP0_DSN_CBS_MASK  0x3
#define PMIC_TOP0_DSN_CBS_SHIFT 0
#define PMIC_TOP0_DSN_BIX_ADDR  MT6358_TOP0_DSN_DBI
#define PMIC_TOP0_DSN_BIX_MASK  0x3
#define PMIC_TOP0_DSN_BIX_SHIFT 2
#define PMIC_TOP0_DSN_ESP_ADDR  MT6358_TOP0_DSN_DBI
#define PMIC_TOP0_DSN_ESP_MASK  0xFF
#define PMIC_TOP0_DSN_ESP_SHIFT 8
#define PMIC_TOP0_DSN_FPI_ADDR  MT6358_TOP0_DSN_DXI
#define PMIC_TOP0_DSN_FPI_MASK  0xFF
#define PMIC_TOP0_DSN_FPI_SHIFT 0
#define PMIC_HWCID_ADDR   MT6358_HWCID
#define PMIC_HWCID_MASK   0xFFFF
#define PMIC_HWCID_SHIFT  0
#define PMIC_SWCID_ADDR   MT6358_SWCID
#define PMIC_SWCID_MASK   0xFFFF
#define PMIC_SWCID_SHIFT  0
#define PMIC_STS_PWRKEY_ADDR MT6358_PONSTS
#define PMIC_STS_PWRKEY_MASK 0x1
#define PMIC_STS_PWRKEY_SHIFT   0
#define PMIC_STS_RTCA_ADDR  MT6358_PONSTS
#define PMIC_STS_RTCA_MASK  0x1
#define PMIC_STS_RTCA_SHIFT  1
#define PMIC_STS_CHRIN_ADDR  MT6358_PONSTS
#define PMIC_STS_CHRIN_MASK  0x1
#define PMIC_STS_CHRIN_SHIFT 2
#define PMIC_STS_SPAR_ADDR  MT6358_PONSTS
#define PMIC_STS_SPAR_MASK  0x1
#define PMIC_STS_SPAR_SHIFT  3
#define PMIC_STS_RBOOT_ADDR  MT6358_PONSTS
#define PMIC_STS_RBOOT_MASK  0x1
#define PMIC_STS_RBOOT_SHIFT 4
#define PMIC_STS_UVLO_ADDR  MT6358_POFFSTS
#define PMIC_STS_UVLO_MASK  0x1
#define PMIC_STS_UVLO_SHIFT  0
#define PMIC_STS_PGFAIL_ADDR MT6358_POFFSTS
#define PMIC_STS_PGFAIL_MASK 0x1
#define PMIC_STS_PGFAIL_SHIFT   1
#define PMIC_STS_PSOC_ADDR  MT6358_POFFSTS
#define PMIC_STS_PSOC_MASK  0x1
#define PMIC_STS_PSOC_SHIFT  2
#define PMIC_STS_THRDN_ADDR  MT6358_POFFSTS
#define PMIC_STS_THRDN_MASK  0x1
#define PMIC_STS_THRDN_SHIFT 3
#define PMIC_STS_WRST_ADDR  MT6358_POFFSTS
#define PMIC_STS_WRST_MASK  0x1
#define PMIC_STS_WRST_SHIFT  4
#define PMIC_STS_CRST_ADDR  MT6358_POFFSTS
#define PMIC_STS_CRST_MASK  0x1
#define PMIC_STS_CRST_SHIFT  5
#define PMIC_STS_PKEYLP_ADDR MT6358_POFFSTS
#define PMIC_STS_PKEYLP_MASK 0x1
#define PMIC_STS_PKEYLP_SHIFT   6
#define PMIC_STS_NORMOFF_ADDR   MT6358_POFFSTS
#define PMIC_STS_NORMOFF_MASK   0x1
#define PMIC_STS_NORMOFF_SHIFT  7
#define PMIC_STS_BWDT_ADDR  MT6358_POFFSTS
#define PMIC_STS_BWDT_MASK  0x1
#define PMIC_STS_BWDT_SHIFT  8
#define PMIC_STS_DDLO_ADDR  MT6358_POFFSTS
#define PMIC_STS_DDLO_MASK  0x1
#define PMIC_STS_DDLO_SHIFT  9
#define PMIC_STS_WDT_ADDR MT6358_POFFSTS
#define PMIC_STS_WDT_MASK 0x1
#define PMIC_STS_WDT_SHIFT  10
#define PMIC_STS_PUPSRC_ADDR MT6358_POFFSTS
#define PMIC_STS_PUPSRC_MASK 0x1
#define PMIC_STS_PUPSRC_SHIFT   11
#define PMIC_STS_KEYPWR_ADDR MT6358_POFFSTS
#define PMIC_STS_KEYPWR_MASK 0x1
#define PMIC_STS_KEYPWR_SHIFT   12
#define PMIC_STS_PKSP_ADDR  MT6358_POFFSTS
#define PMIC_STS_PKSP_MASK  0x1
#define PMIC_STS_PKSP_SHIFT  13
#define PMIC_RG_POFFSTS_CLR_ADDR  MT6358_PSTSCTL
#define PMIC_RG_POFFSTS_CLR_MASK  0x1
#define PMIC_RG_POFFSTS_CLR_SHIFT 0
#define PMIC_RG_PONSTS_CLR_ADDR MT6358_PSTSCTL
#define PMIC_RG_PONSTS_CLR_MASK 0x1
#define PMIC_RG_PONSTS_CLR_SHIFT  8
#define PMIC_VIO18_PG_DEB_ADDR  MT6358_PG_DEB_STS0
#define PMIC_VIO18_PG_DEB_MASK  0x1
#define PMIC_VIO18_PG_DEB_SHIFT 0
#define PMIC_VSRAM_PROC12_PG_DEB_ADDR MT6358_PG_DEB_STS0
#define PMIC_VSRAM_PROC12_PG_DEB_MASK 0x1
#define PMIC_VSRAM_PROC12_PG_DEB_SHIFT  1
#define PMIC_VSRAM_PROC11_PG_DEB_ADDR MT6358_PG_DEB_STS0
#define PMIC_VSRAM_PROC11_PG_DEB_MASK 0x1
#define PMIC_VSRAM_PROC11_PG_DEB_SHIFT  2
#define PMIC_VA12_PG_DEB_ADDR   MT6358_PG_DEB_STS0
#define PMIC_VA12_PG_DEB_MASK   0x1
#define PMIC_VA12_PG_DEB_SHIFT  3
#define PMIC_VSRAM_GPU_PG_DEB_ADDR MT6358_PG_DEB_STS0
#define PMIC_VSRAM_GPU_PG_DEB_MASK 0x1
#define PMIC_VSRAM_GPU_PG_DEB_SHIFT   4
#define PMIC_VSRAM_OTHERS_PG_DEB_ADDR MT6358_PG_DEB_STS0
#define PMIC_VSRAM_OTHERS_PG_DEB_MASK 0x1
#define PMIC_VSRAM_OTHERS_PG_DEB_SHIFT  5
#define PMIC_VAUX18_PG_DEB_ADDR MT6358_PG_DEB_STS0
#define PMIC_VAUX18_PG_DEB_MASK 0x1
#define PMIC_VAUX18_PG_DEB_SHIFT  6
#define PMIC_VXO22_PG_DEB_ADDR  MT6358_PG_DEB_STS0
#define PMIC_VXO22_PG_DEB_MASK  0x1
#define PMIC_VXO22_PG_DEB_SHIFT 7
#define PMIC_VDRAM1_PG_DEB_ADDR MT6358_PG_DEB_STS0
#define PMIC_VDRAM1_PG_DEB_MASK 0x1
#define PMIC_VDRAM1_PG_DEB_SHIFT  8
#define PMIC_VPROC12_PG_DEB_ADDR  MT6358_PG_DEB_STS0
#define PMIC_VPROC12_PG_DEB_MASK  0x1
#define PMIC_VPROC12_PG_DEB_SHIFT 9
#define PMIC_VPROC11_PG_DEB_ADDR  MT6358_PG_DEB_STS0
#define PMIC_VPROC11_PG_DEB_MASK  0x1
#define PMIC_VPROC11_PG_DEB_SHIFT 10
#define PMIC_VS1_PG_DEB_ADDR MT6358_PG_DEB_STS0
#define PMIC_VS1_PG_DEB_MASK 0x1
#define PMIC_VS1_PG_DEB_SHIFT   11
#define PMIC_VGPU_PG_DEB_ADDR   MT6358_PG_DEB_STS0
#define PMIC_VGPU_PG_DEB_MASK   0x1
#define PMIC_VGPU_PG_DEB_SHIFT  12
#define PMIC_VMODEM_PG_DEB_ADDR MT6358_PG_DEB_STS0
#define PMIC_VMODEM_PG_DEB_MASK 0x1
#define PMIC_VMODEM_PG_DEB_SHIFT  13
#define PMIC_VCORE_PG_DEB_ADDR  MT6358_PG_DEB_STS0
#define PMIC_VCORE_PG_DEB_MASK  0x1
#define PMIC_VCORE_PG_DEB_SHIFT 14
#define PMIC_VS2_PG_DEB_ADDR MT6358_PG_DEB_STS0
#define PMIC_VS2_PG_DEB_MASK 0x1
#define PMIC_VS2_PG_DEB_SHIFT   15
#define PMIC_RSV_PG_DEB_ADDR MT6358_PG_DEB_STS1
#define PMIC_RSV_PG_DEB_MASK 0x1
#define PMIC_RSV_PG_DEB_SHIFT   10
#define PMIC_VAUD28_PG_DEB_ADDR MT6358_PG_DEB_STS1
#define PMIC_VAUD28_PG_DEB_MASK 0x1
#define PMIC_VAUD28_PG_DEB_SHIFT  11
#define PMIC_VUSB_PG_DEB_ADDR   MT6358_PG_DEB_STS1
#define PMIC_VUSB_PG_DEB_MASK   0x1
#define PMIC_VUSB_PG_DEB_SHIFT  12
#define PMIC_VDRAM2_PG_DEB_ADDR MT6358_PG_DEB_STS1
#define PMIC_VDRAM2_PG_DEB_MASK 0x1
#define PMIC_VDRAM2_PG_DEB_SHIFT  13
#define PMIC_VIO28_PG_DEB_ADDR  MT6358_PG_DEB_STS1
#define PMIC_VIO28_PG_DEB_MASK  0x1
#define PMIC_VIO28_PG_DEB_SHIFT 14
#define PMIC_VEMC_PG_DEB_ADDR   MT6358_PG_DEB_STS1
#define PMIC_VEMC_PG_DEB_MASK   0x1
#define PMIC_VEMC_PG_DEB_SHIFT  15
#define PMIC_STRUP_VIO18_PG_STATUS_ADDR MT6358_PG_SDN_STS0
#define PMIC_STRUP_VIO18_PG_STATUS_MASK 0x1
#define PMIC_STRUP_VIO18_PG_STATUS_SHIFT   0
#define PMIC_STRUP_VSRAM_PROC12_PG_STATUS_ADDR   MT6358_PG_SDN_STS0
#define PMIC_STRUP_VSRAM_PROC12_PG_STATUS_MASK   0x1
#define PMIC_STRUP_VSRAM_PROC12_PG_STATUS_SHIFT  1
#define PMIC_STRUP_VSRAM_PROC11_PG_STATUS_ADDR   MT6358_PG_SDN_STS0
#define PMIC_STRUP_VSRAM_PROC11_PG_STATUS_MASK   0x1
#define PMIC_STRUP_VSRAM_PROC11_PG_STATUS_SHIFT  2
#define PMIC_STRUP_VA12_PG_STATUS_ADDR  MT6358_PG_SDN_STS0
#define PMIC_STRUP_VA12_PG_STATUS_MASK  0x1
#define PMIC_STRUP_VA12_PG_STATUS_SHIFT 3
#define PMIC_STRUP_VSRAM_GPU_PG_STATUS_ADDR MT6358_PG_SDN_STS0
#define PMIC_STRUP_VSRAM_GPU_PG_STATUS_MASK 0x1
#define PMIC_STRUP_VSRAM_GPU_PG_STATUS_SHIFT  4
#define PMIC_STRUP_VSRAM_OTHERS_PG_STATUS_ADDR   MT6358_PG_SDN_STS0
#define PMIC_STRUP_VSRAM_OTHERS_PG_STATUS_MASK   0x1
#define PMIC_STRUP_VSRAM_OTHERS_PG_STATUS_SHIFT  5
#define PMIC_STRUP_VAUX18_PG_STATUS_ADDR   MT6358_PG_SDN_STS0
#define PMIC_STRUP_VAUX18_PG_STATUS_MASK   0x1
#define PMIC_STRUP_VAUX18_PG_STATUS_SHIFT   6
#define PMIC_STRUP_VXO22_PG_STATUS_ADDR MT6358_PG_SDN_STS0
#define PMIC_STRUP_VXO22_PG_STATUS_MASK 0x1
#define PMIC_STRUP_VXO22_PG_STATUS_SHIFT   7
#define PMIC_STRUP_VDRAM1_PG_STATUS_ADDR   MT6358_PG_SDN_STS0
#define PMIC_STRUP_VDRAM1_PG_STATUS_MASK   0x1
#define PMIC_STRUP_VDRAM1_PG_STATUS_SHIFT   8
#define PMIC_STRUP_VPROC12_PG_STATUS_ADDR   MT6358_PG_SDN_STS0
#define PMIC_STRUP_VPROC12_PG_STATUS_MASK   0x1
#define PMIC_STRUP_VPROC12_PG_STATUS_SHIFT  9
#define PMIC_STRUP_VPROC11_PG_STATUS_ADDR   MT6358_PG_SDN_STS0
#define PMIC_STRUP_VPROC11_PG_STATUS_MASK   0x1
#define PMIC_STRUP_VPROC11_PG_STATUS_SHIFT  10
#define PMIC_STRUP_VS1_PG_STATUS_ADDR MT6358_PG_SDN_STS0
#define PMIC_STRUP_VS1_PG_STATUS_MASK 0x1
#define PMIC_STRUP_VS1_PG_STATUS_SHIFT  11
#define PMIC_STRUP_VGPU_PG_STATUS_ADDR  MT6358_PG_SDN_STS0
#define PMIC_STRUP_VGPU_PG_STATUS_MASK  0x1
#define PMIC_STRUP_VGPU_PG_STATUS_SHIFT 12
#define PMIC_STRUP_VMODEM_PG_STATUS_ADDR   MT6358_PG_SDN_STS0
#define PMIC_STRUP_VMODEM_PG_STATUS_MASK   0x1
#define PMIC_STRUP_VMODEM_PG_STATUS_SHIFT   13
#define PMIC_STRUP_VCORE_PG_STATUS_ADDR MT6358_PG_SDN_STS0
#define PMIC_STRUP_VCORE_PG_STATUS_MASK 0x1
#define PMIC_STRUP_VCORE_PG_STATUS_SHIFT   14
#define PMIC_STRUP_VS2_PG_STATUS_ADDR MT6358_PG_SDN_STS0
#define PMIC_STRUP_VS2_PG_STATUS_MASK 0x1
#define PMIC_STRUP_VS2_PG_STATUS_SHIFT  15
#define PMIC_STRUP_RSV_PG_STATUS_ADDR MT6358_PG_SDN_STS1
#define PMIC_STRUP_RSV_PG_STATUS_MASK 0x1
#define PMIC_STRUP_RSV_PG_STATUS_SHIFT  10
#define PMIC_STRUP_VAUD28_PG_STATUS_ADDR   MT6358_PG_SDN_STS1
#define PMIC_STRUP_VAUD28_PG_STATUS_MASK   0x1
#define PMIC_STRUP_VAUD28_PG_STATUS_SHIFT   11
#define PMIC_STRUP_VUSB_PG_STATUS_ADDR  MT6358_PG_SDN_STS1
#define PMIC_STRUP_VUSB_PG_STATUS_MASK  0x1
#define PMIC_STRUP_VUSB_PG_STATUS_SHIFT 12
#define PMIC_STRUP_VDRAM2_PG_STATUS_ADDR   MT6358_PG_SDN_STS1
#define PMIC_STRUP_VDRAM2_PG_STATUS_MASK   0x1
#define PMIC_STRUP_VDRAM2_PG_STATUS_SHIFT   13
#define PMIC_STRUP_VIO28_PG_STATUS_ADDR MT6358_PG_SDN_STS1
#define PMIC_STRUP_VIO28_PG_STATUS_MASK 0x1
#define PMIC_STRUP_VIO28_PG_STATUS_SHIFT   14
#define PMIC_STRUP_VEMC_PG_STATUS_ADDR  MT6358_PG_SDN_STS1
#define PMIC_STRUP_VEMC_PG_STATUS_MASK  0x1
#define PMIC_STRUP_VEMC_PG_STATUS_SHIFT 15
#define PMIC_STRUP_VDRAM1_OC_STATUS_ADDR   MT6358_OC_SDN_STS0
#define PMIC_STRUP_VDRAM1_OC_STATUS_MASK   0x1
#define PMIC_STRUP_VDRAM1_OC_STATUS_SHIFT   8
#define PMIC_STRUP_VPROC12_OC_STATUS_ADDR   MT6358_OC_SDN_STS0
#define PMIC_STRUP_VPROC12_OC_STATUS_MASK   0x1
#define PMIC_STRUP_VPROC12_OC_STATUS_SHIFT  9
#define PMIC_STRUP_VPROC11_OC_STATUS_ADDR   MT6358_OC_SDN_STS0
#define PMIC_STRUP_VPROC11_OC_STATUS_MASK   0x1
#define PMIC_STRUP_VPROC11_OC_STATUS_SHIFT  10
#define PMIC_STRUP_VS1_OC_STATUS_ADDR MT6358_OC_SDN_STS0
#define PMIC_STRUP_VS1_OC_STATUS_MASK 0x1
#define PMIC_STRUP_VS1_OC_STATUS_SHIFT  11
#define PMIC_STRUP_VGPU_OC_STATUS_ADDR  MT6358_OC_SDN_STS0
#define PMIC_STRUP_VGPU_OC_STATUS_MASK  0x1
#define PMIC_STRUP_VGPU_OC_STATUS_SHIFT 12
#define PMIC_STRUP_VMODEM_OC_STATUS_ADDR   MT6358_OC_SDN_STS0
#define PMIC_STRUP_VMODEM_OC_STATUS_MASK   0x1
#define PMIC_STRUP_VMODEM_OC_STATUS_SHIFT   13
#define PMIC_STRUP_VCORE_OC_STATUS_ADDR MT6358_OC_SDN_STS0
#define PMIC_STRUP_VCORE_OC_STATUS_MASK 0x1
#define PMIC_STRUP_VCORE_OC_STATUS_SHIFT   14
#define PMIC_STRUP_VS2_OC_STATUS_ADDR MT6358_OC_SDN_STS0
#define PMIC_STRUP_VS2_OC_STATUS_MASK 0x1
#define PMIC_STRUP_VS2_OC_STATUS_SHIFT  15
#define PMIC_PMU_THERMAL_DEB_ADDR MT6358_THERMALSTATUS
#define PMIC_PMU_THERMAL_DEB_MASK 0x1
#define PMIC_PMU_THERMAL_DEB_SHIFT 14
#define PMIC_STRUP_THERMAL_STATUS_ADDR  MT6358_THERMALSTATUS
#define PMIC_STRUP_THERMAL_STATUS_MASK  0x1
#define PMIC_STRUP_THERMAL_STATUS_SHIFT 15
#define PMIC_RG_SRCLKEN_IN0_EN_ADDR   MT6358_TOP_CON
#define PMIC_RG_SRCLKEN_IN0_EN_MASK   0x1
#define PMIC_RG_SRCLKEN_IN0_EN_SHIFT  0
#define PMIC_RG_SRCLKEN_IN0_HW_MODE_ADDR   MT6358_TOP_CON
#define PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK   0x1
#define PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT   1
#define PMIC_RG_SRCLKEN_IN1_EN_ADDR   MT6358_TOP_CON
#define PMIC_RG_SRCLKEN_IN1_EN_MASK   0x1
#define PMIC_RG_SRCLKEN_IN1_EN_SHIFT  2
#define PMIC_RG_SRCLKEN_IN1_HW_MODE_ADDR   MT6358_TOP_CON
#define PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK   0x1
#define PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT   3
#define PMIC_RG_SRCLKEN_IN_SYNC_EN_ADDR MT6358_TOP_CON
#define PMIC_RG_SRCLKEN_IN_SYNC_EN_MASK 0x1
#define PMIC_RG_SRCLKEN_IN_SYNC_EN_SHIFT   8
#define PMIC_RG_OSC_EN_AUTO_OFF_ADDR  MT6358_TOP_CON
#define PMIC_RG_OSC_EN_AUTO_OFF_MASK  0x1
#define PMIC_RG_OSC_EN_AUTO_OFF_SHIFT 9
#define PMIC_TEST_OUT_ADDR  MT6358_TEST_OUT
#define PMIC_TEST_OUT_MASK  0xFFF
#define PMIC_TEST_OUT_SHIFT  0
#define PMIC_RG_MON_FLAG_SEL_ADDR MT6358_TEST_CON0
#define PMIC_RG_MON_FLAG_SEL_MASK 0xFF
#define PMIC_RG_MON_FLAG_SEL_SHIFT 0
#define PMIC_RG_MON_GRP_SEL_ADDR  MT6358_TEST_CON0
#define PMIC_RG_MON_GRP_SEL_MASK  0x1F
#define PMIC_RG_MON_GRP_SEL_SHIFT 8
#define PMIC_RG_NANDTREE_MODE_ADDR MT6358_TEST_CON1
#define PMIC_RG_NANDTREE_MODE_MASK 0x1
#define PMIC_RG_NANDTREE_MODE_SHIFT   0
#define PMIC_RG_TEST_AUXADC_ADDR  MT6358_TEST_CON1
#define PMIC_RG_TEST_AUXADC_MASK  0x1
#define PMIC_RG_TEST_AUXADC_SHIFT 1
#define PMIC_RG_EFUSE_MODE_ADDR MT6358_TEST_CON1
#define PMIC_RG_EFUSE_MODE_MASK 0x1
#define PMIC_RG_EFUSE_MODE_SHIFT  2
#define PMIC_RG_TEST_STRUP_ADDR MT6358_TEST_CON1
#define PMIC_RG_TEST_STRUP_MASK 0x1
#define PMIC_RG_TEST_STRUP_SHIFT  3
#define PMIC_TESTMODE_SW_ADDR   MT6358_TESTMODE_SW
#define PMIC_TESTMODE_SW_MASK   0x1
#define PMIC_TESTMODE_SW_SHIFT  0
#define PMIC_PMU_TEST_MODE_SCAN_ADDR  MT6358_TOPSTATUS
#define PMIC_PMU_TEST_MODE_SCAN_MASK  0x1
#define PMIC_PMU_TEST_MODE_SCAN_SHIFT 0
#define PMIC_PWRKEY_DEB_ADDR MT6358_TOPSTATUS
#define PMIC_PWRKEY_DEB_MASK 0x1
#define PMIC_PWRKEY_DEB_SHIFT   1
#define PMIC_CHRDET_DEB_ADDR MT6358_TOPSTATUS
#define PMIC_CHRDET_DEB_MASK 0x1
#define PMIC_CHRDET_DEB_SHIFT   2
#define PMIC_HOMEKEY_DEB_ADDR   MT6358_TOPSTATUS
#define PMIC_HOMEKEY_DEB_MASK   0x1
#define PMIC_HOMEKEY_DEB_SHIFT  3
#define PMIC_RG_PMU_TDSEL_ADDR  MT6358_TDSEL_CON
#define PMIC_RG_PMU_TDSEL_MASK  0x1
#define PMIC_RG_PMU_TDSEL_SHIFT 0
#define PMIC_RG_SPI_TDSEL_ADDR  MT6358_TDSEL_CON
#define PMIC_RG_SPI_TDSEL_MASK  0x1
#define PMIC_RG_SPI_TDSEL_SHIFT 1
#define PMIC_RG_AUD_TDSEL_ADDR  MT6358_TDSEL_CON
#define PMIC_RG_AUD_TDSEL_MASK  0x1
#define PMIC_RG_AUD_TDSEL_SHIFT 2
#define PMIC_RG_E32CAL_TDSEL_ADDR MT6358_TDSEL_CON
#define PMIC_RG_E32CAL_TDSEL_MASK 0x1
#define PMIC_RG_E32CAL_TDSEL_SHIFT 3
#define PMIC_RG_PMU_RDSEL_ADDR  MT6358_RDSEL_CON
#define PMIC_RG_PMU_RDSEL_MASK  0x1
#define PMIC_RG_PMU_RDSEL_SHIFT 0
#define PMIC_RG_SPI_RDSEL_ADDR  MT6358_RDSEL_CON
#define PMIC_RG_SPI_RDSEL_MASK  0x1
#define PMIC_RG_SPI_RDSEL_SHIFT 1
#define PMIC_RG_AUD_RDSEL_ADDR  MT6358_RDSEL_CON
#define PMIC_RG_AUD_RDSEL_MASK  0x1
#define PMIC_RG_AUD_RDSEL_SHIFT 2
#define PMIC_RG_E32CAL_RDSEL_ADDR MT6358_RDSEL_CON
#define PMIC_RG_E32CAL_RDSEL_MASK 0x1
#define PMIC_RG_E32CAL_RDSEL_SHIFT 3
#define PMIC_RG_SMT_WDTRSTB_IN_ADDR   MT6358_SMT_CON0
#define PMIC_RG_SMT_WDTRSTB_IN_MASK   0x1
#define PMIC_RG_SMT_WDTRSTB_IN_SHIFT  0
#define PMIC_RG_SMT_SRCLKEN_IN0_ADDR  MT6358_SMT_CON0
#define PMIC_RG_SMT_SRCLKEN_IN0_MASK  0x1
#define PMIC_RG_SMT_SRCLKEN_IN0_SHIFT 1
#define PMIC_RG_SMT_SRCLKEN_IN1_ADDR  MT6358_SMT_CON0
#define PMIC_RG_SMT_SRCLKEN_IN1_MASK  0x1
#define PMIC_RG_SMT_SRCLKEN_IN1_SHIFT 2
#define PMIC_RG_SMT_RTC_32K1V8_0_ADDR MT6358_SMT_CON0
#define PMIC_RG_SMT_RTC_32K1V8_0_MASK 0x1
#define PMIC_RG_SMT_RTC_32K1V8_0_SHIFT  3
#define PMIC_RG_SMT_RTC_32K1V8_1_ADDR MT6358_SMT_CON0
#define PMIC_RG_SMT_RTC_32K1V8_1_MASK 0x1
#define PMIC_RG_SMT_RTC_32K1V8_1_SHIFT  4
#define PMIC_RG_SMT_HOMEKEY_ADDR  MT6358_SMT_CON0
#define PMIC_RG_SMT_HOMEKEY_MASK  0x1
#define PMIC_RG_SMT_HOMEKEY_SHIFT 5
#define PMIC_RG_SMT_SCP_VREQ_VAO_ADDR MT6358_SMT_CON0
#define PMIC_RG_SMT_SCP_VREQ_VAO_MASK 0x1
#define PMIC_RG_SMT_SCP_VREQ_VAO_SHIFT  6
#define PMIC_RG_SMT_SD_CARD_DET_N_ADDR  MT6358_SMT_CON0
#define PMIC_RG_SMT_SD_CARD_DET_N_MASK  0x1
#define PMIC_RG_SMT_SD_CARD_DET_N_SHIFT 7
#define PMIC_RG_SMT_SPI_CLK_ADDR  MT6358_SMT_CON1
#define PMIC_RG_SMT_SPI_CLK_MASK  0x1
#define PMIC_RG_SMT_SPI_CLK_SHIFT 0
#define PMIC_RG_SMT_SPI_CSN_ADDR  MT6358_SMT_CON1
#define PMIC_RG_SMT_SPI_CSN_MASK  0x1
#define PMIC_RG_SMT_SPI_CSN_SHIFT 1
#define PMIC_RG_SMT_SPI_MOSI_ADDR MT6358_SMT_CON1
#define PMIC_RG_SMT_SPI_MOSI_MASK 0x1
#define PMIC_RG_SMT_SPI_MOSI_SHIFT 2
#define PMIC_RG_SMT_SPI_MISO_ADDR MT6358_SMT_CON1
#define PMIC_RG_SMT_SPI_MISO_MASK 0x1
#define PMIC_RG_SMT_SPI_MISO_SHIFT 3
#define PMIC_RG_SMT_AUD_CLK_MOSI_ADDR MT6358_SMT_CON1
#define PMIC_RG_SMT_AUD_CLK_MOSI_MASK 0x1
#define PMIC_RG_SMT_AUD_CLK_MOSI_SHIFT  4
#define PMIC_RG_SMT_AUD_DAT_MOSI0_ADDR  MT6358_SMT_CON1
#define PMIC_RG_SMT_AUD_DAT_MOSI0_MASK  0x1
#define PMIC_RG_SMT_AUD_DAT_MOSI0_SHIFT 5
#define PMIC_RG_SMT_AUD_DAT_MOSI1_ADDR  MT6358_SMT_CON1
#define PMIC_RG_SMT_AUD_DAT_MOSI1_MASK  0x1
#define PMIC_RG_SMT_AUD_DAT_MOSI1_SHIFT 6
#define PMIC_RG_SMT_AUD_SYNC_MOSI_ADDR  MT6358_SMT_CON1
#define PMIC_RG_SMT_AUD_SYNC_MOSI_MASK  0x1
#define PMIC_RG_SMT_AUD_SYNC_MOSI_SHIFT 7
#define PMIC_RG_SMT_AUD_CLK_MISO_ADDR MT6358_SMT_CON1
#define PMIC_RG_SMT_AUD_CLK_MISO_MASK 0x1
#define PMIC_RG_SMT_AUD_CLK_MISO_SHIFT  8
#define PMIC_RG_SMT_AUD_DAT_MISO0_ADDR  MT6358_SMT_CON1
#define PMIC_RG_SMT_AUD_DAT_MISO0_MASK  0x1
#define PMIC_RG_SMT_AUD_DAT_MISO0_SHIFT 9
#define PMIC_RG_SMT_AUD_DAT_MISO1_ADDR  MT6358_SMT_CON1
#define PMIC_RG_SMT_AUD_DAT_MISO1_MASK  0x1
#define PMIC_RG_SMT_AUD_DAT_MISO1_SHIFT 10
#define PMIC_RG_SMT_AUD_SYNC_MISO_ADDR  MT6358_SMT_CON1
#define PMIC_RG_SMT_AUD_SYNC_MISO_MASK  0x1
#define PMIC_RG_SMT_AUD_SYNC_MISO_SHIFT 11
#define PMIC_RG_TOP_RSV0_ADDR   MT6358_TOP_RSV0
#define PMIC_RG_TOP_RSV0_MASK   0x1
#define PMIC_RG_TOP_RSV0_SHIFT  0
#define PMIC_RG_TOP_RSV1_ADDR   MT6358_TOP_RSV1
#define PMIC_RG_TOP_RSV1_MASK   0x1
#define PMIC_RG_TOP_RSV1_SHIFT  0
#define PMIC_RG_OCTL_SRCLKEN_IN0_ADDR MT6358_DRV_CON0
#define PMIC_RG_OCTL_SRCLKEN_IN0_MASK 0xF
#define PMIC_RG_OCTL_SRCLKEN_IN0_SHIFT  0
#define PMIC_RG_OCTL_SRCLKEN_IN1_ADDR MT6358_DRV_CON0
#define PMIC_RG_OCTL_SRCLKEN_IN1_MASK 0xF
#define PMIC_RG_OCTL_SRCLKEN_IN1_SHIFT  4
#define PMIC_RG_OCTL_RTC_32K1V8_0_ADDR  MT6358_DRV_CON0
#define PMIC_RG_OCTL_RTC_32K1V8_0_MASK  0xF
#define PMIC_RG_OCTL_RTC_32K1V8_0_SHIFT 8
#define PMIC_RG_OCTL_RTC_32K1V8_1_ADDR  MT6358_DRV_CON0
#define PMIC_RG_OCTL_RTC_32K1V8_1_MASK  0xF
#define PMIC_RG_OCTL_RTC_32K1V8_1_SHIFT 12
#define PMIC_RG_OCTL_SPI_CLK_ADDR MT6358_DRV_CON1
#define PMIC_RG_OCTL_SPI_CLK_MASK 0xF
#define PMIC_RG_OCTL_SPI_CLK_SHIFT 0
#define PMIC_RG_OCTL_SPI_CSN_ADDR MT6358_DRV_CON1
#define PMIC_RG_OCTL_SPI_CSN_MASK 0xF
#define PMIC_RG_OCTL_SPI_CSN_SHIFT 4
#define PMIC_RG_OCTL_SPI_MOSI_ADDR MT6358_DRV_CON1
#define PMIC_RG_OCTL_SPI_MOSI_MASK 0xF
#define PMIC_RG_OCTL_SPI_MOSI_SHIFT   8
#define PMIC_RG_OCTL_SPI_MISO_ADDR MT6358_DRV_CON1
#define PMIC_RG_OCTL_SPI_MISO_MASK 0xF
#define PMIC_RG_OCTL_SPI_MISO_SHIFT   12
#define PMIC_RG_OCTL_AUD_CLK_MOSI_ADDR  MT6358_DRV_CON2
#define PMIC_RG_OCTL_AUD_CLK_MOSI_MASK  0xF
#define PMIC_RG_OCTL_AUD_CLK_MOSI_SHIFT 0
#define PMIC_RG_OCTL_AUD_DAT_MOSI0_ADDR MT6358_DRV_CON2
#define PMIC_RG_OCTL_AUD_DAT_MOSI0_MASK 0xF
#define PMIC_RG_OCTL_AUD_DAT_MOSI0_SHIFT   4
#define PMIC_RG_OCTL_AUD_DAT_MOSI1_ADDR MT6358_DRV_CON2
#define PMIC_RG_OCTL_AUD_DAT_MOSI1_MASK 0xF
#define PMIC_RG_OCTL_AUD_DAT_MOSI1_SHIFT   8
#define PMIC_RG_OCTL_AUD_SYNC_MOSI_ADDR MT6358_DRV_CON2
#define PMIC_RG_OCTL_AUD_SYNC_MOSI_MASK 0xF
#define PMIC_RG_OCTL_AUD_SYNC_MOSI_SHIFT   12
#define PMIC_RG_OCTL_AUD_CLK_MISO_ADDR  MT6358_DRV_CON3
#define PMIC_RG_OCTL_AUD_CLK_MISO_MASK  0xF
#define PMIC_RG_OCTL_AUD_CLK_MISO_SHIFT 0
#define PMIC_RG_OCTL_AUD_DAT_MISO0_ADDR MT6358_DRV_CON3
#define PMIC_RG_OCTL_AUD_DAT_MISO0_MASK 0xF
#define PMIC_RG_OCTL_AUD_DAT_MISO0_SHIFT   4
#define PMIC_RG_OCTL_AUD_DAT_MISO1_ADDR MT6358_DRV_CON3
#define PMIC_RG_OCTL_AUD_DAT_MISO1_MASK 0xF
#define PMIC_RG_OCTL_AUD_DAT_MISO1_SHIFT   8
#define PMIC_RG_OCTL_AUD_SYNC_MISO_ADDR MT6358_DRV_CON3
#define PMIC_RG_OCTL_AUD_SYNC_MISO_MASK 0xF
#define PMIC_RG_OCTL_AUD_SYNC_MISO_SHIFT   12
#define PMIC_RG_OCTL_HOMEKEY_ADDR MT6358_DRV_CON4
#define PMIC_RG_OCTL_HOMEKEY_MASK 0xF
#define PMIC_RG_OCTL_HOMEKEY_SHIFT 0
#define PMIC_RG_OCTL_SCP_VREQ_VAO_ADDR  MT6358_DRV_CON4
#define PMIC_RG_OCTL_SCP_VREQ_VAO_MASK  0xF
#define PMIC_RG_OCTL_SCP_VREQ_VAO_SHIFT 4
#define PMIC_RG_OCTL_SD_CARD_DET_N_ADDR MT6358_DRV_CON4
#define PMIC_RG_OCTL_SD_CARD_DET_N_MASK 0xF
#define PMIC_RG_OCTL_SD_CARD_DET_N_SHIFT   8
#define PMIC_RG_SRCLKEN_IN0_FILTER_EN_ADDR  MT6358_FILTER_CON0
#define PMIC_RG_SRCLKEN_IN0_FILTER_EN_MASK  0x1
#define PMIC_RG_SRCLKEN_IN0_FILTER_EN_SHIFT 0
#define PMIC_RG_SRCLKEN_IN1_FILTER_EN_ADDR  MT6358_FILTER_CON0
#define PMIC_RG_SRCLKEN_IN1_FILTER_EN_MASK  0x1
#define PMIC_RG_SRCLKEN_IN1_FILTER_EN_SHIFT 1
#define PMIC_RG_RTC32K_1V8_0_FILTER_EN_ADDR MT6358_FILTER_CON0
#define PMIC_RG_RTC32K_1V8_0_FILTER_EN_MASK 0x1
#define PMIC_RG_RTC32K_1V8_0_FILTER_EN_SHIFT  2
#define PMIC_RG_RTC32K_1V8_1_FILTER_EN_ADDR MT6358_FILTER_CON0
#define PMIC_RG_RTC32K_1V8_1_FILTER_EN_MASK 0x1
#define PMIC_RG_RTC32K_1V8_1_FILTER_EN_SHIFT  3
#define PMIC_RG_SPI_CLK_FILTER_EN_ADDR  MT6358_FILTER_CON0
#define PMIC_RG_SPI_CLK_FILTER_EN_MASK  0x1
#define PMIC_RG_SPI_CLK_FILTER_EN_SHIFT 4
#define PMIC_RG_SPI_CSN_FILTER_EN_ADDR  MT6358_FILTER_CON0
#define PMIC_RG_SPI_CSN_FILTER_EN_MASK  0x1
#define PMIC_RG_SPI_CSN_FILTER_EN_SHIFT 5
#define PMIC_RG_SPI_MOSI_FILTER_EN_ADDR MT6358_FILTER_CON0
#define PMIC_RG_SPI_MOSI_FILTER_EN_MASK 0x1
#define PMIC_RG_SPI_MOSI_FILTER_EN_SHIFT   6
#define PMIC_RG_SPI_MISO_FILTER_EN_ADDR MT6358_FILTER_CON0
#define PMIC_RG_SPI_MISO_FILTER_EN_MASK 0x1
#define PMIC_RG_SPI_MISO_FILTER_EN_SHIFT   7
#define PMIC_RG_AUD_CLK_MOSI_FILTER_EN_ADDR MT6358_FILTER_CON0
#define PMIC_RG_AUD_CLK_MOSI_FILTER_EN_MASK 0x1
#define PMIC_RG_AUD_CLK_MOSI_FILTER_EN_SHIFT  8
#define PMIC_RG_AUD_DAT_MOSI0_FILTER_EN_ADDR  MT6358_FILTER_CON0
#define PMIC_RG_AUD_DAT_MOSI0_FILTER_EN_MASK  0x1
#define PMIC_RG_AUD_DAT_MOSI0_FILTER_EN_SHIFT 9
#define PMIC_RG_AUD_DAT_MOSI1_FILTER_EN_ADDR  MT6358_FILTER_CON0
#define PMIC_RG_AUD_DAT_MOSI1_FILTER_EN_MASK  0x1
#define PMIC_RG_AUD_DAT_MOSI1_FILTER_EN_SHIFT 10
#define PMIC_RG_AUD_SYNC_MOSI_FILTER_EN_ADDR  MT6358_FILTER_CON0
#define PMIC_RG_AUD_SYNC_MOSI_FILTER_EN_MASK  0x1
#define PMIC_RG_AUD_SYNC_MOSI_FILTER_EN_SHIFT 11
#define PMIC_RG_AUD_CLK_MISO_FILTER_EN_ADDR MT6358_FILTER_CON0
#define PMIC_RG_AUD_CLK_MISO_FILTER_EN_MASK 0x1
#define PMIC_RG_AUD_CLK_MISO_FILTER_EN_SHIFT  12
#define PMIC_RG_AUD_DAT_MISO0_FILTER_EN_ADDR  MT6358_FILTER_CON0
#define PMIC_RG_AUD_DAT_MISO0_FILTER_EN_MASK  0x1
#define PMIC_RG_AUD_DAT_MISO0_FILTER_EN_SHIFT 13
#define PMIC_RG_AUD_DAT_MISO1_FILTER_EN_ADDR  MT6358_FILTER_CON0
#define PMIC_RG_AUD_DAT_MISO1_FILTER_EN_MASK  0x1
#define PMIC_RG_AUD_DAT_MISO1_FILTER_EN_SHIFT 14
#define PMIC_RG_AUD_SYNC_MISO_FILTER_EN_ADDR  MT6358_FILTER_CON0
#define PMIC_RG_AUD_SYNC_MISO_FILTER_EN_MASK  0x1
#define PMIC_RG_AUD_SYNC_MISO_FILTER_EN_SHIFT 15
#define PMIC_RG_WDTRSTB_IN_FILTER_EN_ADDR   MT6358_FILTER_CON1
#define PMIC_RG_WDTRSTB_IN_FILTER_EN_MASK   0x1
#define PMIC_RG_WDTRSTB_IN_FILTER_EN_SHIFT  0
#define PMIC_RG_HOMEKEY_FILTER_EN_ADDR  MT6358_FILTER_CON1
#define PMIC_RG_HOMEKEY_FILTER_EN_MASK  0x1
#define PMIC_RG_HOMEKEY_FILTER_EN_SHIFT 1
#define PMIC_RG_SCP_VREQ_VAO_FILTER_EN_ADDR MT6358_FILTER_CON1
#define PMIC_RG_SCP_VREQ_VAO_FILTER_EN_MASK 0x1
#define PMIC_RG_SCP_VREQ_VAO_FILTER_EN_SHIFT  2
#define PMIC_RG_SD_CARD_DET_N_FILTER_EN_ADDR  MT6358_FILTER_CON1
#define PMIC_RG_SD_CARD_DET_N_FILTER_EN_MASK  0x1
#define PMIC_RG_SD_CARD_DET_N_FILTER_EN_SHIFT 3
#define PMIC_RG_SRCLKEN_IN0_RCSEL_ADDR  MT6358_FILTER_CON2
#define PMIC_RG_SRCLKEN_IN0_RCSEL_MASK  0x1
#define PMIC_RG_SRCLKEN_IN0_RCSEL_SHIFT 0
#define PMIC_RG_SRCLKEN_IN1_RCSEL_ADDR  MT6358_FILTER_CON2
#define PMIC_RG_SRCLKEN_IN1_RCSEL_MASK  0x1
#define PMIC_RG_SRCLKEN_IN1_RCSEL_SHIFT 1
#define PMIC_RG_RTC32K_1V8_0_RCSEL_ADDR MT6358_FILTER_CON2
#define PMIC_RG_RTC32K_1V8_0_RCSEL_MASK 0x1
#define PMIC_RG_RTC32K_1V8_0_RCSEL_SHIFT   2
#define PMIC_RG_RTC32K_1V8_1_RCSEL_ADDR MT6358_FILTER_CON2
#define PMIC_RG_RTC32K_1V8_1_RCSEL_MASK 0x1
#define PMIC_RG_RTC32K_1V8_1_RCSEL_SHIFT   3
#define PMIC_RG_SPI_CLK_RCSEL_ADDR MT6358_FILTER_CON2
#define PMIC_RG_SPI_CLK_RCSEL_MASK 0x1
#define PMIC_RG_SPI_CLK_RCSEL_SHIFT   4
#define PMIC_RG_SPI_CSN_RCSEL_ADDR MT6358_FILTER_CON2
#define PMIC_RG_SPI_CSN_RCSEL_MASK 0x1
#define PMIC_RG_SPI_CSN_RCSEL_SHIFT   5
#define PMIC_RG_SPI_MOSI_RCSEL_ADDR   MT6358_FILTER_CON2
#define PMIC_RG_SPI_MOSI_RCSEL_MASK   0x1
#define PMIC_RG_SPI_MOSI_RCSEL_SHIFT  6
#define PMIC_RG_SPI_MISO_RCSEL_ADDR   MT6358_FILTER_CON2
#define PMIC_RG_SPI_MISO_RCSEL_MASK   0x1
#define PMIC_RG_SPI_MISO_RCSEL_SHIFT  7
#define PMIC_RG_AUD_CLK_MOSI_RCSEL_ADDR MT6358_FILTER_CON2
#define PMIC_RG_AUD_CLK_MOSI_RCSEL_MASK 0x1
#define PMIC_RG_AUD_CLK_MOSI_RCSEL_SHIFT   8
#define PMIC_RG_AUD_DAT_MOSI0_RCSEL_ADDR   MT6358_FILTER_CON2
#define PMIC_RG_AUD_DAT_MOSI0_RCSEL_MASK   0x1
#define PMIC_RG_AUD_DAT_MOSI0_RCSEL_SHIFT   9
#define PMIC_RG_AUD_DAT_MOSI1_RCSEL_ADDR   MT6358_FILTER_CON2
#define PMIC_RG_AUD_DAT_MOSI1_RCSEL_MASK   0x1
#define PMIC_RG_AUD_DAT_MOSI1_RCSEL_SHIFT   10
#define PMIC_RG_AUD_SYNC_MOSI_RCSEL_ADDR   MT6358_FILTER_CON2
#define PMIC_RG_AUD_SYNC_MOSI_RCSEL_MASK   0x1
#define PMIC_RG_AUD_SYNC_MOSI_RCSEL_SHIFT   11
#define PMIC_RG_AUD_CLK_MISO_RCSEL_ADDR MT6358_FILTER_CON2
#define PMIC_RG_AUD_CLK_MISO_RCSEL_MASK 0x1
#define PMIC_RG_AUD_CLK_MISO_RCSEL_SHIFT   12
#define PMIC_RG_AUD_DAT_MISO0_RCSEL_ADDR   MT6358_FILTER_CON2
#define PMIC_RG_AUD_DAT_MISO0_RCSEL_MASK   0x1
#define PMIC_RG_AUD_DAT_MISO0_RCSEL_SHIFT   13
#define PMIC_RG_AUD_DAT_MISO1_RCSEL_ADDR   MT6358_FILTER_CON2
#define PMIC_RG_AUD_DAT_MISO1_RCSEL_MASK   0x1
#define PMIC_RG_AUD_DAT_MISO1_RCSEL_SHIFT   14
#define PMIC_RG_AUD_SYNC_MISO_RCSEL_ADDR   MT6358_FILTER_CON2
#define PMIC_RG_AUD_SYNC_MISO_RCSEL_MASK   0x1
#define PMIC_RG_AUD_SYNC_MISO_RCSEL_SHIFT   15
#define PMIC_RG_WDTRSTB_IN_RCSEL_ADDR MT6358_FILTER_CON3
#define PMIC_RG_WDTRSTB_IN_RCSEL_MASK 0x1
#define PMIC_RG_WDTRSTB_IN_RCSEL_SHIFT  0
#define PMIC_RG_HOMEKEY_RCSEL_ADDR MT6358_FILTER_CON3
#define PMIC_RG_HOMEKEY_RCSEL_MASK 0x1
#define PMIC_RG_HOMEKEY_RCSEL_SHIFT   1
#define PMIC_RG_SCP_VREQ_VAO_RCSEL_ADDR MT6358_FILTER_CON3
#define PMIC_RG_SCP_VREQ_VAO_RCSEL_MASK 0x1
#define PMIC_RG_SCP_VREQ_VAO_RCSEL_SHIFT   2
#define PMIC_RG_SD_CARD_DET_N_RCSEL_ADDR   MT6358_FILTER_CON3
#define PMIC_RG_SD_CARD_DET_N_RCSEL_MASK   0x1
#define PMIC_RG_SD_CARD_DET_N_RCSEL_SHIFT   3
#define PMIC_TOP_STATUS_ADDR MT6358_TOP_STATUS
#define PMIC_TOP_STATUS_MASK 0xF
#define PMIC_TOP_STATUS_SHIFT   0
#define PMIC_TOP_STATUS_SET_ADDR  MT6358_TOP_STATUS_SET
#define PMIC_TOP_STATUS_SET_MASK  0x3
#define PMIC_TOP_STATUS_SET_SHIFT 0
#define PMIC_TOP_STATUS_CLR_ADDR  MT6358_TOP_STATUS_CLR
#define PMIC_TOP_STATUS_CLR_MASK  0x3
#define PMIC_TOP_STATUS_CLR_SHIFT 0
#define PMIC_VM_MODE_ADDR MT6358_TOP_TRAP
#define PMIC_VM_MODE_MASK 0x3
#define PMIC_VM_MODE_SHIFT  0
#define PMIC_TOP1_ANA_ID_ADDR   MT6358_TOP1_ID
#define PMIC_TOP1_ANA_ID_MASK   0xFF
#define PMIC_TOP1_ANA_ID_SHIFT  0
#define PMIC_TOP1_DIG_ID_ADDR   MT6358_TOP1_ID
#define PMIC_TOP1_DIG_ID_MASK   0xFF
#define PMIC_TOP1_DIG_ID_SHIFT  8
#define PMIC_TOP1_ANA_MINOR_REV_ADDR  MT6358_TOP1_REV0
#define PMIC_TOP1_ANA_MINOR_REV_MASK  0xF
#define PMIC_TOP1_ANA_MINOR_REV_SHIFT 0
#define PMIC_TOP1_ANA_MAJOR_REV_ADDR  MT6358_TOP1_REV0
#define PMIC_TOP1_ANA_MAJOR_REV_MASK  0xF
#define PMIC_TOP1_ANA_MAJOR_REV_SHIFT 4
#define PMIC_TOP1_DIG_MINOR_REV_ADDR  MT6358_TOP1_REV0
#define PMIC_TOP1_DIG_MINOR_REV_MASK  0xF
#define PMIC_TOP1_DIG_MINOR_REV_SHIFT 8
#define PMIC_TOP1_DIG_MAJOR_REV_ADDR  MT6358_TOP1_REV0
#define PMIC_TOP1_DIG_MAJOR_REV_MASK  0xF
#define PMIC_TOP1_DIG_MAJOR_REV_SHIFT 12
#define PMIC_TOP1_DSN_CBS_ADDR  MT6358_TOP1_DSN_DBI
#define PMIC_TOP1_DSN_CBS_MASK  0x3
#define PMIC_TOP1_DSN_CBS_SHIFT 0
#define PMIC_TOP1_DSN_BIX_ADDR  MT6358_TOP1_DSN_DBI
#define PMIC_TOP1_DSN_BIX_MASK  0x3
#define PMIC_TOP1_DSN_BIX_SHIFT 2
#define PMIC_TOP1_DSN_ESP_ADDR  MT6358_TOP1_DSN_DBI
#define PMIC_TOP1_DSN_ESP_MASK  0xFF
#define PMIC_TOP1_DSN_ESP_SHIFT 8
#define PMIC_TOP1_DSN_FPI_ADDR  MT6358_TOP1_DSN_DXI
#define PMIC_TOP1_DSN_FPI_MASK  0xFF
#define PMIC_TOP1_DSN_FPI_SHIFT 0
#define PMIC_GPIO_DIR0_ADDR  MT6358_GPIO_DIR0
#define PMIC_GPIO_DIR0_MASK  0xFFFF
#define PMIC_GPIO_DIR0_SHIFT 0
#define PMIC_GPIO_DIR0_SET_ADDR MT6358_GPIO_DIR0_SET
#define PMIC_GPIO_DIR0_SET_MASK 0xFFFF
#define PMIC_GPIO_DIR0_SET_SHIFT  0
#define PMIC_GPIO_DIR0_CLR_ADDR MT6358_GPIO_DIR0_CLR
#define PMIC_GPIO_DIR0_CLR_MASK 0xFFFF
#define PMIC_GPIO_DIR0_CLR_SHIFT  0
#define PMIC_GPIO_DIR1_ADDR  MT6358_GPIO_DIR1
#define PMIC_GPIO_DIR1_MASK  0x7
#define PMIC_GPIO_DIR1_SHIFT 0
#define PMIC_GPIO_DIR1_SET_ADDR MT6358_GPIO_DIR1_SET
#define PMIC_GPIO_DIR1_SET_MASK 0xFFFF
#define PMIC_GPIO_DIR1_SET_SHIFT  0
#define PMIC_GPIO_DIR1_CLR_ADDR MT6358_GPIO_DIR1_CLR
#define PMIC_GPIO_DIR1_CLR_MASK 0xFFFF
#define PMIC_GPIO_DIR1_CLR_SHIFT  0
#define PMIC_GPIO_PULLEN0_ADDR  MT6358_GPIO_PULLEN0
#define PMIC_GPIO_PULLEN0_MASK  0xFFFF
#define PMIC_GPIO_PULLEN0_SHIFT 0
#define PMIC_GPIO_PULLEN0_SET_ADDR MT6358_GPIO_PULLEN0_SET
#define PMIC_GPIO_PULLEN0_SET_MASK 0xFFFF
#define PMIC_GPIO_PULLEN0_SET_SHIFT   0
#define PMIC_GPIO_PULLEN0_CLR_ADDR MT6358_GPIO_PULLEN0_CLR
#define PMIC_GPIO_PULLEN0_CLR_MASK 0xFFFF
#define PMIC_GPIO_PULLEN0_CLR_SHIFT   0
#define PMIC_GPIO_PULLEN1_ADDR  MT6358_GPIO_PULLEN1
#define PMIC_GPIO_PULLEN1_MASK  0x7
#define PMIC_GPIO_PULLEN1_SHIFT 0
#define PMIC_GPIO_PULLEN1_SET_ADDR MT6358_GPIO_PULLEN1_SET
#define PMIC_GPIO_PULLEN1_SET_MASK 0xFFFF
#define PMIC_GPIO_PULLEN1_SET_SHIFT   0
#define PMIC_GPIO_PULLEN1_CLR_ADDR MT6358_GPIO_PULLEN1_CLR
#define PMIC_GPIO_PULLEN1_CLR_MASK 0xFFFF
#define PMIC_GPIO_PULLEN1_CLR_SHIFT   0
#define PMIC_GPIO_PULLSEL0_ADDR MT6358_GPIO_PULLSEL0
#define PMIC_GPIO_PULLSEL0_MASK 0xFFFF
#define PMIC_GPIO_PULLSEL0_SHIFT  0
#define PMIC_GPIO_PULLSEL0_SET_ADDR   MT6358_GPIO_PULLSEL0_SET
#define PMIC_GPIO_PULLSEL0_SET_MASK   0xFFFF
#define PMIC_GPIO_PULLSEL0_SET_SHIFT  0
#define PMIC_GPIO_PULLSEL0_CLR_ADDR   MT6358_GPIO_PULLSEL0_CLR
#define PMIC_GPIO_PULLSEL0_CLR_MASK   0xFFFF
#define PMIC_GPIO_PULLSEL0_CLR_SHIFT  0
#define PMIC_GPIO_PULLSEL1_ADDR MT6358_GPIO_PULLSEL1
#define PMIC_GPIO_PULLSEL1_MASK 0x7
#define PMIC_GPIO_PULLSEL1_SHIFT  0
#define PMIC_GPIO_PULLSEL1_SET_ADDR   MT6358_GPIO_PULLSEL1_SET
#define PMIC_GPIO_PULLSEL1_SET_MASK   0xFFFF
#define PMIC_GPIO_PULLSEL1_SET_SHIFT  0
#define PMIC_GPIO_PULLSEL1_CLR_ADDR   MT6358_GPIO_PULLSEL1_CLR
#define PMIC_GPIO_PULLSEL1_CLR_MASK   0xFFFF
#define PMIC_GPIO_PULLSEL1_CLR_SHIFT  0
#define PMIC_GPIO_DINV0_ADDR MT6358_GPIO_DINV0
#define PMIC_GPIO_DINV0_MASK 0xFFFF
#define PMIC_GPIO_DINV0_SHIFT   0
#define PMIC_GPIO_DINV0_SET_ADDR  MT6358_GPIO_DINV0_SET
#define PMIC_GPIO_DINV0_SET_MASK  0xFFFF
#define PMIC_GPIO_DINV0_SET_SHIFT 0
#define PMIC_GPIO_DINV0_CLR_ADDR  MT6358_GPIO_DINV0_CLR
#define PMIC_GPIO_DINV0_CLR_MASK  0xFFFF
#define PMIC_GPIO_DINV0_CLR_SHIFT 0
#define PMIC_GPIO_DINV1_ADDR MT6358_GPIO_DINV1
#define PMIC_GPIO_DINV1_MASK 0x7
#define PMIC_GPIO_DINV1_SHIFT   0
#define PMIC_GPIO_DINV1_SET_ADDR  MT6358_GPIO_DINV1_SET
#define PMIC_GPIO_DINV1_SET_MASK  0xFFFF
#define PMIC_GPIO_DINV1_SET_SHIFT 0
#define PMIC_GPIO_DINV1_CLR_ADDR  MT6358_GPIO_DINV1_CLR
#define PMIC_GPIO_DINV1_CLR_MASK  0xFFFF
#define PMIC_GPIO_DINV1_CLR_SHIFT 0
#define PMIC_GPIO_DOUT0_ADDR MT6358_GPIO_DOUT0
#define PMIC_GPIO_DOUT0_MASK 0xFFFF
#define PMIC_GPIO_DOUT0_SHIFT   0
#define PMIC_GPIO_DOUT0_SET_ADDR  MT6358_GPIO_DOUT0_SET
#define PMIC_GPIO_DOUT0_SET_MASK  0xFFFF
#define PMIC_GPIO_DOUT0_SET_SHIFT 0
#define PMIC_GPIO_DOUT0_CLR_ADDR  MT6358_GPIO_DOUT0_CLR
#define PMIC_GPIO_DOUT0_CLR_MASK  0xFFFF
#define PMIC_GPIO_DOUT0_CLR_SHIFT 0
#define PMIC_GPIO_DOUT1_ADDR MT6358_GPIO_DOUT1
#define PMIC_GPIO_DOUT1_MASK 0x7
#define PMIC_GPIO_DOUT1_SHIFT   0
#define PMIC_GPIO_DOUT1_SET_ADDR  MT6358_GPIO_DOUT1_SET
#define PMIC_GPIO_DOUT1_SET_MASK  0xFFFF
#define PMIC_GPIO_DOUT1_SET_SHIFT 0
#define PMIC_GPIO_DOUT1_CLR_ADDR  MT6358_GPIO_DOUT1_CLR
#define PMIC_GPIO_DOUT1_CLR_MASK  0xFFFF
#define PMIC_GPIO_DOUT1_CLR_SHIFT 0
#define PMIC_GPIO_PI0_ADDR  MT6358_GPIO_PI0
#define PMIC_GPIO_PI0_MASK  0xFFFF
#define PMIC_GPIO_PI0_SHIFT  0
#define PMIC_GPIO_PI1_ADDR  MT6358_GPIO_PI1
#define PMIC_GPIO_PI1_MASK  0x7
#define PMIC_GPIO_PI1_SHIFT  0
#define PMIC_GPIO_POE0_ADDR  MT6358_GPIO_POE0
#define PMIC_GPIO_POE0_MASK  0xFFFF
#define PMIC_GPIO_POE0_SHIFT 0
#define PMIC_GPIO_POE1_ADDR  MT6358_GPIO_POE1
#define PMIC_GPIO_POE1_MASK  0x7
#define PMIC_GPIO_POE1_SHIFT 0
#define PMIC_GPIO0_MODE_ADDR MT6358_GPIO_MODE0
#define PMIC_GPIO0_MODE_MASK 0x7
#define PMIC_GPIO0_MODE_SHIFT   0
#define PMIC_GPIO1_MODE_ADDR MT6358_GPIO_MODE0
#define PMIC_GPIO1_MODE_MASK 0x7
#define PMIC_GPIO1_MODE_SHIFT   3
#define PMIC_GPIO2_MODE_ADDR MT6358_GPIO_MODE0
#define PMIC_GPIO2_MODE_MASK 0x7
#define PMIC_GPIO2_MODE_SHIFT   6
#define PMIC_GPIO3_MODE_ADDR MT6358_GPIO_MODE0
#define PMIC_GPIO3_MODE_MASK 0x7
#define PMIC_GPIO3_MODE_SHIFT   9
#define PMIC_GPIO_MODE0_SET_ADDR  MT6358_GPIO_MODE0_SET
#define PMIC_GPIO_MODE0_SET_MASK  0xFFFF
#define PMIC_GPIO_MODE0_SET_SHIFT 0
#define PMIC_GPIO_MODE0_CLR_ADDR  MT6358_GPIO_MODE0_CLR
#define PMIC_GPIO_MODE0_CLR_MASK  0xFFFF
#define PMIC_GPIO_MODE0_CLR_SHIFT 0
#define PMIC_GPIO4_MODE_ADDR MT6358_GPIO_MODE1
#define PMIC_GPIO4_MODE_MASK 0x7
#define PMIC_GPIO4_MODE_SHIFT   0
#define PMIC_GPIO5_MODE_ADDR MT6358_GPIO_MODE1
#define PMIC_GPIO5_MODE_MASK 0x7
#define PMIC_GPIO5_MODE_SHIFT   3
#define PMIC_GPIO6_MODE_ADDR MT6358_GPIO_MODE1
#define PMIC_GPIO6_MODE_MASK 0x7
#define PMIC_GPIO6_MODE_SHIFT   6
#define PMIC_GPIO7_MODE_ADDR MT6358_GPIO_MODE1
#define PMIC_GPIO7_MODE_MASK 0x7
#define PMIC_GPIO7_MODE_SHIFT   9
#define PMIC_GPIO_MODE1_SET_ADDR  MT6358_GPIO_MODE1_SET
#define PMIC_GPIO_MODE1_SET_MASK  0xFFFF
#define PMIC_GPIO_MODE1_SET_SHIFT 0
#define PMIC_GPIO_MODE1_CLR_ADDR  MT6358_GPIO_MODE1_CLR
#define PMIC_GPIO_MODE1_CLR_MASK  0xFFFF
#define PMIC_GPIO_MODE1_CLR_SHIFT 0
#define PMIC_GPIO8_MODE_ADDR MT6358_GPIO_MODE2
#define PMIC_GPIO8_MODE_MASK 0x7
#define PMIC_GPIO8_MODE_SHIFT   0
#define PMIC_GPIO9_MODE_ADDR MT6358_GPIO_MODE2
#define PMIC_GPIO9_MODE_MASK 0x7
#define PMIC_GPIO9_MODE_SHIFT   3
#define PMIC_GPIO10_MODE_ADDR   MT6358_GPIO_MODE2
#define PMIC_GPIO10_MODE_MASK   0x7
#define PMIC_GPIO10_MODE_SHIFT  6
#define PMIC_GPIO11_MODE_ADDR   MT6358_GPIO_MODE2
#define PMIC_GPIO11_MODE_MASK   0x7
#define PMIC_GPIO11_MODE_SHIFT  9
#define PMIC_GPIO_MODE2_SET_ADDR  MT6358_GPIO_MODE2_SET
#define PMIC_GPIO_MODE2_SET_MASK  0xFFFF
#define PMIC_GPIO_MODE2_SET_SHIFT 0
#define PMIC_GPIO_MODE2_CLR_ADDR  MT6358_GPIO_MODE2_CLR
#define PMIC_GPIO_MODE2_CLR_MASK  0xFFFF
#define PMIC_GPIO_MODE2_CLR_SHIFT 0
#define PMIC_GPIO12_MODE_ADDR   MT6358_GPIO_MODE3
#define PMIC_GPIO12_MODE_MASK   0x7
#define PMIC_GPIO12_MODE_SHIFT  0
#define PMIC_GPIO13_MODE_ADDR   MT6358_GPIO_MODE3
#define PMIC_GPIO13_MODE_MASK   0x7
#define PMIC_GPIO13_MODE_SHIFT  3
#define PMIC_GPIO14_MODE_ADDR   MT6358_GPIO_MODE3
#define PMIC_GPIO14_MODE_MASK   0x7
#define PMIC_GPIO14_MODE_SHIFT  6
#define PMIC_GPIO15_MODE_ADDR   MT6358_GPIO_MODE3
#define PMIC_GPIO15_MODE_MASK   0x7
#define PMIC_GPIO15_MODE_SHIFT  9
#define PMIC_GPIO_MODE3_SET_ADDR  MT6358_GPIO_MODE3_SET
#define PMIC_GPIO_MODE3_SET_MASK  0xFFFF
#define PMIC_GPIO_MODE3_SET_SHIFT 0
#define PMIC_GPIO_MODE3_CLR_ADDR  MT6358_GPIO_MODE3_CLR
#define PMIC_GPIO_MODE3_CLR_MASK  0xFFFF
#define PMIC_GPIO_MODE3_CLR_SHIFT 0
#define PMIC_GPIO16_MODE_ADDR   MT6358_GPIO_MODE4
#define PMIC_GPIO16_MODE_MASK   0x7
#define PMIC_GPIO16_MODE_SHIFT  0
#define PMIC_GPIO17_MODE_ADDR   MT6358_GPIO_MODE4
#define PMIC_GPIO17_MODE_MASK   0x7
#define PMIC_GPIO17_MODE_SHIFT  3
#define PMIC_GPIO18_MODE_ADDR   MT6358_GPIO_MODE4
#define PMIC_GPIO18_MODE_MASK   0x7
#define PMIC_GPIO18_MODE_SHIFT  6
#define PMIC_GPIO_MODE4_SET_ADDR  MT6358_GPIO_MODE4_SET
#define PMIC_GPIO_MODE4_SET_MASK  0xFFFF
#define PMIC_GPIO_MODE4_SET_SHIFT 0
#define PMIC_GPIO_MODE4_CLR_ADDR  MT6358_GPIO_MODE4_CLR
#define PMIC_GPIO_MODE4_CLR_MASK  0xFFFF
#define PMIC_GPIO_MODE4_CLR_SHIFT 0
#define PMIC_GPIO_RSV_ADDR  MT6358_GPIO_RSV
#define PMIC_GPIO_RSV_MASK  0x1
#define PMIC_GPIO_RSV_SHIFT  0
#define PMIC_TOP2_ANA_ID_ADDR   MT6358_TOP2_ID
#define PMIC_TOP2_ANA_ID_MASK   0xFF
#define PMIC_TOP2_ANA_ID_SHIFT  0
#define PMIC_TOP2_DIG_ID_ADDR   MT6358_TOP2_ID
#define PMIC_TOP2_DIG_ID_MASK   0xFF
#define PMIC_TOP2_DIG_ID_SHIFT  8
#define PMIC_TOP2_ANA_MINOR_REV_ADDR  MT6358_TOP2_REV0
#define PMIC_TOP2_ANA_MINOR_REV_MASK  0xF
#define PMIC_TOP2_ANA_MINOR_REV_SHIFT 0
#define PMIC_TOP2_ANA_MAJOR_REV_ADDR  MT6358_TOP2_REV0
#define PMIC_TOP2_ANA_MAJOR_REV_MASK  0xF
#define PMIC_TOP2_ANA_MAJOR_REV_SHIFT 4
#define PMIC_TOP2_DIG_MINOR_REV_ADDR  MT6358_TOP2_REV0
#define PMIC_TOP2_DIG_MINOR_REV_MASK  0xF
#define PMIC_TOP2_DIG_MINOR_REV_SHIFT 8
#define PMIC_TOP2_DIG_MAJOR_REV_ADDR  MT6358_TOP2_REV0
#define PMIC_TOP2_DIG_MAJOR_REV_MASK  0xF
#define PMIC_TOP2_DIG_MAJOR_REV_SHIFT 12
#define PMIC_TOP2_DSN_CBS_ADDR  MT6358_TOP2_DSN_DBI
#define PMIC_TOP2_DSN_CBS_MASK  0x3
#define PMIC_TOP2_DSN_CBS_SHIFT 0
#define PMIC_TOP2_DSN_BIX_ADDR  MT6358_TOP2_DSN_DBI
#define PMIC_TOP2_DSN_BIX_MASK  0x3
#define PMIC_TOP2_DSN_BIX_SHIFT 2
#define PMIC_TOP2_DSN_ESP_ADDR  MT6358_TOP2_DSN_DBI
#define PMIC_TOP2_DSN_ESP_MASK  0xFF
#define PMIC_TOP2_DSN_ESP_SHIFT 8
#define PMIC_TOP2_DSN_FPI_ADDR  MT6358_TOP2_DSN_DXI
#define PMIC_TOP2_DSN_FPI_MASK  0xFF
#define PMIC_TOP2_DSN_FPI_SHIFT 0
#define PMIC_TOP_CLK_OFFSET_ADDR  MT6358_TOP_PAM0
#define PMIC_TOP_CLK_OFFSET_MASK  0xFF
#define PMIC_TOP_CLK_OFFSET_SHIFT 0
#define PMIC_TOP_RST_OFFSET_ADDR  MT6358_TOP_PAM0
#define PMIC_TOP_RST_OFFSET_MASK  0xFF
#define PMIC_TOP_RST_OFFSET_SHIFT 8
#define PMIC_TOP_INT_OFFSET_ADDR  MT6358_TOP_PAM1
#define PMIC_TOP_INT_OFFSET_MASK  0xFF
#define PMIC_TOP_INT_OFFSET_SHIFT 0
#define PMIC_TOP_INT_LEN_ADDR   MT6358_TOP_PAM1
#define PMIC_TOP_INT_LEN_MASK   0xFF
#define PMIC_TOP_INT_LEN_SHIFT  8
#define PMIC_RG_G_SMPS_CK_PDN_ADDR MT6358_TOP_CKPDN_CON0
#define PMIC_RG_G_SMPS_CK_PDN_MASK 0x1
#define PMIC_RG_G_SMPS_CK_PDN_SHIFT   0
#define PMIC_RG_G_SMPS_TEST_CK_PDN_ADDR MT6358_TOP_CKPDN_CON0
#define PMIC_RG_G_SMPS_TEST_CK_PDN_MASK 0x1
#define PMIC_RG_G_SMPS_TEST_CK_PDN_SHIFT   1
#define PMIC_RG_INTRP_CK_PDN_ADDR MT6358_TOP_CKPDN_CON0
#define PMIC_RG_INTRP_CK_PDN_MASK 0x1
#define PMIC_RG_INTRP_CK_PDN_SHIFT 2
#define PMIC_RG_INTRP_PRE_OC_CK_PDN_ADDR   MT6358_TOP_CKPDN_CON0
#define PMIC_RG_INTRP_PRE_OC_CK_PDN_MASK   0x1
#define PMIC_RG_INTRP_PRE_OC_CK_PDN_SHIFT   3
#define PMIC_RG_EFUSE_CK_PDN_ADDR MT6358_TOP_CKPDN_CON0
#define PMIC_RG_EFUSE_CK_PDN_MASK 0x1
#define PMIC_RG_EFUSE_CK_PDN_SHIFT 4
#define PMIC_RG_EINT_32K_CK_PDN_ADDR  MT6358_TOP_CKPDN_CON0
#define PMIC_RG_EINT_32K_CK_PDN_MASK  0x1
#define PMIC_RG_EINT_32K_CK_PDN_SHIFT 5
#define PMIC_RG_PMU1M_CK_PDN_ADDR MT6358_TOP_CKPDN_CON0
#define PMIC_RG_PMU1M_CK_PDN_MASK 0x1
#define PMIC_RG_PMU1M_CK_PDN_SHIFT 6
#define PMIC_RG_SPI_CK_PDN_ADDR MT6358_TOP_CKPDN_CON0
#define PMIC_RG_SPI_CK_PDN_MASK 0x1
#define PMIC_RG_SPI_CK_PDN_SHIFT  7
#define PMIC_RG_REG_CK_PDN_ADDR MT6358_TOP_CKPDN_CON0
#define PMIC_RG_REG_CK_PDN_MASK 0x1
#define PMIC_RG_REG_CK_PDN_SHIFT  8
#define PMIC_RG_PMU32K_CK_PDN_ADDR MT6358_TOP_CKPDN_CON0
#define PMIC_RG_PMU32K_CK_PDN_MASK 0x1
#define PMIC_RG_PMU32K_CK_PDN_SHIFT   9
#define PMIC_RG_FQMTR_32K_CK_PDN_ADDR MT6358_TOP_CKPDN_CON0
#define PMIC_RG_FQMTR_32K_CK_PDN_MASK 0x1
#define PMIC_RG_FQMTR_32K_CK_PDN_SHIFT  10
#define PMIC_RG_FQMTR_CK_PDN_ADDR MT6358_TOP_CKPDN_CON0
#define PMIC_RG_FQMTR_CK_PDN_MASK 0x1
#define PMIC_RG_FQMTR_CK_PDN_SHIFT 11
#define PMIC_RG_PMU26M_CK_PDN_ADDR MT6358_TOP_CKPDN_CON0
#define PMIC_RG_PMU26M_CK_PDN_MASK 0x1
#define PMIC_RG_PMU26M_CK_PDN_SHIFT   12
#define PMIC_RG_PMU128K_CK_PDN_ADDR   MT6358_TOP_CKPDN_CON0
#define PMIC_RG_PMU128K_CK_PDN_MASK   0x1
#define PMIC_RG_PMU128K_CK_PDN_SHIFT  13
#define PMIC_RG_RTC26M_CK_PDN_ADDR MT6358_TOP_CKPDN_CON0
#define PMIC_RG_RTC26M_CK_PDN_MASK 0x1
#define PMIC_RG_RTC26M_CK_PDN_SHIFT   14
#define PMIC_RG_RTC32K_CK_PDN_ADDR MT6358_TOP_CKPDN_CON0
#define PMIC_RG_RTC32K_CK_PDN_MASK 0x1
#define PMIC_RG_RTC32K_CK_PDN_SHIFT   15
#define PMIC_TOP_CKPDN_CON0_SET_ADDR  MT6358_TOP_CKPDN_CON0_SET
#define PMIC_TOP_CKPDN_CON0_SET_MASK  0xFFFF
#define PMIC_TOP_CKPDN_CON0_SET_SHIFT 0
#define PMIC_TOP_CKPDN_CON0_CLR_ADDR  MT6358_TOP_CKPDN_CON0_CLR
#define PMIC_TOP_CKPDN_CON0_CLR_MASK  0xFFFF
#define PMIC_TOP_CKPDN_CON0_CLR_SHIFT 0
#define PMIC_RG_RTC32K_1V8_0_PDN_ADDR MT6358_TOP_CKPDN_CON1
#define PMIC_RG_RTC32K_1V8_0_PDN_MASK 0x1
#define PMIC_RG_RTC32K_1V8_0_PDN_SHIFT  0
#define PMIC_RG_RTC32K_1V8_1_PDN_ADDR MT6358_TOP_CKPDN_CON1
#define PMIC_RG_RTC32K_1V8_1_PDN_MASK 0x1
#define PMIC_RG_RTC32K_1V8_1_PDN_SHIFT  1
#define PMIC_RG_TRIM_128K_CK_PDN_ADDR MT6358_TOP_CKPDN_CON1
#define PMIC_RG_TRIM_128K_CK_PDN_MASK 0x1
#define PMIC_RG_TRIM_128K_CK_PDN_SHIFT  2
#define PMIC_RG_BGR_TEST_CK_PDN_ADDR  MT6358_TOP_CKPDN_CON1
#define PMIC_RG_BGR_TEST_CK_PDN_MASK  0x1
#define PMIC_RG_BGR_TEST_CK_PDN_SHIFT 3
#define PMIC_RG_PCHR_TEST_CK_PDN_ADDR MT6358_TOP_CKPDN_CON1
#define PMIC_RG_PCHR_TEST_CK_PDN_MASK 0x1
#define PMIC_RG_PCHR_TEST_CK_PDN_SHIFT  4
#define PMIC_TOP_CKPDN_CON1_SET_ADDR  MT6358_TOP_CKPDN_CON1_SET
#define PMIC_TOP_CKPDN_CON1_SET_MASK  0xFFFF
#define PMIC_TOP_CKPDN_CON1_SET_SHIFT 0
#define PMIC_TOP_CKPDN_CON1_CLR_ADDR  MT6358_TOP_CKPDN_CON1_CLR
#define PMIC_TOP_CKPDN_CON1_CLR_MASK  0xFFFF
#define PMIC_TOP_CKPDN_CON1_CLR_SHIFT 0
#define PMIC_RG_FQMTR_CK_CKSEL_ADDR   MT6358_TOP_CKSEL_CON0
#define PMIC_RG_FQMTR_CK_CKSEL_MASK   0x7
#define PMIC_RG_FQMTR_CK_CKSEL_SHIFT  0
#define PMIC_RG_RTC_32K1V8_SEL_ADDR   MT6358_TOP_CKSEL_CON0
#define PMIC_RG_RTC_32K1V8_SEL_MASK   0x1
#define PMIC_RG_RTC_32K1V8_SEL_SHIFT  3
#define PMIC_RG_BGR_TEST_CK_CKSEL_ADDR  MT6358_TOP_CKSEL_CON0
#define PMIC_RG_BGR_TEST_CK_CKSEL_MASK  0x1
#define PMIC_RG_BGR_TEST_CK_CKSEL_SHIFT 4
#define PMIC_RG_PCHR_TEST_CK_CKSEL_ADDR MT6358_TOP_CKSEL_CON0
#define PMIC_RG_PCHR_TEST_CK_CKSEL_MASK 0x1
#define PMIC_RG_PCHR_TEST_CK_CKSEL_SHIFT   5
#define PMIC_RG_26M_CK_SEL_HWEN_ADDR  MT6358_TOP_CKSEL_CON0
#define PMIC_RG_26M_CK_SEL_HWEN_MASK  0x1
#define PMIC_RG_26M_CK_SEL_HWEN_SHIFT 6
#define PMIC_RG_26M_CK_SEL_ADDR MT6358_TOP_CKSEL_CON0
#define PMIC_RG_26M_CK_SEL_MASK 0x1
#define PMIC_RG_26M_CK_SEL_SHIFT  7
#define PMIC_RG_PMU_1M_CK_SEL_HWEN_ADDR MT6358_TOP_CKSEL_CON0
#define PMIC_RG_PMU_1M_CK_SEL_HWEN_MASK 0x1
#define PMIC_RG_PMU_1M_CK_SEL_HWEN_SHIFT   8
#define PMIC_RG_PMU_1M_CK_SEL_ADDR MT6358_TOP_CKSEL_CON0
#define PMIC_RG_PMU_1M_CK_SEL_MASK 0x1
#define PMIC_RG_PMU_1M_CK_SEL_SHIFT   9
#define PMIC_RG_PMU32K_CK_CKSEL_ADDR  MT6358_TOP_CKSEL_CON0
#define PMIC_RG_PMU32K_CK_CKSEL_MASK  0x1
#define PMIC_RG_PMU32K_CK_CKSEL_SHIFT 10
#define PMIC_RG_TOP_CKSEL_CON0_RSV_ADDR MT6358_TOP_CKSEL_CON0
#define PMIC_RG_TOP_CKSEL_CON0_RSV_MASK 0x1F
#define PMIC_RG_TOP_CKSEL_CON0_RSV_SHIFT   11
#define PMIC_TOP_CKSEL_CON0_SET_ADDR  MT6358_TOP_CKSEL_CON0_SET
#define PMIC_TOP_CKSEL_CON0_SET_MASK  0xFFFF
#define PMIC_TOP_CKSEL_CON0_SET_SHIFT 0
#define PMIC_TOP_CKSEL_CON0_CLR_ADDR  MT6358_TOP_CKSEL_CON0_CLR
#define PMIC_TOP_CKSEL_CON0_CLR_MASK  0xFFFF
#define PMIC_TOP_CKSEL_CON0_CLR_SHIFT 0
#define PMIC_RG_SRCVOLTEN_SW_ADDR MT6358_TOP_CKSEL_CON1
#define PMIC_RG_SRCVOLTEN_SW_MASK 0x1
#define PMIC_RG_SRCVOLTEN_SW_SHIFT 0
#define PMIC_RG_VOWEN_SW_ADDR   MT6358_TOP_CKSEL_CON1
#define PMIC_RG_VOWEN_SW_MASK   0x1
#define PMIC_RG_VOWEN_SW_SHIFT  1
#define PMIC_RG_VOW_LDO_VSRAM_CORE_DVS_DONE_ADDR  MT6358_TOP_CKSEL_CON1
#define PMIC_RG_VOW_LDO_VSRAM_CORE_DVS_DONE_MASK  0x1
#define PMIC_RG_VOW_LDO_VSRAM_CORE_DVS_DONE_SHIFT 2
#define PMIC_RG_VOW_BUCK_VCORE_DVS_DONE_ADDR  MT6358_TOP_CKSEL_CON1
#define PMIC_RG_VOW_BUCK_VCORE_DVS_DONE_MASK  0x1
#define PMIC_RG_VOW_BUCK_VCORE_DVS_DONE_SHIFT 3
#define PMIC_RG_SRCVOLTEN_MODE_ADDR   MT6358_TOP_CKSEL_CON1
#define PMIC_RG_SRCVOLTEN_MODE_MASK   0x1
#define PMIC_RG_SRCVOLTEN_MODE_SHIFT  8
#define PMIC_RG_VOWEN_MODE_ADDR MT6358_TOP_CKSEL_CON1
#define PMIC_RG_VOWEN_MODE_MASK 0x1
#define PMIC_RG_VOWEN_MODE_SHIFT  9
#define PMIC_RG_VOW_LDO_VSRAM_CORE_DVS_SW_MODE_ADDR MT6358_TOP_CKSEL_CON1
#define PMIC_RG_VOW_LDO_VSRAM_CORE_DVS_SW_MODE_MASK 0x1
#define PMIC_RG_VOW_LDO_VSRAM_CORE_DVS_SW_MODE_SHIFT   10
#define PMIC_RG_VOW_BUCK_VCORE_DVS_SW_MODE_ADDR  MT6358_TOP_CKSEL_CON1
#define PMIC_RG_VOW_BUCK_VCORE_DVS_SW_MODE_MASK  0x1
#define PMIC_RG_VOW_BUCK_VCORE_DVS_SW_MODE_SHIFT  11
#define PMIC_RG_TOP_CKSEL_CON2_RSV_ADDR MT6358_TOP_CKSEL_CON1
#define PMIC_RG_TOP_CKSEL_CON2_RSV_MASK 0xF
#define PMIC_RG_TOP_CKSEL_CON2_RSV_SHIFT   12
#define PMIC_TOP_CKSEL_CON1_SET_ADDR  MT6358_TOP_CKSEL_CON1_SET
#define PMIC_TOP_CKSEL_CON1_SET_MASK  0xFFFF
#define PMIC_TOP_CKSEL_CON1_SET_SHIFT 0
#define PMIC_TOP_CKSEL_CON1_CLR_ADDR  MT6358_TOP_CKSEL_CON1_CLR
#define PMIC_TOP_CKSEL_CON1_CLR_MASK  0xFFFF
#define PMIC_TOP_CKSEL_CON1_CLR_SHIFT 0
#define PMIC_RG_REG_CK_DIVSEL_ADDR MT6358_TOP_CKDIVSEL_CON0
#define PMIC_RG_REG_CK_DIVSEL_MASK 0x3
#define PMIC_RG_REG_CK_DIVSEL_SHIFT   0
#define PMIC_TOP_CKDIVSEL_CON0_RSV_ADDR MT6358_TOP_CKDIVSEL_CON0
#define PMIC_TOP_CKDIVSEL_CON0_RSV_MASK 0x3F
#define PMIC_TOP_CKDIVSEL_CON0_RSV_SHIFT   10
#define PMIC_TOP_CKDIVSEL_CON0_SET_ADDR MT6358_TOP_CKDIVSEL_CON0_SET
#define PMIC_TOP_CKDIVSEL_CON0_SET_MASK 0xFFFF
#define PMIC_TOP_CKDIVSEL_CON0_SET_SHIFT   0
#define PMIC_TOP_CKDIVSEL_CON0_CLR_ADDR MT6358_TOP_CKDIVSEL_CON0_CLR
#define PMIC_TOP_CKDIVSEL_CON0_CLR_MASK 0xFFFF
#define PMIC_TOP_CKDIVSEL_CON0_CLR_SHIFT   0
#define PMIC_RG_G_SMPS_CK_PDN_HWEN_ADDR MT6358_TOP_CKHWEN_CON0
#define PMIC_RG_G_SMPS_CK_PDN_HWEN_MASK 0x1
#define PMIC_RG_G_SMPS_CK_PDN_HWEN_SHIFT   0
#define PMIC_RG_REG_CK_PDN_HWEN_ADDR  MT6358_TOP_CKHWEN_CON0
#define PMIC_RG_REG_CK_PDN_HWEN_MASK  0x1
#define PMIC_RG_REG_CK_PDN_HWEN_SHIFT 1
#define PMIC_RG_EFUSE_CK_PDN_HWEN_ADDR  MT6358_TOP_CKHWEN_CON0
#define PMIC_RG_EFUSE_CK_PDN_HWEN_MASK  0x1
#define PMIC_RG_EFUSE_CK_PDN_HWEN_SHIFT 2
#define PMIC_RG_EINT_32K_CK_PDN_HWEN_ADDR   MT6358_TOP_CKHWEN_CON0
#define PMIC_RG_EINT_32K_CK_PDN_HWEN_MASK   0x1
#define PMIC_RG_EINT_32K_CK_PDN_HWEN_SHIFT  3
#define PMIC_RG_RTC26M_CK_PDN_HWEN_ADDR MT6358_TOP_CKHWEN_CON0
#define PMIC_RG_RTC26M_CK_PDN_HWEN_MASK 0x1
#define PMIC_RG_RTC26M_CK_PDN_HWEN_SHIFT   5
#define PMIC_RG_PMU26M_CK_PDN_HWEN_ADDR MT6358_TOP_CKHWEN_CON0
#define PMIC_RG_PMU26M_CK_PDN_HWEN_MASK 0x1
#define PMIC_RG_PMU26M_CK_PDN_HWEN_SHIFT   6
#define PMIC_RG_PMU_VXO22_ON_ADDR MT6358_TOP_CKHWEN_CON0
#define PMIC_RG_PMU_VXO22_ON_MASK 0x1
#define PMIC_RG_PMU_VXO22_ON_SHIFT 7
#define PMIC_RG_PMU_VXO22_ON_SW_EN_ADDR MT6358_TOP_CKHWEN_CON0
#define PMIC_RG_PMU_VXO22_ON_SW_EN_MASK 0x1
#define PMIC_RG_PMU_VXO22_ON_SW_EN_SHIFT   8
#define PMIC_TOP_CKHWEN_CON0_RSV_ADDR MT6358_TOP_CKHWEN_CON0
#define PMIC_TOP_CKHWEN_CON0_RSV_MASK 0x3
#define PMIC_TOP_CKHWEN_CON0_RSV_SHIFT  14
#define PMIC_TOP_CKHWEN_CON0_SET_ADDR MT6358_TOP_CKHWEN_CON0_SET
#define PMIC_TOP_CKHWEN_CON0_SET_MASK 0xFFFF
#define PMIC_TOP_CKHWEN_CON0_SET_SHIFT  0
#define PMIC_TOP_CKHWEN_CON0_CLR_ADDR MT6358_TOP_CKHWEN_CON0_CLR
#define PMIC_TOP_CKHWEN_CON0_CLR_MASK 0xFFFF
#define PMIC_TOP_CKHWEN_CON0_CLR_SHIFT  0
#define PMIC_RG_PMU128K_CK_TST_DIS_ADDR MT6358_TOP_CKTST_CON0
#define PMIC_RG_PMU128K_CK_TST_DIS_MASK 0x1
#define PMIC_RG_PMU128K_CK_TST_DIS_SHIFT   0
#define PMIC_RG_SMPS_CK_TST_DIS_ADDR  MT6358_TOP_CKTST_CON0
#define PMIC_RG_SMPS_CK_TST_DIS_MASK  0x1
#define PMIC_RG_SMPS_CK_TST_DIS_SHIFT 1
#define PMIC_RG_XO_CLK_26M_PMU_TST_DIS_ADDR MT6358_TOP_CKTST_CON0
#define PMIC_RG_XO_CLK_26M_PMU_TST_DIS_MASK 0x1
#define PMIC_RG_XO_CLK_26M_PMU_TST_DIS_SHIFT  2
#define PMIC_RG_XO_CLK_26M_DIG_TST_DIS_ADDR MT6358_TOP_CKTST_CON0
#define PMIC_RG_XO_CLK_26M_DIG_TST_DIS_MASK 0x1
#define PMIC_RG_XO_CLK_26M_DIG_TST_DIS_SHIFT  3
#define PMIC_RG_RTC_26M_CK_TST_DIS_ADDR MT6358_TOP_CKTST_CON0
#define PMIC_RG_RTC_26M_CK_TST_DIS_MASK 0x1
#define PMIC_RG_RTC_26M_CK_TST_DIS_SHIFT   4
#define PMIC_RG_RTC_32K_CK_TST_DIS_ADDR MT6358_TOP_CKTST_CON0
#define PMIC_RG_RTC_32K_CK_TST_DIS_MASK 0x1
#define PMIC_RG_RTC_32K_CK_TST_DIS_SHIFT   5
#define PMIC_RG_PMU_M_CK_TST_DIS_ADDR MT6358_TOP_CKTST_CON0
#define PMIC_RG_PMU_M_CK_TST_DIS_MASK 0x1
#define PMIC_RG_PMU_M_CK_TST_DIS_SHIFT  6
#define PMIC_TOP_CKTST_CON0_RSV_ADDR  MT6358_TOP_CKTST_CON0
#define PMIC_TOP_CKTST_CON0_RSV_MASK  0xFF
#define PMIC_TOP_CKTST_CON0_RSV_SHIFT 8
#define PMIC_RG_PMU128K_CK_TSTSEL_ADDR  MT6358_TOP_CKTST_CON1
#define PMIC_RG_PMU128K_CK_TSTSEL_MASK  0x1
#define PMIC_RG_PMU128K_CK_TSTSEL_SHIFT 0
#define PMIC_RG_SMPS_CK_TSTSEL_ADDR   MT6358_TOP_CKTST_CON1
#define PMIC_RG_SMPS_CK_TSTSEL_MASK   0x1
#define PMIC_RG_SMPS_CK_TSTSEL_SHIFT  1
#define PMIC_RG_XO_CLK_26M_PMU_TSTSEL_ADDR  MT6358_TOP_CKTST_CON1
#define PMIC_RG_XO_CLK_26M_PMU_TSTSEL_MASK  0x1
#define PMIC_RG_XO_CLK_26M_PMU_TSTSEL_SHIFT 2
#define PMIC_RG_XO_CLK_26M_DIG_TSTSEL_ADDR  MT6358_TOP_CKTST_CON1
#define PMIC_RG_XO_CLK_26M_DIG_TSTSEL_MASK  0x1
#define PMIC_RG_XO_CLK_26M_DIG_TSTSEL_SHIFT 3
#define PMIC_RG_RTC_26M_CK_TSTSEL_ADDR  MT6358_TOP_CKTST_CON1
#define PMIC_RG_RTC_26M_CK_TSTSEL_MASK  0x1
#define PMIC_RG_RTC_26M_CK_TSTSEL_SHIFT 4
#define PMIC_RG_RTC_32K_CK_TSTSEL_ADDR  MT6358_TOP_CKTST_CON1
#define PMIC_RG_RTC_32K_CK_TSTSEL_MASK  0x1
#define PMIC_RG_RTC_32K_CK_TSTSEL_SHIFT 5
#define PMIC_RG_PMU_M_CK_TSTSEL_ADDR  MT6358_TOP_CKTST_CON1
#define PMIC_RG_PMU_M_CK_TSTSEL_MASK  0x1
#define PMIC_RG_PMU_M_CK_TSTSEL_SHIFT 6
#define PMIC_RG_EFUSE_CK_TSTSEL_ADDR  MT6358_TOP_CKTST_CON1
#define PMIC_RG_EFUSE_CK_TSTSEL_MASK  0x1
#define PMIC_RG_EFUSE_CK_TSTSEL_SHIFT 7
#define PMIC_RG_BGR_TEST_CK_TSTSEL_ADDR MT6358_TOP_CKTST_CON1
#define PMIC_RG_BGR_TEST_CK_TSTSEL_MASK 0x1
#define PMIC_RG_BGR_TEST_CK_TSTSEL_SHIFT   8
#define PMIC_RG_PCHR_TEST_CK_TSTSEL_ADDR   MT6358_TOP_CKTST_CON1
#define PMIC_RG_PCHR_TEST_CK_TSTSEL_MASK   0x1
#define PMIC_RG_PCHR_TEST_CK_TSTSEL_SHIFT   9
#define PMIC_RG_FQMTR_CK_TSTSEL_ADDR  MT6358_TOP_CKTST_CON1
#define PMIC_RG_FQMTR_CK_TSTSEL_MASK  0x1
#define PMIC_RG_FQMTR_CK_TSTSEL_SHIFT 10
#define PMIC_RG_OSC_SEL_SW_EN_ADDR MT6358_TOP_CLK_CON0
#define PMIC_RG_OSC_SEL_SW_EN_MASK 0x1
#define PMIC_RG_OSC_SEL_SW_EN_SHIFT   0
#define PMIC_RG_OSC_SEL_ADDR MT6358_TOP_CLK_CON0
#define PMIC_RG_OSC_SEL_MASK 0x1
#define PMIC_RG_OSC_SEL_SHIFT   1
#define PMIC_RG_OSC_EN_SW_EN_ADDR MT6358_TOP_CLK_CON0
#define PMIC_RG_OSC_EN_SW_EN_MASK 0x1
#define PMIC_RG_OSC_EN_SW_EN_SHIFT 2
#define PMIC_RG_OSC_EN_ADDR  MT6358_TOP_CLK_CON0
#define PMIC_RG_OSC_EN_MASK  0x1
#define PMIC_RG_OSC_EN_SHIFT 3
#define PMIC_RG_SRCVOLTEN_LP_EN_ADDR  MT6358_TOP_CLK_CON0
#define PMIC_RG_SRCVOLTEN_LP_EN_MASK  0x1
#define PMIC_RG_SRCVOLTEN_LP_EN_SHIFT 4
#define PMIC_RG_SRCLKEN0_LP_EN_ADDR   MT6358_TOP_CLK_CON0
#define PMIC_RG_SRCLKEN0_LP_EN_MASK   0x1
#define PMIC_RG_SRCLKEN0_LP_EN_SHIFT  5
#define PMIC_RG_SRCLKEN1_LP_EN_ADDR   MT6358_TOP_CLK_CON0
#define PMIC_RG_SRCLKEN1_LP_EN_MASK   0x1
#define PMIC_RG_SRCLKEN1_LP_EN_SHIFT  6
#define PMIC_RG_SRCLKEN2_LP_EN_ADDR   MT6358_TOP_CLK_CON0
#define PMIC_RG_SRCLKEN2_LP_EN_MASK   0x1
#define PMIC_RG_SRCLKEN2_LP_EN_SHIFT  7
#define PMIC_RG_BUCK_LP_EN_ADDR MT6358_TOP_CLK_CON0
#define PMIC_RG_BUCK_LP_EN_MASK 0x1
#define PMIC_RG_BUCK_LP_EN_SHIFT  8
#define PMIC_RG_LDO_LP_EN_ADDR  MT6358_TOP_CLK_CON0
#define PMIC_RG_LDO_LP_EN_MASK  0x1
#define PMIC_RG_LDO_LP_EN_SHIFT 9
#define PMIC_RG_BUCK_PFM_FLAG_ADDR MT6358_TOP_CLK_CON0
#define PMIC_RG_BUCK_PFM_FLAG_MASK 0x1
#define PMIC_RG_BUCK_PFM_FLAG_SHIFT   10
#define PMIC_RG_BUCK_PFM_FLAG_SW_EN_ADDR   MT6358_TOP_CLK_CON0
#define PMIC_RG_BUCK_PFM_FLAG_SW_EN_MASK   0x1
#define PMIC_RG_BUCK_PFM_FLAG_SW_EN_SHIFT   11
#define PMIC_RG_DCXO26M_RDY_ADDR  MT6358_TOP_CLK_CON0
#define PMIC_RG_DCXO26M_RDY_MASK  0x1
#define PMIC_RG_DCXO26M_RDY_SHIFT 12
#define PMIC_RG_DCXO26M_RDY_SW_EN_ADDR  MT6358_TOP_CLK_CON0
#define PMIC_RG_DCXO26M_RDY_SW_EN_MASK  0x1
#define PMIC_RG_DCXO26M_RDY_SW_EN_SHIFT 13
#define PMIC_RG_PMU_LP_ADDR  MT6358_TOP_CLK_CON0
#define PMIC_RG_PMU_LP_MASK  0x1
#define PMIC_RG_PMU_LP_SHIFT 14
#define PMIC_RG_PMU_LP_SW_EN_ADDR MT6358_TOP_CLK_CON0
#define PMIC_RG_PMU_LP_SW_EN_MASK 0x1
#define PMIC_RG_PMU_LP_SW_EN_SHIFT 15
#define PMIC_TOP_CLK_CON0_SET_ADDR MT6358_TOP_CLK_CON0_SET
#define PMIC_TOP_CLK_CON0_SET_MASK 0xFFFF
#define PMIC_TOP_CLK_CON0_SET_SHIFT   0
#define PMIC_TOP_CLK_CON0_CLR_ADDR MT6358_TOP_CLK_CON0_CLR
#define PMIC_TOP_CLK_CON0_CLR_MASK 0xFFFF
#define PMIC_TOP_CLK_CON0_CLR_SHIFT   0
#define PMIC_RG_PMU_MDB_DCM_SW_EN_ADDR  MT6358_TOP_DCM_CON0
#define PMIC_RG_PMU_MDB_DCM_SW_EN_MASK  0x1
#define PMIC_RG_PMU_MDB_DCM_SW_EN_SHIFT 0
#define PMIC_RG_PMU_MDB_DCM_SW_MODE_ADDR   MT6358_TOP_DCM_CON0
#define PMIC_RG_PMU_MDB_DCM_SW_MODE_MASK   0x1
#define PMIC_RG_PMU_MDB_DCM_SW_MODE_SHIFT   1
#define PMIC_RO_HANDOVER_DEBUG_ADDR   MT6358_TOP_HANDOVER_DEBUG0
#define PMIC_RO_HANDOVER_DEBUG_MASK   0xFFFF
#define PMIC_RO_HANDOVER_DEBUG_SHIFT  0
#define PMIC_RG_EFUSE_MAN_RST_ADDR MT6358_TOP_RST_CON0
#define PMIC_RG_EFUSE_MAN_RST_MASK 0x1
#define PMIC_RG_EFUSE_MAN_RST_SHIFT   0
#define PMIC_RG_DRIVER_RST_ADDR MT6358_TOP_RST_CON0
#define PMIC_RG_DRIVER_RST_MASK 0x1
#define PMIC_RG_DRIVER_RST_SHIFT  6
#define PMIC_RG_FQMTR_RST_ADDR  MT6358_TOP_RST_CON0
#define PMIC_RG_FQMTR_RST_MASK  0x1
#define PMIC_RG_FQMTR_RST_SHIFT 8
#define PMIC_RG_RTC_RST_ADDR MT6358_TOP_RST_CON0
#define PMIC_RG_RTC_RST_MASK 0x1
#define PMIC_RG_RTC_RST_SHIFT   9
#define PMIC_RG_TYPE_C_CC_RST_ADDR MT6358_TOP_RST_CON0
#define PMIC_RG_TYPE_C_CC_RST_MASK 0x1
#define PMIC_RG_TYPE_C_CC_RST_SHIFT   10
#define PMIC_RG_CLK_TRIM_RST_ADDR MT6358_TOP_RST_CON0
#define PMIC_RG_CLK_TRIM_RST_MASK 0x1
#define PMIC_RG_CLK_TRIM_RST_SHIFT 14
#define PMIC_RG_BUCK_SRCLKEN_RST_ADDR MT6358_TOP_RST_CON0
#define PMIC_RG_BUCK_SRCLKEN_RST_MASK 0x1
#define PMIC_RG_BUCK_SRCLKEN_RST_SHIFT  15
#define PMIC_TOP_RST_CON0_SET_ADDR MT6358_TOP_RST_CON0_SET
#define PMIC_TOP_RST_CON0_SET_MASK 0xFFFF
#define PMIC_TOP_RST_CON0_SET_SHIFT   0
#define PMIC_TOP_RST_CON0_CLR_ADDR MT6358_TOP_RST_CON0_CLR
#define PMIC_TOP_RST_CON0_CLR_MASK 0xFFFF
#define PMIC_TOP_RST_CON0_CLR_SHIFT   0
#define PMIC_RG_BUCK_PROT_PMPP_RST_ADDR MT6358_TOP_RST_CON1
#define PMIC_RG_BUCK_PROT_PMPP_RST_MASK 0x1
#define PMIC_RG_BUCK_PROT_PMPP_RST_SHIFT   1
#define PMIC_RG_SPK_RST_ADDR MT6358_TOP_RST_CON1
#define PMIC_RG_SPK_RST_MASK 0x1
#define PMIC_RG_SPK_RST_SHIFT   2
#define PMIC_RG_FT_VR_SYSRSTB_ADDR MT6358_TOP_RST_CON1
#define PMIC_RG_FT_VR_SYSRSTB_MASK 0x1
#define PMIC_RG_FT_VR_SYSRSTB_SHIFT   4
#define PMIC_RG_LDO_CALI_RST_ADDR MT6358_TOP_RST_CON1
#define PMIC_RG_LDO_CALI_RST_MASK 0x1
#define PMIC_RG_LDO_CALI_RST_SHIFT 7
#define PMIC_TOP_RST_CON1_RSV_ADDR MT6358_TOP_RST_CON1
#define PMIC_TOP_RST_CON1_RSV_MASK 0x1
#define PMIC_TOP_RST_CON1_RSV_SHIFT   8
#define PMIC_TOP_RST_CON1_SET_ADDR MT6358_TOP_RST_CON1_SET
#define PMIC_TOP_RST_CON1_SET_MASK 0xFFFF
#define PMIC_TOP_RST_CON1_SET_SHIFT   0
#define PMIC_TOP_RST_CON1_CLR_ADDR MT6358_TOP_RST_CON1_CLR
#define PMIC_TOP_RST_CON1_CLR_MASK 0xFFFF
#define PMIC_TOP_RST_CON1_CLR_SHIFT   0
#define PMIC_RG_CHR_LDO_DET_MODE_ADDR MT6358_TOP_RST_CON2
#define PMIC_RG_CHR_LDO_DET_MODE_MASK 0x1
#define PMIC_RG_CHR_LDO_DET_MODE_SHIFT  0
#define PMIC_RG_CHR_LDO_DET_SW_ADDR   MT6358_TOP_RST_CON2
#define PMIC_RG_CHR_LDO_DET_SW_MASK   0x1
#define PMIC_RG_CHR_LDO_DET_SW_SHIFT  1
#define PMIC_RG_CHRWDT_FLAG_MODE_ADDR MT6358_TOP_RST_CON2
#define PMIC_RG_CHRWDT_FLAG_MODE_MASK 0x1
#define PMIC_RG_CHRWDT_FLAG_MODE_SHIFT  2
#define PMIC_RG_CHRWDT_FLAG_SW_ADDR   MT6358_TOP_RST_CON2
#define PMIC_RG_CHRWDT_FLAG_SW_MASK   0x1
#define PMIC_RG_CHRWDT_FLAG_SW_SHIFT  3
#define PMIC_TOP_RST_CON2_RSV_ADDR MT6358_TOP_RST_CON2
#define PMIC_TOP_RST_CON2_RSV_MASK 0xF
#define PMIC_TOP_RST_CON2_RSV_SHIFT   4
#define PMIC_RG_WDTRSTB_EN_ADDR MT6358_TOP_RST_MISC
#define PMIC_RG_WDTRSTB_EN_MASK 0x1
#define PMIC_RG_WDTRSTB_EN_SHIFT  0
#define PMIC_RG_WDTRSTB_MODE_ADDR MT6358_TOP_RST_MISC
#define PMIC_RG_WDTRSTB_MODE_MASK 0x1
#define PMIC_RG_WDTRSTB_MODE_SHIFT 1
#define PMIC_WDTRSTB_STATUS_ADDR  MT6358_TOP_RST_MISC
#define PMIC_WDTRSTB_STATUS_MASK  0x1
#define PMIC_WDTRSTB_STATUS_SHIFT 2
#define PMIC_WDTRSTB_STATUS_CLR_ADDR  MT6358_TOP_RST_MISC
#define PMIC_WDTRSTB_STATUS_CLR_MASK  0x1
#define PMIC_WDTRSTB_STATUS_CLR_SHIFT 3
#define PMIC_RG_WDTRSTB_FB_EN_ADDR MT6358_TOP_RST_MISC
#define PMIC_RG_WDTRSTB_FB_EN_MASK 0x1
#define PMIC_RG_WDTRSTB_FB_EN_SHIFT   4
#define PMIC_RG_WDTRSTB_DEB_ADDR  MT6358_TOP_RST_MISC
#define PMIC_RG_WDTRSTB_DEB_MASK  0x1
#define PMIC_RG_WDTRSTB_DEB_SHIFT 5
#define PMIC_RG_HOMEKEY_RST_EN_ADDR   MT6358_TOP_RST_MISC
#define PMIC_RG_HOMEKEY_RST_EN_MASK   0x1
#define PMIC_RG_HOMEKEY_RST_EN_SHIFT  8
#define PMIC_RG_PWRKEY_RST_EN_ADDR MT6358_TOP_RST_MISC
#define PMIC_RG_PWRKEY_RST_EN_MASK 0x1
#define PMIC_RG_PWRKEY_RST_EN_SHIFT   9
#define PMIC_RG_PWRRST_TMR_DIS_ADDR   MT6358_TOP_RST_MISC
#define PMIC_RG_PWRRST_TMR_DIS_MASK   0x1
#define PMIC_RG_PWRRST_TMR_DIS_SHIFT  10
#define PMIC_RG_PWRKEY_RST_TD_ADDR MT6358_TOP_RST_MISC
#define PMIC_RG_PWRKEY_RST_TD_MASK 0x3
#define PMIC_RG_PWRKEY_RST_TD_SHIFT   12
#define PMIC_TOP_RST_MISC_RSV_ADDR MT6358_TOP_RST_MISC
#define PMIC_TOP_RST_MISC_RSV_MASK 0x3
#define PMIC_TOP_RST_MISC_RSV_SHIFT   14
#define PMIC_TOP_RST_MISC_SET_ADDR MT6358_TOP_RST_MISC_SET
#define PMIC_TOP_RST_MISC_SET_MASK 0xFFFF
#define PMIC_TOP_RST_MISC_SET_SHIFT   0
#define PMIC_TOP_RST_MISC_CLR_ADDR MT6358_TOP_RST_MISC_CLR
#define PMIC_TOP_RST_MISC_CLR_MASK 0xFFFF
#define PMIC_TOP_RST_MISC_CLR_SHIFT   0
#define PMIC_VPWRIN_RSTB_STATUS_ADDR  MT6358_TOP_RST_STATUS
#define PMIC_VPWRIN_RSTB_STATUS_MASK  0x1
#define PMIC_VPWRIN_RSTB_STATUS_SHIFT 0
#define PMIC_DDLO_RSTB_STATUS_ADDR MT6358_TOP_RST_STATUS
#define PMIC_DDLO_RSTB_STATUS_MASK 0x1
#define PMIC_DDLO_RSTB_STATUS_SHIFT   1
#define PMIC_UVLO_RSTB_STATUS_ADDR MT6358_TOP_RST_STATUS
#define PMIC_UVLO_RSTB_STATUS_MASK 0x1
#define PMIC_UVLO_RSTB_STATUS_SHIFT   2
#define PMIC_RTC_DDLO_RSTB_STATUS_ADDR  MT6358_TOP_RST_STATUS
#define PMIC_RTC_DDLO_RSTB_STATUS_MASK  0x1
#define PMIC_RTC_DDLO_RSTB_STATUS_SHIFT 3
#define PMIC_CHRWDT_REG_RSTB_STATUS_ADDR   MT6358_TOP_RST_STATUS
#define PMIC_CHRWDT_REG_RSTB_STATUS_MASK   0x1
#define PMIC_CHRWDT_REG_RSTB_STATUS_SHIFT   4
#define PMIC_CHRDET_REG_RSTB_STATUS_ADDR   MT6358_TOP_RST_STATUS
#define PMIC_CHRDET_REG_RSTB_STATUS_MASK   0x1
#define PMIC_CHRDET_REG_RSTB_STATUS_SHIFT   5
#define PMIC_BWDT_DDLO_RSTB_STATUS_ADDR MT6358_TOP_RST_STATUS
#define PMIC_BWDT_DDLO_RSTB_STATUS_MASK 0x1
#define PMIC_BWDT_DDLO_RSTB_STATUS_SHIFT   6
#define PMIC_TOP_RST_STATUS_RSV_ADDR  MT6358_TOP_RST_STATUS
#define PMIC_TOP_RST_STATUS_RSV_MASK  0x1
#define PMIC_TOP_RST_STATUS_RSV_SHIFT 7
#define PMIC_TOP_RST_STATUS_SET_ADDR  MT6358_TOP_RST_STATUS_SET
#define PMIC_TOP_RST_STATUS_SET_MASK  0xFFFF
#define PMIC_TOP_RST_STATUS_SET_SHIFT 0
#define PMIC_TOP_RST_STATUS_CLR_ADDR  MT6358_TOP_RST_STATUS_CLR
#define PMIC_TOP_RST_STATUS_CLR_MASK  0xFFFF
#define PMIC_TOP_RST_STATUS_CLR_SHIFT 0
#define PMIC_TOP2_ELR_LEN_ADDR  MT6358_TOP2_ELR_NUM
#define PMIC_TOP2_ELR_LEN_MASK  0xFF
#define PMIC_TOP2_ELR_LEN_SHIFT 0
#define PMIC_RG_TOP2_RSV0_ADDR  MT6358_TOP2_ELR0
#define PMIC_RG_TOP2_RSV0_MASK  0xFFFF
#define PMIC_RG_TOP2_RSV0_SHIFT 0
#define PMIC_RG_TOP2_RSV1_ADDR  MT6358_TOP2_ELR1
#define PMIC_RG_TOP2_RSV1_MASK  0xFFFF
#define PMIC_RG_TOP2_RSV1_SHIFT 0
#define PMIC_TOP3_ANA_ID_ADDR   MT6358_TOP3_ID
#define PMIC_TOP3_ANA_ID_MASK   0xFF
#define PMIC_TOP3_ANA_ID_SHIFT  0
#define PMIC_TOP3_DIG_ID_ADDR   MT6358_TOP3_ID
#define PMIC_TOP3_DIG_ID_MASK   0xFF
#define PMIC_TOP3_DIG_ID_SHIFT  8
#define PMIC_TOP3_ANA_MINOR_REV_ADDR  MT6358_TOP3_REV0
#define PMIC_TOP3_ANA_MINOR_REV_MASK  0xF
#define PMIC_TOP3_ANA_MINOR_REV_SHIFT 0
#define PMIC_TOP3_ANA_MAJOR_REV_ADDR  MT6358_TOP3_REV0
#define PMIC_TOP3_ANA_MAJOR_REV_MASK  0xF
#define PMIC_TOP3_ANA_MAJOR_REV_SHIFT 4
#define PMIC_TOP3_DIG_MINOR_REV_ADDR  MT6358_TOP3_REV0
#define PMIC_TOP3_DIG_MINOR_REV_MASK  0xF
#define PMIC_TOP3_DIG_MINOR_REV_SHIFT 8
#define PMIC_TOP3_DIG_MAJOR_REV_ADDR  MT6358_TOP3_REV0
#define PMIC_TOP3_DIG_MAJOR_REV_MASK  0xF
#define PMIC_TOP3_DIG_MAJOR_REV_SHIFT 12
#define PMIC_TOP3_DSN_CBS_ADDR  MT6358_TOP3_DSN_DBI
#define PMIC_TOP3_DSN_CBS_MASK  0x3
#define PMIC_TOP3_DSN_CBS_SHIFT 0
#define PMIC_TOP3_DSN_BIX_ADDR  MT6358_TOP3_DSN_DBI
#define PMIC_TOP3_DSN_BIX_MASK  0x3
#define PMIC_TOP3_DSN_BIX_SHIFT 2
#define PMIC_TOP3_DSN_ESP_ADDR  MT6358_TOP3_DSN_DBI
#define PMIC_TOP3_DSN_ESP_MASK  0xFF
#define PMIC_TOP3_DSN_ESP_SHIFT 8
#define PMIC_TOP3_DSN_FPI_ADDR  MT6358_TOP3_DSN_DXI
#define PMIC_TOP3_DSN_FPI_MASK  0xFF
#define PMIC_TOP3_DSN_FPI_SHIFT 0
#define PMIC_RG_INT_EN_SPI_CMD_ALERT_ADDR   MT6358_MISC_TOP_INT_CON0
#define PMIC_RG_INT_EN_SPI_CMD_ALERT_MASK   0x1
#define PMIC_RG_INT_EN_SPI_CMD_ALERT_SHIFT  0
#define PMIC_MISC_TOP_INT_CON0_SET_ADDR MT6358_MISC_TOP_INT_CON0_SET
#define PMIC_MISC_TOP_INT_CON0_SET_MASK 0xFFFF
#define PMIC_MISC_TOP_INT_CON0_SET_SHIFT   0
#define PMIC_MISC_TOP_INT_CON0_CLR_ADDR MT6358_MISC_TOP_INT_CON0_CLR
#define PMIC_MISC_TOP_INT_CON0_CLR_MASK 0xFFFF
#define PMIC_MISC_TOP_INT_CON0_CLR_SHIFT   0
#define PMIC_RG_INT_MASK_SPI_CMD_ALERT_ADDR MT6358_MISC_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_SPI_CMD_ALERT_MASK 0x1
#define PMIC_RG_INT_MASK_SPI_CMD_ALERT_SHIFT  0
#define PMIC_MISC_TOP_INT_MASK_CON0_SET_ADDR  MT6358_MISC_TOP_INT_MASK_CON0_SET
#define PMIC_MISC_TOP_INT_MASK_CON0_SET_MASK  0xFFFF
#define PMIC_MISC_TOP_INT_MASK_CON0_SET_SHIFT 0
#define PMIC_MISC_TOP_INT_MASK_CON0_CLR_ADDR  MT6358_MISC_TOP_INT_MASK_CON0_CLR
#define PMIC_MISC_TOP_INT_MASK_CON0_CLR_MASK  0xFFFF
#define PMIC_MISC_TOP_INT_MASK_CON0_CLR_SHIFT 0
#define PMIC_RG_INT_STATUS_SPI_CMD_ALERT_ADDR MT6358_MISC_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_SPI_CMD_ALERT_MASK 0x1
#define PMIC_RG_INT_STATUS_SPI_CMD_ALERT_SHIFT   0
#define PMIC_RG_INT_RAW_STATUS_SPI_CMD_ALERT_ADDR \
MT6358_MISC_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_SPI_CMD_ALERT_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_SPI_CMD_ALERT_SHIFT  0
#define PMIC_RG_INT_MASK_BUCK_TOP_ADDR  MT6358_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_BUCK_TOP_MASK  0x1
#define PMIC_RG_INT_MASK_BUCK_TOP_SHIFT 0
#define PMIC_RG_INT_MASK_LDO_TOP_ADDR MT6358_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_LDO_TOP_MASK 0x1
#define PMIC_RG_INT_MASK_LDO_TOP_SHIFT  1
#define PMIC_RG_INT_MASK_PSC_TOP_ADDR MT6358_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_PSC_TOP_MASK 0x1
#define PMIC_RG_INT_MASK_PSC_TOP_SHIFT  2
#define PMIC_RG_INT_MASK_SCK_TOP_ADDR MT6358_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_SCK_TOP_MASK 0x1
#define PMIC_RG_INT_MASK_SCK_TOP_SHIFT  3
#define PMIC_RG_INT_MASK_BM_TOP_ADDR  MT6358_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_BM_TOP_MASK  0x1
#define PMIC_RG_INT_MASK_BM_TOP_SHIFT 4
#define PMIC_RG_INT_MASK_HK_TOP_ADDR  MT6358_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_HK_TOP_MASK  0x1
#define PMIC_RG_INT_MASK_HK_TOP_SHIFT 5
#define PMIC_RG_INT_MASK_XPP_TOP_ADDR MT6358_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_XPP_TOP_MASK 0x1
#define PMIC_RG_INT_MASK_XPP_TOP_SHIFT  6
#define PMIC_RG_INT_MASK_AUD_TOP_ADDR MT6358_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_AUD_TOP_MASK 0x1
#define PMIC_RG_INT_MASK_AUD_TOP_SHIFT  7
#define PMIC_RG_INT_MASK_MISC_TOP_ADDR  MT6358_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_MISC_TOP_MASK  0x1
#define PMIC_RG_INT_MASK_MISC_TOP_SHIFT 8
#define PMIC_TOP_INT_MASK_CON0_SET_ADDR MT6358_TOP_INT_MASK_CON0_SET
#define PMIC_TOP_INT_MASK_CON0_SET_MASK 0xFFFF
#define PMIC_TOP_INT_MASK_CON0_SET_SHIFT   0
#define PMIC_TOP_INT_MASK_CON0_CLR_ADDR MT6358_TOP_INT_MASK_CON0_CLR
#define PMIC_TOP_INT_MASK_CON0_CLR_MASK 0xFFFF
#define PMIC_TOP_INT_MASK_CON0_CLR_SHIFT   0
#define PMIC_INT_STATUS_BUCK_TOP_ADDR MT6358_TOP_INT_STATUS0
#define PMIC_INT_STATUS_BUCK_TOP_MASK 0x1
#define PMIC_INT_STATUS_BUCK_TOP_SHIFT  0
#define PMIC_INT_STATUS_LDO_TOP_ADDR  MT6358_TOP_INT_STATUS0
#define PMIC_INT_STATUS_LDO_TOP_MASK  0x1
#define PMIC_INT_STATUS_LDO_TOP_SHIFT 1
#define PMIC_INT_STATUS_PSC_TOP_ADDR  MT6358_TOP_INT_STATUS0
#define PMIC_INT_STATUS_PSC_TOP_MASK  0x1
#define PMIC_INT_STATUS_PSC_TOP_SHIFT 2
#define PMIC_INT_STATUS_SCK_TOP_ADDR  MT6358_TOP_INT_STATUS0
#define PMIC_INT_STATUS_SCK_TOP_MASK  0x1
#define PMIC_INT_STATUS_SCK_TOP_SHIFT 3
#define PMIC_INT_STATUS_BM_TOP_ADDR   MT6358_TOP_INT_STATUS0
#define PMIC_INT_STATUS_BM_TOP_MASK   0x1
#define PMIC_INT_STATUS_BM_TOP_SHIFT  4
#define PMIC_INT_STATUS_HK_TOP_ADDR   MT6358_TOP_INT_STATUS0
#define PMIC_INT_STATUS_HK_TOP_MASK   0x1
#define PMIC_INT_STATUS_HK_TOP_SHIFT  5
#define PMIC_INT_STATUS_XPP_TOP_ADDR  MT6358_TOP_INT_STATUS0
#define PMIC_INT_STATUS_XPP_TOP_MASK  0x1
#define PMIC_INT_STATUS_XPP_TOP_SHIFT 6
#define PMIC_INT_STATUS_AUD_TOP_ADDR  MT6358_TOP_INT_STATUS0
#define PMIC_INT_STATUS_AUD_TOP_MASK  0x1
#define PMIC_INT_STATUS_AUD_TOP_SHIFT 7
#define PMIC_INT_STATUS_MISC_TOP_ADDR MT6358_TOP_INT_STATUS0
#define PMIC_INT_STATUS_MISC_TOP_MASK 0x1
#define PMIC_INT_STATUS_MISC_TOP_SHIFT  8
#define PMIC_INT_STATUS_TOP_RSV_ADDR  MT6358_TOP_INT_STATUS0
#define PMIC_INT_STATUS_TOP_RSV_MASK  0x7F
#define PMIC_INT_STATUS_TOP_RSV_SHIFT 9
#define PMIC_INT_RAW_STATUS_BUCK_TOP_ADDR   MT6358_TOP_INT_RAW_STATUS0
#define PMIC_INT_RAW_STATUS_BUCK_TOP_MASK   0x1
#define PMIC_INT_RAW_STATUS_BUCK_TOP_SHIFT  0
#define PMIC_INT_RAW_STATUS_LDO_TOP_ADDR   MT6358_TOP_INT_RAW_STATUS0
#define PMIC_INT_RAW_STATUS_LDO_TOP_MASK   0x1
#define PMIC_INT_RAW_STATUS_LDO_TOP_SHIFT   1
#define PMIC_INT_RAW_STATUS_PSC_TOP_ADDR   MT6358_TOP_INT_RAW_STATUS0
#define PMIC_INT_RAW_STATUS_PSC_TOP_MASK   0x1
#define PMIC_INT_RAW_STATUS_PSC_TOP_SHIFT   2
#define PMIC_INT_RAW_STATUS_SCK_TOP_ADDR   MT6358_TOP_INT_RAW_STATUS0
#define PMIC_INT_RAW_STATUS_SCK_TOP_MASK   0x1
#define PMIC_INT_RAW_STATUS_SCK_TOP_SHIFT   3
#define PMIC_INT_RAW_STATUS_BM_TOP_ADDR MT6358_TOP_INT_RAW_STATUS0
#define PMIC_INT_RAW_STATUS_BM_TOP_MASK 0x1
#define PMIC_INT_RAW_STATUS_BM_TOP_SHIFT   4
#define PMIC_INT_RAW_STATUS_HK_TOP_ADDR MT6358_TOP_INT_RAW_STATUS0
#define PMIC_INT_RAW_STATUS_HK_TOP_MASK 0x1
#define PMIC_INT_RAW_STATUS_HK_TOP_SHIFT   5
#define PMIC_INT_RAW_STATUS_XPP_TOP_ADDR   MT6358_TOP_INT_RAW_STATUS0
#define PMIC_INT_RAW_STATUS_XPP_TOP_MASK   0x1
#define PMIC_INT_RAW_STATUS_XPP_TOP_SHIFT   6
#define PMIC_INT_RAW_STATUS_AUD_TOP_ADDR   MT6358_TOP_INT_RAW_STATUS0
#define PMIC_INT_RAW_STATUS_AUD_TOP_MASK   0x1
#define PMIC_INT_RAW_STATUS_AUD_TOP_SHIFT   7
#define PMIC_INT_RAW_STATUS_MISC_TOP_ADDR   MT6358_TOP_INT_RAW_STATUS0
#define PMIC_INT_RAW_STATUS_MISC_TOP_MASK   0x1
#define PMIC_INT_RAW_STATUS_MISC_TOP_SHIFT  8
#define PMIC_INT_RAW_STATUS_TOP_RSV_ADDR   MT6358_TOP_INT_RAW_STATUS0
#define PMIC_INT_RAW_STATUS_TOP_RSV_MASK   0x7F
#define PMIC_INT_RAW_STATUS_TOP_RSV_SHIFT   9
#define PMIC_RG_INT_POLARITY_ADDR MT6358_TOP_INT_CON0
#define PMIC_RG_INT_POLARITY_MASK 0x1
#define PMIC_RG_INT_POLARITY_SHIFT 0
#define PMIC_PLT0_ANA_ID_ADDR   MT6358_PLT0_ID
#define PMIC_PLT0_ANA_ID_MASK   0xFF
#define PMIC_PLT0_ANA_ID_SHIFT  0
#define PMIC_PLT0_DIG_ID_ADDR   MT6358_PLT0_ID
#define PMIC_PLT0_DIG_ID_MASK   0xFF
#define PMIC_PLT0_DIG_ID_SHIFT  8
#define PMIC_PLT0_ANA_MINOR_REV_ADDR  MT6358_PLT0_REV0
#define PMIC_PLT0_ANA_MINOR_REV_MASK  0xF
#define PMIC_PLT0_ANA_MINOR_REV_SHIFT 0
#define PMIC_PLT0_ANA_MAJOR_REV_ADDR  MT6358_PLT0_REV0
#define PMIC_PLT0_ANA_MAJOR_REV_MASK  0xF
#define PMIC_PLT0_ANA_MAJOR_REV_SHIFT 4
#define PMIC_PLT0_DIG_MINOR_REV_ADDR  MT6358_PLT0_REV0
#define PMIC_PLT0_DIG_MINOR_REV_MASK  0xF
#define PMIC_PLT0_DIG_MINOR_REV_SHIFT 8
#define PMIC_PLT0_DIG_MAJOR_REV_ADDR  MT6358_PLT0_REV0
#define PMIC_PLT0_DIG_MAJOR_REV_MASK  0xF
#define PMIC_PLT0_DIG_MAJOR_REV_SHIFT 12
#define PMIC_PLT0_DSN_CBS_ADDR  MT6358_PLT0_REV1
#define PMIC_PLT0_DSN_CBS_MASK  0x3
#define PMIC_PLT0_DSN_CBS_SHIFT 0
#define PMIC_PLT0_DSN_BIX_ADDR  MT6358_PLT0_REV1
#define PMIC_PLT0_DSN_BIX_MASK  0x3
#define PMIC_PLT0_DSN_BIX_SHIFT 2
#define PMIC_PLT0_DSN_ESP_ADDR  MT6358_PLT0_REV1
#define PMIC_PLT0_DSN_ESP_MASK  0xFF
#define PMIC_PLT0_DSN_ESP_SHIFT 8
#define PMIC_PLT0_DSN_FPI_ADDR  MT6358_PLT0_DSN_DXI
#define PMIC_PLT0_DSN_FPI_MASK  0xFF
#define PMIC_PLT0_DSN_FPI_SHIFT 0
#define PMIC_RG_OSC_128K_TRIM_EN_ADDR MT6358_TOP_CLK_TRIM
#define PMIC_RG_OSC_128K_TRIM_EN_MASK 0x1
#define PMIC_RG_OSC_128K_TRIM_EN_SHIFT  6
#define PMIC_RG_OSC_128K_TRIM_RATE_ADDR MT6358_TOP_CLK_TRIM
#define PMIC_RG_OSC_128K_TRIM_RATE_MASK 0x3
#define PMIC_RG_OSC_128K_TRIM_RATE_SHIFT   7
#define PMIC_DA_OSC_128K_TRIM_ADDR MT6358_TOP_CLK_TRIM
#define PMIC_DA_OSC_128K_TRIM_MASK 0x3F
#define PMIC_DA_OSC_128K_TRIM_SHIFT   9
#define PMIC_RG_OTP_PA_ADDR  MT6358_OTP_CON0
#define PMIC_RG_OTP_PA_MASK  0xFF
#define PMIC_RG_OTP_PA_SHIFT 0
#define PMIC_RG_OTP_PDIN_ADDR   MT6358_OTP_CON1
#define PMIC_RG_OTP_PDIN_MASK   0xFF
#define PMIC_RG_OTP_PDIN_SHIFT  0
#define PMIC_RG_OTP_PTM_ADDR MT6358_OTP_CON2
#define PMIC_RG_OTP_PTM_MASK 0x3
#define PMIC_RG_OTP_PTM_SHIFT   0
#define PMIC_RG_OTP_PWE_ADDR MT6358_OTP_CON3
#define PMIC_RG_OTP_PWE_MASK 0x3
#define PMIC_RG_OTP_PWE_SHIFT   0
#define PMIC_RG_OTP_PPROG_ADDR  MT6358_OTP_CON4
#define PMIC_RG_OTP_PPROG_MASK  0x1
#define PMIC_RG_OTP_PPROG_SHIFT 0
#define PMIC_RG_OTP_PWE_SRC_ADDR  MT6358_OTP_CON5
#define PMIC_RG_OTP_PWE_SRC_MASK  0x1
#define PMIC_RG_OTP_PWE_SRC_SHIFT 0
#define PMIC_RG_OTP_PROG_PKEY_ADDR MT6358_OTP_CON6
#define PMIC_RG_OTP_PROG_PKEY_MASK 0xFFFF
#define PMIC_RG_OTP_PROG_PKEY_SHIFT   0
#define PMIC_RG_OTP_RD_PKEY_ADDR  MT6358_OTP_CON7
#define PMIC_RG_OTP_RD_PKEY_MASK  0xFFFF
#define PMIC_RG_OTP_RD_PKEY_SHIFT 0
#define PMIC_RG_OTP_RD_TRIG_ADDR  MT6358_OTP_CON8
#define PMIC_RG_OTP_RD_TRIG_MASK  0x1
#define PMIC_RG_OTP_RD_TRIG_SHIFT 0
#define PMIC_RG_RD_RDY_BYPASS_ADDR MT6358_OTP_CON9
#define PMIC_RG_RD_RDY_BYPASS_MASK 0x1
#define PMIC_RG_RD_RDY_BYPASS_SHIFT   0
#define PMIC_RG_SKIP_OTP_OUT_ADDR MT6358_OTP_CON10
#define PMIC_RG_SKIP_OTP_OUT_MASK 0x1
#define PMIC_RG_SKIP_OTP_OUT_SHIFT 0
#define PMIC_RG_OTP_RD_SW_ADDR  MT6358_OTP_CON11
#define PMIC_RG_OTP_RD_SW_MASK  0x1
#define PMIC_RG_OTP_RD_SW_SHIFT 0
#define PMIC_RG_OTP_DOUT_SW_ADDR  MT6358_OTP_CON12
#define PMIC_RG_OTP_DOUT_SW_MASK  0xFFFF
#define PMIC_RG_OTP_DOUT_SW_SHIFT 0
#define PMIC_RG_OTP_RD_BUSY_ADDR  MT6358_OTP_CON13
#define PMIC_RG_OTP_RD_BUSY_MASK  0x1
#define PMIC_RG_OTP_RD_BUSY_SHIFT 0
#define PMIC_RG_OTP_RD_ACK_ADDR MT6358_OTP_CON13
#define PMIC_RG_OTP_RD_ACK_MASK 0x1
#define PMIC_RG_OTP_RD_ACK_SHIFT  2
#define PMIC_RG_OTP_PA_SW_ADDR  MT6358_OTP_CON14
#define PMIC_RG_OTP_PA_SW_MASK  0x7F
#define PMIC_RG_OTP_PA_SW_SHIFT 0
#define PMIC_TMA_KEY_ADDR MT6358_TOP_TMA_KEY
#define PMIC_TMA_KEY_MASK 0xFFFF
#define PMIC_TMA_KEY_SHIFT  0
#define PMIC_TOP_MDB_RSV0_ADDR  MT6358_TOP_MDB_CONF0
#define PMIC_TOP_MDB_RSV0_MASK  0xFFFF
#define PMIC_TOP_MDB_RSV0_SHIFT 0
#define PMIC_RG_MDB_DM1_DS_EN_ADDR MT6358_TOP_MDB_CONF1
#define PMIC_RG_MDB_DM1_DS_EN_MASK 0x1
#define PMIC_RG_MDB_DM1_DS_EN_SHIFT   0
#define PMIC_TOP_MDB_RSV1_ADDR  MT6358_TOP_MDB_CONF1
#define PMIC_TOP_MDB_RSV1_MASK  0x7FFF
#define PMIC_TOP_MDB_RSV1_SHIFT 1
#define PMIC_RG_PMU_MDB_BRIDGE_BYPASS_EN_ADDR MT6358_TOP_MDB_CONF2
#define PMIC_RG_PMU_MDB_BRIDGE_BYPASS_EN_MASK 0x1
#define PMIC_RG_PMU_MDB_BRIDGE_BYPASS_EN_SHIFT   0
#define PMIC_PLT0_ELR_LEN_ADDR  MT6358_PLT0_ELR_NUM
#define PMIC_PLT0_ELR_LEN_MASK  0xFF
#define PMIC_PLT0_ELR_LEN_SHIFT 0
#define PMIC_RG_OSC_128K_TRIM_ADDR MT6358_PLT0_ELR0
#define PMIC_RG_OSC_128K_TRIM_MASK 0x3F
#define PMIC_RG_OSC_128K_TRIM_SHIFT   0
#define PMIC_EFUSE_OSC_MODE_ADDR  MT6358_PLT0_ELR1
#define PMIC_EFUSE_OSC_MODE_MASK  0x3
#define PMIC_EFUSE_OSC_MODE_SHIFT 0
#define PMIC_SPISLV_ANA_ID_ADDR MT6358_SPISLV_ID
#define PMIC_SPISLV_ANA_ID_MASK 0xFF
#define PMIC_SPISLV_ANA_ID_SHIFT  0
#define PMIC_SPISLV_DIG_ID_ADDR MT6358_SPISLV_ID
#define PMIC_SPISLV_DIG_ID_MASK 0xFF
#define PMIC_SPISLV_DIG_ID_SHIFT  8
#define PMIC_SPISLV_ANA_MINOR_REV_ADDR  MT6358_SPISLV_REV0
#define PMIC_SPISLV_ANA_MINOR_REV_MASK  0xF
#define PMIC_SPISLV_ANA_MINOR_REV_SHIFT 0
#define PMIC_SPISLV_ANA_MAJOR_REV_ADDR  MT6358_SPISLV_REV0
#define PMIC_SPISLV_ANA_MAJOR_REV_MASK  0xF
#define PMIC_SPISLV_ANA_MAJOR_REV_SHIFT 4
#define PMIC_SPISLV_DIG_MINOR_REV_ADDR  MT6358_SPISLV_REV0
#define PMIC_SPISLV_DIG_MINOR_REV_MASK  0xF
#define PMIC_SPISLV_DIG_MINOR_REV_SHIFT 8
#define PMIC_SPISLV_DIG_MAJOR_REV_ADDR  MT6358_SPISLV_REV0
#define PMIC_SPISLV_DIG_MAJOR_REV_MASK  0xF
#define PMIC_SPISLV_DIG_MAJOR_REV_SHIFT 12
#define PMIC_SPISLV_DSN_CBS_ADDR  MT6358_SPISLV_REV1
#define PMIC_SPISLV_DSN_CBS_MASK  0x3
#define PMIC_SPISLV_DSN_CBS_SHIFT 0
#define PMIC_SPISLV_DSN_BIX_ADDR  MT6358_SPISLV_REV1
#define PMIC_SPISLV_DSN_BIX_MASK  0x3
#define PMIC_SPISLV_DSN_BIX_SHIFT 2
#define PMIC_SPISLV_DSN_ESP_ADDR  MT6358_SPISLV_REV1
#define PMIC_SPISLV_DSN_ESP_MASK  0xFF
#define PMIC_SPISLV_DSN_ESP_SHIFT 8
#define PMIC_SPISLV_DSN_FPI_ADDR  MT6358_SPISLV_DSN_DXI
#define PMIC_SPISLV_DSN_FPI_MASK  0xFF
#define PMIC_SPISLV_DSN_FPI_SHIFT 0
#define PMIC_RG_SLP_RW_EN_ADDR  MT6358_RG_SPI_CON0
#define PMIC_RG_SLP_RW_EN_MASK  0x1
#define PMIC_RG_SLP_RW_EN_SHIFT 0
#define PMIC_RG_EN_RECORD_ADDR  MT6358_RG_SPI_RECORD0
#define PMIC_RG_EN_RECORD_MASK  0x1
#define PMIC_RG_EN_RECORD_SHIFT 0
#define PMIC_RG_SPI_RSV_ADDR MT6358_RG_SPI_RECORD0
#define PMIC_RG_SPI_RSV_MASK 0x7FFF
#define PMIC_RG_SPI_RSV_SHIFT   1
#define PMIC_DEW_DIO_EN_ADDR MT6358_DEW_DIO_EN
#define PMIC_DEW_DIO_EN_MASK 0x1
#define PMIC_DEW_DIO_EN_SHIFT   0
#define PMIC_DEW_READ_TEST_ADDR MT6358_DEW_READ_TEST
#define PMIC_DEW_READ_TEST_MASK 0xFFFF
#define PMIC_DEW_READ_TEST_SHIFT  0
#define PMIC_DEW_WRITE_TEST_ADDR  MT6358_DEW_WRITE_TEST
#define PMIC_DEW_WRITE_TEST_MASK  0xFFFF
#define PMIC_DEW_WRITE_TEST_SHIFT 0
#define PMIC_DEW_CRC_SWRST_ADDR MT6358_DEW_CRC_SWRST
#define PMIC_DEW_CRC_SWRST_MASK 0x1
#define PMIC_DEW_CRC_SWRST_SHIFT  0
#define PMIC_DEW_CRC_EN_ADDR MT6358_DEW_CRC_EN
#define PMIC_DEW_CRC_EN_MASK 0x1
#define PMIC_DEW_CRC_EN_SHIFT   0
#define PMIC_DEW_CRC_VAL_ADDR   MT6358_DEW_CRC_VAL
#define PMIC_DEW_CRC_VAL_MASK   0xFF
#define PMIC_DEW_CRC_VAL_SHIFT  0
#define PMIC_DEW_DBG_MON_SEL_ADDR MT6358_DEW_DBG_MON_SEL
#define PMIC_DEW_DBG_MON_SEL_MASK 0xF
#define PMIC_DEW_DBG_MON_SEL_SHIFT 0
#define PMIC_DEW_CIPHER_KEY_SEL_ADDR  MT6358_DEW_CIPHER_KEY_SEL
#define PMIC_DEW_CIPHER_KEY_SEL_MASK  0x3
#define PMIC_DEW_CIPHER_KEY_SEL_SHIFT 0
#define PMIC_DEW_CIPHER_IV_SEL_ADDR   MT6358_DEW_CIPHER_IV_SEL
#define PMIC_DEW_CIPHER_IV_SEL_MASK   0x3
#define PMIC_DEW_CIPHER_IV_SEL_SHIFT  0
#define PMIC_DEW_CIPHER_EN_ADDR MT6358_DEW_CIPHER_EN
#define PMIC_DEW_CIPHER_EN_MASK 0x1
#define PMIC_DEW_CIPHER_EN_SHIFT  0
#define PMIC_DEW_CIPHER_RDY_ADDR  MT6358_DEW_CIPHER_RDY
#define PMIC_DEW_CIPHER_RDY_MASK  0x1
#define PMIC_DEW_CIPHER_RDY_SHIFT 0
#define PMIC_DEW_CIPHER_MODE_ADDR MT6358_DEW_CIPHER_MODE
#define PMIC_DEW_CIPHER_MODE_MASK 0x1
#define PMIC_DEW_CIPHER_MODE_SHIFT 0
#define PMIC_DEW_CIPHER_SWRST_ADDR MT6358_DEW_CIPHER_SWRST
#define PMIC_DEW_CIPHER_SWRST_MASK 0x1
#define PMIC_DEW_CIPHER_SWRST_SHIFT   0
#define PMIC_DEW_RDDMY_NO_ADDR  MT6358_DEW_RDDMY_NO
#define PMIC_DEW_RDDMY_NO_MASK  0xF
#define PMIC_DEW_RDDMY_NO_SHIFT 0
#define PMIC_INT_TYPE_CON0_ADDR MT6358_INT_TYPE_CON0
#define PMIC_INT_TYPE_CON0_MASK 0xFFFF
#define PMIC_INT_TYPE_CON0_SHIFT  0
#define PMIC_INT_TYPE_CON0_SET_ADDR   MT6358_INT_TYPE_CON0_SET
#define PMIC_INT_TYPE_CON0_SET_MASK   0xFFFF
#define PMIC_INT_TYPE_CON0_SET_SHIFT  0
#define PMIC_INT_TYPE_CON0_CLR_ADDR   MT6358_INT_TYPE_CON0_CLR
#define PMIC_INT_TYPE_CON0_CLR_MASK   0xFFFF
#define PMIC_INT_TYPE_CON0_CLR_SHIFT  0
#define PMIC_CPU_INT_STA_ADDR   MT6358_INT_STA
#define PMIC_CPU_INT_STA_MASK   0x1
#define PMIC_CPU_INT_STA_SHIFT  0
#define PMIC_MD32_INT_STA_ADDR  MT6358_INT_STA
#define PMIC_MD32_INT_STA_MASK  0x1
#define PMIC_MD32_INT_STA_SHIFT 1
#define PMIC_RG_SRCLKEN_IN3_SMPS_CLK_MODE_ADDR   MT6358_RG_SPI_CON1
#define PMIC_RG_SRCLKEN_IN3_SMPS_CLK_MODE_MASK   0x1
#define PMIC_RG_SRCLKEN_IN3_SMPS_CLK_MODE_SHIFT  0
#define PMIC_RG_SRCLKEN_IN3_EN_SMPS_TEST_ADDR MT6358_RG_SPI_CON1
#define PMIC_RG_SRCLKEN_IN3_EN_SMPS_TEST_MASK 0x1
#define PMIC_RG_SRCLKEN_IN3_EN_SMPS_TEST_SHIFT   1
#define PMIC_RG_SRCLKEN_IN2_SMPS_CLK_MODE_ADDR   MT6358_RG_SPI_CON1
#define PMIC_RG_SRCLKEN_IN2_SMPS_CLK_MODE_MASK   0x1
#define PMIC_RG_SRCLKEN_IN2_SMPS_CLK_MODE_SHIFT  2
#define PMIC_RG_SRCLKEN_IN2_EN_SMPS_TEST_ADDR MT6358_RG_SPI_CON1
#define PMIC_RG_SRCLKEN_IN2_EN_SMPS_TEST_MASK 0x1
#define PMIC_RG_SRCLKEN_IN2_EN_SMPS_TEST_SHIFT   3
#define PMIC_RG_SPI_DLY_SEL_ADDR  MT6358_RG_SPI_CON2
#define PMIC_RG_SPI_DLY_SEL_MASK  0xF
#define PMIC_RG_SPI_DLY_SEL_SHIFT 0
#define PMIC_RECORD_CMD0_ADDR   MT6358_RG_SPI_CON3
#define PMIC_RECORD_CMD0_MASK   0xFFFF
#define PMIC_RECORD_CMD0_SHIFT  0
#define PMIC_RECORD_CMD1_ADDR   MT6358_RG_SPI_CON4
#define PMIC_RECORD_CMD1_MASK   0xFFFF
#define PMIC_RECORD_CMD1_SHIFT  0
#define PMIC_RECORD_CMD2_ADDR   MT6358_RG_SPI_CON5
#define PMIC_RECORD_CMD2_MASK   0xFFFF
#define PMIC_RECORD_CMD2_SHIFT  0
#define PMIC_RECORD_WDATA0_ADDR MT6358_RG_SPI_CON6
#define PMIC_RECORD_WDATA0_MASK 0xFFFF
#define PMIC_RECORD_WDATA0_SHIFT  0
#define PMIC_RECORD_WDATA1_ADDR MT6358_RG_SPI_CON7
#define PMIC_RECORD_WDATA1_MASK 0xFFFF
#define PMIC_RECORD_WDATA1_SHIFT  0
#define PMIC_RECORD_WDATA2_ADDR MT6358_RG_SPI_CON8
#define PMIC_RECORD_WDATA2_MASK 0xFFFF
#define PMIC_RECORD_WDATA2_SHIFT  0
#define PMIC_RG_ADDR_TARGET_ADDR  MT6358_RG_SPI_CON9
#define PMIC_RG_ADDR_TARGET_MASK  0xFFFF
#define PMIC_RG_ADDR_TARGET_SHIFT 0
#define PMIC_RG_ADDR_MASK_ADDR  MT6358_RG_SPI_CON10
#define PMIC_RG_ADDR_MASK_MASK  0xFFFF
#define PMIC_RG_ADDR_MASK_SHIFT 0
#define PMIC_RG_WDATA_TARGET_ADDR MT6358_RG_SPI_CON11
#define PMIC_RG_WDATA_TARGET_MASK 0xFFFF
#define PMIC_RG_WDATA_TARGET_SHIFT 0
#define PMIC_RG_WDATA_MASK_ADDR MT6358_RG_SPI_CON12
#define PMIC_RG_WDATA_MASK_MASK 0xFFFF
#define PMIC_RG_WDATA_MASK_SHIFT  0
#define PMIC_RG_SPI_RECORD_CLR_ADDR   MT6358_RG_SPI_CON13
#define PMIC_RG_SPI_RECORD_CLR_MASK   0x1
#define PMIC_RG_SPI_RECORD_CLR_SHIFT  0
#define PMIC_RG_CMD_ALERT_CLR_ADDR MT6358_RG_SPI_CON13
#define PMIC_RG_CMD_ALERT_CLR_MASK 0x1
#define PMIC_RG_CMD_ALERT_CLR_SHIFT   15
#define PMIC_SPISLV_KEY_ADDR MT6358_SPISLV_KEY
#define PMIC_SPISLV_KEY_MASK 0xFFFF
#define PMIC_SPISLV_KEY_SHIFT   0
#define PMIC_RG_SRCLKEN_IN2_EN_ADDR   MT6358_TOP_SPI_CON0
#define PMIC_RG_SRCLKEN_IN2_EN_MASK   0x1
#define PMIC_RG_SRCLKEN_IN2_EN_SHIFT  0
#define PMIC_RG_SRCLKEN_IN3_EN_ADDR   MT6358_TOP_SPI_CON1
#define PMIC_RG_SRCLKEN_IN3_EN_MASK   0x1
#define PMIC_RG_SRCLKEN_IN3_EN_SHIFT  0
#define PMIC_SCK_TOP_ANA_ID_ADDR  MT6358_SCK_TOP_DSN_ID
#define PMIC_SCK_TOP_ANA_ID_MASK  0xFF
#define PMIC_SCK_TOP_ANA_ID_SHIFT 0
#define PMIC_SCK_TOP_DIG_ID_ADDR  MT6358_SCK_TOP_DSN_ID
#define PMIC_SCK_TOP_DIG_ID_MASK  0xFF
#define PMIC_SCK_TOP_DIG_ID_SHIFT 8
#define PMIC_SCK_TOP_ANA_MINOR_REV_ADDR MT6358_SCK_TOP_DSN_REV0
#define PMIC_SCK_TOP_ANA_MINOR_REV_MASK 0xF
#define PMIC_SCK_TOP_ANA_MINOR_REV_SHIFT   0
#define PMIC_SCK_TOP_ANA_MAJOR_REV_ADDR MT6358_SCK_TOP_DSN_REV0
#define PMIC_SCK_TOP_ANA_MAJOR_REV_MASK 0xF
#define PMIC_SCK_TOP_ANA_MAJOR_REV_SHIFT   4
#define PMIC_SCK_TOP_DIG_MINOR_REV_ADDR MT6358_SCK_TOP_DSN_REV0
#define PMIC_SCK_TOP_DIG_MINOR_REV_MASK 0xF
#define PMIC_SCK_TOP_DIG_MINOR_REV_SHIFT   8
#define PMIC_SCK_TOP_DIG_MAJOR_REV_ADDR MT6358_SCK_TOP_DSN_REV0
#define PMIC_SCK_TOP_DIG_MAJOR_REV_MASK 0xF
#define PMIC_SCK_TOP_DIG_MAJOR_REV_SHIFT   12
#define PMIC_SCK_TOP_CBS_ADDR   MT6358_SCK_TOP_DBI
#define PMIC_SCK_TOP_CBS_MASK   0x3
#define PMIC_SCK_TOP_CBS_SHIFT  0
#define PMIC_SCK_TOP_BIX_ADDR   MT6358_SCK_TOP_DBI
#define PMIC_SCK_TOP_BIX_MASK   0x3
#define PMIC_SCK_TOP_BIX_SHIFT  2
#define PMIC_SCK_TOP_ESP_ADDR   MT6358_SCK_TOP_DBI
#define PMIC_SCK_TOP_ESP_MASK   0xFF
#define PMIC_SCK_TOP_ESP_SHIFT  8
#define PMIC_SCK_TOP_FPI_ADDR   MT6358_SCK_TOP_DXI
#define PMIC_SCK_TOP_FPI_MASK   0xFF
#define PMIC_SCK_TOP_FPI_SHIFT  0
#define PMIC_SCK_TOP_CLK_OFFSET_ADDR  MT6358_SCK_TOP_TPM0
#define PMIC_SCK_TOP_CLK_OFFSET_MASK  0xFF
#define PMIC_SCK_TOP_CLK_OFFSET_SHIFT 0
#define PMIC_SCK_TOP_RST_OFFSET_ADDR  MT6358_SCK_TOP_TPM0
#define PMIC_SCK_TOP_RST_OFFSET_MASK  0xFF
#define PMIC_SCK_TOP_RST_OFFSET_SHIFT 8
#define PMIC_SCK_TOP_INT_OFFSET_ADDR  MT6358_SCK_TOP_TPM1
#define PMIC_SCK_TOP_INT_OFFSET_MASK  0xFF
#define PMIC_SCK_TOP_INT_OFFSET_SHIFT 0
#define PMIC_SCK_TOP_INT_LEN_ADDR MT6358_SCK_TOP_TPM1
#define PMIC_SCK_TOP_INT_LEN_MASK 0xFF
#define PMIC_SCK_TOP_INT_LEN_SHIFT 8
#define PMIC_SCK_TOP_XTAL_SEL_ADDR MT6358_SCK_TOP_CON0
#define PMIC_SCK_TOP_XTAL_SEL_MASK 0x1
#define PMIC_SCK_TOP_XTAL_SEL_SHIFT   0
#define PMIC_SCK_TOP_RESERVED_ADDR MT6358_SCK_TOP_CON0
#define PMIC_SCK_TOP_RESERVED_MASK 0x7FFF
#define PMIC_SCK_TOP_RESERVED_SHIFT   1
#define PMIC_XOSC32_ENB_DET_ADDR  MT6358_SCK_TOP_CON1
#define PMIC_XOSC32_ENB_DET_MASK  0x1
#define PMIC_XOSC32_ENB_DET_SHIFT 0
#define PMIC_SCK_TOP_TEST_OUT_ADDR MT6358_SCK_TOP_TEST_OUT
#define PMIC_SCK_TOP_TEST_OUT_MASK 0xFF
#define PMIC_SCK_TOP_TEST_OUT_SHIFT   0
#define PMIC_SCK_TOP_MON_FLAG_SEL_ADDR  MT6358_SCK_TOP_TEST_CON0
#define PMIC_SCK_TOP_MON_FLAG_SEL_MASK  0xFF
#define PMIC_SCK_TOP_MON_FLAG_SEL_SHIFT 0
#define PMIC_SCK_TOP_MON_GRP_SEL_ADDR MT6358_SCK_TOP_TEST_CON0
#define PMIC_SCK_TOP_MON_GRP_SEL_MASK 0x3
#define PMIC_SCK_TOP_MON_GRP_SEL_SHIFT  8
#define PMIC_FQMTR_TCKSEL_ADDR  MT6358_FQMTR_CON0
#define PMIC_FQMTR_TCKSEL_MASK  0x7
#define PMIC_FQMTR_TCKSEL_SHIFT 0
#define PMIC_FQMTR_BUSY_ADDR MT6358_FQMTR_CON0
#define PMIC_FQMTR_BUSY_MASK 0x1
#define PMIC_FQMTR_BUSY_SHIFT   3
#define PMIC_FQMTR_DCXO26M_EN_ADDR MT6358_FQMTR_CON0
#define PMIC_FQMTR_DCXO26M_EN_MASK 0x1
#define PMIC_FQMTR_DCXO26M_EN_SHIFT   4
#define PMIC_FQMTR_EN_ADDR  MT6358_FQMTR_CON0
#define PMIC_FQMTR_EN_MASK  0x1
#define PMIC_FQMTR_EN_SHIFT  15
#define PMIC_FQMTR_WINSET_ADDR  MT6358_FQMTR_CON1
#define PMIC_FQMTR_WINSET_MASK  0xFFFF
#define PMIC_FQMTR_WINSET_SHIFT 0
#define PMIC_FQMTR_DATA_ADDR MT6358_FQMTR_CON2
#define PMIC_FQMTR_DATA_MASK 0xFFFF
#define PMIC_FQMTR_DATA_SHIFT   0
#define PMIC_RG_RTC_SEC_MCLK_PDN_ADDR MT6358_SCK_TOP_CKPDN_CON0
#define PMIC_RG_RTC_SEC_MCLK_PDN_MASK 0x1
#define PMIC_RG_RTC_SEC_MCLK_PDN_SHIFT  0
#define PMIC_RG_EOSC_CALI_TEST_CK_PDN_ADDR  MT6358_SCK_TOP_CKPDN_CON0
#define PMIC_RG_EOSC_CALI_TEST_CK_PDN_MASK  0x1
#define PMIC_RG_EOSC_CALI_TEST_CK_PDN_SHIFT 1
#define PMIC_RG_RTC_EOSC32_CK_PDN_ADDR  MT6358_SCK_TOP_CKPDN_CON0
#define PMIC_RG_RTC_EOSC32_CK_PDN_MASK  0x1
#define PMIC_RG_RTC_EOSC32_CK_PDN_SHIFT 2
#define PMIC_RG_RTC_SEC_32K_CK_PDN_ADDR MT6358_SCK_TOP_CKPDN_CON0
#define PMIC_RG_RTC_SEC_32K_CK_PDN_MASK 0x1
#define PMIC_RG_RTC_SEC_32K_CK_PDN_SHIFT   3
#define PMIC_RG_RTC_MCLK_PDN_ADDR MT6358_SCK_TOP_CKPDN_CON0
#define PMIC_RG_RTC_MCLK_PDN_MASK 0x1
#define PMIC_RG_RTC_MCLK_PDN_SHIFT 4
#define PMIC_RG_RTC_32K_CK_PDN_ADDR   MT6358_SCK_TOP_CKPDN_CON0
#define PMIC_RG_RTC_32K_CK_PDN_MASK   0x1
#define PMIC_RG_RTC_32K_CK_PDN_SHIFT  5
#define PMIC_RG_RTC_26M_CK_PDN_ADDR   MT6358_SCK_TOP_CKPDN_CON0
#define PMIC_RG_RTC_26M_CK_PDN_MASK   0x1
#define PMIC_RG_RTC_26M_CK_PDN_SHIFT  6
#define PMIC_RG_RTC_2SEC_OFF_DET_PDN_ADDR   MT6358_SCK_TOP_CKPDN_CON0
#define PMIC_RG_RTC_2SEC_OFF_DET_PDN_MASK   0x1
#define PMIC_RG_RTC_2SEC_OFF_DET_PDN_SHIFT  7
#define PMIC_RG_RTC_INTRP_CK_PDN_ADDR MT6358_SCK_TOP_CKPDN_CON0
#define PMIC_RG_RTC_INTRP_CK_PDN_MASK 0x1
#define PMIC_RG_RTC_INTRP_CK_PDN_SHIFT  8
#define PMIC_SCK_TOP_CKPDN_CON0_SET_ADDR   MT6358_SCK_TOP_CKPDN_CON0_SET
#define PMIC_SCK_TOP_CKPDN_CON0_SET_MASK   0xFF
#define PMIC_SCK_TOP_CKPDN_CON0_SET_SHIFT   0
#define PMIC_SCK_TOP_CKPDN_CON0_CLR_ADDR   MT6358_SCK_TOP_CKPDN_CON0_CLR
#define PMIC_SCK_TOP_CKPDN_CON0_CLR_MASK   0xFF
#define PMIC_SCK_TOP_CKPDN_CON0_CLR_SHIFT   0
#define PMIC_RG_RTC_26M_CK_PDN_HWEN_ADDR   MT6358_SCK_TOP_CKHWEN_CON0
#define PMIC_RG_RTC_26M_CK_PDN_HWEN_MASK   0x1
#define PMIC_RG_RTC_26M_CK_PDN_HWEN_SHIFT   0
#define PMIC_RG_RTC_MCLK_PDN_HWEN_ADDR  MT6358_SCK_TOP_CKHWEN_CON0
#define PMIC_RG_RTC_MCLK_PDN_HWEN_MASK  0x1
#define PMIC_RG_RTC_MCLK_PDN_HWEN_SHIFT 1
#define PMIC_RG_RTC_SEC_32K_CK_PDN_HWEN_ADDR  MT6358_SCK_TOP_CKHWEN_CON0
#define PMIC_RG_RTC_SEC_32K_CK_PDN_HWEN_MASK  0x1
#define PMIC_RG_RTC_SEC_32K_CK_PDN_HWEN_SHIFT 2
#define PMIC_RG_RTC_SEC_MCLK_PDN_HWEN_ADDR  MT6358_SCK_TOP_CKHWEN_CON0
#define PMIC_RG_RTC_SEC_MCLK_PDN_HWEN_MASK  0x1
#define PMIC_RG_RTC_SEC_MCLK_PDN_HWEN_SHIFT 3
#define PMIC_RG_RTC_INTRP_CK_PDN_HWEN_ADDR  MT6358_SCK_TOP_CKHWEN_CON0
#define PMIC_RG_RTC_INTRP_CK_PDN_HWEN_MASK  0x1
#define PMIC_RG_RTC_INTRP_CK_PDN_HWEN_SHIFT 4
#define PMIC_RG_RTC_CLK_PDN_HWEN_RSV_1_ADDR MT6358_SCK_TOP_CKHWEN_CON0
#define PMIC_RG_RTC_CLK_PDN_HWEN_RSV_1_MASK 0x1F
#define PMIC_RG_RTC_CLK_PDN_HWEN_RSV_1_SHIFT  5
#define PMIC_RG_RTC_CLK_PDN_HWEN_RSV_0_ADDR MT6358_SCK_TOP_CKHWEN_CON0
#define PMIC_RG_RTC_CLK_PDN_HWEN_RSV_0_MASK 0x3F
#define PMIC_RG_RTC_CLK_PDN_HWEN_RSV_0_SHIFT  10
#define PMIC_SCK_TOP_CKHWEN_CON_SET_ADDR   MT6358_SCK_TOP_CKHWEN_CON0_SET
#define PMIC_SCK_TOP_CKHWEN_CON_SET_MASK   0xFFFF
#define PMIC_SCK_TOP_CKHWEN_CON_SET_SHIFT   0
#define PMIC_SCK_TOP_CKHWEN_CON_CLR_ADDR   MT6358_SCK_TOP_CKHWEN_CON0_CLR
#define PMIC_SCK_TOP_CKHWEN_CON_CLR_MASK   0xFFFF
#define PMIC_SCK_TOP_CKHWEN_CON_CLR_SHIFT   0
#define PMIC_RG_RTC_CK_TSTSEL_RSV_ADDR  MT6358_SCK_TOP_CKTST_CON
#define PMIC_RG_RTC_CK_TSTSEL_RSV_MASK  0xF
#define PMIC_RG_RTC_CK_TSTSEL_RSV_SHIFT 0
#define PMIC_RG_RTCDET_CK_TSTSEL_ADDR MT6358_SCK_TOP_CKTST_CON
#define PMIC_RG_RTCDET_CK_TSTSEL_MASK 0x1
#define PMIC_RG_RTCDET_CK_TSTSEL_SHIFT  4
#define PMIC_RG_EOSC_CALI_TEST_CK_TSTSEL_ADDR MT6358_SCK_TOP_CKTST_CON
#define PMIC_RG_EOSC_CALI_TEST_CK_TSTSEL_MASK 0x1
#define PMIC_RG_EOSC_CALI_TEST_CK_TSTSEL_SHIFT   5
#define PMIC_RG_RTC_EOSC32_CK_TSTSEL_ADDR   MT6358_SCK_TOP_CKTST_CON
#define PMIC_RG_RTC_EOSC32_CK_TSTSEL_MASK   0x1
#define PMIC_RG_RTC_EOSC32_CK_TSTSEL_SHIFT  6
#define PMIC_RG_RTC_SWRST_ADDR  MT6358_SCK_TOP_RST_CON0
#define PMIC_RG_RTC_SWRST_MASK  0x1
#define PMIC_RG_RTC_SWRST_SHIFT 0
#define PMIC_RG_RTC_SEC_SWRST_ADDR MT6358_SCK_TOP_RST_CON0
#define PMIC_RG_RTC_SEC_SWRST_MASK 0x1
#define PMIC_RG_RTC_SEC_SWRST_SHIFT   1
#define PMIC_RG_BANK_RTC_SWRST_ADDR   MT6358_SCK_TOP_RST_CON0
#define PMIC_RG_BANK_RTC_SWRST_MASK   0x1
#define PMIC_RG_BANK_RTC_SWRST_SHIFT  2
#define PMIC_RG_BANK_RTC_SEC_SWRST_ADDR MT6358_SCK_TOP_RST_CON0
#define PMIC_RG_BANK_RTC_SEC_SWRST_MASK 0x1
#define PMIC_RG_BANK_RTC_SEC_SWRST_SHIFT   3
#define PMIC_RG_BANK_EOSC_CALI_SWRST_ADDR   MT6358_SCK_TOP_RST_CON0
#define PMIC_RG_BANK_EOSC_CALI_SWRST_MASK   0x1
#define PMIC_RG_BANK_EOSC_CALI_SWRST_SHIFT  4
#define PMIC_RG_BANK_SCK_TOP_SWRST_ADDR MT6358_SCK_TOP_RST_CON0
#define PMIC_RG_BANK_SCK_TOP_SWRST_MASK 0x1
#define PMIC_RG_BANK_SCK_TOP_SWRST_SHIFT   5
#define PMIC_SCK_TOP_RST_CON0_SET_ADDR  MT6358_SCK_TOP_RST_CON0_SET
#define PMIC_SCK_TOP_RST_CON0_SET_MASK  0x3F
#define PMIC_SCK_TOP_RST_CON0_SET_SHIFT 0
#define PMIC_SCK_TOP_RST_CON0_CLR_ADDR  MT6358_SCK_TOP_RST_CON0_CLR
#define PMIC_SCK_TOP_RST_CON0_CLR_MASK  0x3F
#define PMIC_SCK_TOP_RST_CON0_CLR_SHIFT 0
#define PMIC_RG_INT_EN_RTC_ADDR MT6358_SCK_TOP_INT_CON0
#define PMIC_RG_INT_EN_RTC_MASK 0x1
#define PMIC_RG_INT_EN_RTC_SHIFT  0
#define PMIC_SCK_TOP_INT_CON0_SET_ADDR  MT6358_SCK_TOP_INT_CON0_SET
#define PMIC_SCK_TOP_INT_CON0_SET_MASK  0x1
#define PMIC_SCK_TOP_INT_CON0_SET_SHIFT 0
#define PMIC_SCK_TOP_INT_CON0_CLR_ADDR  MT6358_SCK_TOP_INT_CON0_CLR
#define PMIC_SCK_TOP_INT_CON0_CLR_MASK  0x1
#define PMIC_SCK_TOP_INT_CON0_CLR_SHIFT 0
#define PMIC_RG_INT_MASK_RTC_ADDR MT6358_SCK_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_RTC_MASK 0x1
#define PMIC_RG_INT_MASK_RTC_SHIFT 0
#define PMIC_SCK_TOP_INT_MASK_CON0_SET_ADDR MT6358_SCK_TOP_INT_MASK_CON0_SET
#define PMIC_SCK_TOP_INT_MASK_CON0_SET_MASK 0x1
#define PMIC_SCK_TOP_INT_MASK_CON0_SET_SHIFT  0
#define PMIC_SCK_TOP_INT_MASK_CON0_CLR_ADDR MT6358_SCK_TOP_INT_MASK_CON0_CLR
#define PMIC_SCK_TOP_INT_MASK_CON0_CLR_MASK 0x1
#define PMIC_SCK_TOP_INT_MASK_CON0_CLR_SHIFT  0
#define PMIC_RG_INT_STATUS_RTC_ADDR   MT6358_SCK_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_RTC_MASK   0x1
#define PMIC_RG_INT_STATUS_RTC_SHIFT  0
#define PMIC_RG_INT_RAW_STATUS_RTC_ADDR MT6358_SCK_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_RTC_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_RTC_SHIFT   0
#define PMIC_SCK_TOP_POLARITY_ADDR MT6358_SCK_TOP_INT_MISC_CON
#define PMIC_SCK_TOP_POLARITY_MASK 0x1
#define PMIC_SCK_TOP_POLARITY_SHIFT   0
#define PMIC_EOSC_CALI_START_ADDR MT6358_EOSC_CALI_CON0
#define PMIC_EOSC_CALI_START_MASK 0x1
#define PMIC_EOSC_CALI_START_SHIFT 0
#define PMIC_EOSC_CALI_TD_ADDR  MT6358_EOSC_CALI_CON0
#define PMIC_EOSC_CALI_TD_MASK  0x7
#define PMIC_EOSC_CALI_TD_SHIFT 5
#define PMIC_EOSC_CALI_TEST_ADDR  MT6358_EOSC_CALI_CON0
#define PMIC_EOSC_CALI_TEST_MASK  0xF
#define PMIC_EOSC_CALI_TEST_SHIFT 9
#define PMIC_EOSC_CALI_DCXO_RDY_TD_ADDR MT6358_EOSC_CALI_CON1
#define PMIC_EOSC_CALI_DCXO_RDY_TD_MASK 0x7
#define PMIC_EOSC_CALI_DCXO_RDY_TD_SHIFT   0
#define PMIC_FRC_VTCXO0_ON_ADDR MT6358_EOSC_CALI_CON1
#define PMIC_FRC_VTCXO0_ON_MASK 0x1
#define PMIC_FRC_VTCXO0_ON_SHIFT  8
#define PMIC_EOSC_CALI_RSV_ADDR MT6358_EOSC_CALI_CON1
#define PMIC_EOSC_CALI_RSV_MASK 0xF
#define PMIC_EOSC_CALI_RSV_SHIFT  11
#define PMIC_MIX_EOSC32_STP_LPDTB_ADDR  MT6358_RTC_MIX_CON0
#define PMIC_MIX_EOSC32_STP_LPDTB_MASK  0x1
#define PMIC_MIX_EOSC32_STP_LPDTB_SHIFT 1
#define PMIC_MIX_EOSC32_STP_LPDEN_ADDR  MT6358_RTC_MIX_CON0
#define PMIC_MIX_EOSC32_STP_LPDEN_MASK  0x1
#define PMIC_MIX_EOSC32_STP_LPDEN_SHIFT 2
#define PMIC_MIX_XOSC32_STP_PWDB_ADDR MT6358_RTC_MIX_CON0
#define PMIC_MIX_XOSC32_STP_PWDB_MASK 0x1
#define PMIC_MIX_XOSC32_STP_PWDB_SHIFT  3
#define PMIC_MIX_XOSC32_STP_LPDTB_ADDR  MT6358_RTC_MIX_CON0
#define PMIC_MIX_XOSC32_STP_LPDTB_MASK  0x1
#define PMIC_MIX_XOSC32_STP_LPDTB_SHIFT 4
#define PMIC_MIX_XOSC32_STP_LPDEN_ADDR  MT6358_RTC_MIX_CON0
#define PMIC_MIX_XOSC32_STP_LPDEN_MASK  0x1
#define PMIC_MIX_XOSC32_STP_LPDEN_SHIFT 5
#define PMIC_MIX_XOSC32_STP_LPDRST_ADDR MT6358_RTC_MIX_CON0
#define PMIC_MIX_XOSC32_STP_LPDRST_MASK 0x1
#define PMIC_MIX_XOSC32_STP_LPDRST_SHIFT   6
#define PMIC_MIX_XOSC32_STP_CALI_ADDR MT6358_RTC_MIX_CON0
#define PMIC_MIX_XOSC32_STP_CALI_MASK 0x1F
#define PMIC_MIX_XOSC32_STP_CALI_SHIFT  7
#define PMIC_STMP_MODE_ADDR  MT6358_RTC_MIX_CON0
#define PMIC_STMP_MODE_MASK  0x1
#define PMIC_STMP_MODE_SHIFT 12
#define PMIC_MIX_EOSC32_STP_CHOP_EN_ADDR   MT6358_RTC_MIX_CON1
#define PMIC_MIX_EOSC32_STP_CHOP_EN_MASK   0x1
#define PMIC_MIX_EOSC32_STP_CHOP_EN_SHIFT   0
#define PMIC_MIX_DCXO_STP_LVSH_EN_ADDR  MT6358_RTC_MIX_CON1
#define PMIC_MIX_DCXO_STP_LVSH_EN_MASK  0x1
#define PMIC_MIX_DCXO_STP_LVSH_EN_SHIFT 1
#define PMIC_MIX_PMU_STP_DDLO_VRTC_ADDR MT6358_RTC_MIX_CON1
#define PMIC_MIX_PMU_STP_DDLO_VRTC_MASK 0x1
#define PMIC_MIX_PMU_STP_DDLO_VRTC_SHIFT   2
#define PMIC_MIX_PMU_STP_DDLO_VRTC_EN_ADDR  MT6358_RTC_MIX_CON1
#define PMIC_MIX_PMU_STP_DDLO_VRTC_EN_MASK  0x1
#define PMIC_MIX_PMU_STP_DDLO_VRTC_EN_SHIFT 3
#define PMIC_MIX_RTC_STP_XOSC32_ENB_ADDR   MT6358_RTC_MIX_CON1
#define PMIC_MIX_RTC_STP_XOSC32_ENB_MASK   0x1
#define PMIC_MIX_RTC_STP_XOSC32_ENB_SHIFT   4
#define PMIC_MIX_DCXO_STP_TEST_DEGLITCH_MODE_ADDR MT6358_RTC_MIX_CON1
#define PMIC_MIX_DCXO_STP_TEST_DEGLITCH_MODE_MASK 0x1
#define PMIC_MIX_DCXO_STP_TEST_DEGLITCH_MODE_SHIFT  5
#define PMIC_MIX_EOSC32_STP_RSV_ADDR  MT6358_RTC_MIX_CON1
#define PMIC_MIX_EOSC32_STP_RSV_MASK  0x3
#define PMIC_MIX_EOSC32_STP_RSV_SHIFT 6
#define PMIC_MIX_EOSC32_VCT_EN_ADDR   MT6358_RTC_MIX_CON1
#define PMIC_MIX_EOSC32_VCT_EN_MASK   0x1
#define PMIC_MIX_EOSC32_VCT_EN_SHIFT  8
#define PMIC_MIX_EOSC32_OPT_ADDR  MT6358_RTC_MIX_CON1
#define PMIC_MIX_EOSC32_OPT_MASK  0x3
#define PMIC_MIX_EOSC32_OPT_SHIFT 9
#define PMIC_MIX_DCXO_STP_LVSH_EN_INT_ADDR  MT6358_RTC_MIX_CON1
#define PMIC_MIX_DCXO_STP_LVSH_EN_INT_MASK  0x1
#define PMIC_MIX_DCXO_STP_LVSH_EN_INT_SHIFT 11
#define PMIC_MIX_RTC_GPIO_COREDETB_ADDR MT6358_RTC_MIX_CON1
#define PMIC_MIX_RTC_GPIO_COREDETB_MASK 0x1
#define PMIC_MIX_RTC_GPIO_COREDETB_SHIFT   12
#define PMIC_MIX_RTC_GPIO_F32KOB_ADDR MT6358_RTC_MIX_CON1
#define PMIC_MIX_RTC_GPIO_F32KOB_MASK 0x1
#define PMIC_MIX_RTC_GPIO_F32KOB_SHIFT  13
#define PMIC_MIX_RTC_GPIO_GPO_ADDR MT6358_RTC_MIX_CON1
#define PMIC_MIX_RTC_GPIO_GPO_MASK 0x1
#define PMIC_MIX_RTC_GPIO_GPO_SHIFT   14
#define PMIC_MIX_RTC_GPIO_OE_ADDR MT6358_RTC_MIX_CON1
#define PMIC_MIX_RTC_GPIO_OE_MASK 0x1
#define PMIC_MIX_RTC_GPIO_OE_SHIFT 15
#define PMIC_MIX_RTC_STP_DEBUG_OUT_ADDR MT6358_RTC_MIX_CON2
#define PMIC_MIX_RTC_STP_DEBUG_OUT_MASK 0x3
#define PMIC_MIX_RTC_STP_DEBUG_OUT_SHIFT   0
#define PMIC_MIX_RTC_STP_DEBUG_SEL_ADDR MT6358_RTC_MIX_CON2
#define PMIC_MIX_RTC_STP_DEBUG_SEL_MASK 0x3
#define PMIC_MIX_RTC_STP_DEBUG_SEL_SHIFT   4
#define PMIC_MIX_RTC_STP_K_EOSC32_EN_ADDR   MT6358_RTC_MIX_CON2
#define PMIC_MIX_RTC_STP_K_EOSC32_EN_MASK   0x1
#define PMIC_MIX_RTC_STP_K_EOSC32_EN_SHIFT  7
#define PMIC_MIX_RTC_STP_EMBCK_SEL_ADDR MT6358_RTC_MIX_CON2
#define PMIC_MIX_RTC_STP_EMBCK_SEL_MASK 0x1
#define PMIC_MIX_RTC_STP_EMBCK_SEL_SHIFT   8
#define PMIC_MIX_STP_BBWAKEUP_ADDR MT6358_RTC_MIX_CON2
#define PMIC_MIX_STP_BBWAKEUP_MASK 0x1
#define PMIC_MIX_STP_BBWAKEUP_SHIFT   9
#define PMIC_MIX_STP_RTC_DDLO_ADDR MT6358_RTC_MIX_CON2
#define PMIC_MIX_STP_RTC_DDLO_MASK 0x1
#define PMIC_MIX_STP_RTC_DDLO_SHIFT   10
#define PMIC_MIX_RTC_XOSC32_ENB_ADDR  MT6358_RTC_MIX_CON2
#define PMIC_MIX_RTC_XOSC32_ENB_MASK  0x1
#define PMIC_MIX_RTC_XOSC32_ENB_SHIFT 11
#define PMIC_MIX_EFUSE_XOSC32_ENB_OPT_ADDR  MT6358_RTC_MIX_CON2
#define PMIC_MIX_EFUSE_XOSC32_ENB_OPT_MASK  0x1
#define PMIC_MIX_EFUSE_XOSC32_ENB_OPT_SHIFT 12
#define PMIC_RTC_ANA_ID_ADDR MT6358_RTC_DSN_ID
#define PMIC_RTC_ANA_ID_MASK 0xFF
#define PMIC_RTC_ANA_ID_SHIFT   0
#define PMIC_RTC_DIG_ID_ADDR MT6358_RTC_DSN_ID
#define PMIC_RTC_DIG_ID_MASK 0xFF
#define PMIC_RTC_DIG_ID_SHIFT   8
#define PMIC_RTC_ANA_MINOR_REV_ADDR   MT6358_RTC_DSN_REV0
#define PMIC_RTC_ANA_MINOR_REV_MASK   0xF
#define PMIC_RTC_ANA_MINOR_REV_SHIFT  0
#define PMIC_RTC_ANA_MAJOR_REV_ADDR   MT6358_RTC_DSN_REV0
#define PMIC_RTC_ANA_MAJOR_REV_MASK   0xF
#define PMIC_RTC_ANA_MAJOR_REV_SHIFT  4
#define PMIC_RTC_DIG_MINOR_REV_ADDR   MT6358_RTC_DSN_REV0
#define PMIC_RTC_DIG_MINOR_REV_MASK   0xF
#define PMIC_RTC_DIG_MINOR_REV_SHIFT  8
#define PMIC_RTC_DIG_MAJOR_REV_ADDR   MT6358_RTC_DSN_REV0
#define PMIC_RTC_DIG_MAJOR_REV_MASK   0xF
#define PMIC_RTC_DIG_MAJOR_REV_SHIFT  12
#define PMIC_RTC_DSN_CBS_ADDR   MT6358_RTC_DBI
#define PMIC_RTC_DSN_CBS_MASK   0x3
#define PMIC_RTC_DSN_CBS_SHIFT  0
#define PMIC_RTC_DSN_BIX_ADDR   MT6358_RTC_DBI
#define PMIC_RTC_DSN_BIX_MASK   0x3
#define PMIC_RTC_DSN_BIX_SHIFT  2
#define PMIC_RTC_DSN_ESP_ADDR   MT6358_RTC_DBI
#define PMIC_RTC_DSN_ESP_MASK   0xFF
#define PMIC_RTC_DSN_ESP_SHIFT  8
#define PMIC_RTC_DSN_FPI_ADDR   MT6358_RTC_DXI
#define PMIC_RTC_DSN_FPI_MASK   0xFF
#define PMIC_RTC_DSN_FPI_SHIFT  0
#define PMIC_PWREN_ADDR   MT6358_RTC_BBPU
#define PMIC_PWREN_MASK   0x1
#define PMIC_PWREN_SHIFT  0
#define PMIC_BBPU_CLR_ADDR  MT6358_RTC_BBPU
#define PMIC_BBPU_CLR_MASK  0x1
#define PMIC_BBPU_CLR_SHIFT  1
#define PMIC_BBPU_INIT_ADDR  MT6358_RTC_BBPU
#define PMIC_BBPU_INIT_MASK  0x1
#define PMIC_BBPU_INIT_SHIFT 2
#define PMIC_AUTO_ADDR MT6358_RTC_BBPU
#define PMIC_AUTO_MASK 0x1
#define PMIC_AUTO_SHIFT   3
#define PMIC_CLRPKY_ADDR  MT6358_RTC_BBPU
#define PMIC_CLRPKY_MASK  0x1
#define PMIC_CLRPKY_SHIFT 4
#define PMIC_RELOAD_ADDR  MT6358_RTC_BBPU
#define PMIC_RELOAD_MASK  0x1
#define PMIC_RELOAD_SHIFT 5
#define PMIC_CBUSY_ADDR   MT6358_RTC_BBPU
#define PMIC_CBUSY_MASK   0x1
#define PMIC_CBUSY_SHIFT  6
#define PMIC_KEY_BBPU_ADDR  MT6358_RTC_BBPU
#define PMIC_KEY_BBPU_MASK  0xFF
#define PMIC_KEY_BBPU_SHIFT  8
#define PMIC_ALSTA_ADDR   MT6358_RTC_IRQ_STA
#define PMIC_ALSTA_MASK   0x1
#define PMIC_ALSTA_SHIFT  0
#define PMIC_TCSTA_ADDR   MT6358_RTC_IRQ_STA
#define PMIC_TCSTA_MASK   0x1
#define PMIC_TCSTA_SHIFT  1
#define PMIC_LPSTA_ADDR   MT6358_RTC_IRQ_STA
#define PMIC_LPSTA_MASK   0x1
#define PMIC_LPSTA_SHIFT  3
#define PMIC_AL_EN_ADDR   MT6358_RTC_IRQ_EN
#define PMIC_AL_EN_MASK   0x1
#define PMIC_AL_EN_SHIFT  0
#define PMIC_TC_EN_ADDR   MT6358_RTC_IRQ_EN
#define PMIC_TC_EN_MASK   0x1
#define PMIC_TC_EN_SHIFT  1
#define PMIC_ONESHOT_ADDR MT6358_RTC_IRQ_EN
#define PMIC_ONESHOT_MASK 0x1
#define PMIC_ONESHOT_SHIFT  2
#define PMIC_LP_EN_ADDR   MT6358_RTC_IRQ_EN
#define PMIC_LP_EN_MASK   0x1
#define PMIC_LP_EN_SHIFT  3
#define PMIC_SECCII_ADDR  MT6358_RTC_CII_EN
#define PMIC_SECCII_MASK  0x1
#define PMIC_SECCII_SHIFT 0
#define PMIC_MINCII_ADDR  MT6358_RTC_CII_EN
#define PMIC_MINCII_MASK  0x1
#define PMIC_MINCII_SHIFT 1
#define PMIC_HOUCII_ADDR  MT6358_RTC_CII_EN
#define PMIC_HOUCII_MASK  0x1
#define PMIC_HOUCII_SHIFT 2
#define PMIC_DOMCII_ADDR  MT6358_RTC_CII_EN
#define PMIC_DOMCII_MASK  0x1
#define PMIC_DOMCII_SHIFT 3
#define PMIC_DOWCII_ADDR  MT6358_RTC_CII_EN
#define PMIC_DOWCII_MASK  0x1
#define PMIC_DOWCII_SHIFT 4
#define PMIC_MTHCII_ADDR  MT6358_RTC_CII_EN
#define PMIC_MTHCII_MASK  0x1
#define PMIC_MTHCII_SHIFT 5
#define PMIC_YEACII_ADDR  MT6358_RTC_CII_EN
#define PMIC_YEACII_MASK  0x1
#define PMIC_YEACII_SHIFT 6
#define PMIC_SECCII_1_2_ADDR MT6358_RTC_CII_EN
#define PMIC_SECCII_1_2_MASK 0x1
#define PMIC_SECCII_1_2_SHIFT   7
#define PMIC_SECCII_1_4_ADDR MT6358_RTC_CII_EN
#define PMIC_SECCII_1_4_MASK 0x1
#define PMIC_SECCII_1_4_SHIFT   8
#define PMIC_SECCII_1_8_ADDR MT6358_RTC_CII_EN
#define PMIC_SECCII_1_8_MASK 0x1
#define PMIC_SECCII_1_8_SHIFT   9
#define PMIC_SEC_MSK_ADDR MT6358_RTC_AL_MASK
#define PMIC_SEC_MSK_MASK 0x1
#define PMIC_SEC_MSK_SHIFT  0
#define PMIC_MIN_MSK_ADDR MT6358_RTC_AL_MASK
#define PMIC_MIN_MSK_MASK 0x1
#define PMIC_MIN_MSK_SHIFT  1
#define PMIC_HOU_MSK_ADDR MT6358_RTC_AL_MASK
#define PMIC_HOU_MSK_MASK 0x1
#define PMIC_HOU_MSK_SHIFT  2
#define PMIC_DOM_MSK_ADDR MT6358_RTC_AL_MASK
#define PMIC_DOM_MSK_MASK 0x1
#define PMIC_DOM_MSK_SHIFT  3
#define PMIC_DOW_MSK_ADDR MT6358_RTC_AL_MASK
#define PMIC_DOW_MSK_MASK 0x1
#define PMIC_DOW_MSK_SHIFT  4
#define PMIC_MTH_MSK_ADDR MT6358_RTC_AL_MASK
#define PMIC_MTH_MSK_MASK 0x1
#define PMIC_MTH_MSK_SHIFT  5
#define PMIC_YEA_MSK_ADDR MT6358_RTC_AL_MASK
#define PMIC_YEA_MSK_MASK 0x1
#define PMIC_YEA_MSK_SHIFT  6
#define PMIC_TC_SECOND_ADDR  MT6358_RTC_TC_SEC
#define PMIC_TC_SECOND_MASK  0x3F
#define PMIC_TC_SECOND_SHIFT 0
#define PMIC_TC_MINUTE_ADDR  MT6358_RTC_TC_MIN
#define PMIC_TC_MINUTE_MASK  0x3F
#define PMIC_TC_MINUTE_SHIFT 0
#define PMIC_TC_HOUR_ADDR MT6358_RTC_TC_HOU
#define PMIC_TC_HOUR_MASK 0x1F
#define PMIC_TC_HOUR_SHIFT  0
#define PMIC_TC_DOM_ADDR  MT6358_RTC_TC_DOM
#define PMIC_TC_DOM_MASK  0x1F
#define PMIC_TC_DOM_SHIFT 0
#define PMIC_TC_DOW_ADDR  MT6358_RTC_TC_DOW
#define PMIC_TC_DOW_MASK  0x7
#define PMIC_TC_DOW_SHIFT 0
#define PMIC_TC_MONTH_ADDR  MT6358_RTC_TC_MTH
#define PMIC_TC_MONTH_MASK  0xF
#define PMIC_TC_MONTH_SHIFT  0
#define PMIC_TC_YEAR_ADDR MT6358_RTC_TC_YEA
#define PMIC_TC_YEAR_MASK 0x7F
#define PMIC_TC_YEAR_SHIFT  0
#define PMIC_AL_SECOND_ADDR  MT6358_RTC_AL_SEC
#define PMIC_AL_SECOND_MASK  0x3F
#define PMIC_AL_SECOND_SHIFT 0
#define PMIC_BBPU_AUTO_PDN_SEL_ADDR   MT6358_RTC_AL_SEC
#define PMIC_BBPU_AUTO_PDN_SEL_MASK   0x1
#define PMIC_BBPU_AUTO_PDN_SEL_SHIFT  6
#define PMIC_BBPU_2SEC_CK_SEL_ADDR MT6358_RTC_AL_SEC
#define PMIC_BBPU_2SEC_CK_SEL_MASK 0x1
#define PMIC_BBPU_2SEC_CK_SEL_SHIFT   7
#define PMIC_BBPU_2SEC_EN_ADDR  MT6358_RTC_AL_SEC
#define PMIC_BBPU_2SEC_EN_MASK  0x1
#define PMIC_BBPU_2SEC_EN_SHIFT 8
#define PMIC_BBPU_2SEC_MODE_ADDR  MT6358_RTC_AL_SEC
#define PMIC_BBPU_2SEC_MODE_MASK  0x3
#define PMIC_BBPU_2SEC_MODE_SHIFT 9
#define PMIC_BBPU_2SEC_STAT_CLEAR_ADDR  MT6358_RTC_AL_SEC
#define PMIC_BBPU_2SEC_STAT_CLEAR_MASK  0x1
#define PMIC_BBPU_2SEC_STAT_CLEAR_SHIFT 11
#define PMIC_BBPU_2SEC_STAT_STA_ADDR  MT6358_RTC_AL_SEC
#define PMIC_BBPU_2SEC_STAT_STA_MASK  0x1
#define PMIC_BBPU_2SEC_STAT_STA_SHIFT 12
#define PMIC_RTC_LPD_OPT_ADDR   MT6358_RTC_AL_SEC
#define PMIC_RTC_LPD_OPT_MASK   0x3
#define PMIC_RTC_LPD_OPT_SHIFT  13
#define PMIC_K_EOSC32_VTCXO_ON_SEL_ADDR MT6358_RTC_AL_SEC
#define PMIC_K_EOSC32_VTCXO_ON_SEL_MASK 0x1
#define PMIC_K_EOSC32_VTCXO_ON_SEL_SHIFT   15
#define PMIC_AL_MINUTE_ADDR  MT6358_RTC_AL_MIN
#define PMIC_AL_MINUTE_MASK  0x3F
#define PMIC_AL_MINUTE_SHIFT 0
#define PMIC_AL_HOUR_ADDR MT6358_RTC_AL_HOU
#define PMIC_AL_HOUR_MASK 0x1F
#define PMIC_AL_HOUR_SHIFT  0
#define PMIC_NEW_SPARE0_ADDR MT6358_RTC_AL_HOU
#define PMIC_NEW_SPARE0_MASK 0xFF
#define PMIC_NEW_SPARE0_SHIFT   8
#define PMIC_AL_DOM_ADDR  MT6358_RTC_AL_DOM
#define PMIC_AL_DOM_MASK  0x1F
#define PMIC_AL_DOM_SHIFT 0
#define PMIC_NEW_SPARE1_ADDR MT6358_RTC_AL_DOM
#define PMIC_NEW_SPARE1_MASK 0xFF
#define PMIC_NEW_SPARE1_SHIFT   8
#define PMIC_AL_DOW_ADDR  MT6358_RTC_AL_DOW
#define PMIC_AL_DOW_MASK  0x7
#define PMIC_AL_DOW_SHIFT 0
#define PMIC_NEW_SPARE2_ADDR MT6358_RTC_AL_DOW
#define PMIC_NEW_SPARE2_MASK 0xFF
#define PMIC_NEW_SPARE2_SHIFT   8
#define PMIC_AL_MONTH_ADDR  MT6358_RTC_AL_MTH
#define PMIC_AL_MONTH_MASK  0xF
#define PMIC_AL_MONTH_SHIFT  0
#define PMIC_NEW_SPARE3_ADDR MT6358_RTC_AL_MTH
#define PMIC_NEW_SPARE3_MASK 0xFF
#define PMIC_NEW_SPARE3_SHIFT   8
#define PMIC_AL_YEAR_ADDR MT6358_RTC_AL_YEA
#define PMIC_AL_YEAR_MASK 0x7F
#define PMIC_AL_YEAR_SHIFT  0
#define PMIC_RTC_K_EOSC_RSV_ADDR  MT6358_RTC_AL_YEA
#define PMIC_RTC_K_EOSC_RSV_MASK  0xFF
#define PMIC_RTC_K_EOSC_RSV_SHIFT 8
#define PMIC_XOSCCALI_ADDR  MT6358_RTC_OSC32CON
#define PMIC_XOSCCALI_MASK  0x1F
#define PMIC_XOSCCALI_SHIFT  0
#define PMIC_RTC_XOSC32_ENB_ADDR  MT6358_RTC_OSC32CON
#define PMIC_RTC_XOSC32_ENB_MASK  0x1
#define PMIC_RTC_XOSC32_ENB_SHIFT 5
#define PMIC_RTC_EMBCK_SEL_MODE_ADDR  MT6358_RTC_OSC32CON
#define PMIC_RTC_EMBCK_SEL_MODE_MASK  0x3
#define PMIC_RTC_EMBCK_SEL_MODE_SHIFT 6
#define PMIC_RTC_EMBCK_SRC_SEL_ADDR   MT6358_RTC_OSC32CON
#define PMIC_RTC_EMBCK_SRC_SEL_MASK   0x1
#define PMIC_RTC_EMBCK_SRC_SEL_SHIFT  8
#define PMIC_RTC_EMBCK_SEL_OPTION_ADDR  MT6358_RTC_OSC32CON
#define PMIC_RTC_EMBCK_SEL_OPTION_MASK  0x1
#define PMIC_RTC_EMBCK_SEL_OPTION_SHIFT 9
#define PMIC_RTC_GPS_CKOUT_EN_ADDR MT6358_RTC_OSC32CON
#define PMIC_RTC_GPS_CKOUT_EN_MASK 0x1
#define PMIC_RTC_GPS_CKOUT_EN_SHIFT   10
#define PMIC_RTC_EOSC32_VCT_EN_ADDR   MT6358_RTC_OSC32CON
#define PMIC_RTC_EOSC32_VCT_EN_MASK   0x1
#define PMIC_RTC_EOSC32_VCT_EN_SHIFT  11
#define PMIC_RTC_EOSC32_CHOP_EN_ADDR  MT6358_RTC_OSC32CON
#define PMIC_RTC_EOSC32_CHOP_EN_MASK  0x1
#define PMIC_RTC_EOSC32_CHOP_EN_SHIFT 12
#define PMIC_RTC_GP_OSC32_CON_ADDR MT6358_RTC_OSC32CON
#define PMIC_RTC_GP_OSC32_CON_MASK 0x3
#define PMIC_RTC_GP_OSC32_CON_SHIFT   13
#define PMIC_RTC_REG_XOSC32_ENB_ADDR  MT6358_RTC_OSC32CON
#define PMIC_RTC_REG_XOSC32_ENB_MASK  0x1
#define PMIC_RTC_REG_XOSC32_ENB_SHIFT 15
#define PMIC_RTC_POWERKEY1_ADDR MT6358_RTC_POWERKEY1
#define PMIC_RTC_POWERKEY1_MASK 0xFFFF
#define PMIC_RTC_POWERKEY1_SHIFT  0
#define PMIC_RTC_POWERKEY2_ADDR MT6358_RTC_POWERKEY2
#define PMIC_RTC_POWERKEY2_MASK 0xFFFF
#define PMIC_RTC_POWERKEY2_SHIFT  0
#define PMIC_RTC_PDN1_ADDR  MT6358_RTC_PDN1
#define PMIC_RTC_PDN1_MASK  0xFFFF
#define PMIC_RTC_PDN1_SHIFT  0
#define PMIC_RTC_PDN2_ADDR  MT6358_RTC_PDN2
#define PMIC_RTC_PDN2_MASK  0xFFFF
#define PMIC_RTC_PDN2_SHIFT  0
#define PMIC_RTC_SPAR0_ADDR  MT6358_RTC_SPAR0
#define PMIC_RTC_SPAR0_MASK  0xFFFF
#define PMIC_RTC_SPAR0_SHIFT 0
#define PMIC_RTC_SPAR1_ADDR  MT6358_RTC_SPAR1
#define PMIC_RTC_SPAR1_MASK  0xFFFF
#define PMIC_RTC_SPAR1_SHIFT 0
#define PMIC_RTC_PROT_ADDR  MT6358_RTC_PROT
#define PMIC_RTC_PROT_MASK  0xFFFF
#define PMIC_RTC_PROT_SHIFT  0
#define PMIC_RTC_DIFF_ADDR  MT6358_RTC_DIFF
#define PMIC_RTC_DIFF_MASK  0xFFF
#define PMIC_RTC_DIFF_SHIFT  0
#define PMIC_POWER_DETECTED_ADDR  MT6358_RTC_DIFF
#define PMIC_POWER_DETECTED_MASK  0x1
#define PMIC_POWER_DETECTED_SHIFT 12
#define PMIC_K_EOSC32_RSV_ADDR  MT6358_RTC_DIFF
#define PMIC_K_EOSC32_RSV_MASK  0x1
#define PMIC_K_EOSC32_RSV_SHIFT 14
#define PMIC_CALI_RD_SEL_ADDR   MT6358_RTC_DIFF
#define PMIC_CALI_RD_SEL_MASK   0x1
#define PMIC_CALI_RD_SEL_SHIFT  15
#define PMIC_RTC_CALI_ADDR  MT6358_RTC_CALI
#define PMIC_RTC_CALI_MASK  0x3FFF
#define PMIC_RTC_CALI_SHIFT  0
#define PMIC_CALI_WR_SEL_ADDR   MT6358_RTC_CALI
#define PMIC_CALI_WR_SEL_MASK   0x1
#define PMIC_CALI_WR_SEL_SHIFT  14
#define PMIC_K_EOSC32_OVERFLOW_ADDR   MT6358_RTC_CALI
#define PMIC_K_EOSC32_OVERFLOW_MASK   0x1
#define PMIC_K_EOSC32_OVERFLOW_SHIFT  15
#define PMIC_WRTGR_ADDR   MT6358_RTC_WRTGR
#define PMIC_WRTGR_MASK   0x1
#define PMIC_WRTGR_SHIFT  0
#define PMIC_VBAT_LPSTA_RAW_ADDR  MT6358_RTC_CON
#define PMIC_VBAT_LPSTA_RAW_MASK  0x1
#define PMIC_VBAT_LPSTA_RAW_SHIFT 0
#define PMIC_EOSC32_LPEN_ADDR   MT6358_RTC_CON
#define PMIC_EOSC32_LPEN_MASK   0x1
#define PMIC_EOSC32_LPEN_SHIFT  1
#define PMIC_XOSC32_LPEN_ADDR   MT6358_RTC_CON
#define PMIC_XOSC32_LPEN_MASK   0x1
#define PMIC_XOSC32_LPEN_SHIFT  2
#define PMIC_LPRST_ADDR   MT6358_RTC_CON
#define PMIC_LPRST_MASK   0x1
#define PMIC_LPRST_SHIFT  3
#define PMIC_CDBO_ADDR MT6358_RTC_CON
#define PMIC_CDBO_MASK 0x1
#define PMIC_CDBO_SHIFT   4
#define PMIC_F32KOB_ADDR  MT6358_RTC_CON
#define PMIC_F32KOB_MASK  0x1
#define PMIC_F32KOB_SHIFT 5
#define PMIC_GPO_ADDR  MT6358_RTC_CON
#define PMIC_GPO_MASK  0x1
#define PMIC_GPO_SHIFT 6
#define PMIC_GOE_ADDR  MT6358_RTC_CON
#define PMIC_GOE_MASK  0x1
#define PMIC_GOE_SHIFT 7
#define PMIC_GSR_ADDR  MT6358_RTC_CON
#define PMIC_GSR_MASK  0x1
#define PMIC_GSR_SHIFT 8
#define PMIC_GSMT_ADDR MT6358_RTC_CON
#define PMIC_GSMT_MASK 0x1
#define PMIC_GSMT_SHIFT   9
#define PMIC_GPEN_ADDR MT6358_RTC_CON
#define PMIC_GPEN_MASK 0x1
#define PMIC_GPEN_SHIFT   10
#define PMIC_GPU_ADDR  MT6358_RTC_CON
#define PMIC_GPU_MASK  0x1
#define PMIC_GPU_SHIFT 11
#define PMIC_GE4_ADDR  MT6358_RTC_CON
#define PMIC_GE4_MASK  0x1
#define PMIC_GE4_SHIFT 12
#define PMIC_GE8_ADDR  MT6358_RTC_CON
#define PMIC_GE8_MASK  0x1
#define PMIC_GE8_SHIFT 13
#define PMIC_GPI_ADDR  MT6358_RTC_CON
#define PMIC_GPI_MASK  0x1
#define PMIC_GPI_SHIFT 14
#define PMIC_LPSTA_RAW_ADDR  MT6358_RTC_CON
#define PMIC_LPSTA_RAW_MASK  0x1
#define PMIC_LPSTA_RAW_SHIFT 15
#define PMIC_DAT0_LOCK_ADDR  MT6358_RTC_SEC_CTRL
#define PMIC_DAT0_LOCK_MASK  0x1
#define PMIC_DAT0_LOCK_SHIFT 0
#define PMIC_DAT1_LOCK_ADDR  MT6358_RTC_SEC_CTRL
#define PMIC_DAT1_LOCK_MASK  0x1
#define PMIC_DAT1_LOCK_SHIFT 1
#define PMIC_DAT2_LOCK_ADDR  MT6358_RTC_SEC_CTRL
#define PMIC_DAT2_LOCK_MASK  0x1
#define PMIC_DAT2_LOCK_SHIFT 2
#define PMIC_RTC_INT_CNT_ADDR   MT6358_RTC_INT_CNT
#define PMIC_RTC_INT_CNT_MASK   0x7FFF
#define PMIC_RTC_INT_CNT_SHIFT  0
#define PMIC_RTC_SEC_DAT0_ADDR  MT6358_RTC_SEC_DAT0
#define PMIC_RTC_SEC_DAT0_MASK  0xFFFF
#define PMIC_RTC_SEC_DAT0_SHIFT 0
#define PMIC_RTC_SEC_DAT1_ADDR  MT6358_RTC_SEC_DAT1
#define PMIC_RTC_SEC_DAT1_MASK  0xFFFF
#define PMIC_RTC_SEC_DAT1_SHIFT 0
#define PMIC_RTC_SEC_DAT2_ADDR  MT6358_RTC_SEC_DAT2
#define PMIC_RTC_SEC_DAT2_MASK  0xFFFF
#define PMIC_RTC_SEC_DAT2_SHIFT 0
#define PMIC_RTC_SEC_ANA_ID_ADDR  MT6358_RTC_SEC_DSN_ID
#define PMIC_RTC_SEC_ANA_ID_MASK  0xFF
#define PMIC_RTC_SEC_ANA_ID_SHIFT 0
#define PMIC_RTC_SEC_DIG_ID_ADDR  MT6358_RTC_SEC_DSN_ID
#define PMIC_RTC_SEC_DIG_ID_MASK  0xFF
#define PMIC_RTC_SEC_DIG_ID_SHIFT 8
#define PMIC_RTC_SEC_ANA_MINOR_REV_ADDR MT6358_RTC_SEC_DSN_REV0
#define PMIC_RTC_SEC_ANA_MINOR_REV_MASK 0xF
#define PMIC_RTC_SEC_ANA_MINOR_REV_SHIFT   0
#define PMIC_RTC_SEC_ANA_MAJOR_REV_ADDR MT6358_RTC_SEC_DSN_REV0
#define PMIC_RTC_SEC_ANA_MAJOR_REV_MASK 0xF
#define PMIC_RTC_SEC_ANA_MAJOR_REV_SHIFT   4
#define PMIC_RTC_SEC_DIG_MINOR_REV_ADDR MT6358_RTC_SEC_DSN_REV0
#define PMIC_RTC_SEC_DIG_MINOR_REV_MASK 0xF
#define PMIC_RTC_SEC_DIG_MINOR_REV_SHIFT   8
#define PMIC_RTC_SEC_DIG_MAJOR_REV_ADDR MT6358_RTC_SEC_DSN_REV0
#define PMIC_RTC_SEC_DIG_MAJOR_REV_MASK 0xF
#define PMIC_RTC_SEC_DIG_MAJOR_REV_SHIFT   12
#define PMIC_RTC_SEC_DSN_CBS_ADDR MT6358_RTC_SEC_DBI
#define PMIC_RTC_SEC_DSN_CBS_MASK 0x3
#define PMIC_RTC_SEC_DSN_CBS_SHIFT 0
#define PMIC_RTC_SEC_DSN_BIX_ADDR MT6358_RTC_SEC_DBI
#define PMIC_RTC_SEC_DSN_BIX_MASK 0x3
#define PMIC_RTC_SEC_DSN_BIX_SHIFT 2
#define PMIC_RTC_SEC_DSN_ESP_ADDR MT6358_RTC_SEC_DBI
#define PMIC_RTC_SEC_DSN_ESP_MASK 0xFF
#define PMIC_RTC_SEC_DSN_ESP_SHIFT 8
#define PMIC_RTC_SEC_DSN_FPI_ADDR MT6358_RTC_SEC_DXI
#define PMIC_RTC_SEC_DSN_FPI_MASK 0xFF
#define PMIC_RTC_SEC_DSN_FPI_SHIFT 0
#define PMIC_TC_SECOND_SEC_ADDR MT6358_RTC_TC_SEC_SEC
#define PMIC_TC_SECOND_SEC_MASK 0x3F
#define PMIC_TC_SECOND_SEC_SHIFT  0
#define PMIC_TC_MINUTE_SEC_ADDR MT6358_RTC_TC_MIN_SEC
#define PMIC_TC_MINUTE_SEC_MASK 0x3F
#define PMIC_TC_MINUTE_SEC_SHIFT  0
#define PMIC_TC_HOUR_SEC_ADDR   MT6358_RTC_TC_HOU_SEC
#define PMIC_TC_HOUR_SEC_MASK   0x1F
#define PMIC_TC_HOUR_SEC_SHIFT  0
#define PMIC_TC_DOM_SEC_ADDR MT6358_RTC_TC_DOM_SEC
#define PMIC_TC_DOM_SEC_MASK 0x1F
#define PMIC_TC_DOM_SEC_SHIFT   0
#define PMIC_TC_DOW_SEC_ADDR MT6358_RTC_TC_DOW_SEC
#define PMIC_TC_DOW_SEC_MASK 0x7
#define PMIC_TC_DOW_SEC_SHIFT   0
#define PMIC_TC_MONTH_SEC_ADDR  MT6358_RTC_TC_MTH_SEC
#define PMIC_TC_MONTH_SEC_MASK  0xF
#define PMIC_TC_MONTH_SEC_SHIFT 0
#define PMIC_TC_YEAR_SEC_ADDR   MT6358_RTC_TC_YEA_SEC
#define PMIC_TC_YEAR_SEC_MASK   0x7F
#define PMIC_TC_YEAR_SEC_SHIFT  0
#define PMIC_RTC_SEC_CK_PDN_ADDR  MT6358_RTC_SEC_CK_PDN
#define PMIC_RTC_SEC_CK_PDN_MASK  0x1
#define PMIC_RTC_SEC_CK_PDN_SHIFT 0
#define PMIC_RTC_SEC_WRTGR_ADDR MT6358_RTC_SEC_WRTGR
#define PMIC_RTC_SEC_WRTGR_MASK 0x1
#define PMIC_RTC_SEC_WRTGR_SHIFT  0
#define PMIC_DCXO_ANA_ID_ADDR   MT6358_DCXO_DSN_ID
#define PMIC_DCXO_ANA_ID_MASK   0xFF
#define PMIC_DCXO_ANA_ID_SHIFT  0
#define PMIC_DCXO_DIG_ID_ADDR   MT6358_DCXO_DSN_ID
#define PMIC_DCXO_DIG_ID_MASK   0xFF
#define PMIC_DCXO_DIG_ID_SHIFT  8
#define PMIC_DCXO_ANA_MINOR_REV_ADDR  MT6358_DCXO_DSN_REV0
#define PMIC_DCXO_ANA_MINOR_REV_MASK  0xF
#define PMIC_DCXO_ANA_MINOR_REV_SHIFT 0
#define PMIC_DCXO_ANA_MAJOR_REV_ADDR  MT6358_DCXO_DSN_REV0
#define PMIC_DCXO_ANA_MAJOR_REV_MASK  0xF
#define PMIC_DCXO_ANA_MAJOR_REV_SHIFT 4
#define PMIC_DCXO_DIG_MINOR_REV_ADDR  MT6358_DCXO_DSN_REV0
#define PMIC_DCXO_DIG_MINOR_REV_MASK  0xF
#define PMIC_DCXO_DIG_MINOR_REV_SHIFT 8
#define PMIC_DCXO_DIG_MAJOR_REV_ADDR  MT6358_DCXO_DSN_REV0
#define PMIC_DCXO_DIG_MAJOR_REV_MASK  0xF
#define PMIC_DCXO_DIG_MAJOR_REV_SHIFT 12
#define PMIC_DCXO_DSN_CBS_ADDR  MT6358_DCXO_DSN_DBI
#define PMIC_DCXO_DSN_CBS_MASK  0x3
#define PMIC_DCXO_DSN_CBS_SHIFT 0
#define PMIC_DCXO_DSN_BIX_ADDR  MT6358_DCXO_DSN_DBI
#define PMIC_DCXO_DSN_BIX_MASK  0x3
#define PMIC_DCXO_DSN_BIX_SHIFT 2
#define PMIC_DCXO_DSN_ESP_ADDR  MT6358_DCXO_DSN_DBI
#define PMIC_DCXO_DSN_ESP_MASK  0xFF
#define PMIC_DCXO_DSN_ESP_SHIFT 8
#define PMIC_DCXO_DSN_FPI_ADDR  MT6358_DCXO_DSN_DXI
#define PMIC_DCXO_DSN_FPI_MASK  0xFF
#define PMIC_DCXO_DSN_FPI_SHIFT 0
#define PMIC_XO_EXTBUF1_MODE_ADDR MT6358_DCXO_CW00
#define PMIC_XO_EXTBUF1_MODE_MASK 0x3
#define PMIC_XO_EXTBUF1_MODE_SHIFT 0
#define PMIC_XO_EXTBUF1_EN_M_ADDR MT6358_DCXO_CW00
#define PMIC_XO_EXTBUF1_EN_M_MASK 0x1
#define PMIC_XO_EXTBUF1_EN_M_SHIFT 2
#define PMIC_XO_EXTBUF2_MODE_ADDR MT6358_DCXO_CW00
#define PMIC_XO_EXTBUF2_MODE_MASK 0x3
#define PMIC_XO_EXTBUF2_MODE_SHIFT 3
#define PMIC_XO_EXTBUF2_EN_M_ADDR MT6358_DCXO_CW00
#define PMIC_XO_EXTBUF2_EN_M_MASK 0x1
#define PMIC_XO_EXTBUF2_EN_M_SHIFT 5
#define PMIC_XO_EXTBUF3_MODE_ADDR MT6358_DCXO_CW00
#define PMIC_XO_EXTBUF3_MODE_MASK 0x3
#define PMIC_XO_EXTBUF3_MODE_SHIFT 6
#define PMIC_XO_EXTBUF3_EN_M_ADDR MT6358_DCXO_CW00
#define PMIC_XO_EXTBUF3_EN_M_MASK 0x1
#define PMIC_XO_EXTBUF3_EN_M_SHIFT 8
#define PMIC_XO_EXTBUF4_MODE_ADDR MT6358_DCXO_CW00
#define PMIC_XO_EXTBUF4_MODE_MASK 0x3
#define PMIC_XO_EXTBUF4_MODE_SHIFT 9
#define PMIC_XO_EXTBUF4_EN_M_ADDR MT6358_DCXO_CW00
#define PMIC_XO_EXTBUF4_EN_M_MASK 0x1
#define PMIC_XO_EXTBUF4_EN_M_SHIFT 11
#define PMIC_XO_BB_LPM_EN_ADDR  MT6358_DCXO_CW00
#define PMIC_XO_BB_LPM_EN_MASK  0x1
#define PMIC_XO_BB_LPM_EN_SHIFT 12
#define PMIC_XO_ENBB_MAN_ADDR   MT6358_DCXO_CW00
#define PMIC_XO_ENBB_MAN_MASK   0x1
#define PMIC_XO_ENBB_MAN_SHIFT  13
#define PMIC_XO_ENBB_EN_M_ADDR  MT6358_DCXO_CW00
#define PMIC_XO_ENBB_EN_M_MASK  0x1
#define PMIC_XO_ENBB_EN_M_SHIFT 14
#define PMIC_XO_CLKSEL_MAN_ADDR MT6358_DCXO_CW00
#define PMIC_XO_CLKSEL_MAN_MASK 0x1
#define PMIC_XO_CLKSEL_MAN_SHIFT  15
#define PMIC_DCXO_CW00_SET_ADDR MT6358_DCXO_CW00_SET
#define PMIC_DCXO_CW00_SET_MASK 0xFFFF
#define PMIC_DCXO_CW00_SET_SHIFT  0
#define PMIC_DCXO_CW00_CLR_ADDR MT6358_DCXO_CW00_CLR
#define PMIC_DCXO_CW00_CLR_MASK 0xFFFF
#define PMIC_DCXO_CW00_CLR_SHIFT  0
#define PMIC_XO_CLKSEL_EN_M_ADDR  MT6358_DCXO_CW01
#define PMIC_XO_CLKSEL_EN_M_MASK  0x1
#define PMIC_XO_CLKSEL_EN_M_SHIFT 0
#define PMIC_XO_EXTBUF1_CKG_MAN_ADDR  MT6358_DCXO_CW01
#define PMIC_XO_EXTBUF1_CKG_MAN_MASK  0x1
#define PMIC_XO_EXTBUF1_CKG_MAN_SHIFT 1
#define PMIC_XO_EXTBUF1_CKG_EN_M_ADDR MT6358_DCXO_CW01
#define PMIC_XO_EXTBUF1_CKG_EN_M_MASK 0x1
#define PMIC_XO_EXTBUF1_CKG_EN_M_SHIFT  2
#define PMIC_XO_EXTBUF2_CKG_MAN_ADDR  MT6358_DCXO_CW01
#define PMIC_XO_EXTBUF2_CKG_MAN_MASK  0x1
#define PMIC_XO_EXTBUF2_CKG_MAN_SHIFT 3
#define PMIC_XO_EXTBUF2_CKG_EN_M_ADDR MT6358_DCXO_CW01
#define PMIC_XO_EXTBUF2_CKG_EN_M_MASK 0x1
#define PMIC_XO_EXTBUF2_CKG_EN_M_SHIFT  4
#define PMIC_XO_EXTBUF3_CKG_MAN_ADDR  MT6358_DCXO_CW01
#define PMIC_XO_EXTBUF3_CKG_MAN_MASK  0x1
#define PMIC_XO_EXTBUF3_CKG_MAN_SHIFT 5
#define PMIC_XO_EXTBUF3_CKG_EN_M_ADDR MT6358_DCXO_CW01
#define PMIC_XO_EXTBUF3_CKG_EN_M_MASK 0x1
#define PMIC_XO_EXTBUF3_CKG_EN_M_SHIFT  6
#define PMIC_XO_EXTBUF4_CKG_MAN_ADDR  MT6358_DCXO_CW01
#define PMIC_XO_EXTBUF4_CKG_MAN_MASK  0x1
#define PMIC_XO_EXTBUF4_CKG_MAN_SHIFT 7
#define PMIC_XO_EXTBUF4_CKG_EN_M_ADDR MT6358_DCXO_CW01
#define PMIC_XO_EXTBUF4_CKG_EN_M_MASK 0x1
#define PMIC_XO_EXTBUF4_CKG_EN_M_SHIFT  8
#define PMIC_XO_INTBUF_MAN_ADDR MT6358_DCXO_CW01
#define PMIC_XO_INTBUF_MAN_MASK 0x1
#define PMIC_XO_INTBUF_MAN_SHIFT  9
#define PMIC_XO_PBUF_EN_M_ADDR  MT6358_DCXO_CW01
#define PMIC_XO_PBUF_EN_M_MASK  0x1
#define PMIC_XO_PBUF_EN_M_SHIFT 10
#define PMIC_XO_IBUF_EN_M_ADDR  MT6358_DCXO_CW01
#define PMIC_XO_IBUF_EN_M_MASK  0x1
#define PMIC_XO_IBUF_EN_M_SHIFT 11
#define PMIC_XO_LPMBUF_MAN_ADDR MT6358_DCXO_CW01
#define PMIC_XO_LPMBUF_MAN_MASK 0x1
#define PMIC_XO_LPMBUF_MAN_SHIFT  12
#define PMIC_XO_LPM_PREBUF_EN_M_ADDR  MT6358_DCXO_CW01
#define PMIC_XO_LPM_PREBUF_EN_M_MASK  0x1
#define PMIC_XO_LPM_PREBUF_EN_M_SHIFT 13
#define PMIC_XO_LPBUF_EN_M_ADDR MT6358_DCXO_CW01
#define PMIC_XO_LPBUF_EN_M_MASK 0x1
#define PMIC_XO_LPBUF_EN_M_SHIFT  14
#define PMIC_XO_BBLPM_CKSEL_M_ADDR MT6358_DCXO_CW01
#define PMIC_XO_BBLPM_CKSEL_M_MASK 0x1
#define PMIC_XO_BBLPM_CKSEL_M_SHIFT   15
#define PMIC_XO_EN32K_MAN_ADDR  MT6358_DCXO_CW02
#define PMIC_XO_EN32K_MAN_MASK  0x1
#define PMIC_XO_EN32K_MAN_SHIFT 0
#define PMIC_XO_EN32K_M_ADDR MT6358_DCXO_CW02
#define PMIC_XO_EN32K_M_MASK 0x1
#define PMIC_XO_EN32K_M_SHIFT   1
#define PMIC_XO_XMODE_MAN_ADDR  MT6358_DCXO_CW02
#define PMIC_XO_XMODE_MAN_MASK  0x1
#define PMIC_XO_XMODE_MAN_SHIFT 2
#define PMIC_XO_XMODE_M_ADDR MT6358_DCXO_CW02
#define PMIC_XO_XMODE_M_MASK 0x1
#define PMIC_XO_XMODE_M_SHIFT   3
#define PMIC_XO_STRUP_MODE_ADDR MT6358_DCXO_CW02
#define PMIC_XO_STRUP_MODE_MASK 0x1
#define PMIC_XO_STRUP_MODE_SHIFT  4
#define PMIC_XO_AAC_FPM_TIME_ADDR MT6358_DCXO_CW02
#define PMIC_XO_AAC_FPM_TIME_MASK 0x3
#define PMIC_XO_AAC_FPM_TIME_SHIFT 5
#define PMIC_XO_AAC_MODE_LPM_ADDR MT6358_DCXO_CW02
#define PMIC_XO_AAC_MODE_LPM_MASK 0x3
#define PMIC_XO_AAC_MODE_LPM_SHIFT 7
#define PMIC_XO_AAC_MODE_FPM_ADDR MT6358_DCXO_CW02
#define PMIC_XO_AAC_MODE_FPM_MASK 0x3
#define PMIC_XO_AAC_MODE_FPM_SHIFT 9
#define PMIC_XO_EN26M_OFFSQ_EN_ADDR   MT6358_DCXO_CW02
#define PMIC_XO_EN26M_OFFSQ_EN_MASK   0x1
#define PMIC_XO_EN26M_OFFSQ_EN_SHIFT  11
#define PMIC_XO_LDOCAL_EN_ADDR  MT6358_DCXO_CW02
#define PMIC_XO_LDOCAL_EN_MASK  0x1
#define PMIC_XO_LDOCAL_EN_SHIFT 12
#define PMIC_XO_CBANK_SYNC_DYN_ADDR   MT6358_DCXO_CW02
#define PMIC_XO_CBANK_SYNC_DYN_MASK   0x1
#define PMIC_XO_CBANK_SYNC_DYN_SHIFT  13
#define PMIC_XO_26MLP_MAN_EN_ADDR MT6358_DCXO_CW02
#define PMIC_XO_26MLP_MAN_EN_MASK 0x1
#define PMIC_XO_26MLP_MAN_EN_SHIFT 14
#define PMIC_XO_BUFLDOK_EN_ADDR MT6358_DCXO_CW02
#define PMIC_XO_BUFLDOK_EN_MASK 0x1
#define PMIC_XO_BUFLDOK_EN_SHIFT  15
#define PMIC_XO_PMU_CKEN_M_ADDR MT6358_DCXO_CW03
#define PMIC_XO_PMU_CKEN_M_MASK 0x1
#define PMIC_XO_PMU_CKEN_M_SHIFT  0
#define PMIC_XO_PMU_CKEN_MAN_ADDR MT6358_DCXO_CW03
#define PMIC_XO_PMU_CKEN_MAN_MASK 0x1
#define PMIC_XO_PMU_CKEN_MAN_SHIFT 1
#define PMIC_XO_EXTBUF6_CKG_MAN_ADDR  MT6358_DCXO_CW03
#define PMIC_XO_EXTBUF6_CKG_MAN_MASK  0x1
#define PMIC_XO_EXTBUF6_CKG_MAN_SHIFT 2
#define PMIC_XO_EXTBUF6_CKG_EN_M_ADDR MT6358_DCXO_CW03
#define PMIC_XO_EXTBUF6_CKG_EN_M_MASK 0x1
#define PMIC_XO_EXTBUF6_CKG_EN_M_SHIFT  3
#define PMIC_XO_EXTBUF7_CKG_MAN_ADDR  MT6358_DCXO_CW03
#define PMIC_XO_EXTBUF7_CKG_MAN_MASK  0x1
#define PMIC_XO_EXTBUF7_CKG_MAN_SHIFT 4
#define PMIC_XO_EXTBUF7_CKG_EN_M_ADDR MT6358_DCXO_CW03
#define PMIC_XO_EXTBUF7_CKG_EN_M_MASK 0x1
#define PMIC_XO_EXTBUF7_CKG_EN_M_SHIFT  5
#define PMIC_XO_LPM_ISEL_MAN_ADDR MT6358_DCXO_CW03
#define PMIC_XO_LPM_ISEL_MAN_MASK 0x1F
#define PMIC_XO_LPM_ISEL_MAN_SHIFT 6
#define PMIC_XO_FPM_ISEL_MAN_ADDR MT6358_DCXO_CW03
#define PMIC_XO_FPM_ISEL_MAN_MASK 0x1F
#define PMIC_XO_FPM_ISEL_MAN_SHIFT 11
#define PMIC_XO_CDAC_FPM_ADDR   MT6358_DCXO_CW04
#define PMIC_XO_CDAC_FPM_MASK   0xFF
#define PMIC_XO_CDAC_FPM_SHIFT  0
#define PMIC_XO_CDAC_LPM_ADDR   MT6358_DCXO_CW04
#define PMIC_XO_CDAC_LPM_MASK   0xFF
#define PMIC_XO_CDAC_LPM_SHIFT  8
#define PMIC_XO_32KDIV_NFRAC_FPM_ADDR MT6358_DCXO_CW05
#define PMIC_XO_32KDIV_NFRAC_FPM_MASK 0x3FFF
#define PMIC_XO_32KDIV_NFRAC_FPM_SHIFT  0
#define PMIC_XO_COFST_FPM_ADDR  MT6358_DCXO_CW05
#define PMIC_XO_COFST_FPM_MASK  0x3
#define PMIC_XO_COFST_FPM_SHIFT 14
#define PMIC_XO_32KDIV_NFRAC_LPM_ADDR MT6358_DCXO_CW06
#define PMIC_XO_32KDIV_NFRAC_LPM_MASK 0x3FFF
#define PMIC_XO_32KDIV_NFRAC_LPM_SHIFT  0
#define PMIC_XO_COFST_LPM_ADDR  MT6358_DCXO_CW06
#define PMIC_XO_COFST_LPM_MASK  0x3
#define PMIC_XO_COFST_LPM_SHIFT 14
#define PMIC_XO_CORE_MAN_ADDR   MT6358_DCXO_CW07
#define PMIC_XO_CORE_MAN_MASK   0x1
#define PMIC_XO_CORE_MAN_SHIFT  0
#define PMIC_XO_CORE_EN_M_ADDR  MT6358_DCXO_CW07
#define PMIC_XO_CORE_EN_M_MASK  0x1
#define PMIC_XO_CORE_EN_M_SHIFT 1
#define PMIC_XO_CORE_TURBO_EN_M_ADDR  MT6358_DCXO_CW07
#define PMIC_XO_CORE_TURBO_EN_M_MASK  0x1
#define PMIC_XO_CORE_TURBO_EN_M_SHIFT 2
#define PMIC_XO_CORE_AAC_EN_M_ADDR MT6358_DCXO_CW07
#define PMIC_XO_CORE_AAC_EN_M_MASK 0x1
#define PMIC_XO_CORE_AAC_EN_M_SHIFT   3
#define PMIC_XO_STARTUP_EN_M_ADDR MT6358_DCXO_CW07
#define PMIC_XO_STARTUP_EN_M_MASK 0x1
#define PMIC_XO_STARTUP_EN_M_SHIFT 4
#define PMIC_XO_CORE_VBFPM_EN_M_ADDR  MT6358_DCXO_CW07
#define PMIC_XO_CORE_VBFPM_EN_M_MASK  0x1
#define PMIC_XO_CORE_VBFPM_EN_M_SHIFT 5
#define PMIC_XO_CORE_VBLPM_EN_M_ADDR  MT6358_DCXO_CW07
#define PMIC_XO_CORE_VBLPM_EN_M_MASK  0x1
#define PMIC_XO_CORE_VBLPM_EN_M_SHIFT 6
#define PMIC_XO_LPMBIAS_EN_M_ADDR MT6358_DCXO_CW07
#define PMIC_XO_LPMBIAS_EN_M_MASK 0x1
#define PMIC_XO_LPMBIAS_EN_M_SHIFT 7
#define PMIC_XO_VTCGEN_EN_M_ADDR  MT6358_DCXO_CW07
#define PMIC_XO_VTCGEN_EN_M_MASK  0x1
#define PMIC_XO_VTCGEN_EN_M_SHIFT 8
#define PMIC_XO_IAAC_COMP_EN_M_ADDR   MT6358_DCXO_CW07
#define PMIC_XO_IAAC_COMP_EN_M_MASK   0x1
#define PMIC_XO_IAAC_COMP_EN_M_SHIFT  9
#define PMIC_XO_IFPM_COMP_EN_M_ADDR   MT6358_DCXO_CW07
#define PMIC_XO_IFPM_COMP_EN_M_MASK   0x1
#define PMIC_XO_IFPM_COMP_EN_M_SHIFT  10
#define PMIC_XO_ILPM_COMP_EN_M_ADDR   MT6358_DCXO_CW07
#define PMIC_XO_ILPM_COMP_EN_M_MASK   0x1
#define PMIC_XO_ILPM_COMP_EN_M_SHIFT  11
#define PMIC_XO_CORE_BYPCAS_FPM_ADDR  MT6358_DCXO_CW07
#define PMIC_XO_CORE_BYPCAS_FPM_MASK  0x1
#define PMIC_XO_CORE_BYPCAS_FPM_SHIFT 12
#define PMIC_XO_CORE_GMX2_FPM_ADDR MT6358_DCXO_CW07
#define PMIC_XO_CORE_GMX2_FPM_MASK 0x1
#define PMIC_XO_CORE_GMX2_FPM_SHIFT   13
#define PMIC_XO_CORE_IDAC_FPM_ADDR MT6358_DCXO_CW07
#define PMIC_XO_CORE_IDAC_FPM_MASK 0x3
#define PMIC_XO_CORE_IDAC_FPM_SHIFT   14
#define PMIC_XO_AAC_COMP_MAN_ADDR MT6358_DCXO_CW08
#define PMIC_XO_AAC_COMP_MAN_MASK 0x1
#define PMIC_XO_AAC_COMP_MAN_SHIFT 0
#define PMIC_XO_AAC_EN_M_ADDR   MT6358_DCXO_CW08
#define PMIC_XO_AAC_EN_M_MASK   0x1
#define PMIC_XO_AAC_EN_M_SHIFT  1
#define PMIC_XO_AAC_MONEN_M_ADDR  MT6358_DCXO_CW08
#define PMIC_XO_AAC_MONEN_M_MASK  0x1
#define PMIC_XO_AAC_MONEN_M_SHIFT 2
#define PMIC_XO_COMP_EN_M_ADDR  MT6358_DCXO_CW08
#define PMIC_XO_COMP_EN_M_MASK  0x1
#define PMIC_XO_COMP_EN_M_SHIFT 3
#define PMIC_XO_COMP_TSTEN_M_ADDR MT6358_DCXO_CW08
#define PMIC_XO_COMP_TSTEN_M_MASK 0x1
#define PMIC_XO_COMP_TSTEN_M_SHIFT 4
#define PMIC_XO_AAC_HV_FPM_ADDR MT6358_DCXO_CW08
#define PMIC_XO_AAC_HV_FPM_MASK 0x1
#define PMIC_XO_AAC_HV_FPM_SHIFT  5
#define PMIC_XO_AAC_IBIAS_FPM_ADDR MT6358_DCXO_CW08
#define PMIC_XO_AAC_IBIAS_FPM_MASK 0x3
#define PMIC_XO_AAC_IBIAS_FPM_SHIFT   6
#define PMIC_XO_AAC_VOFST_FPM_ADDR MT6358_DCXO_CW08
#define PMIC_XO_AAC_VOFST_FPM_MASK 0x3
#define PMIC_XO_AAC_VOFST_FPM_SHIFT   8
#define PMIC_XO_AAC_COMP_HV_FPM_ADDR  MT6358_DCXO_CW08
#define PMIC_XO_AAC_COMP_HV_FPM_MASK  0x1
#define PMIC_XO_AAC_COMP_HV_FPM_SHIFT 10
#define PMIC_XO_AAC_VSEL_FPM_ADDR MT6358_DCXO_CW08
#define PMIC_XO_AAC_VSEL_FPM_MASK 0xF
#define PMIC_XO_AAC_VSEL_FPM_SHIFT 11
#define PMIC_XO_AAC_COMP_POL_ADDR MT6358_DCXO_CW08
#define PMIC_XO_AAC_COMP_POL_MASK 0x1
#define PMIC_XO_AAC_COMP_POL_SHIFT 15
#define PMIC_XO_CORE_BYPCAS_LPM_ADDR  MT6358_DCXO_CW09
#define PMIC_XO_CORE_BYPCAS_LPM_MASK  0x1
#define PMIC_XO_CORE_BYPCAS_LPM_SHIFT 0
#define PMIC_XO_CORE_GMX2_LPM_ADDR MT6358_DCXO_CW09
#define PMIC_XO_CORE_GMX2_LPM_MASK 0x1
#define PMIC_XO_CORE_GMX2_LPM_SHIFT   1
#define PMIC_XO_CORE_IDAC_LPM_ADDR MT6358_DCXO_CW09
#define PMIC_XO_CORE_IDAC_LPM_MASK 0x3
#define PMIC_XO_CORE_IDAC_LPM_SHIFT   2
#define PMIC_XO_AAC_COMP_HV_LPM_ADDR  MT6358_DCXO_CW09
#define PMIC_XO_AAC_COMP_HV_LPM_MASK  0x1
#define PMIC_XO_AAC_COMP_HV_LPM_SHIFT 4
#define PMIC_XO_AAC_VSEL_LPM_ADDR MT6358_DCXO_CW09
#define PMIC_XO_AAC_VSEL_LPM_MASK 0xF
#define PMIC_XO_AAC_VSEL_LPM_SHIFT 5
#define PMIC_XO_AAC_HV_LPM_ADDR MT6358_DCXO_CW09
#define PMIC_XO_AAC_HV_LPM_MASK 0x1
#define PMIC_XO_AAC_HV_LPM_SHIFT  9
#define PMIC_XO_AAC_IBIAS_LPM_ADDR MT6358_DCXO_CW09
#define PMIC_XO_AAC_IBIAS_LPM_MASK 0x3
#define PMIC_XO_AAC_IBIAS_LPM_SHIFT   10
#define PMIC_XO_AAC_VOFST_LPM_ADDR MT6358_DCXO_CW09
#define PMIC_XO_AAC_VOFST_LPM_MASK 0x3
#define PMIC_XO_AAC_VOFST_LPM_SHIFT   12
#define PMIC_XO_AAC_FPM_SWEN_ADDR MT6358_DCXO_CW09
#define PMIC_XO_AAC_FPM_SWEN_MASK 0x1
#define PMIC_XO_AAC_FPM_SWEN_SHIFT 14
#define PMIC_XO_SWRST_ADDR  MT6358_DCXO_CW09
#define PMIC_XO_SWRST_MASK  0x1
#define PMIC_XO_SWRST_SHIFT  15
#define PMIC_XO_32KDIV_SWRST_ADDR MT6358_DCXO_CW10
#define PMIC_XO_32KDIV_SWRST_MASK 0x1
#define PMIC_XO_32KDIV_SWRST_SHIFT 0
#define PMIC_XO_32KDIV_RATIO_MAN_ADDR MT6358_DCXO_CW10
#define PMIC_XO_32KDIV_RATIO_MAN_MASK 0x1
#define PMIC_XO_32KDIV_RATIO_MAN_SHIFT  1
#define PMIC_XO_32KDIV_TEST_EN_ADDR   MT6358_DCXO_CW10
#define PMIC_XO_32KDIV_TEST_EN_MASK   0x1
#define PMIC_XO_32KDIV_TEST_EN_SHIFT  2
#define PMIC_XO_CBANK_SYNC_MAN_ADDR   MT6358_DCXO_CW10
#define PMIC_XO_CBANK_SYNC_MAN_MASK   0x1
#define PMIC_XO_CBANK_SYNC_MAN_SHIFT  3
#define PMIC_XO_CBANK_SYNC_EN_M_ADDR  MT6358_DCXO_CW10
#define PMIC_XO_CBANK_SYNC_EN_M_MASK  0x1
#define PMIC_XO_CBANK_SYNC_EN_M_SHIFT 4
#define PMIC_XO_CTL_SYNC_MAN_ADDR MT6358_DCXO_CW10
#define PMIC_XO_CTL_SYNC_MAN_MASK 0x1
#define PMIC_XO_CTL_SYNC_MAN_SHIFT 5
#define PMIC_XO_CTL_SYNC_EN_M_ADDR MT6358_DCXO_CW10
#define PMIC_XO_CTL_SYNC_EN_M_MASK 0x1
#define PMIC_XO_CTL_SYNC_EN_M_SHIFT   6
#define PMIC_XO_LDO_MAN_ADDR MT6358_DCXO_CW10
#define PMIC_XO_LDO_MAN_MASK 0x1
#define PMIC_XO_LDO_MAN_SHIFT   7
#define PMIC_XO_LDOPBUF_EN_M_ADDR MT6358_DCXO_CW10
#define PMIC_XO_LDOPBUF_EN_M_MASK 0x1
#define PMIC_XO_LDOPBUF_EN_M_SHIFT 8
#define PMIC_XO_LDOPBUF_VSET_M_ADDR   MT6358_DCXO_CW10
#define PMIC_XO_LDOPBUF_VSET_M_MASK   0xF
#define PMIC_XO_LDOPBUF_VSET_M_SHIFT  9
#define PMIC_XO_LDOVTST_EN_M_ADDR MT6358_DCXO_CW10
#define PMIC_XO_LDOVTST_EN_M_MASK 0x1
#define PMIC_XO_LDOVTST_EN_M_SHIFT 13
#define PMIC_XO_TEST_VCAL_EN_M_ADDR   MT6358_DCXO_CW10
#define PMIC_XO_TEST_VCAL_EN_M_MASK   0x1
#define PMIC_XO_TEST_VCAL_EN_M_SHIFT  14
#define PMIC_XO_VBIST_EN_M_ADDR MT6358_DCXO_CW10
#define PMIC_XO_VBIST_EN_M_MASK 0x1
#define PMIC_XO_VBIST_EN_M_SHIFT  15
#define PMIC_XO_VTEST_SEL_MUX_ADDR MT6358_DCXO_CW11
#define PMIC_XO_VTEST_SEL_MUX_MASK 0x1F
#define PMIC_XO_VTEST_SEL_MUX_SHIFT   0
#define PMIC_XO_RESERVED3_ADDR  MT6358_DCXO_CW11
#define PMIC_XO_RESERVED3_MASK  0x7
#define PMIC_XO_RESERVED3_SHIFT 5
#define PMIC_XO_EXTBUF6_MODE_ADDR MT6358_DCXO_CW11
#define PMIC_XO_EXTBUF6_MODE_MASK 0x3
#define PMIC_XO_EXTBUF6_MODE_SHIFT 8
#define PMIC_XO_EXTBUF6_EN_M_ADDR MT6358_DCXO_CW11
#define PMIC_XO_EXTBUF6_EN_M_MASK 0x1
#define PMIC_XO_EXTBUF6_EN_M_SHIFT 10
#define PMIC_XO_EXTBUF7_MODE_ADDR MT6358_DCXO_CW11
#define PMIC_XO_EXTBUF7_MODE_MASK 0x3
#define PMIC_XO_EXTBUF7_MODE_SHIFT 11
#define PMIC_XO_EXTBUF7_EN_M_ADDR MT6358_DCXO_CW11
#define PMIC_XO_EXTBUF7_EN_M_MASK 0x1
#define PMIC_XO_EXTBUF7_EN_M_SHIFT 13
#define PMIC_XO_BUFLDOK_MAN_ADDR  MT6358_DCXO_CW11
#define PMIC_XO_BUFLDOK_MAN_MASK  0x1
#define PMIC_XO_BUFLDOK_MAN_SHIFT 14
#define PMIC_XO_BUF1LDO_CAL_M_ADDR MT6358_DCXO_CW11
#define PMIC_XO_BUF1LDO_CAL_M_MASK 0x1
#define PMIC_XO_BUF1LDO_CAL_M_SHIFT   15
#define PMIC_DCXO_CW11_SET_ADDR MT6358_DCXO_CW11_SET
#define PMIC_DCXO_CW11_SET_MASK 0xFFFF
#define PMIC_DCXO_CW11_SET_SHIFT  0
#define PMIC_DCXO_CW11_CLR_ADDR MT6358_DCXO_CW11_CLR
#define PMIC_DCXO_CW11_CLR_MASK 0xFFFF
#define PMIC_DCXO_CW11_CLR_SHIFT  0
#define PMIC_XO_BUFLDO_CAL_M_ADDR MT6358_DCXO_CW12
#define PMIC_XO_BUFLDO_CAL_M_MASK 0x1
#define PMIC_XO_BUFLDO_CAL_M_SHIFT 0
#define PMIC_XO_EXTBUF4_CLKSEL_MAN_ADDR MT6358_DCXO_CW12
#define PMIC_XO_EXTBUF4_CLKSEL_MAN_MASK 0x1
#define PMIC_XO_EXTBUF4_CLKSEL_MAN_SHIFT   1
#define PMIC_XO_VIO18PG_BUFEN_ADDR MT6358_DCXO_CW12
#define PMIC_XO_VIO18PG_BUFEN_MASK 0x1
#define PMIC_XO_VIO18PG_BUFEN_SHIFT   2
#define PMIC_XO_CAL_EN_MAN_ADDR MT6358_DCXO_CW12
#define PMIC_XO_CAL_EN_MAN_MASK 0x1
#define PMIC_XO_CAL_EN_MAN_SHIFT  3
#define PMIC_XO_CAL_EN_M_ADDR   MT6358_DCXO_CW12
#define PMIC_XO_CAL_EN_M_MASK   0x1
#define PMIC_XO_CAL_EN_M_SHIFT  4
#define PMIC_RG_XO_CORE_OSCTD_ADDR MT6358_DCXO_CW12
#define PMIC_RG_XO_CORE_OSCTD_MASK 0x3
#define PMIC_RG_XO_CORE_OSCTD_SHIFT   5
#define PMIC_XO_THADC_EN_ADDR   MT6358_DCXO_CW12
#define PMIC_XO_THADC_EN_MASK   0x1
#define PMIC_XO_THADC_EN_SHIFT  7
#define PMIC_RG_XO_SYNC_CKPOL_ADDR MT6358_DCXO_CW12
#define PMIC_RG_XO_SYNC_CKPOL_MASK 0x1
#define PMIC_RG_XO_SYNC_CKPOL_SHIFT   8
#define PMIC_RG_XO_CBANK_POL_ADDR MT6358_DCXO_CW12
#define PMIC_RG_XO_CBANK_POL_MASK 0x1
#define PMIC_RG_XO_CBANK_POL_SHIFT 9
#define PMIC_RG_XO_CBANK_SYNC_BYP_ADDR  MT6358_DCXO_CW12
#define PMIC_RG_XO_CBANK_SYNC_BYP_MASK  0x1
#define PMIC_RG_XO_CBANK_SYNC_BYP_SHIFT 10
#define PMIC_RG_XO_CTL_POL_ADDR MT6358_DCXO_CW12
#define PMIC_RG_XO_CTL_POL_MASK 0x1
#define PMIC_RG_XO_CTL_POL_SHIFT  11
#define PMIC_RG_XO_CTL_SYNC_BYP_ADDR  MT6358_DCXO_CW12
#define PMIC_RG_XO_CTL_SYNC_BYP_MASK  0x1
#define PMIC_RG_XO_CTL_SYNC_BYP_SHIFT 12
#define PMIC_RG_XO_LPBUF_INV_ADDR MT6358_DCXO_CW12
#define PMIC_RG_XO_LPBUF_INV_MASK 0x1
#define PMIC_RG_XO_LPBUF_INV_SHIFT 13
#define PMIC_RG_XO_LDOPBUF_BYP_ADDR   MT6358_DCXO_CW12
#define PMIC_RG_XO_LDOPBUF_BYP_MASK   0x1
#define PMIC_RG_XO_LDOPBUF_BYP_SHIFT  14
#define PMIC_RG_XO_LDOPBUF_ENCL_ADDR  MT6358_DCXO_CW12
#define PMIC_RG_XO_LDOPBUF_ENCL_MASK  0x1
#define PMIC_RG_XO_LDOPBUF_ENCL_SHIFT 15
#define PMIC_RG_XO_VGBIAS_VSET_ADDR   MT6358_DCXO_CW13
#define PMIC_RG_XO_VGBIAS_VSET_MASK   0x3
#define PMIC_RG_XO_VGBIAS_VSET_SHIFT  0
#define PMIC_RG_XO_PBUF_ISET_ADDR MT6358_DCXO_CW13
#define PMIC_RG_XO_PBUF_ISET_MASK 0x3
#define PMIC_RG_XO_PBUF_ISET_SHIFT 2
#define PMIC_RG_XO_IBUF_ISET_ADDR MT6358_DCXO_CW13
#define PMIC_RG_XO_IBUF_ISET_MASK 0x3
#define PMIC_RG_XO_IBUF_ISET_SHIFT 4
#define PMIC_RG_XO_RESERVED4_ADDR MT6358_DCXO_CW13
#define PMIC_RG_XO_RESERVED4_MASK 0x3
#define PMIC_RG_XO_RESERVED4_SHIFT 6
#define PMIC_RG_XO_VOW_EN_ADDR  MT6358_DCXO_CW13
#define PMIC_RG_XO_VOW_EN_MASK  0x1
#define PMIC_RG_XO_VOW_EN_SHIFT 8
#define PMIC_RG_XO_VOW_DIV_ADDR MT6358_DCXO_CW13
#define PMIC_RG_XO_VOW_DIV_MASK 0x3
#define PMIC_RG_XO_VOW_DIV_SHIFT  9
#define PMIC_RG_XO_BUFLDO24_ENCL_ADDR MT6358_DCXO_CW13
#define PMIC_RG_XO_BUFLDO24_ENCL_MASK 0x1
#define PMIC_RG_XO_BUFLDO24_ENCL_SHIFT  11
#define PMIC_RG_XO_BUFLDO24_IBX2_ADDR MT6358_DCXO_CW13
#define PMIC_RG_XO_BUFLDO24_IBX2_MASK 0x1
#define PMIC_RG_XO_BUFLDO24_IBX2_SHIFT  12
#define PMIC_RG_XO_RESERVED5_ADDR MT6358_DCXO_CW13
#define PMIC_RG_XO_RESERVED5_MASK 0x7
#define PMIC_RG_XO_RESERVED5_SHIFT 13
#define PMIC_RG_XO_BUFLDO13_ENCL_ADDR MT6358_DCXO_CW14
#define PMIC_RG_XO_BUFLDO13_ENCL_MASK 0x1
#define PMIC_RG_XO_BUFLDO13_ENCL_SHIFT  0
#define PMIC_RG_XO_BUFLDO13_IBX2_ADDR MT6358_DCXO_CW14
#define PMIC_RG_XO_BUFLDO13_IBX2_MASK 0x1
#define PMIC_RG_XO_BUFLDO13_IBX2_SHIFT  1
#define PMIC_RG_XO_BUFLDO13_IX2_ADDR  MT6358_DCXO_CW14
#define PMIC_RG_XO_BUFLDO13_IX2_MASK  0x1
#define PMIC_RG_XO_BUFLDO13_IX2_SHIFT 2
#define PMIC_RG_XO_LVLDO_I_CTRL_ADDR  MT6358_DCXO_CW14
#define PMIC_RG_XO_LVLDO_I_CTRL_MASK  0x3
#define PMIC_RG_XO_LVLDO_I_CTRL_SHIFT 3
#define PMIC_RG_XO_BUFLDO67_ENCL_ADDR MT6358_DCXO_CW14
#define PMIC_RG_XO_BUFLDO67_ENCL_MASK 0x1
#define PMIC_RG_XO_BUFLDO67_ENCL_SHIFT  5
#define PMIC_RG_XO_BUFLDO67_IBX2_ADDR MT6358_DCXO_CW14
#define PMIC_RG_XO_BUFLDO67_IBX2_MASK 0x1
#define PMIC_RG_XO_BUFLDO67_IBX2_SHIFT  6
#define PMIC_RG_XO_BUFLDO67_IX2_ADDR  MT6358_DCXO_CW14
#define PMIC_RG_XO_BUFLDO67_IX2_MASK  0x1
#define PMIC_RG_XO_BUFLDO67_IX2_SHIFT 7
#define PMIC_RG_XO_LVLDO_RFB_ADDR MT6358_DCXO_CW14
#define PMIC_RG_XO_LVLDO_RFB_MASK 0x3
#define PMIC_RG_XO_LVLDO_RFB_SHIFT 8
#define PMIC_RG_XO_EXTBUF_INV_ADDR MT6358_DCXO_CW14
#define PMIC_RG_XO_EXTBUF_INV_MASK 0x1
#define PMIC_RG_XO_EXTBUF_INV_SHIFT   10
#define PMIC_RG_XO_RESERVED0_ADDR MT6358_DCXO_CW14
#define PMIC_RG_XO_RESERVED0_MASK 0x1
#define PMIC_RG_XO_RESERVED0_SHIFT 11
#define PMIC_XO_EXTBUF2_CLKSEL_MAN_ADDR MT6358_DCXO_CW14
#define PMIC_XO_EXTBUF2_CLKSEL_MAN_MASK 0x1
#define PMIC_XO_EXTBUF2_CLKSEL_MAN_SHIFT   12
#define PMIC_XO_AUDIO_EN_M_ADDR MT6358_DCXO_CW14
#define PMIC_XO_AUDIO_EN_M_MASK 0x1
#define PMIC_XO_AUDIO_EN_M_SHIFT  13
#define PMIC_RG_XO_AUDIO_ATTEN_ADDR   MT6358_DCXO_CW14
#define PMIC_RG_XO_AUDIO_ATTEN_MASK   0x3
#define PMIC_RG_XO_AUDIO_ATTEN_SHIFT  14
#define PMIC_RG_XO_AUDIO_ISET_ADDR MT6358_DCXO_CW15
#define PMIC_RG_XO_AUDIO_ISET_MASK 0x3
#define PMIC_RG_XO_AUDIO_ISET_SHIFT   0
#define PMIC_RG_XO_EXTBUF1_HD_ADDR MT6358_DCXO_CW15
#define PMIC_RG_XO_EXTBUF1_HD_MASK 0x3
#define PMIC_RG_XO_EXTBUF1_HD_SHIFT   2
#define PMIC_RG_XO_EXTBUF2_HD_ADDR MT6358_DCXO_CW15
#define PMIC_RG_XO_EXTBUF2_HD_MASK 0x3
#define PMIC_RG_XO_EXTBUF2_HD_SHIFT   4
#define PMIC_RG_XO_EXTBUF3_HD_ADDR MT6358_DCXO_CW15
#define PMIC_RG_XO_EXTBUF3_HD_MASK 0x3
#define PMIC_RG_XO_EXTBUF3_HD_SHIFT   6
#define PMIC_RG_XO_EXTBUF4_HD_ADDR MT6358_DCXO_CW15
#define PMIC_RG_XO_EXTBUF4_HD_MASK 0x3
#define PMIC_RG_XO_EXTBUF4_HD_SHIFT   8
#define PMIC_RG_XO_RESERVED8_ADDR MT6358_DCXO_CW15
#define PMIC_RG_XO_RESERVED8_MASK 0x3
#define PMIC_RG_XO_RESERVED8_SHIFT 10
#define PMIC_RG_XO_EXTBUF6_HD_ADDR MT6358_DCXO_CW15
#define PMIC_RG_XO_EXTBUF6_HD_MASK 0x3
#define PMIC_RG_XO_EXTBUF6_HD_SHIFT   12
#define PMIC_RG_XO_EXTBUF7_HD_ADDR MT6358_DCXO_CW15
#define PMIC_RG_XO_EXTBUF7_HD_MASK 0x3
#define PMIC_RG_XO_EXTBUF7_HD_SHIFT   14
#define PMIC_XO_EXTBUF1_ISET_M_ADDR   MT6358_DCXO_CW16
#define PMIC_XO_EXTBUF1_ISET_M_MASK   0x3
#define PMIC_XO_EXTBUF1_ISET_M_SHIFT  0
#define PMIC_XO_EXTBUF2_ISET_M_ADDR   MT6358_DCXO_CW16
#define PMIC_XO_EXTBUF2_ISET_M_MASK   0x3
#define PMIC_XO_EXTBUF2_ISET_M_SHIFT  2
#define PMIC_XO_EXTBUF3_ISET_M_ADDR   MT6358_DCXO_CW16
#define PMIC_XO_EXTBUF3_ISET_M_MASK   0x3
#define PMIC_XO_EXTBUF3_ISET_M_SHIFT  4
#define PMIC_XO_EXTBUF4_ISET_M_ADDR   MT6358_DCXO_CW16
#define PMIC_XO_EXTBUF4_ISET_M_MASK   0x3
#define PMIC_XO_EXTBUF4_ISET_M_SHIFT  6
#define PMIC_XO_RESERVED9_ADDR  MT6358_DCXO_CW16
#define PMIC_XO_RESERVED9_MASK  0x3
#define PMIC_XO_RESERVED9_SHIFT 8
#define PMIC_XO_EXTBUF6_ISET_M_ADDR   MT6358_DCXO_CW16
#define PMIC_XO_EXTBUF6_ISET_M_MASK   0x3
#define PMIC_XO_EXTBUF6_ISET_M_SHIFT  10
#define PMIC_XO_EXTBUF7_ISET_M_ADDR   MT6358_DCXO_CW16
#define PMIC_XO_EXTBUF7_ISET_M_MASK   0x3
#define PMIC_XO_EXTBUF7_ISET_M_SHIFT  12
#define PMIC_RG_XO_LPM_PREBUF_ISET_ADDR MT6358_DCXO_CW16
#define PMIC_RG_XO_LPM_PREBUF_ISET_MASK 0x3
#define PMIC_RG_XO_LPM_PREBUF_ISET_SHIFT   14
#define PMIC_RG_XO_RESERVED1_ADDR MT6358_DCXO_CW17
#define PMIC_RG_XO_RESERVED1_MASK 0x3
#define PMIC_RG_XO_RESERVED1_SHIFT 0
#define PMIC_XO_THADC_EN_MAN_ADDR MT6358_DCXO_CW17
#define PMIC_XO_THADC_EN_MAN_MASK 0x1
#define PMIC_XO_THADC_EN_MAN_SHIFT 2
#define PMIC_RG_XO_TSOURCE_EN_ADDR MT6358_DCXO_CW17
#define PMIC_RG_XO_TSOURCE_EN_MASK 0x1
#define PMIC_RG_XO_TSOURCE_EN_SHIFT   3
#define PMIC_XO_BUFLDO13_VSET_M_ADDR  MT6358_DCXO_CW17
#define PMIC_XO_BUFLDO13_VSET_M_MASK  0xF
#define PMIC_XO_BUFLDO13_VSET_M_SHIFT 4
#define PMIC_XO_BUFLDO24_VSET_M_ADDR  MT6358_DCXO_CW17
#define PMIC_XO_BUFLDO24_VSET_M_MASK  0xF
#define PMIC_XO_BUFLDO24_VSET_M_SHIFT 8
#define PMIC_XO_BUFLDO67_VSET_M_ADDR  MT6358_DCXO_CW17
#define PMIC_XO_BUFLDO67_VSET_M_MASK  0xF
#define PMIC_XO_BUFLDO67_VSET_M_SHIFT 12
#define PMIC_XO_STATIC_AUXOUT_SEL_ADDR  MT6358_DCXO_CW18
#define PMIC_XO_STATIC_AUXOUT_SEL_MASK  0x3F
#define PMIC_XO_STATIC_AUXOUT_SEL_SHIFT 0
#define PMIC_XO_AUXOUT_SEL_ADDR MT6358_DCXO_CW18
#define PMIC_XO_AUXOUT_SEL_MASK 0x3FF
#define PMIC_XO_AUXOUT_SEL_SHIFT  6
#define PMIC_XO_STATIC_AUXOUT_ADDR MT6358_DCXO_CW19
#define PMIC_XO_STATIC_AUXOUT_MASK 0xFFFF
#define PMIC_XO_STATIC_AUXOUT_SHIFT   0
#define PMIC_RG_XO_PCTAT_COMP_EN_ADDR MT6358_DCXO_CW20
#define PMIC_RG_XO_PCTAT_COMP_EN_MASK 0x1
#define PMIC_RG_XO_PCTAT_COMP_EN_SHIFT  0
#define PMIC_RG_XO_HEATER_SEL_ADDR MT6358_DCXO_CW20
#define PMIC_RG_XO_HEATER_SEL_MASK 0x3
#define PMIC_RG_XO_HEATER_SEL_SHIFT   1
#define PMIC_RG_XO_CORNER_DETECT_EN_ADDR   MT6358_DCXO_CW20
#define PMIC_RG_XO_CORNER_DETECT_EN_MASK   0x1
#define PMIC_RG_XO_CORNER_DETECT_EN_SHIFT   3
#define PMIC_RG_XO_CORNER_DETECT_EN_MAN_ADDR  MT6358_DCXO_CW20
#define PMIC_RG_XO_CORNER_DETECT_EN_MAN_MASK  0x1
#define PMIC_RG_XO_CORNER_DETECT_EN_MAN_SHIFT 4
#define PMIC_RG_XO_RESRVED10_ADDR MT6358_DCXO_CW20
#define PMIC_RG_XO_RESRVED10_MASK 0x7FF
#define PMIC_RG_XO_RESRVED10_SHIFT 5
#define PMIC_RG_XO_CORNER_SETTING_TUNE_ADDR MT6358_DCXO_CW21
#define PMIC_RG_XO_CORNER_SETTING_TUNE_MASK 0x3FF
#define PMIC_RG_XO_CORNER_SETTING_TUNE_SHIFT  0
#define PMIC_RG_XO_RESRVED11_ADDR MT6358_DCXO_CW21
#define PMIC_RG_XO_RESRVED11_MASK 0x3F
#define PMIC_RG_XO_RESRVED11_SHIFT 10
#define PMIC_RGS_AD_XO_CORNER_CAL_DONE_ADDR MT6358_DCXO_CW22
#define PMIC_RGS_AD_XO_CORNER_CAL_DONE_MASK 0x1
#define PMIC_RGS_AD_XO_CORNER_CAL_DONE_SHIFT  0
#define PMIC_RGS_AD_XO_CORNER_SEL_ADDR  MT6358_DCXO_CW22
#define PMIC_RGS_AD_XO_CORNER_SEL_MASK  0xF
#define PMIC_RGS_AD_XO_CORNER_SEL_SHIFT 1
#define PMIC_XO_MDB_TBO_EN_SEL_ADDR   MT6358_DCXO_CW22
#define PMIC_XO_MDB_TBO_EN_SEL_MASK   0x1
#define PMIC_XO_MDB_TBO_EN_SEL_SHIFT  5
#define PMIC_XO_PTATCTAT_EN_MAN_ADDR  MT6358_DCXO_CW22
#define PMIC_XO_PTATCTAT_EN_MAN_MASK  0x1
#define PMIC_XO_PTATCTAT_EN_MAN_SHIFT 6
#define PMIC_XO_PTATCTAT_EN_M_ADDR MT6358_DCXO_CW22
#define PMIC_XO_PTATCTAT_EN_M_MASK 0x1
#define PMIC_XO_PTATCTAT_EN_M_SHIFT   7
#define PMIC_XO_PTATCTAT_EN_LPM_ADDR  MT6358_DCXO_CW22
#define PMIC_XO_PTATCTAT_EN_LPM_MASK  0x1
#define PMIC_XO_PTATCTAT_EN_LPM_SHIFT 8
#define PMIC_XO_PTATCTAT_EN_FPM_ADDR  MT6358_DCXO_CW22
#define PMIC_XO_PTATCTAT_EN_FPM_MASK  0x1
#define PMIC_XO_PTATCTAT_EN_FPM_SHIFT 9
#define PMIC_XO_BB_LPM_CEL_ADDR MT6358_DCXO_CW23
#define PMIC_XO_BB_LPM_CEL_MASK 0x1
#define PMIC_XO_BB_LPM_CEL_SHIFT  0
#define PMIC_XO_BUF1_BBLPM_EN_MASK_ADDR MT6358_DCXO_CW23
#define PMIC_XO_BUF1_BBLPM_EN_MASK_MASK 0x1
#define PMIC_XO_BUF1_BBLPM_EN_MASK_SHIFT   1
#define PMIC_XO_BUF2_BBLPM_EN_MASK_ADDR MT6358_DCXO_CW23
#define PMIC_XO_BUF2_BBLPM_EN_MASK_MASK 0x1
#define PMIC_XO_BUF2_BBLPM_EN_MASK_SHIFT   2
#define PMIC_XO_BUF3_BBLPM_EN_MASK_ADDR MT6358_DCXO_CW23
#define PMIC_XO_BUF3_BBLPM_EN_MASK_MASK 0x1
#define PMIC_XO_BUF3_BBLPM_EN_MASK_SHIFT   3
#define PMIC_XO_BUF4_BBLPM_EN_MASK_ADDR MT6358_DCXO_CW23
#define PMIC_XO_BUF4_BBLPM_EN_MASK_MASK 0x1
#define PMIC_XO_BUF4_BBLPM_EN_MASK_SHIFT   4
#define PMIC_XO_BUF6_BBLPM_EN_MASK_ADDR MT6358_DCXO_CW23
#define PMIC_XO_BUF6_BBLPM_EN_MASK_MASK 0x1
#define PMIC_XO_BUF6_BBLPM_EN_MASK_SHIFT   5
#define PMIC_XO_BUF7_BBLPM_EN_MASK_ADDR MT6358_DCXO_CW23
#define PMIC_XO_BUF7_BBLPM_EN_MASK_MASK 0x1
#define PMIC_XO_BUF7_BBLPM_EN_MASK_SHIFT   6
#define PMIC_XO_PMU_CKEN_MODE_ADDR MT6358_DCXO_CW23
#define PMIC_XO_PMU_CKEN_MODE_MASK 0x1
#define PMIC_XO_PMU_CKEN_MODE_SHIFT   7
#define PMIC_XO_RESERVED2_ADDR  MT6358_DCXO_CW23
#define PMIC_XO_RESERVED2_MASK  0xF
#define PMIC_XO_RESERVED2_SHIFT 8
#define PMIC_RG_XO_RESRVED12_ADDR MT6358_DCXO_CW24
#define PMIC_RG_XO_RESRVED12_MASK 0xFFFF
#define PMIC_RG_XO_RESRVED12_SHIFT 0
#define PMIC_DCXO_ELR_LEN_ADDR  MT6358_DCXO_ELR_NUM
#define PMIC_DCXO_ELR_LEN_MASK  0xFF
#define PMIC_DCXO_ELR_LEN_SHIFT 0
#define PMIC_RG_XO_PCTAT_RDEG_SEL_ADDR  MT6358_DCXO_ELR0
#define PMIC_RG_XO_PCTAT_RDEG_SEL_MASK  0x1
#define PMIC_RG_XO_PCTAT_RDEG_SEL_SHIFT 0
#define PMIC_RG_XO_GS_VTEMP_ADDR  MT6358_DCXO_ELR0
#define PMIC_RG_XO_GS_VTEMP_MASK  0x7
#define PMIC_RG_XO_GS_VTEMP_SHIFT 1
#define PMIC_XO_PWRKEY_RSTB_SEL_ADDR  MT6358_DCXO_ELR0
#define PMIC_XO_PWRKEY_RSTB_SEL_MASK  0x1
#define PMIC_XO_PWRKEY_RSTB_SEL_SHIFT 4
#define PMIC_PSC_TOP_ANA_ID_ADDR  MT6358_PSC_TOP_ID
#define PMIC_PSC_TOP_ANA_ID_MASK  0xFF
#define PMIC_PSC_TOP_ANA_ID_SHIFT 0
#define PMIC_PSC_TOP_DIG_ID_ADDR  MT6358_PSC_TOP_ID
#define PMIC_PSC_TOP_DIG_ID_MASK  0xFF
#define PMIC_PSC_TOP_DIG_ID_SHIFT 8
#define PMIC_PSC_TOP_ANA_MINOR_REV_ADDR MT6358_PSC_TOP_REV0
#define PMIC_PSC_TOP_ANA_MINOR_REV_MASK 0xF
#define PMIC_PSC_TOP_ANA_MINOR_REV_SHIFT   0
#define PMIC_PSC_TOP_ANA_MAJOR_REV_ADDR MT6358_PSC_TOP_REV0
#define PMIC_PSC_TOP_ANA_MAJOR_REV_MASK 0xF
#define PMIC_PSC_TOP_ANA_MAJOR_REV_SHIFT   4
#define PMIC_PSC_TOP_DIG_MINOR_REV_ADDR MT6358_PSC_TOP_REV0
#define PMIC_PSC_TOP_DIG_MINOR_REV_MASK 0xF
#define PMIC_PSC_TOP_DIG_MINOR_REV_SHIFT   8
#define PMIC_PSC_TOP_DIG_MAJOR_REV_ADDR MT6358_PSC_TOP_REV0
#define PMIC_PSC_TOP_DIG_MAJOR_REV_MASK 0xF
#define PMIC_PSC_TOP_DIG_MAJOR_REV_SHIFT   12
#define PMIC_PSC_TOP_CBS_ADDR   MT6358_PSC_TOP_DBI
#define PMIC_PSC_TOP_CBS_MASK   0x3
#define PMIC_PSC_TOP_CBS_SHIFT  0
#define PMIC_PSC_TOP_BIX_ADDR   MT6358_PSC_TOP_DBI
#define PMIC_PSC_TOP_BIX_MASK   0x3
#define PMIC_PSC_TOP_BIX_SHIFT  2
#define PMIC_PSC_TOP_ESP_ADDR   MT6358_PSC_TOP_DBI
#define PMIC_PSC_TOP_ESP_MASK   0xFF
#define PMIC_PSC_TOP_ESP_SHIFT  8
#define PMIC_PSC_TOP_FPI_ADDR   MT6358_PSC_TOP_DXI
#define PMIC_PSC_TOP_FPI_MASK   0xFF
#define PMIC_PSC_TOP_FPI_SHIFT  0
#define PMIC_PSC_TOP_CLK_OFFSET_ADDR  MT6358_PSC_TPM0
#define PMIC_PSC_TOP_CLK_OFFSET_MASK  0xFF
#define PMIC_PSC_TOP_CLK_OFFSET_SHIFT 0
#define PMIC_PSC_TOP_RST_OFFSET_ADDR  MT6358_PSC_TPM0
#define PMIC_PSC_TOP_RST_OFFSET_MASK  0xFF
#define PMIC_PSC_TOP_RST_OFFSET_SHIFT 8
#define PMIC_PSC_TOP_INT_OFFSET_ADDR  MT6358_PSC_TPM1
#define PMIC_PSC_TOP_INT_OFFSET_MASK  0xFF
#define PMIC_PSC_TOP_INT_OFFSET_SHIFT 0
#define PMIC_PSC_TOP_INT_LEN_ADDR MT6358_PSC_TPM1
#define PMIC_PSC_TOP_INT_LEN_MASK 0xFF
#define PMIC_PSC_TOP_INT_LEN_SHIFT 8
#define PMIC_RG_PSC_INTRP_CK_PDN_HWEN_ADDR  MT6358_PSC_TOP_CLKCTL_0
#define PMIC_RG_PSC_INTRP_CK_PDN_HWEN_MASK  0x1
#define PMIC_RG_PSC_INTRP_CK_PDN_HWEN_SHIFT 0
#define PMIC_RG_PSC_INTRP_CK_PDN_ADDR MT6358_PSC_TOP_CLKCTL_0
#define PMIC_RG_PSC_INTRP_CK_PDN_MASK 0x1
#define PMIC_RG_PSC_INTRP_CK_PDN_SHIFT  1
#define PMIC_RG_CHRDET_32K_CK_PDN_ADDR  MT6358_PSC_TOP_CLKCTL_0
#define PMIC_RG_CHRDET_32K_CK_PDN_MASK  0x1
#define PMIC_RG_CHRDET_32K_CK_PDN_SHIFT 2
#define PMIC_RG_STRUP_LONG_PRESS_RST_ADDR   MT6358_PSC_TOP_RSTCTL_0
#define PMIC_RG_STRUP_LONG_PRESS_RST_MASK   0x1
#define PMIC_RG_STRUP_LONG_PRESS_RST_SHIFT  0
#define PMIC_RG_PSEQ_PWRMSK_RST_SEL_ADDR   MT6358_PSC_TOP_RSTCTL_0
#define PMIC_RG_PSEQ_PWRMSK_RST_SEL_MASK   0x1
#define PMIC_RG_PSEQ_PWRMSK_RST_SEL_SHIFT   4
#define PMIC_BANK_STRUP_SWRST_ADDR MT6358_PSC_TOP_RSTCTL_0
#define PMIC_BANK_STRUP_SWRST_MASK 0x1
#define PMIC_BANK_STRUP_SWRST_SHIFT   8
#define PMIC_BANK_PSEQ_SWRST_ADDR MT6358_PSC_TOP_RSTCTL_0
#define PMIC_BANK_PSEQ_SWRST_MASK 0x1
#define PMIC_BANK_PSEQ_SWRST_SHIFT 9
#define PMIC_BANK_CHRDET_SWRST_ADDR   MT6358_PSC_TOP_RSTCTL_0
#define PMIC_BANK_CHRDET_SWRST_MASK   0x1
#define PMIC_BANK_CHRDET_SWRST_SHIFT  12
#define PMIC_RG_CHRDET_RST_ADDR MT6358_PSC_TOP_RSTCTL_0
#define PMIC_RG_CHRDET_RST_MASK 0x1
#define PMIC_RG_CHRDET_RST_SHIFT  13
#define PMIC_RG_INT_EN_PWRKEY_ADDR MT6358_PSC_TOP_INT_CON0
#define PMIC_RG_INT_EN_PWRKEY_MASK 0x1
#define PMIC_RG_INT_EN_PWRKEY_SHIFT   0
#define PMIC_RG_INT_EN_HOMEKEY_ADDR   MT6358_PSC_TOP_INT_CON0
#define PMIC_RG_INT_EN_HOMEKEY_MASK   0x1
#define PMIC_RG_INT_EN_HOMEKEY_SHIFT  1
#define PMIC_RG_INT_EN_PWRKEY_R_ADDR  MT6358_PSC_TOP_INT_CON0
#define PMIC_RG_INT_EN_PWRKEY_R_MASK  0x1
#define PMIC_RG_INT_EN_PWRKEY_R_SHIFT 2
#define PMIC_RG_INT_EN_HOMEKEY_R_ADDR MT6358_PSC_TOP_INT_CON0
#define PMIC_RG_INT_EN_HOMEKEY_R_MASK 0x1
#define PMIC_RG_INT_EN_HOMEKEY_R_SHIFT  3
#define PMIC_RG_INT_EN_NI_LBAT_INT_ADDR MT6358_PSC_TOP_INT_CON0
#define PMIC_RG_INT_EN_NI_LBAT_INT_MASK 0x1
#define PMIC_RG_INT_EN_NI_LBAT_INT_SHIFT   4
#define PMIC_RG_INT_EN_CHRDET_ADDR MT6358_PSC_TOP_INT_CON0
#define PMIC_RG_INT_EN_CHRDET_MASK 0x1
#define PMIC_RG_INT_EN_CHRDET_SHIFT   5
#define PMIC_RG_INT_EN_CHRDET_EDGE_ADDR MT6358_PSC_TOP_INT_CON0
#define PMIC_RG_INT_EN_CHRDET_EDGE_MASK 0x1
#define PMIC_RG_INT_EN_CHRDET_EDGE_SHIFT   6
#define PMIC_RG_INT_EN_VCDT_HV_DET_ADDR MT6358_PSC_TOP_INT_CON0
#define PMIC_RG_INT_EN_VCDT_HV_DET_MASK 0x1
#define PMIC_RG_INT_EN_VCDT_HV_DET_SHIFT   7
#define PMIC_PSC_INT_CON0_SET_ADDR MT6358_PSC_TOP_INT_CON0_SET
#define PMIC_PSC_INT_CON0_SET_MASK 0xFFFF
#define PMIC_PSC_INT_CON0_SET_SHIFT   0
#define PMIC_PSC_INT_CON0_CLR_ADDR MT6358_PSC_TOP_INT_CON0_CLR
#define PMIC_PSC_INT_CON0_CLR_MASK 0xFFFF
#define PMIC_PSC_INT_CON0_CLR_SHIFT   0
#define PMIC_RG_INT_MASK_PWRKEY_ADDR  MT6358_PSC_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_PWRKEY_MASK  0x1
#define PMIC_RG_INT_MASK_PWRKEY_SHIFT 0
#define PMIC_RG_INT_MASK_HOMEKEY_ADDR MT6358_PSC_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_HOMEKEY_MASK 0x1
#define PMIC_RG_INT_MASK_HOMEKEY_SHIFT  1
#define PMIC_RG_INT_MASK_PWRKEY_R_ADDR  MT6358_PSC_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_PWRKEY_R_MASK  0x1
#define PMIC_RG_INT_MASK_PWRKEY_R_SHIFT 2
#define PMIC_RG_INT_MASK_HOMEKEY_R_ADDR MT6358_PSC_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_HOMEKEY_R_MASK 0x1
#define PMIC_RG_INT_MASK_HOMEKEY_R_SHIFT   3
#define PMIC_RG_INT_MASK_NI_LBAT_INT_ADDR   MT6358_PSC_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_NI_LBAT_INT_MASK   0x1
#define PMIC_RG_INT_MASK_NI_LBAT_INT_SHIFT  4
#define PMIC_RG_INT_MASK_CHRDET_ADDR  MT6358_PSC_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_CHRDET_MASK  0x1
#define PMIC_RG_INT_MASK_CHRDET_SHIFT 5
#define PMIC_RG_INT_MASK_CHRDET_EDGE_ADDR   MT6358_PSC_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_CHRDET_EDGE_MASK   0x1
#define PMIC_RG_INT_MASK_CHRDET_EDGE_SHIFT  6
#define PMIC_RG_INT_MASK_VCDT_HV_DET_ADDR   MT6358_PSC_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_VCDT_HV_DET_MASK   0x1
#define PMIC_RG_INT_MASK_VCDT_HV_DET_SHIFT  7
#define PMIC_PSC_INT_MASK_CON0_SET_ADDR MT6358_PSC_TOP_INT_MASK_CON0_SET
#define PMIC_PSC_INT_MASK_CON0_SET_MASK 0xFFFF
#define PMIC_PSC_INT_MASK_CON0_SET_SHIFT   0
#define PMIC_PSC_INT_MASK_CON0_CLR_ADDR MT6358_PSC_TOP_INT_MASK_CON0_CLR
#define PMIC_PSC_INT_MASK_CON0_CLR_MASK 0xFFFF
#define PMIC_PSC_INT_MASK_CON0_CLR_SHIFT   0
#define PMIC_RG_INT_STATUS_PWRKEY_ADDR  MT6358_PSC_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_PWRKEY_MASK  0x1
#define PMIC_RG_INT_STATUS_PWRKEY_SHIFT 0
#define PMIC_RG_INT_STATUS_HOMEKEY_ADDR MT6358_PSC_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_HOMEKEY_MASK 0x1
#define PMIC_RG_INT_STATUS_HOMEKEY_SHIFT   1
#define PMIC_RG_INT_STATUS_PWRKEY_R_ADDR   MT6358_PSC_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_PWRKEY_R_MASK   0x1
#define PMIC_RG_INT_STATUS_PWRKEY_R_SHIFT   2
#define PMIC_RG_INT_STATUS_HOMEKEY_R_ADDR   MT6358_PSC_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_HOMEKEY_R_MASK   0x1
#define PMIC_RG_INT_STATUS_HOMEKEY_R_SHIFT  3
#define PMIC_RG_INT_STATUS_NI_LBAT_INT_ADDR MT6358_PSC_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_NI_LBAT_INT_MASK 0x1
#define PMIC_RG_INT_STATUS_NI_LBAT_INT_SHIFT  4
#define PMIC_RG_INT_STATUS_CHRDET_ADDR  MT6358_PSC_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_CHRDET_MASK  0x1
#define PMIC_RG_INT_STATUS_CHRDET_SHIFT 5
#define PMIC_RG_INT_STATUS_CHRDET_EDGE_ADDR MT6358_PSC_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_CHRDET_EDGE_MASK 0x1
#define PMIC_RG_INT_STATUS_CHRDET_EDGE_SHIFT  6
#define PMIC_RG_INT_STATUS_VCDT_HV_DET_ADDR MT6358_PSC_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_VCDT_HV_DET_MASK 0x1
#define PMIC_RG_INT_STATUS_VCDT_HV_DET_SHIFT  7
#define PMIC_RG_INT_RAW_STATUS_PWRKEY_ADDR  MT6358_PSC_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_PWRKEY_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_PWRKEY_SHIFT 0
#define PMIC_RG_INT_RAW_STATUS_HOMEKEY_ADDR MT6358_PSC_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_HOMEKEY_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_HOMEKEY_SHIFT  1
#define PMIC_RG_INT_RAW_STATUS_PWRKEY_R_ADDR  MT6358_PSC_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_PWRKEY_R_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_PWRKEY_R_SHIFT 2
#define PMIC_RG_INT_RAW_STATUS_HOMEKEY_R_ADDR MT6358_PSC_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_HOMEKEY_R_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_HOMEKEY_R_SHIFT   3
#define PMIC_RG_INT_RAW_STATUS_NI_LBAT_INT_ADDR  MT6358_PSC_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_NI_LBAT_INT_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_NI_LBAT_INT_SHIFT  4
#define PMIC_RG_INT_RAW_STATUS_CHRDET_ADDR  MT6358_PSC_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_CHRDET_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_CHRDET_SHIFT 5
#define PMIC_RG_INT_RAW_STATUS_CHRDET_EDGE_ADDR  MT6358_PSC_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_CHRDET_EDGE_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_CHRDET_EDGE_SHIFT  6
#define PMIC_RG_INT_RAW_STATUS_VCDT_HV_DET_ADDR  MT6358_PSC_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_VCDT_HV_DET_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_VCDT_HV_DET_SHIFT  7
#define PMIC_RG_PSC_INT_POLARITY_ADDR MT6358_PSC_TOP_INT_MISC_CON
#define PMIC_RG_PSC_INT_POLARITY_MASK 0x1
#define PMIC_RG_PSC_INT_POLARITY_SHIFT  0
#define PMIC_RG_HOMEKEY_INT_SEL_ADDR  MT6358_PSC_TOP_INT_MISC_CON
#define PMIC_RG_HOMEKEY_INT_SEL_MASK  0x1
#define PMIC_RG_HOMEKEY_INT_SEL_SHIFT 1
#define PMIC_RG_PWRKEY_INT_SEL_ADDR   MT6358_PSC_TOP_INT_MISC_CON
#define PMIC_RG_PWRKEY_INT_SEL_MASK   0x1
#define PMIC_RG_PWRKEY_INT_SEL_SHIFT  2
#define PMIC_INT_MISC_CON_SET_ADDR MT6358_PSC_TOP_INT_MISC_CON_SET
#define PMIC_INT_MISC_CON_SET_MASK 0xFFFF
#define PMIC_INT_MISC_CON_SET_SHIFT   0
#define PMIC_INT_MISC_CON_CLR_ADDR MT6358_PSC_TOP_INT_MISC_CON_CLR
#define PMIC_INT_MISC_CON_CLR_MASK 0xFFFF
#define PMIC_INT_MISC_CON_CLR_SHIFT   0
#define PMIC_RG_PSC_MON_GRP_SEL_ADDR  MT6358_PSC_TOP_MON_CTL
#define PMIC_RG_PSC_MON_GRP_SEL_MASK  0x7
#define PMIC_RG_PSC_MON_GRP_SEL_SHIFT 0
#define PMIC_STRUP_ANA_ID_ADDR  MT6358_STRUP_ID
#define PMIC_STRUP_ANA_ID_MASK  0xFF
#define PMIC_STRUP_ANA_ID_SHIFT 0
#define PMIC_STRUP_DIG_ID_ADDR  MT6358_STRUP_ID
#define PMIC_STRUP_DIG_ID_MASK  0xFF
#define PMIC_STRUP_DIG_ID_SHIFT 8
#define PMIC_STRUP_ANA_MINOR_REV_ADDR MT6358_STRUP_REV0
#define PMIC_STRUP_ANA_MINOR_REV_MASK 0xF
#define PMIC_STRUP_ANA_MINOR_REV_SHIFT  0
#define PMIC_STRUP_ANA_MAJOR_REV_ADDR MT6358_STRUP_REV0
#define PMIC_STRUP_ANA_MAJOR_REV_MASK 0xF
#define PMIC_STRUP_ANA_MAJOR_REV_SHIFT  4
#define PMIC_STRUP_DIG_MINOR_REV_ADDR MT6358_STRUP_REV0
#define PMIC_STRUP_DIG_MINOR_REV_MASK 0xF
#define PMIC_STRUP_DIG_MINOR_REV_SHIFT  8
#define PMIC_STRUP_DIG_MAJOR_REV_ADDR MT6358_STRUP_REV0
#define PMIC_STRUP_DIG_MAJOR_REV_MASK 0xF
#define PMIC_STRUP_DIG_MAJOR_REV_SHIFT  12
#define PMIC_STRUP_CBS_ADDR  MT6358_STRUP_DBI
#define PMIC_STRUP_CBS_MASK  0x3
#define PMIC_STRUP_CBS_SHIFT 0
#define PMIC_STRUP_BIX_ADDR  MT6358_STRUP_DBI
#define PMIC_STRUP_BIX_MASK  0x3
#define PMIC_STRUP_BIX_SHIFT 2
#define PMIC_STRUP_DSN_ESP_ADDR MT6358_STRUP_DBI
#define PMIC_STRUP_DSN_ESP_MASK 0xFF
#define PMIC_STRUP_DSN_ESP_SHIFT  8
#define PMIC_STRUP_DSN_FPI_ADDR MT6358_STRUP_DSN_FPI
#define PMIC_STRUP_DSN_FPI_MASK 0xFF
#define PMIC_STRUP_DSN_FPI_SHIFT  0
#define PMIC_RG_TM_OUT_ADDR  MT6358_STRUP_ANA_CON0
#define PMIC_RG_TM_OUT_MASK  0xF
#define PMIC_RG_TM_OUT_SHIFT 0
#define PMIC_RG_THRDET_SEL_ADDR MT6358_STRUP_ANA_CON0
#define PMIC_RG_THRDET_SEL_MASK 0x1
#define PMIC_RG_THRDET_SEL_SHIFT  8
#define PMIC_RG_STRUP_THR_SEL_ADDR MT6358_STRUP_ANA_CON0
#define PMIC_RG_STRUP_THR_SEL_MASK 0x3
#define PMIC_RG_STRUP_THR_SEL_SHIFT   9
#define PMIC_RG_THR_TMODE_ADDR  MT6358_STRUP_ANA_CON0
#define PMIC_RG_THR_TMODE_MASK  0x1
#define PMIC_RG_THR_TMODE_SHIFT 11
#define PMIC_RG_VREF_BG_ADDR MT6358_STRUP_ANA_CON0
#define PMIC_RG_VREF_BG_MASK 0x7
#define PMIC_RG_VREF_BG_SHIFT   12
#define PMIC_RG_RST_DRVSEL_ADDR MT6358_STRUP_ANA_CON1
#define PMIC_RG_RST_DRVSEL_MASK 0x1
#define PMIC_RG_RST_DRVSEL_SHIFT  6
#define PMIC_RG_EN1_DRVSEL_ADDR MT6358_STRUP_ANA_CON1
#define PMIC_RG_EN1_DRVSEL_MASK 0x1
#define PMIC_RG_EN1_DRVSEL_SHIFT  7
#define PMIC_RG_EN2_DRVSEL_ADDR MT6358_STRUP_ANA_CON1
#define PMIC_RG_EN2_DRVSEL_MASK 0x1
#define PMIC_RG_EN2_DRVSEL_SHIFT  8
#define PMIC_RG_PMU_RSV_ADDR MT6358_STRUP_ANA_CON1
#define PMIC_RG_PMU_RSV_MASK 0xF
#define PMIC_RG_PMU_RSV_SHIFT   9
#define PMIC_RGS_ANA_CHIP_ID_ADDR MT6358_STRUP_ANA_CON1
#define PMIC_RGS_ANA_CHIP_ID_MASK 0x7
#define PMIC_RGS_ANA_CHIP_ID_SHIFT 13
#define PMIC_STRUP_ELR_LEN_ADDR MT6358_STRUP_ELR_NUM
#define PMIC_STRUP_ELR_LEN_MASK 0xFF
#define PMIC_STRUP_ELR_LEN_SHIFT  0
#define PMIC_RG_STRUP_IREF_TRIM_ADDR  MT6358_STRUP_ELR_0
#define PMIC_RG_STRUP_IREF_TRIM_MASK  0x3F
#define PMIC_RG_STRUP_IREF_TRIM_SHIFT 0
#define PMIC_RG_THR_LOC_SEL_ADDR  MT6358_STRUP_ELR_1
#define PMIC_RG_THR_LOC_SEL_MASK  0xF
#define PMIC_RG_THR_LOC_SEL_SHIFT 0
#define PMIC_PSEQ_ANA_ID_ADDR   MT6358_PSEQ_ID
#define PMIC_PSEQ_ANA_ID_MASK   0xFF
#define PMIC_PSEQ_ANA_ID_SHIFT  0
#define PMIC_PSEQ_DIG_ID_ADDR   MT6358_PSEQ_ID
#define PMIC_PSEQ_DIG_ID_MASK   0xFF
#define PMIC_PSEQ_DIG_ID_SHIFT  8
#define PMIC_PSEQ_ANA_MINOR_REV_ADDR  MT6358_PSEQ_REV0
#define PMIC_PSEQ_ANA_MINOR_REV_MASK  0xF
#define PMIC_PSEQ_ANA_MINOR_REV_SHIFT 0
#define PMIC_PSEQ_ANA_MAJOR_REV_ADDR  MT6358_PSEQ_REV0
#define PMIC_PSEQ_ANA_MAJOR_REV_MASK  0xF
#define PMIC_PSEQ_ANA_MAJOR_REV_SHIFT 4
#define PMIC_PSEQ_DIG_MINOR_REV_ADDR  MT6358_PSEQ_REV0
#define PMIC_PSEQ_DIG_MINOR_REV_MASK  0xF
#define PMIC_PSEQ_DIG_MINOR_REV_SHIFT 8
#define PMIC_PSEQ_DIG_MAJOR_REV_ADDR  MT6358_PSEQ_REV0
#define PMIC_PSEQ_DIG_MAJOR_REV_MASK  0xF
#define PMIC_PSEQ_DIG_MAJOR_REV_SHIFT 12
#define PMIC_PSEQ_CBS_ADDR  MT6358_PSEQ_DBI
#define PMIC_PSEQ_CBS_MASK  0x3
#define PMIC_PSEQ_CBS_SHIFT  0
#define PMIC_PSEQ_BIX_ADDR  MT6358_PSEQ_DBI
#define PMIC_PSEQ_BIX_MASK  0x3
#define PMIC_PSEQ_BIX_SHIFT  2
#define PMIC_PSEQ_ESP_ADDR  MT6358_PSEQ_DBI
#define PMIC_PSEQ_ESP_MASK  0xFF
#define PMIC_PSEQ_ESP_SHIFT  8
#define PMIC_PSEQ_FPI_ADDR  MT6358_PSEQ_DXI
#define PMIC_PSEQ_FPI_MASK  0xFF
#define PMIC_PSEQ_FPI_SHIFT  0
#define PMIC_RG_PWRHOLD_ADDR MT6358_PPCCTL0
#define PMIC_RG_PWRHOLD_MASK 0x1
#define PMIC_RG_PWRHOLD_SHIFT   0
#define PMIC_RG_USBDL_MODE_ADDR MT6358_PPCCTL0
#define PMIC_RG_USBDL_MODE_MASK 0x1
#define PMIC_RG_USBDL_MODE_SHIFT  4
#define PMIC_RG_CRST_ADDR MT6358_PPCCTL0
#define PMIC_RG_CRST_MASK 0x1
#define PMIC_RG_CRST_SHIFT  8
#define PMIC_RG_WRST_ADDR MT6358_PPCCTL0
#define PMIC_RG_WRST_MASK 0x1
#define PMIC_RG_WRST_SHIFT  9
#define PMIC_RG_CRST_INTV_ADDR  MT6358_PPCCTL1
#define PMIC_RG_CRST_INTV_MASK  0x3
#define PMIC_RG_CRST_INTV_SHIFT 8
#define PMIC_RG_WRST_INTV_ADDR  MT6358_PPCCTL1
#define PMIC_RG_WRST_INTV_MASK  0x3
#define PMIC_RG_WRST_INTV_SHIFT 10
#define PMIC_RG_PSEQ_PG_CK_SEL_ADDR   MT6358_PPCCTL2
#define PMIC_RG_PSEQ_PG_CK_SEL_MASK   0x1
#define PMIC_RG_PSEQ_PG_CK_SEL_SHIFT  0
#define PMIC_RG_PSEQ_SPAR_XCPT_MASK_ADDR   MT6358_PPCCTL2
#define PMIC_RG_PSEQ_SPAR_XCPT_MASK_MASK   0x1
#define PMIC_RG_PSEQ_SPAR_XCPT_MASK_SHIFT   4
#define PMIC_RG_PSEQ_RTCA_XCPT_MASK_ADDR   MT6358_PPCCTL2
#define PMIC_RG_PSEQ_RTCA_XCPT_MASK_MASK   0x1
#define PMIC_RG_PSEQ_RTCA_XCPT_MASK_SHIFT   5
#define PMIC_RG_THM_SHDN_EN_ADDR  MT6358_PPCCTL2
#define PMIC_RG_THM_SHDN_EN_MASK  0x1
#define PMIC_RG_THM_SHDN_EN_SHIFT 8
#define PMIC_RG_WDTRST_EN_ADDR  MT6358_PPCCFG0
#define PMIC_RG_WDTRST_EN_MASK  0x1
#define PMIC_RG_WDTRST_EN_SHIFT 0
#define PMIC_RG_WDTRST_ACT_ADDR MT6358_PPCCFG0
#define PMIC_RG_WDTRST_ACT_MASK 0x3
#define PMIC_RG_WDTRST_ACT_SHIFT  4
#define PMIC_RG_KEYPWR_VCORE_OPT_ADDR MT6358_PPCCFG0
#define PMIC_RG_KEYPWR_VCORE_OPT_MASK 0x1
#define PMIC_RG_KEYPWR_VCORE_OPT_SHIFT  8
#define PMIC_RG_PSEQ_FORCE_ON_ADDR MT6358_PPCTST0
#define PMIC_RG_PSEQ_FORCE_ON_MASK 0x1
#define PMIC_RG_PSEQ_FORCE_ON_SHIFT   0
#define PMIC_RG_PSEQ_FORCE_ALL_DOFF_ADDR   MT6358_PPCTST0
#define PMIC_RG_PSEQ_FORCE_ALL_DOFF_MASK   0x1
#define PMIC_RG_PSEQ_FORCE_ALL_DOFF_SHIFT   8
#define PMIC_RG_POR_FLAG_ADDR   MT6358_PORFLAG
#define PMIC_RG_POR_FLAG_MASK   0x1
#define PMIC_RG_POR_FLAG_SHIFT  0
#define PMIC_USBDL_ADDR   MT6358_STRUP_CON0
#define PMIC_USBDL_MASK   0x1
#define PMIC_USBDL_SHIFT  0
#define PMIC_RG_THR_TEST_ADDR   MT6358_STRUP_CON0
#define PMIC_RG_THR_TEST_MASK   0x3
#define PMIC_RG_THR_TEST_SHIFT  12
#define PMIC_RG_STRUP_THER_DEB_RTD_ADDR MT6358_STRUP_CON1
#define PMIC_RG_STRUP_THER_DEB_RTD_MASK 0x3
#define PMIC_RG_STRUP_THER_DEB_RTD_SHIFT   0
#define PMIC_RG_STRUP_THER_DEB_FTD_ADDR MT6358_STRUP_CON2
#define PMIC_RG_STRUP_THER_DEB_FTD_MASK 0x3
#define PMIC_RG_STRUP_THER_DEB_FTD_SHIFT   0
#define PMIC_DDUVLO_DEB_EN_ADDR MT6358_STRUP_CON3
#define PMIC_DDUVLO_DEB_EN_MASK 0x1
#define PMIC_DDUVLO_DEB_EN_SHIFT  0
#define PMIC_RG_STRUP_PG_DEB_MODE_ADDR  MT6358_STRUP_CON3
#define PMIC_RG_STRUP_PG_DEB_MODE_MASK  0x1
#define PMIC_RG_STRUP_PG_DEB_MODE_SHIFT 1
#define PMIC_RG_STRUP_OSC_EN_ADDR MT6358_STRUP_CON3
#define PMIC_RG_STRUP_OSC_EN_MASK 0x1
#define PMIC_RG_STRUP_OSC_EN_SHIFT 2
#define PMIC_RG_STRUP_OSC_EN_SEL_ADDR MT6358_STRUP_CON3
#define PMIC_RG_STRUP_OSC_EN_SEL_MASK 0x1
#define PMIC_RG_STRUP_OSC_EN_SEL_SHIFT  3
#define PMIC_RG_STRUP_FT_CTRL_ADDR MT6358_STRUP_CON3
#define PMIC_RG_STRUP_FT_CTRL_MASK 0x3
#define PMIC_RG_STRUP_FT_CTRL_SHIFT   4
#define PMIC_RG_STRUP_PWRON_FORCE_ADDR  MT6358_STRUP_CON3
#define PMIC_RG_STRUP_PWRON_FORCE_MASK  0x1
#define PMIC_RG_STRUP_PWRON_FORCE_SHIFT 6
#define PMIC_RG_BIASGEN_FORCE_ADDR MT6358_STRUP_CON3
#define PMIC_RG_BIASGEN_FORCE_MASK 0x1
#define PMIC_RG_BIASGEN_FORCE_SHIFT   7
#define PMIC_RG_STRUP_PWRON_ADDR  MT6358_STRUP_CON3
#define PMIC_RG_STRUP_PWRON_MASK  0x1
#define PMIC_RG_STRUP_PWRON_SHIFT 8
#define PMIC_RG_STRUP_PWRON_SEL_ADDR  MT6358_STRUP_CON3
#define PMIC_RG_STRUP_PWRON_SEL_MASK  0x1
#define PMIC_RG_STRUP_PWRON_SEL_SHIFT 9
#define PMIC_RG_BIASGEN_ADDR MT6358_STRUP_CON3
#define PMIC_RG_BIASGEN_MASK 0x1
#define PMIC_RG_BIASGEN_SHIFT   10
#define PMIC_RG_BIASGEN_SEL_ADDR  MT6358_STRUP_CON3
#define PMIC_RG_BIASGEN_SEL_MASK  0x1
#define PMIC_RG_BIASGEN_SEL_SHIFT 11
#define PMIC_RG_RTC_XOSC32_ENB_ADDR   MT6358_STRUP_CON3
#define PMIC_RG_RTC_XOSC32_ENB_MASK   0x1
#define PMIC_RG_RTC_XOSC32_ENB_SHIFT  12
#define PMIC_RG_RTC_XOSC32_ENB_SEL_ADDR MT6358_STRUP_CON3
#define PMIC_RG_RTC_XOSC32_ENB_SEL_MASK 0x1
#define PMIC_RG_RTC_XOSC32_ENB_SEL_SHIFT   13
#define PMIC_STRUP_DIG_IO_PG_FORCE_ADDR MT6358_STRUP_CON3
#define PMIC_STRUP_DIG_IO_PG_FORCE_MASK 0x1
#define PMIC_STRUP_DIG_IO_PG_FORCE_SHIFT   15
#define PMIC_RG_CLR_JUST_SMART_RST_ADDR MT6358_STRUP_CON4
#define PMIC_RG_CLR_JUST_SMART_RST_MASK 0x1
#define PMIC_RG_CLR_JUST_SMART_RST_SHIFT   3
#define PMIC_CLR_JUST_RST_ADDR  MT6358_STRUP_CON4
#define PMIC_CLR_JUST_RST_MASK  0x1
#define PMIC_CLR_JUST_RST_SHIFT 4
#define PMIC_JUST_SMART_RST_ADDR  MT6358_STRUP_CON4
#define PMIC_JUST_SMART_RST_MASK  0x1
#define PMIC_JUST_SMART_RST_SHIFT 13
#define PMIC_JUST_PWRKEY_RST_ADDR MT6358_STRUP_CON4
#define PMIC_JUST_PWRKEY_RST_MASK 0x1
#define PMIC_JUST_PWRKEY_RST_SHIFT 14
#define PMIC_DA_QI_OSC_EN_ADDR  MT6358_STRUP_CON4
#define PMIC_DA_QI_OSC_EN_MASK  0x1
#define PMIC_DA_QI_OSC_EN_SHIFT 15
#define PMIC_RG_STRUP_EXT_PMIC_EN_ADDR  MT6358_STRUP_CON5
#define PMIC_RG_STRUP_EXT_PMIC_EN_MASK  0x3
#define PMIC_RG_STRUP_EXT_PMIC_EN_SHIFT 0
#define PMIC_RG_STRUP_EXT_PMIC_SEL_ADDR MT6358_STRUP_CON5
#define PMIC_RG_STRUP_EXT_PMIC_SEL_MASK 0x3
#define PMIC_RG_STRUP_EXT_PMIC_SEL_SHIFT   4
#define PMIC_DA_EXT_PMIC_EN1_ADDR MT6358_STRUP_CON5
#define PMIC_DA_EXT_PMIC_EN1_MASK 0x1
#define PMIC_DA_EXT_PMIC_EN1_SHIFT 8
#define PMIC_DA_EXT_PMIC_EN2_ADDR MT6358_STRUP_CON5
#define PMIC_DA_EXT_PMIC_EN2_MASK 0x1
#define PMIC_DA_EXT_PMIC_EN2_SHIFT 9
#define PMIC_RG_STRUP_AUXADC_START_SW_ADDR  MT6358_STRUP_CON6
#define PMIC_RG_STRUP_AUXADC_START_SW_MASK  0x1
#define PMIC_RG_STRUP_AUXADC_START_SW_SHIFT 0
#define PMIC_RG_STRUP_AUXADC_RSTB_SW_ADDR   MT6358_STRUP_CON6
#define PMIC_RG_STRUP_AUXADC_RSTB_SW_MASK   0x1
#define PMIC_RG_STRUP_AUXADC_RSTB_SW_SHIFT  1
#define PMIC_RG_STRUP_AUXADC_START_SEL_ADDR MT6358_STRUP_CON6
#define PMIC_RG_STRUP_AUXADC_START_SEL_MASK 0x1
#define PMIC_RG_STRUP_AUXADC_START_SEL_SHIFT  2
#define PMIC_RG_STRUP_AUXADC_RSTB_SEL_ADDR  MT6358_STRUP_CON6
#define PMIC_RG_STRUP_AUXADC_RSTB_SEL_MASK  0x1
#define PMIC_RG_STRUP_AUXADC_RSTB_SEL_SHIFT 3
#define PMIC_RG_STRUP_AUXADC_RPCNT_MAX_ADDR MT6358_STRUP_CON6
#define PMIC_RG_STRUP_AUXADC_RPCNT_MAX_MASK 0x7F
#define PMIC_RG_STRUP_AUXADC_RPCNT_MAX_SHIFT  4
#define PMIC_STRUP_PWROFF_SEQ_EN_ADDR MT6358_STRUP_CON7
#define PMIC_STRUP_PWROFF_SEQ_EN_MASK 0x1
#define PMIC_STRUP_PWROFF_SEQ_EN_SHIFT  0
#define PMIC_STRUP_PWROFF_PREOFF_EN_ADDR   MT6358_STRUP_CON7
#define PMIC_STRUP_PWROFF_PREOFF_EN_MASK   0x1
#define PMIC_STRUP_PWROFF_PREOFF_EN_SHIFT   1
#define PMIC_RG_SLOT_INTV_DOWN_ADDR   MT6358_CPSCFG0
#define PMIC_RG_SLOT_INTV_DOWN_MASK   0x3
#define PMIC_RG_SLOT_INTV_DOWN_SHIFT  0
#define PMIC_RG_DSEQ_LEN_ADDR   MT6358_CPSCFG0
#define PMIC_RG_DSEQ_LEN_MASK   0x1F
#define PMIC_RG_DSEQ_LEN_SHIFT  8
#define PMIC_RG_VXO22_DSA_ADDR  MT6358_CPSDSA0
#define PMIC_RG_VXO22_DSA_MASK  0x1F
#define PMIC_RG_VXO22_DSA_SHIFT 0
#define PMIC_RG_VAUX18_DSA_ADDR MT6358_CPSDSA0
#define PMIC_RG_VAUX18_DSA_MASK 0x1F
#define PMIC_RG_VAUX18_DSA_SHIFT  5
#define PMIC_RG_VS2_DSA_ADDR MT6358_CPSDSA0
#define PMIC_RG_VS2_DSA_MASK 0x1F
#define PMIC_RG_VS2_DSA_SHIFT   10
#define PMIC_RG_VCORE_DSA_ADDR  MT6358_CPSDSA1
#define PMIC_RG_VCORE_DSA_MASK  0x1F
#define PMIC_RG_VCORE_DSA_SHIFT 0
#define PMIC_RG_VMODEM_DSA_ADDR MT6358_CPSDSA1
#define PMIC_RG_VMODEM_DSA_MASK 0x1F
#define PMIC_RG_VMODEM_DSA_SHIFT  5
#define PMIC_RG_VGPU_DSA_ADDR   MT6358_CPSDSA1
#define PMIC_RG_VGPU_DSA_MASK   0x1F
#define PMIC_RG_VGPU_DSA_SHIFT  10
#define PMIC_RG_VSRAM_OTHERS_DSA_ADDR MT6358_CPSDSA2
#define PMIC_RG_VSRAM_OTHERS_DSA_MASK 0x1F
#define PMIC_RG_VSRAM_OTHERS_DSA_SHIFT  0
#define PMIC_RG_VSRAM_GPU_DSA_ADDR MT6358_CPSDSA2
#define PMIC_RG_VSRAM_GPU_DSA_MASK 0x1F
#define PMIC_RG_VSRAM_GPU_DSA_SHIFT   5
#define PMIC_RG_EXT_PMIC_2_DSA_ADDR   MT6358_CPSDSA2
#define PMIC_RG_EXT_PMIC_2_DSA_MASK   0x1F
#define PMIC_RG_EXT_PMIC_2_DSA_SHIFT  10
#define PMIC_RG_VS1_DSA_ADDR MT6358_CPSDSA3
#define PMIC_RG_VS1_DSA_MASK 0x1F
#define PMIC_RG_VS1_DSA_SHIFT   0
#define PMIC_RG_VA12_DSA_ADDR   MT6358_CPSDSA3
#define PMIC_RG_VA12_DSA_MASK   0x1F
#define PMIC_RG_VA12_DSA_SHIFT  5
#define PMIC_RG_VPROC11_DSA_ADDR  MT6358_CPSDSA3
#define PMIC_RG_VPROC11_DSA_MASK  0x1F
#define PMIC_RG_VPROC11_DSA_SHIFT 10
#define PMIC_RG_VPROC12_DSA_ADDR  MT6358_CPSDSA4
#define PMIC_RG_VPROC12_DSA_MASK  0x1F
#define PMIC_RG_VPROC12_DSA_SHIFT 0
#define PMIC_RG_VSRAM_PROC11_DSA_ADDR MT6358_CPSDSA4
#define PMIC_RG_VSRAM_PROC11_DSA_MASK 0x1F
#define PMIC_RG_VSRAM_PROC11_DSA_SHIFT  5
#define PMIC_RG_VSRAM_PROC12_DSA_ADDR MT6358_CPSDSA4
#define PMIC_RG_VSRAM_PROC12_DSA_MASK 0x1F
#define PMIC_RG_VSRAM_PROC12_DSA_SHIFT  10
#define PMIC_RG_VIO18_DSA_ADDR  MT6358_CPSDSA5
#define PMIC_RG_VIO18_DSA_MASK  0x1F
#define PMIC_RG_VIO18_DSA_SHIFT 0
#define PMIC_RG_VEMC_DSA_ADDR   MT6358_CPSDSA5
#define PMIC_RG_VEMC_DSA_MASK   0x1F
#define PMIC_RG_VEMC_DSA_SHIFT  5
#define PMIC_RG_EXT_PMIC_1_DSA_ADDR   MT6358_CPSDSA5
#define PMIC_RG_EXT_PMIC_1_DSA_MASK   0x1F
#define PMIC_RG_EXT_PMIC_1_DSA_SHIFT  10
#define PMIC_RG_VIO28_DSA_ADDR  MT6358_CPSDSA6
#define PMIC_RG_VIO28_DSA_MASK  0x1F
#define PMIC_RG_VIO28_DSA_SHIFT 0
#define PMIC_RG_VDRAM1_DSA_ADDR MT6358_CPSDSA6
#define PMIC_RG_VDRAM1_DSA_MASK 0x1F
#define PMIC_RG_VDRAM1_DSA_SHIFT  5
#define PMIC_RG_VDRAM2_DSA_ADDR MT6358_CPSDSA6
#define PMIC_RG_VDRAM2_DSA_MASK 0x1F
#define PMIC_RG_VDRAM2_DSA_SHIFT  10
#define PMIC_RG_VUSB_DSA_ADDR   MT6358_CPSDSA7
#define PMIC_RG_VUSB_DSA_MASK   0x1F
#define PMIC_RG_VUSB_DSA_SHIFT  0
#define PMIC_RG_VAUD28_DSA_ADDR MT6358_CPSDSA7
#define PMIC_RG_VAUD28_DSA_MASK 0x1F
#define PMIC_RG_VAUD28_DSA_SHIFT  5
#define PMIC_RG_RSV_DSA_ADDR MT6358_CPSDSA7
#define PMIC_RG_RSV_DSA_MASK 0x1F
#define PMIC_RG_RSV_DSA_SHIFT   10
#define PMIC_RG_RSV_SWREG_ADDR  MT6358_STRUP_CON9
#define PMIC_RG_RSV_SWREG_MASK  0xFFFF
#define PMIC_RG_RSV_SWREG_SHIFT 0
#define PMIC_RG_STRUP_UVLO_U1U2_SEL_ADDR   MT6358_STRUP_CON10
#define PMIC_RG_STRUP_UVLO_U1U2_SEL_MASK   0x1
#define PMIC_RG_STRUP_UVLO_U1U2_SEL_SHIFT   0
#define PMIC_RG_STRUP_UVLO_U1U2_SEL_SWCTRL_ADDR  MT6358_STRUP_CON10
#define PMIC_RG_STRUP_UVLO_U1U2_SEL_SWCTRL_MASK  0x1
#define PMIC_RG_STRUP_UVLO_U1U2_SEL_SWCTRL_SHIFT  1
#define PMIC_RG_UVLO_DEC_EN_ADDR  MT6358_STRUP_CON10
#define PMIC_RG_UVLO_DEC_EN_MASK  0x1
#define PMIC_RG_UVLO_DEC_EN_SHIFT 8
#define PMIC_RG_STRUP_THR_CLR_ADDR MT6358_STRUP_CON11
#define PMIC_RG_STRUP_THR_CLR_MASK 0x1
#define PMIC_RG_STRUP_THR_CLR_SHIFT   0
#define PMIC_RG_STRUP_LONG_PRESS_EXT_SEL_ADDR MT6358_STRUP_CON12
#define PMIC_RG_STRUP_LONG_PRESS_EXT_SEL_MASK 0x3
#define PMIC_RG_STRUP_LONG_PRESS_EXT_SEL_SHIFT   0
#define PMIC_RG_STRUP_LONG_PRESS_EXT_TD_ADDR  MT6358_STRUP_CON12
#define PMIC_RG_STRUP_LONG_PRESS_EXT_TD_MASK  0x3
#define PMIC_RG_STRUP_LONG_PRESS_EXT_TD_SHIFT 2
#define PMIC_RG_STRUP_LONG_PRESS_EXT_EN_ADDR  MT6358_STRUP_CON12
#define PMIC_RG_STRUP_LONG_PRESS_EXT_EN_MASK  0x1
#define PMIC_RG_STRUP_LONG_PRESS_EXT_EN_SHIFT 4
#define PMIC_RG_STRUP_LONG_PRESS_EXT_CHR_CTRL_ADDR  MT6358_STRUP_CON12
#define PMIC_RG_STRUP_LONG_PRESS_EXT_CHR_CTRL_MASK  0x1
#define PMIC_RG_STRUP_LONG_PRESS_EXT_CHR_CTRL_SHIFT 5
#define PMIC_RG_STRUP_LONG_PRESS_EXT_PWRKEY_CTRL_ADDR  MT6358_STRUP_CON12
#define PMIC_RG_STRUP_LONG_PRESS_EXT_PWRKEY_CTRL_MASK  0x1
#define PMIC_RG_STRUP_LONG_PRESS_EXT_PWRKEY_CTRL_SHIFT 6
#define PMIC_RG_STRUP_LONG_PRESS_EXT_SPAR_CTRL_ADDR MT6358_STRUP_CON12
#define PMIC_RG_STRUP_LONG_PRESS_EXT_SPAR_CTRL_MASK 0x1
#define PMIC_RG_STRUP_LONG_PRESS_EXT_SPAR_CTRL_SHIFT   7
#define PMIC_RG_STRUP_LONG_PRESS_EXT_RTCA_CTRL_ADDR MT6358_STRUP_CON12
#define PMIC_RG_STRUP_LONG_PRESS_EXT_RTCA_CTRL_MASK 0x1
#define PMIC_RG_STRUP_LONG_PRESS_EXT_RTCA_CTRL_SHIFT   8
#define PMIC_RG_SMART_RST_SDN_EN_ADDR MT6358_STRUP_CON12
#define PMIC_RG_SMART_RST_SDN_EN_MASK 0x1
#define PMIC_RG_SMART_RST_SDN_EN_SHIFT  12
#define PMIC_RG_SMART_RST_MODE_ADDR   MT6358_STRUP_CON12
#define PMIC_RG_SMART_RST_MODE_MASK   0x1
#define PMIC_RG_SMART_RST_MODE_SHIFT  13
#define PMIC_RG_STRUP_ENVTEM_ADDR MT6358_STRUP_CON12
#define PMIC_RG_STRUP_ENVTEM_MASK 0x1
#define PMIC_RG_STRUP_ENVTEM_SHIFT 14
#define PMIC_RG_STRUP_ENVTEM_CTRL_ADDR  MT6358_STRUP_CON12
#define PMIC_RG_STRUP_ENVTEM_CTRL_MASK  0x1
#define PMIC_RG_STRUP_ENVTEM_CTRL_SHIFT 15
#define PMIC_RG_STRUP_PWRKEY_COUNT_RESET_ADDR MT6358_STRUP_CON13
#define PMIC_RG_STRUP_PWRKEY_COUNT_RESET_MASK 0x1
#define PMIC_RG_STRUP_PWRKEY_COUNT_RESET_SHIFT   0
#define PMIC_PUP_PKEY_RELEASE_ADDR MT6358_PWRKEY_PRESS_STS
#define PMIC_PUP_PKEY_RELEASE_MASK 0x1
#define PMIC_PUP_PKEY_RELEASE_SHIFT   0
#define PMIC_PWRKEY_LONG_PRESS_COUNT_ADDR   MT6358_PWRKEY_PRESS_STS
#define PMIC_PWRKEY_LONG_PRESS_COUNT_MASK   0x3FF
#define PMIC_PWRKEY_LONG_PRESS_COUNT_SHIFT  5
#define PMIC_RG_RTC_SPAR_DEB_EN_ADDR  MT6358_STRUP_CON19
#define PMIC_RG_RTC_SPAR_DEB_EN_MASK  0x1
#define PMIC_RG_RTC_SPAR_DEB_EN_SHIFT 8
#define PMIC_RG_RTC_ALARM_DEB_EN_ADDR MT6358_STRUP_CON19
#define PMIC_RG_RTC_ALARM_DEB_EN_MASK 0x1
#define PMIC_RG_RTC_ALARM_DEB_EN_SHIFT  9
#define PMIC_RG_STRUP_VDRAM2_PG_H2L_EN_ADDR MT6358_STRUP_CON14
#define PMIC_RG_STRUP_VDRAM2_PG_H2L_EN_MASK 0x1
#define PMIC_RG_STRUP_VDRAM2_PG_H2L_EN_SHIFT  0
#define PMIC_RG_STRUP_VEMC_PG_H2L_EN_ADDR   MT6358_STRUP_CON14
#define PMIC_RG_STRUP_VEMC_PG_H2L_EN_MASK   0x1
#define PMIC_RG_STRUP_VEMC_PG_H2L_EN_SHIFT  1
#define PMIC_RG_STRUP_VSRAM_PROC12_PG_H2L_EN_ADDR MT6358_STRUP_CON14
#define PMIC_RG_STRUP_VSRAM_PROC12_PG_H2L_EN_MASK 0x1
#define PMIC_RG_STRUP_VSRAM_PROC12_PG_H2L_EN_SHIFT  2
#define PMIC_RG_STRUP_VSRAM_PROC11_PG_H2L_EN_ADDR MT6358_STRUP_CON14
#define PMIC_RG_STRUP_VSRAM_PROC11_PG_H2L_EN_MASK 0x1
#define PMIC_RG_STRUP_VSRAM_PROC11_PG_H2L_EN_SHIFT  3
#define PMIC_RG_STRUP_VA12_PG_H2L_EN_ADDR   MT6358_STRUP_CON14
#define PMIC_RG_STRUP_VA12_PG_H2L_EN_MASK   0x1
#define PMIC_RG_STRUP_VA12_PG_H2L_EN_SHIFT  4
#define PMIC_RG_STRUP_VSRAM_GPU_PG_H2L_EN_ADDR   MT6358_STRUP_CON14
#define PMIC_RG_STRUP_VSRAM_GPU_PG_H2L_EN_MASK   0x1
#define PMIC_RG_STRUP_VSRAM_GPU_PG_H2L_EN_SHIFT  5
#define PMIC_RG_STRUP_VSRAM_OTHERS_PG_H2L_EN_ADDR MT6358_STRUP_CON14
#define PMIC_RG_STRUP_VSRAM_OTHERS_PG_H2L_EN_MASK 0x1
#define PMIC_RG_STRUP_VSRAM_OTHERS_PG_H2L_EN_SHIFT  6
#define PMIC_RG_STRUP_VAUX18_PG_H2L_EN_ADDR MT6358_STRUP_CON14
#define PMIC_RG_STRUP_VAUX18_PG_H2L_EN_MASK 0x1
#define PMIC_RG_STRUP_VAUX18_PG_H2L_EN_SHIFT  7
#define PMIC_RG_STRUP_VDRAM1_PG_H2L_EN_ADDR MT6358_STRUP_CON14
#define PMIC_RG_STRUP_VDRAM1_PG_H2L_EN_MASK 0x1
#define PMIC_RG_STRUP_VDRAM1_PG_H2L_EN_SHIFT  8
#define PMIC_RG_STRUP_VPROC12_PG_H2L_EN_ADDR  MT6358_STRUP_CON14
#define PMIC_RG_STRUP_VPROC12_PG_H2L_EN_MASK  0x1
#define PMIC_RG_STRUP_VPROC12_PG_H2L_EN_SHIFT 9
#define PMIC_RG_STRUP_VPROC11_PG_H2L_EN_ADDR  MT6358_STRUP_CON14
#define PMIC_RG_STRUP_VPROC11_PG_H2L_EN_MASK  0x1
#define PMIC_RG_STRUP_VPROC11_PG_H2L_EN_SHIFT 10
#define PMIC_RG_STRUP_VS1_PG_H2L_EN_ADDR   MT6358_STRUP_CON14
#define PMIC_RG_STRUP_VS1_PG_H2L_EN_MASK   0x1
#define PMIC_RG_STRUP_VS1_PG_H2L_EN_SHIFT   11
#define PMIC_RG_STRUP_VGPU_PG_H2L_EN_ADDR   MT6358_STRUP_CON14
#define PMIC_RG_STRUP_VGPU_PG_H2L_EN_MASK   0x1
#define PMIC_RG_STRUP_VGPU_PG_H2L_EN_SHIFT  12
#define PMIC_RG_STRUP_VMODEM_PG_H2L_EN_ADDR MT6358_STRUP_CON14
#define PMIC_RG_STRUP_VMODEM_PG_H2L_EN_MASK 0x1
#define PMIC_RG_STRUP_VMODEM_PG_H2L_EN_SHIFT  13
#define PMIC_RG_STRUP_VCORE_PG_H2L_EN_ADDR  MT6358_STRUP_CON14
#define PMIC_RG_STRUP_VCORE_PG_H2L_EN_MASK  0x1
#define PMIC_RG_STRUP_VCORE_PG_H2L_EN_SHIFT 14
#define PMIC_RG_STRUP_VS2_PG_H2L_EN_ADDR   MT6358_STRUP_CON14
#define PMIC_RG_STRUP_VS2_PG_H2L_EN_MASK   0x1
#define PMIC_RG_STRUP_VS2_PG_H2L_EN_SHIFT   15
#define PMIC_RG_STRUP_RSV_PG_H2L_EN_ADDR   MT6358_STRUP_CON15
#define PMIC_RG_STRUP_RSV_PG_H2L_EN_MASK   0x1
#define PMIC_RG_STRUP_RSV_PG_H2L_EN_SHIFT   13
#define PMIC_RG_STRUP_VAUD28_PG_H2L_EN_ADDR MT6358_STRUP_CON15
#define PMIC_RG_STRUP_VAUD28_PG_H2L_EN_MASK 0x1
#define PMIC_RG_STRUP_VAUD28_PG_H2L_EN_SHIFT  14
#define PMIC_RG_STRUP_VUSB_PG_H2L_EN_ADDR   MT6358_STRUP_CON15
#define PMIC_RG_STRUP_VUSB_PG_H2L_EN_MASK   0x1
#define PMIC_RG_STRUP_VUSB_PG_H2L_EN_SHIFT  15
#define PMIC_RG_STRUP_VIO18_PG_ENB_ADDR MT6358_STRUP_CON16
#define PMIC_RG_STRUP_VIO18_PG_ENB_MASK 0x1
#define PMIC_RG_STRUP_VIO18_PG_ENB_SHIFT   0
#define PMIC_RG_STRUP_VSRAM_PROC12_PG_ENB_ADDR   MT6358_STRUP_CON16
#define PMIC_RG_STRUP_VSRAM_PROC12_PG_ENB_MASK   0x1
#define PMIC_RG_STRUP_VSRAM_PROC12_PG_ENB_SHIFT  1
#define PMIC_RG_STRUP_VSRAM_PROC11_PG_ENB_ADDR   MT6358_STRUP_CON16
#define PMIC_RG_STRUP_VSRAM_PROC11_PG_ENB_MASK   0x1
#define PMIC_RG_STRUP_VSRAM_PROC11_PG_ENB_SHIFT  2
#define PMIC_RG_STRUP_VA12_PG_ENB_ADDR  MT6358_STRUP_CON16
#define PMIC_RG_STRUP_VA12_PG_ENB_MASK  0x1
#define PMIC_RG_STRUP_VA12_PG_ENB_SHIFT 3
#define PMIC_RG_STRUP_VSRAM_GPU_PG_ENB_ADDR MT6358_STRUP_CON16
#define PMIC_RG_STRUP_VSRAM_GPU_PG_ENB_MASK 0x1
#define PMIC_RG_STRUP_VSRAM_GPU_PG_ENB_SHIFT  4
#define PMIC_RG_STRUP_VSRAM_OTHERS_PG_ENB_ADDR   MT6358_STRUP_CON16
#define PMIC_RG_STRUP_VSRAM_OTHERS_PG_ENB_MASK   0x1
#define PMIC_RG_STRUP_VSRAM_OTHERS_PG_ENB_SHIFT  5
#define PMIC_RG_STRUP_VAUX18_PG_ENB_ADDR   MT6358_STRUP_CON16
#define PMIC_RG_STRUP_VAUX18_PG_ENB_MASK   0x1
#define PMIC_RG_STRUP_VAUX18_PG_ENB_SHIFT   6
#define PMIC_RG_STRUP_VXO22_PG_ENB_ADDR MT6358_STRUP_CON16
#define PMIC_RG_STRUP_VXO22_PG_ENB_MASK 0x1
#define PMIC_RG_STRUP_VXO22_PG_ENB_SHIFT   7
#define PMIC_RG_STRUP_VDRAM1_PG_ENB_ADDR   MT6358_STRUP_CON16
#define PMIC_RG_STRUP_VDRAM1_PG_ENB_MASK   0x1
#define PMIC_RG_STRUP_VDRAM1_PG_ENB_SHIFT   8
#define PMIC_RG_STRUP_VPROC12_PG_ENB_ADDR   MT6358_STRUP_CON16
#define PMIC_RG_STRUP_VPROC12_PG_ENB_MASK   0x1
#define PMIC_RG_STRUP_VPROC12_PG_ENB_SHIFT  9
#define PMIC_RG_STRUP_VPROC11_PG_ENB_ADDR   MT6358_STRUP_CON16
#define PMIC_RG_STRUP_VPROC11_PG_ENB_MASK   0x1
#define PMIC_RG_STRUP_VPROC11_PG_ENB_SHIFT  10
#define PMIC_RG_STRUP_VS1_PG_ENB_ADDR MT6358_STRUP_CON16
#define PMIC_RG_STRUP_VS1_PG_ENB_MASK 0x1
#define PMIC_RG_STRUP_VS1_PG_ENB_SHIFT  11
#define PMIC_RG_STRUP_VGPU_PG_ENB_ADDR  MT6358_STRUP_CON16
#define PMIC_RG_STRUP_VGPU_PG_ENB_MASK  0x1
#define PMIC_RG_STRUP_VGPU_PG_ENB_SHIFT 12
#define PMIC_RG_STRUP_VMODEM_PG_ENB_ADDR   MT6358_STRUP_CON16
#define PMIC_RG_STRUP_VMODEM_PG_ENB_MASK   0x1
#define PMIC_RG_STRUP_VMODEM_PG_ENB_SHIFT   13
#define PMIC_RG_STRUP_VCORE_PG_ENB_ADDR MT6358_STRUP_CON16
#define PMIC_RG_STRUP_VCORE_PG_ENB_MASK 0x1
#define PMIC_RG_STRUP_VCORE_PG_ENB_SHIFT   14
#define PMIC_RG_STRUP_VS2_PG_ENB_ADDR MT6358_STRUP_CON16
#define PMIC_RG_STRUP_VS2_PG_ENB_MASK 0x1
#define PMIC_RG_STRUP_VS2_PG_ENB_SHIFT  15
#define PMIC_RG_STRUP_RSV_PG_ENB_ADDR MT6358_STRUP_CON17
#define PMIC_RG_STRUP_RSV_PG_ENB_MASK 0x1
#define PMIC_RG_STRUP_RSV_PG_ENB_SHIFT  10
#define PMIC_RG_STRUP_VAUD28_PG_ENB_ADDR   MT6358_STRUP_CON17
#define PMIC_RG_STRUP_VAUD28_PG_ENB_MASK   0x1
#define PMIC_RG_STRUP_VAUD28_PG_ENB_SHIFT   11
#define PMIC_RG_STRUP_VUSB_PG_ENB_ADDR  MT6358_STRUP_CON17
#define PMIC_RG_STRUP_VUSB_PG_ENB_MASK  0x1
#define PMIC_RG_STRUP_VUSB_PG_ENB_SHIFT 12
#define PMIC_RG_STRUP_VDRAM2_PG_ENB_ADDR   MT6358_STRUP_CON17
#define PMIC_RG_STRUP_VDRAM2_PG_ENB_MASK   0x1
#define PMIC_RG_STRUP_VDRAM2_PG_ENB_SHIFT   13
#define PMIC_RG_STRUP_VIO28_PG_ENB_ADDR MT6358_STRUP_CON17
#define PMIC_RG_STRUP_VIO28_PG_ENB_MASK 0x1
#define PMIC_RG_STRUP_VIO28_PG_ENB_SHIFT   14
#define PMIC_RG_STRUP_VEMC_PG_ENB_ADDR  MT6358_STRUP_CON17
#define PMIC_RG_STRUP_VEMC_PG_ENB_MASK  0x1
#define PMIC_RG_STRUP_VEMC_PG_ENB_SHIFT 15
#define PMIC_RG_STRUP_VDRAM1_OC_ENB_ADDR   MT6358_STRUP_CON18
#define PMIC_RG_STRUP_VDRAM1_OC_ENB_MASK   0x1
#define PMIC_RG_STRUP_VDRAM1_OC_ENB_SHIFT   8
#define PMIC_RG_STRUP_VPROC12_OC_ENB_ADDR   MT6358_STRUP_CON18
#define PMIC_RG_STRUP_VPROC12_OC_ENB_MASK   0x1
#define PMIC_RG_STRUP_VPROC12_OC_ENB_SHIFT  9
#define PMIC_RG_STRUP_VPROC11_OC_ENB_ADDR   MT6358_STRUP_CON18
#define PMIC_RG_STRUP_VPROC11_OC_ENB_MASK   0x1
#define PMIC_RG_STRUP_VPROC11_OC_ENB_SHIFT  10
#define PMIC_RG_STRUP_VS1_OC_ENB_ADDR MT6358_STRUP_CON18
#define PMIC_RG_STRUP_VS1_OC_ENB_MASK 0x1
#define PMIC_RG_STRUP_VS1_OC_ENB_SHIFT  11
#define PMIC_RG_STRUP_VGPU_OC_ENB_ADDR  MT6358_STRUP_CON18
#define PMIC_RG_STRUP_VGPU_OC_ENB_MASK  0x1
#define PMIC_RG_STRUP_VGPU_OC_ENB_SHIFT 12
#define PMIC_RG_STRUP_VMODEM_OC_ENB_ADDR   MT6358_STRUP_CON18
#define PMIC_RG_STRUP_VMODEM_OC_ENB_MASK   0x1
#define PMIC_RG_STRUP_VMODEM_OC_ENB_SHIFT   13
#define PMIC_RG_STRUP_VCORE_OC_ENB_ADDR MT6358_STRUP_CON18
#define PMIC_RG_STRUP_VCORE_OC_ENB_MASK 0x1
#define PMIC_RG_STRUP_VCORE_OC_ENB_SHIFT   14
#define PMIC_RG_STRUP_VS2_OC_ENB_ADDR MT6358_STRUP_CON18
#define PMIC_RG_STRUP_VS2_OC_ENB_MASK 0x1
#define PMIC_RG_STRUP_VS2_OC_ENB_SHIFT  15
#define PMIC_PSEQ_ELR_LEN_ADDR  MT6358_PSEQ_ELR_NUM
#define PMIC_PSEQ_ELR_LEN_MASK  0xFF
#define PMIC_PSEQ_ELR_LEN_SHIFT 0
#define PMIC_RG_VXO22_USA_ADDR  MT6358_PSEQ_ELR0
#define PMIC_RG_VXO22_USA_MASK  0x1F
#define PMIC_RG_VXO22_USA_SHIFT 0
#define PMIC_RG_VAUX18_USA_ADDR MT6358_PSEQ_ELR0
#define PMIC_RG_VAUX18_USA_MASK 0x1F
#define PMIC_RG_VAUX18_USA_SHIFT  5
#define PMIC_RG_VS2_USA_ADDR MT6358_PSEQ_ELR0
#define PMIC_RG_VS2_USA_MASK 0x1F
#define PMIC_RG_VS2_USA_SHIFT   10
#define PMIC_RG_VCORE_USA_ADDR  MT6358_PSEQ_ELR1
#define PMIC_RG_VCORE_USA_MASK  0x1F
#define PMIC_RG_VCORE_USA_SHIFT 0
#define PMIC_RG_VMODEM_USA_ADDR MT6358_PSEQ_ELR1
#define PMIC_RG_VMODEM_USA_MASK 0x1F
#define PMIC_RG_VMODEM_USA_SHIFT  5
#define PMIC_RG_VGPU_USA_ADDR   MT6358_PSEQ_ELR1
#define PMIC_RG_VGPU_USA_MASK   0x1F
#define PMIC_RG_VGPU_USA_SHIFT  10
#define PMIC_RG_VSRAM_OTHERS_USA_ADDR MT6358_PSEQ_ELR2
#define PMIC_RG_VSRAM_OTHERS_USA_MASK 0x1F
#define PMIC_RG_VSRAM_OTHERS_USA_SHIFT  0
#define PMIC_RG_VSRAM_GPU_USA_ADDR MT6358_PSEQ_ELR2
#define PMIC_RG_VSRAM_GPU_USA_MASK 0x1F
#define PMIC_RG_VSRAM_GPU_USA_SHIFT   5
#define PMIC_RG_EXT_PMIC_2_USA_ADDR   MT6358_PSEQ_ELR2
#define PMIC_RG_EXT_PMIC_2_USA_MASK   0x1F
#define PMIC_RG_EXT_PMIC_2_USA_SHIFT  10
#define PMIC_RG_VS1_USA_ADDR MT6358_PSEQ_ELR3
#define PMIC_RG_VS1_USA_MASK 0x1F
#define PMIC_RG_VS1_USA_SHIFT   0
#define PMIC_RG_VA12_USA_ADDR   MT6358_PSEQ_ELR3
#define PMIC_RG_VA12_USA_MASK   0x1F
#define PMIC_RG_VA12_USA_SHIFT  5
#define PMIC_RG_VPROC11_USA_ADDR  MT6358_PSEQ_ELR3
#define PMIC_RG_VPROC11_USA_MASK  0x1F
#define PMIC_RG_VPROC11_USA_SHIFT 10
#define PMIC_RG_VPROC12_USA_ADDR  MT6358_PSEQ_ELR4
#define PMIC_RG_VPROC12_USA_MASK  0x1F
#define PMIC_RG_VPROC12_USA_SHIFT 0
#define PMIC_RG_VSRAM_PROC11_USA_ADDR MT6358_PSEQ_ELR4
#define PMIC_RG_VSRAM_PROC11_USA_MASK 0x1F
#define PMIC_RG_VSRAM_PROC11_USA_SHIFT  5
#define PMIC_RG_VSRAM_PROC12_USA_ADDR MT6358_PSEQ_ELR4
#define PMIC_RG_VSRAM_PROC12_USA_MASK 0x1F
#define PMIC_RG_VSRAM_PROC12_USA_SHIFT  10
#define PMIC_RG_VIO18_USA_ADDR  MT6358_PSEQ_ELR5
#define PMIC_RG_VIO18_USA_MASK  0x1F
#define PMIC_RG_VIO18_USA_SHIFT 0
#define PMIC_RG_VEMC_USA_ADDR   MT6358_PSEQ_ELR5
#define PMIC_RG_VEMC_USA_MASK   0x1F
#define PMIC_RG_VEMC_USA_SHIFT  5
#define PMIC_RG_EXT_PMIC_1_USA_ADDR   MT6358_PSEQ_ELR5
#define PMIC_RG_EXT_PMIC_1_USA_MASK   0x1F
#define PMIC_RG_EXT_PMIC_1_USA_SHIFT  10
#define PMIC_RG_VIO28_USA_ADDR  MT6358_PSEQ_ELR6
#define PMIC_RG_VIO28_USA_MASK  0x1F
#define PMIC_RG_VIO28_USA_SHIFT 0
#define PMIC_RG_VDRAM1_USA_ADDR MT6358_PSEQ_ELR6
#define PMIC_RG_VDRAM1_USA_MASK 0x1F
#define PMIC_RG_VDRAM1_USA_SHIFT  5
#define PMIC_RG_VDRAM2_USA_ADDR MT6358_PSEQ_ELR6
#define PMIC_RG_VDRAM2_USA_MASK 0x1F
#define PMIC_RG_VDRAM2_USA_SHIFT  10
#define PMIC_RG_VUSB_USA_ADDR   MT6358_PSEQ_ELR7
#define PMIC_RG_VUSB_USA_MASK   0x1F
#define PMIC_RG_VUSB_USA_SHIFT  0
#define PMIC_RG_VAUD28_USA_ADDR MT6358_PSEQ_ELR7
#define PMIC_RG_VAUD28_USA_MASK 0x1F
#define PMIC_RG_VAUD28_USA_SHIFT  5
#define PMIC_RG_RSV_USA_ADDR MT6358_PSEQ_ELR7
#define PMIC_RG_RSV_USA_MASK 0x1F
#define PMIC_RG_RSV_USA_SHIFT   10
#define PMIC_RG_BWDT_EN_ADDR MT6358_PSEQ_ELR10
#define PMIC_RG_BWDT_EN_MASK 0x1
#define PMIC_RG_BWDT_EN_SHIFT   0
#define PMIC_RG_BWDT_TSEL_ADDR  MT6358_PSEQ_ELR10
#define PMIC_RG_BWDT_TSEL_MASK  0x1
#define PMIC_RG_BWDT_TSEL_SHIFT 1
#define PMIC_RG_BWDT_CSEL_ADDR  MT6358_PSEQ_ELR10
#define PMIC_RG_BWDT_CSEL_MASK  0x1
#define PMIC_RG_BWDT_CSEL_SHIFT 2
#define PMIC_RG_BWDT_TD_ADDR MT6358_PSEQ_ELR10
#define PMIC_RG_BWDT_TD_MASK 0x3
#define PMIC_RG_BWDT_TD_SHIFT   3
#define PMIC_RG_BWDT_CHRTD_ADDR MT6358_PSEQ_ELR10
#define PMIC_RG_BWDT_CHRTD_MASK 0x1
#define PMIC_RG_BWDT_CHRTD_SHIFT  5
#define PMIC_RG_BWDT_DDLO_TD_ADDR MT6358_PSEQ_ELR10
#define PMIC_RG_BWDT_DDLO_TD_MASK 0x3
#define PMIC_RG_BWDT_DDLO_TD_SHIFT 6
#define PMIC_RG_BWDT_SRCSEL_ADDR  MT6358_PSEQ_ELR10
#define PMIC_RG_BWDT_SRCSEL_MASK  0x1
#define PMIC_RG_BWDT_SRCSEL_SHIFT 8
#define PMIC_RG_SLOT_INTV_UP_ADDR MT6358_PSEQ_ELR10
#define PMIC_RG_SLOT_INTV_UP_MASK 0x3
#define PMIC_RG_SLOT_INTV_UP_SHIFT 9
#define PMIC_RG_SEQ_LEN_ADDR MT6358_PSEQ_ELR10
#define PMIC_RG_SEQ_LEN_MASK 0x1F
#define PMIC_RG_SEQ_LEN_SHIFT   11
#define PMIC_RG_PSPG_SHDN_EN_ADDR MT6358_PSEQ_ELR11
#define PMIC_RG_PSPG_SHDN_EN_MASK 0x3
#define PMIC_RG_PSPG_SHDN_EN_SHIFT 0
#define PMIC_RG_RSTB_ONINTV_ADDR  MT6358_PSEQ_ELR11
#define PMIC_RG_RSTB_ONINTV_MASK  0x3
#define PMIC_RG_RSTB_ONINTV_SHIFT 2
#define PMIC_RG_PSEQ_F75K_FORCE_ADDR  MT6358_PSEQ_ELR11
#define PMIC_RG_PSEQ_F75K_FORCE_MASK  0x1
#define PMIC_RG_PSEQ_F75K_FORCE_SHIFT 4
#define PMIC_RG_PSEQ_1MS_TK_EXT_ADDR  MT6358_PSEQ_ELR11
#define PMIC_RG_PSEQ_1MS_TK_EXT_MASK  0x1
#define PMIC_RG_PSEQ_1MS_TK_EXT_SHIFT 5
#define PMIC_RG_SMPS_IVGEN_SEL_ADDR   MT6358_PSEQ_ELR11
#define PMIC_RG_SMPS_IVGEN_SEL_MASK   0x1
#define PMIC_RG_SMPS_IVGEN_SEL_SHIFT  6
#define PMIC_RG_STRUP_LONG_PRESS_RESET_EXTEND_ADDR  MT6358_PSEQ_ELR11
#define PMIC_RG_STRUP_LONG_PRESS_RESET_EXTEND_MASK  0x1
#define PMIC_RG_STRUP_LONG_PRESS_RESET_EXTEND_SHIFT 7
#define PMIC_RG_CPS_S0EXT_ENB_ADDR MT6358_PSEQ_ELR11
#define PMIC_RG_CPS_S0EXT_ENB_MASK 0x1
#define PMIC_RG_CPS_S0EXT_ENB_SHIFT   8
#define PMIC_RG_CPS_S0EXT_TD_ADDR MT6358_PSEQ_ELR11
#define PMIC_RG_CPS_S0EXT_TD_MASK 0x1
#define PMIC_RG_CPS_S0EXT_TD_SHIFT 9
#define PMIC_RG_SDN_DLY_ENB_ADDR  MT6358_PSEQ_ELR11
#define PMIC_RG_SDN_DLY_ENB_MASK  0x1
#define PMIC_RG_SDN_DLY_ENB_SHIFT 10
#define PMIC_RG_CHRDET_DEB_TD_ADDR MT6358_PSEQ_ELR11
#define PMIC_RG_CHRDET_DEB_TD_MASK 0x1
#define PMIC_RG_CHRDET_DEB_TD_SHIFT   11
#define PMIC_EFUSE_IVGEN_ENB_SEL_ADDR MT6358_PSEQ_ELR11
#define PMIC_EFUSE_IVGEN_ENB_SEL_MASK 0x1
#define PMIC_EFUSE_IVGEN_ENB_SEL_SHIFT  12
#define PMIC_RG_PWRKEY_EVENT_MODE_ADDR  MT6358_PSEQ_ELR11
#define PMIC_RG_PWRKEY_EVENT_MODE_MASK  0x1
#define PMIC_RG_PWRKEY_EVENT_MODE_SHIFT 13
#define PMIC_RG_PWRKEY_EVENT_MODE_HW_ADDR   MT6358_PSEQ_ELR11
#define PMIC_RG_PWRKEY_EVENT_MODE_HW_MASK   0x1
#define PMIC_RG_PWRKEY_EVENT_MODE_HW_SHIFT  14
#define PMIC_RG_LDO_PG_STB_MODE_ADDR  MT6358_PSEQ_ELR11
#define PMIC_RG_LDO_PG_STB_MODE_MASK  0x1
#define PMIC_RG_LDO_PG_STB_MODE_SHIFT 15
#define PMIC_CHRDET_ANA_ID_ADDR MT6358_CHRDET_ID
#define PMIC_CHRDET_ANA_ID_MASK 0xFF
#define PMIC_CHRDET_ANA_ID_SHIFT  0
#define PMIC_CHRDET_DIG_ID_ADDR MT6358_CHRDET_ID
#define PMIC_CHRDET_DIG_ID_MASK 0xFF
#define PMIC_CHRDET_DIG_ID_SHIFT  8
#define PMIC_CHRDET_ANA_MINOR_REV_ADDR  MT6358_CHRDET_REV0
#define PMIC_CHRDET_ANA_MINOR_REV_MASK  0xF
#define PMIC_CHRDET_ANA_MINOR_REV_SHIFT 0
#define PMIC_CHRDET_ANA_MAJOR_REV_ADDR  MT6358_CHRDET_REV0
#define PMIC_CHRDET_ANA_MAJOR_REV_MASK  0xF
#define PMIC_CHRDET_ANA_MAJOR_REV_SHIFT 4
#define PMIC_CHRDET_DIG_MINOR_REV_ADDR  MT6358_CHRDET_REV0
#define PMIC_CHRDET_DIG_MINOR_REV_MASK  0xF
#define PMIC_CHRDET_DIG_MINOR_REV_SHIFT 8
#define PMIC_CHRDET_DIG_MAJOR_REV_ADDR  MT6358_CHRDET_REV0
#define PMIC_CHRDET_DIG_MAJOR_REV_MASK  0xF
#define PMIC_CHRDET_DIG_MAJOR_REV_SHIFT 12
#define PMIC_CHRDET_CBS_ADDR MT6358_CHRDET_DBI
#define PMIC_CHRDET_CBS_MASK 0x3
#define PMIC_CHRDET_CBS_SHIFT   0
#define PMIC_CHRDET_BIX_ADDR MT6358_CHRDET_DBI
#define PMIC_CHRDET_BIX_MASK 0x3
#define PMIC_CHRDET_BIX_SHIFT   2
#define PMIC_CHRDET_ESP_ADDR MT6358_CHRDET_DBI
#define PMIC_CHRDET_ESP_MASK 0xFF
#define PMIC_CHRDET_ESP_SHIFT   8
#define PMIC_CHRDET_FPI_ADDR MT6358_CHRDET_DXI
#define PMIC_CHRDET_FPI_MASK 0xFF
#define PMIC_CHRDET_FPI_SHIFT   0
#define PMIC_RG_VCDT_RST_SEL_ADDR MT6358_CHR_CON0
#define PMIC_RG_VCDT_RST_SEL_MASK 0x1
#define PMIC_RG_VCDT_RST_SEL_SHIFT 0
#define PMIC_RG_VCDT_HV_EN_ADDR MT6358_CHR_CON0
#define PMIC_RG_VCDT_HV_EN_MASK 0x1
#define PMIC_RG_VCDT_HV_EN_SHIFT  1
#define PMIC_RG_VCDT_DEB_SEL_ADDR MT6358_CHR_CON0
#define PMIC_RG_VCDT_DEB_SEL_MASK 0x1
#define PMIC_RG_VCDT_DEB_SEL_SHIFT 2
#define PMIC_RG_PCHR_FT_CTRL_ADDR MT6358_CHR_CON0
#define PMIC_RG_PCHR_FT_CTRL_MASK 0x1
#define PMIC_RG_PCHR_FT_CTRL_SHIFT 4
#define PMIC_RGS_CHRDET_ADDR MT6358_CHR_CON0
#define PMIC_RGS_CHRDET_MASK 0x1
#define PMIC_RGS_CHRDET_SHIFT   5
#define PMIC_RGS_VCDT_LV_DET_ADDR MT6358_CHR_CON0
#define PMIC_RGS_VCDT_LV_DET_MASK 0x1
#define PMIC_RGS_VCDT_LV_DET_SHIFT 6
#define PMIC_RGS_VCDT_HV_DET_ADDR MT6358_CHR_CON0
#define PMIC_RGS_VCDT_HV_DET_MASK 0x1
#define PMIC_RGS_VCDT_HV_DET_SHIFT 7
#define PMIC_RG_VCDT_LV_VTH_ADDR  MT6358_CHR_CON1
#define PMIC_RG_VCDT_LV_VTH_MASK  0xF
#define PMIC_RG_VCDT_LV_VTH_SHIFT 0
#define PMIC_RG_VCDT_HV_VTH_ADDR  MT6358_CHR_CON1
#define PMIC_RG_VCDT_HV_VTH_MASK  0xF
#define PMIC_RG_VCDT_HV_VTH_SHIFT 4
#define PMIC_RGS_PCHR_FLAG_OUT_ADDR   MT6358_CHR_CON2
#define PMIC_RGS_PCHR_FLAG_OUT_MASK   0xF
#define PMIC_RGS_PCHR_FLAG_OUT_SHIFT  0
#define PMIC_RG_PCHR_FLAG_EN_ADDR MT6358_CHR_CON2
#define PMIC_RG_PCHR_FLAG_EN_MASK 0x1
#define PMIC_RG_PCHR_FLAG_EN_SHIFT 4
#define PMIC_RG_PCHR_FLAG_SEL_ADDR MT6358_CHR_CON3
#define PMIC_RG_PCHR_FLAG_SEL_MASK 0xF
#define PMIC_RG_PCHR_FLAG_SEL_SHIFT   0
#define PMIC_RG_ENVTEM_D_ADDR   MT6358_CHR_CON4
#define PMIC_RG_ENVTEM_D_MASK   0x1
#define PMIC_RG_ENVTEM_D_SHIFT  0
#define PMIC_RG_ENVTEM_EN_ADDR  MT6358_CHR_CON4
#define PMIC_RG_ENVTEM_EN_MASK  0x1
#define PMIC_RG_ENVTEM_EN_SHIFT 1
#define PMIC_DA_QI_BGR_EXT_BUF_EN_ADDR  MT6358_PCHR_VREF_ANA_DA0
#define PMIC_DA_QI_BGR_EXT_BUF_EN_MASK  0x1
#define PMIC_DA_QI_BGR_EXT_BUF_EN_SHIFT 1
#define PMIC_RG_BGR_TEST_RSTB_ADDR MT6358_PCHR_VREF_ANA_CON0
#define PMIC_RG_BGR_TEST_RSTB_MASK 0x1
#define PMIC_RG_BGR_TEST_RSTB_SHIFT   1
#define PMIC_RG_BGR_TEST_EN_ADDR  MT6358_PCHR_VREF_ANA_CON0
#define PMIC_RG_BGR_TEST_EN_MASK  0x1
#define PMIC_RG_BGR_TEST_EN_SHIFT 2
#define PMIC_RG_BGR_UNCHOP_ADDR MT6358_PCHR_VREF_ANA_CON1
#define PMIC_RG_BGR_UNCHOP_MASK 0x1
#define PMIC_RG_BGR_UNCHOP_SHIFT  1
#define PMIC_RG_BGR_UNCHOP_PH_ADDR MT6358_PCHR_VREF_ANA_CON1
#define PMIC_RG_BGR_UNCHOP_PH_MASK 0x1
#define PMIC_RG_BGR_UNCHOP_PH_SHIFT   2
#define PMIC_RG_OTG_BVALID_EN_ADDR MT6358_PCHR_VREF_ANA_CON1
#define PMIC_RG_OTG_BVALID_EN_MASK 0x1
#define PMIC_RG_OTG_BVALID_EN_SHIFT   8
#define PMIC_RG_UVLO_VTHL_ADDR  MT6358_PCHR_VREF_ANA_CON2
#define PMIC_RG_UVLO_VTHL_MASK  0x1F
#define PMIC_RG_UVLO_VTHL_SHIFT 0
#define PMIC_RG_LBAT_INT_VTH_ADDR MT6358_PCHR_VREF_ANA_CON2
#define PMIC_RG_LBAT_INT_VTH_MASK 0x1F
#define PMIC_RG_LBAT_INT_VTH_SHIFT 5
#define PMIC_RG_PCHR_RV_ADDR MT6358_PCHR_VREF_ANA_CON3
#define PMIC_RG_PCHR_RV_MASK 0xF
#define PMIC_RG_PCHR_RV_SHIFT   0
#define PMIC_RGS_OTG_BVALID_DET_ADDR  MT6358_PCHR_VREF_ANA_CON3
#define PMIC_RGS_OTG_BVALID_DET_MASK  0x1
#define PMIC_RGS_OTG_BVALID_DET_SHIFT 4
#define PMIC_RGS_CHR_LDO_DET_ADDR MT6358_PCHR_VREF_ANA_CON3
#define PMIC_RGS_CHR_LDO_DET_MASK 0x1
#define PMIC_RGS_CHR_LDO_DET_SHIFT 5
#define PMIC_RG_VCDT_UVLO_VTH_ADDR MT6358_PCHR_VREF_ANA_CON3
#define PMIC_RG_VCDT_UVLO_VTH_MASK 0xF
#define PMIC_RG_VCDT_UVLO_VTH_SHIFT   6
#define PMIC_CHRDET_ELR_LEN_ADDR  MT6358_PCHR_VREF_ELR_NUM
#define PMIC_CHRDET_ELR_LEN_MASK  0xFF
#define PMIC_CHRDET_ELR_LEN_SHIFT 0
#define PMIC_RG_VCDT_TRIM_ADDR  MT6358_PCHR_VREF_ELR_0
#define PMIC_RG_VCDT_TRIM_MASK  0xF
#define PMIC_RG_VCDT_TRIM_SHIFT 0
#define PMIC_RG_BGR_TRIM_ADDR   MT6358_PCHR_VREF_ELR_0
#define PMIC_RG_BGR_TRIM_MASK   0x1F
#define PMIC_RG_BGR_TRIM_SHIFT  8
#define PMIC_RG_BGR_RSEL_ADDR   MT6358_PCHR_VREF_ELR_1
#define PMIC_RG_BGR_RSEL_MASK   0xF
#define PMIC_RG_BGR_RSEL_SHIFT  0
#define PMIC_RG_BGR_TRIM_EN_ADDR  MT6358_PCHR_VREF_ELR_1
#define PMIC_RG_BGR_TRIM_EN_MASK  0x1
#define PMIC_RG_BGR_TRIM_EN_SHIFT 4
#define PMIC_BM_TOP_ANA_ID_ADDR MT6358_BM_TOP_DSN_ID
#define PMIC_BM_TOP_ANA_ID_MASK 0xFF
#define PMIC_BM_TOP_ANA_ID_SHIFT  0
#define PMIC_BM_TOP_DIG_ID_ADDR MT6358_BM_TOP_DSN_ID
#define PMIC_BM_TOP_DIG_ID_MASK 0xFF
#define PMIC_BM_TOP_DIG_ID_SHIFT  8
#define PMIC_BM_TOP_ANA_MINOR_REV_ADDR  MT6358_BM_TOP_DSN_REV0
#define PMIC_BM_TOP_ANA_MINOR_REV_MASK  0xF
#define PMIC_BM_TOP_ANA_MINOR_REV_SHIFT 0
#define PMIC_BM_TOP_ANA_MAJOR_REV_ADDR  MT6358_BM_TOP_DSN_REV0
#define PMIC_BM_TOP_ANA_MAJOR_REV_MASK  0xF
#define PMIC_BM_TOP_ANA_MAJOR_REV_SHIFT 4
#define PMIC_BM_TOP_DIG_MINOR_REV_ADDR  MT6358_BM_TOP_DSN_REV0
#define PMIC_BM_TOP_DIG_MINOR_REV_MASK  0xF
#define PMIC_BM_TOP_DIG_MINOR_REV_SHIFT 8
#define PMIC_BM_TOP_DIG_MAJOR_REV_ADDR  MT6358_BM_TOP_DSN_REV0
#define PMIC_BM_TOP_DIG_MAJOR_REV_MASK  0xF
#define PMIC_BM_TOP_DIG_MAJOR_REV_SHIFT 12
#define PMIC_BM_TOP_CBS_ADDR MT6358_BM_TOP_DBI
#define PMIC_BM_TOP_CBS_MASK 0x3
#define PMIC_BM_TOP_CBS_SHIFT   0
#define PMIC_BM_TOP_BIX_ADDR MT6358_BM_TOP_DBI
#define PMIC_BM_TOP_BIX_MASK 0x3
#define PMIC_BM_TOP_BIX_SHIFT   2
#define PMIC_BM_TOP_ESP_ADDR MT6358_BM_TOP_DBI
#define PMIC_BM_TOP_ESP_MASK 0xFF
#define PMIC_BM_TOP_ESP_SHIFT   8
#define PMIC_BM_TOP_FPI_ADDR MT6358_BM_TOP_DXI
#define PMIC_BM_TOP_FPI_MASK 0xFF
#define PMIC_BM_TOP_FPI_SHIFT   0
#define PMIC_BM_TOP_CLK_OFFSET_ADDR   MT6358_BM_TPM0
#define PMIC_BM_TOP_CLK_OFFSET_MASK   0xFF
#define PMIC_BM_TOP_CLK_OFFSET_SHIFT  0
#define PMIC_BM_TOP_RST_OFFSET_ADDR   MT6358_BM_TPM0
#define PMIC_BM_TOP_RST_OFFSET_MASK   0xFF
#define PMIC_BM_TOP_RST_OFFSET_SHIFT  8
#define PMIC_BM_TOP_INT_OFFSET_ADDR   MT6358_BM_TPM1
#define PMIC_BM_TOP_INT_OFFSET_MASK   0xFF
#define PMIC_BM_TOP_INT_OFFSET_SHIFT  0
#define PMIC_BM_TOP_INT_LEN_ADDR  MT6358_BM_TPM1
#define PMIC_BM_TOP_INT_LEN_MASK  0xFF
#define PMIC_BM_TOP_INT_LEN_SHIFT 8
#define PMIC_RG_BATON_32K_CK_PDN_ADDR MT6358_BM_TOP_CKPDN_CON0
#define PMIC_RG_BATON_32K_CK_PDN_MASK 0x1
#define PMIC_RG_BATON_32K_CK_PDN_SHIFT  0
#define PMIC_RG_BATON_1K_CK_PDN_ADDR  MT6358_BM_TOP_CKPDN_CON0
#define PMIC_RG_BATON_1K_CK_PDN_MASK  0x1
#define PMIC_RG_BATON_1K_CK_PDN_SHIFT 1
#define PMIC_RG_FGADC_FT_CK_PDN_ADDR  MT6358_BM_TOP_CKPDN_CON0
#define PMIC_RG_FGADC_FT_CK_PDN_MASK  0x1
#define PMIC_RG_FGADC_FT_CK_PDN_SHIFT 2
#define PMIC_RG_FGADC_DIG_CK_PDN_ADDR MT6358_BM_TOP_CKPDN_CON0
#define PMIC_RG_FGADC_DIG_CK_PDN_MASK 0x1
#define PMIC_RG_FGADC_DIG_CK_PDN_SHIFT  3
#define PMIC_RG_FGADC_ANA_CK_PDN_ADDR MT6358_BM_TOP_CKPDN_CON0
#define PMIC_RG_FGADC_ANA_CK_PDN_MASK 0x1
#define PMIC_RG_FGADC_ANA_CK_PDN_SHIFT  4
#define PMIC_RG_G_BIF_1M_CK_PDN_ADDR  MT6358_BM_TOP_CKPDN_CON0
#define PMIC_RG_G_BIF_1M_CK_PDN_MASK  0x1
#define PMIC_RG_G_BIF_1M_CK_PDN_SHIFT 5
#define PMIC_RG_BIF_X1_CK_PDN_ADDR MT6358_BM_TOP_CKPDN_CON0
#define PMIC_RG_BIF_X1_CK_PDN_MASK 0x1
#define PMIC_RG_BIF_X1_CK_PDN_SHIFT   6
#define PMIC_RG_BIF_X4_CK_PDN_ADDR MT6358_BM_TOP_CKPDN_CON0
#define PMIC_RG_BIF_X4_CK_PDN_MASK 0x1
#define PMIC_RG_BIF_X4_CK_PDN_SHIFT   7
#define PMIC_RG_BIF_X104_CK_PDN_ADDR  MT6358_BM_TOP_CKPDN_CON0
#define PMIC_RG_BIF_X104_CK_PDN_MASK  0x1
#define PMIC_RG_BIF_X104_CK_PDN_SHIFT 8
#define PMIC_RG_BM_INTRP_CK_PDN_ADDR  MT6358_BM_TOP_CKPDN_CON0
#define PMIC_RG_BM_INTRP_CK_PDN_MASK  0x1
#define PMIC_RG_BM_INTRP_CK_PDN_SHIFT 10
#define PMIC_RG_BM_TOP_CKPDN_CON0_RSV_ADDR  MT6358_BM_TOP_CKPDN_CON0
#define PMIC_RG_BM_TOP_CKPDN_CON0_RSV_MASK  0x3
#define PMIC_RG_BM_TOP_CKPDN_CON0_RSV_SHIFT 12
#define PMIC_BM_TOP_CKPDN_CON0_SET_ADDR MT6358_BM_TOP_CKPDN_CON0_SET
#define PMIC_BM_TOP_CKPDN_CON0_SET_MASK 0xFFFF
#define PMIC_BM_TOP_CKPDN_CON0_SET_SHIFT   0
#define PMIC_BM_TOP_CKPDN_CON0_CLR_ADDR MT6358_BM_TOP_CKPDN_CON0_CLR
#define PMIC_BM_TOP_CKPDN_CON0_CLR_MASK 0xFFFF
#define PMIC_BM_TOP_CKPDN_CON0_CLR_SHIFT   0
#define PMIC_RG_FGADC_ANA_CK_CKSEL_ADDR MT6358_BM_TOP_CKSEL_CON0
#define PMIC_RG_FGADC_ANA_CK_CKSEL_MASK 0x1
#define PMIC_RG_FGADC_ANA_CK_CKSEL_SHIFT   0
#define PMIC_BM_TOP_CKSEL_CON0_SET_ADDR MT6358_BM_TOP_CKSEL_CON0_SET
#define PMIC_BM_TOP_CKSEL_CON0_SET_MASK 0xFFFF
#define PMIC_BM_TOP_CKSEL_CON0_SET_SHIFT   0
#define PMIC_BM_TOP_CKSEL_CON0_CLR_ADDR MT6358_BM_TOP_CKSEL_CON0_CLR
#define PMIC_BM_TOP_CKSEL_CON0_CLR_MASK 0xFFFF
#define PMIC_BM_TOP_CKSEL_CON0_CLR_SHIFT   0
#define PMIC_RG_BIF_X4_CK_DIVSEL_ADDR MT6358_BM_TOP_CKDIVSEL_CON0
#define PMIC_RG_BIF_X4_CK_DIVSEL_MASK 0x7
#define PMIC_RG_BIF_X4_CK_DIVSEL_SHIFT  0
#define PMIC_BM_TOP_CKDIVSEL_CON0_RSV_ADDR  MT6358_BM_TOP_CKDIVSEL_CON0
#define PMIC_BM_TOP_CKDIVSEL_CON0_RSV_MASK  0x3
#define PMIC_BM_TOP_CKDIVSEL_CON0_RSV_SHIFT 3
#define PMIC_BM_TOP_CKDIVSEL_CON0_SET_ADDR  MT6358_BM_TOP_CKDIVSEL_CON0_SET
#define PMIC_BM_TOP_CKDIVSEL_CON0_SET_MASK  0xFFFF
#define PMIC_BM_TOP_CKDIVSEL_CON0_SET_SHIFT 0
#define PMIC_BM_TOP_CKDIVSEL_CON0_CLR_ADDR  MT6358_BM_TOP_CKDIVSEL_CON0_CLR
#define PMIC_BM_TOP_CKDIVSEL_CON0_CLR_MASK  0xFFFF
#define PMIC_BM_TOP_CKDIVSEL_CON0_CLR_SHIFT 0
#define PMIC_RG_BIF_X4_CK_PDN_HWEN_ADDR MT6358_BM_TOP_CKHWEN_CON0
#define PMIC_RG_BIF_X4_CK_PDN_HWEN_MASK 0x1
#define PMIC_RG_BIF_X4_CK_PDN_HWEN_SHIFT   0
#define PMIC_RG_BIF_X104_CK_PDN_HWEN_ADDR   MT6358_BM_TOP_CKHWEN_CON0
#define PMIC_RG_BIF_X104_CK_PDN_HWEN_MASK   0x1
#define PMIC_RG_BIF_X104_CK_PDN_HWEN_SHIFT  1
#define PMIC_RG_BM_INTRP_CK_PDN_HWEN_ADDR   MT6358_BM_TOP_CKHWEN_CON0
#define PMIC_RG_BM_INTRP_CK_PDN_HWEN_MASK   0x1
#define PMIC_RG_BM_INTRP_CK_PDN_HWEN_SHIFT  2
#define PMIC_BM_TOP_CKHWEN_CON0_RSV_ADDR   MT6358_BM_TOP_CKHWEN_CON0
#define PMIC_BM_TOP_CKHWEN_CON0_RSV_MASK   0x1
#define PMIC_BM_TOP_CKHWEN_CON0_RSV_SHIFT   3
#define PMIC_BM_TOP_CKHWEN_CON0_SET_ADDR   MT6358_BM_TOP_CKHWEN_CON0_SET
#define PMIC_BM_TOP_CKHWEN_CON0_SET_MASK   0xFFFF
#define PMIC_BM_TOP_CKHWEN_CON0_SET_SHIFT   0
#define PMIC_BM_TOP_CKHWEN_CON0_CLR_ADDR   MT6358_BM_TOP_CKHWEN_CON0_CLR
#define PMIC_BM_TOP_CKHWEN_CON0_CLR_MASK   0xFFFF
#define PMIC_BM_TOP_CKHWEN_CON0_CLR_SHIFT   0
#define PMIC_RG_FG_CK_TSTSEL_ADDR MT6358_BM_TOP_CKTST_CON0
#define PMIC_RG_FG_CK_TSTSEL_MASK 0x1
#define PMIC_RG_FG_CK_TSTSEL_SHIFT 0
#define PMIC_RG_FGADC_ANA_CK_TSTSEL_ADDR   MT6358_BM_TOP_CKTST_CON0
#define PMIC_RG_FGADC_ANA_CK_TSTSEL_MASK   0x1
#define PMIC_RG_FGADC_ANA_CK_TSTSEL_SHIFT   1
#define PMIC_RG_FG_CK_TST_DIS_ADDR MT6358_BM_TOP_CKTST_CON0
#define PMIC_RG_FG_CK_TST_DIS_MASK 0x1
#define PMIC_RG_FG_CK_TST_DIS_SHIFT   2
#define PMIC_RG_FGADC_SWRST_ADDR  MT6358_BM_TOP_RST_CON0
#define PMIC_RG_FGADC_SWRST_MASK  0x1
#define PMIC_RG_FGADC_SWRST_SHIFT 0
#define PMIC_RG_BATON_SWRST_ADDR  MT6358_BM_TOP_RST_CON0
#define PMIC_RG_BATON_SWRST_MASK  0x1
#define PMIC_RG_BATON_SWRST_SHIFT 1
#define PMIC_RG_BIF_SWRST_ADDR  MT6358_BM_TOP_RST_CON0
#define PMIC_RG_BIF_SWRST_MASK  0x1
#define PMIC_RG_BIF_SWRST_SHIFT 2
#define PMIC_RG_BANK_FGADC_ANA_SWRST_ADDR   MT6358_BM_TOP_RST_CON0
#define PMIC_RG_BANK_FGADC_ANA_SWRST_MASK   0x1
#define PMIC_RG_BANK_FGADC_ANA_SWRST_SHIFT  4
#define PMIC_RG_BANK_FGADC0_SWRST_ADDR  MT6358_BM_TOP_RST_CON0
#define PMIC_RG_BANK_FGADC0_SWRST_MASK  0x1
#define PMIC_RG_BANK_FGADC0_SWRST_SHIFT 5
#define PMIC_RG_BANK_FGADC1_SWRST_ADDR  MT6358_BM_TOP_RST_CON0
#define PMIC_RG_BANK_FGADC1_SWRST_MASK  0x1
#define PMIC_RG_BANK_FGADC1_SWRST_SHIFT 6
#define PMIC_RG_BANK_BATON_ANA_SWRST_ADDR   MT6358_BM_TOP_RST_CON0
#define PMIC_RG_BANK_BATON_ANA_SWRST_MASK   0x1
#define PMIC_RG_BANK_BATON_ANA_SWRST_SHIFT  7
#define PMIC_RG_BANK_BATON_SWRST_ADDR MT6358_BM_TOP_RST_CON0
#define PMIC_RG_BANK_BATON_SWRST_MASK 0x1
#define PMIC_RG_BANK_BATON_SWRST_SHIFT  8
#define PMIC_RG_BANK_BIF_SWRST_ADDR   MT6358_BM_TOP_RST_CON0
#define PMIC_RG_BANK_BIF_SWRST_MASK   0x1
#define PMIC_RG_BANK_BIF_SWRST_SHIFT  9
#define PMIC_BM_TOP_RST_CON0_SET_ADDR MT6358_BM_TOP_RST_CON0_SET
#define PMIC_BM_TOP_RST_CON0_SET_MASK 0xFFFF
#define PMIC_BM_TOP_RST_CON0_SET_SHIFT  0
#define PMIC_BM_TOP_RST_CON0_CLR_ADDR MT6358_BM_TOP_RST_CON0_CLR
#define PMIC_BM_TOP_RST_CON0_CLR_MASK 0xFFFF
#define PMIC_BM_TOP_RST_CON0_CLR_SHIFT  0
#define PMIC_RG_FGADC_RST_SRC_SEL_ADDR  MT6358_BM_TOP_RST_CON1
#define PMIC_RG_FGADC_RST_SRC_SEL_MASK  0x1
#define PMIC_RG_FGADC_RST_SRC_SEL_SHIFT 0
#define PMIC_BM_TOP_RST_CON1_RSV_ADDR MT6358_BM_TOP_RST_CON1
#define PMIC_BM_TOP_RST_CON1_RSV_MASK 0x1
#define PMIC_BM_TOP_RST_CON1_RSV_SHIFT  1
#define PMIC_BM_TOP_RST_CON1_SET_ADDR MT6358_BM_TOP_RST_CON1_SET
#define PMIC_BM_TOP_RST_CON1_SET_MASK 0xFFFF
#define PMIC_BM_TOP_RST_CON1_SET_SHIFT  0
#define PMIC_BM_TOP_RST_CON1_CLR_ADDR MT6358_BM_TOP_RST_CON1_CLR
#define PMIC_BM_TOP_RST_CON1_CLR_MASK 0xFFFF
#define PMIC_BM_TOP_RST_CON1_CLR_SHIFT  0
#define PMIC_RG_INT_EN_FG_BAT0_H_ADDR MT6358_BM_TOP_INT_CON0
#define PMIC_RG_INT_EN_FG_BAT0_H_MASK 0x1
#define PMIC_RG_INT_EN_FG_BAT0_H_SHIFT  0
#define PMIC_RG_INT_EN_FG_BAT0_L_ADDR MT6358_BM_TOP_INT_CON0
#define PMIC_RG_INT_EN_FG_BAT0_L_MASK 0x1
#define PMIC_RG_INT_EN_FG_BAT0_L_SHIFT  1
#define PMIC_RG_INT_EN_FG_CUR_H_ADDR  MT6358_BM_TOP_INT_CON0
#define PMIC_RG_INT_EN_FG_CUR_H_MASK  0x1
#define PMIC_RG_INT_EN_FG_CUR_H_SHIFT 2
#define PMIC_RG_INT_EN_FG_CUR_L_ADDR  MT6358_BM_TOP_INT_CON0
#define PMIC_RG_INT_EN_FG_CUR_L_MASK  0x1
#define PMIC_RG_INT_EN_FG_CUR_L_SHIFT 3
#define PMIC_RG_INT_EN_FG_ZCV_ADDR MT6358_BM_TOP_INT_CON0
#define PMIC_RG_INT_EN_FG_ZCV_MASK 0x1
#define PMIC_RG_INT_EN_FG_ZCV_SHIFT   4
#define PMIC_RG_INT_EN_FG_BAT1_H_ADDR MT6358_BM_TOP_INT_CON0
#define PMIC_RG_INT_EN_FG_BAT1_H_MASK 0x1
#define PMIC_RG_INT_EN_FG_BAT1_H_SHIFT  5
#define PMIC_RG_INT_EN_FG_BAT1_L_ADDR MT6358_BM_TOP_INT_CON0
#define PMIC_RG_INT_EN_FG_BAT1_L_MASK 0x1
#define PMIC_RG_INT_EN_FG_BAT1_L_SHIFT  6
#define PMIC_RG_INT_EN_FG_N_CHARGE_L_ADDR   MT6358_BM_TOP_INT_CON0
#define PMIC_RG_INT_EN_FG_N_CHARGE_L_MASK   0x1
#define PMIC_RG_INT_EN_FG_N_CHARGE_L_SHIFT  7
#define PMIC_RG_INT_EN_FG_IAVG_H_ADDR MT6358_BM_TOP_INT_CON0
#define PMIC_RG_INT_EN_FG_IAVG_H_MASK 0x1
#define PMIC_RG_INT_EN_FG_IAVG_H_SHIFT  8
#define PMIC_RG_INT_EN_FG_IAVG_L_ADDR MT6358_BM_TOP_INT_CON0
#define PMIC_RG_INT_EN_FG_IAVG_L_MASK 0x1
#define PMIC_RG_INT_EN_FG_IAVG_L_SHIFT  9
#define PMIC_RG_INT_EN_FG_TIME_H_ADDR MT6358_BM_TOP_INT_CON0
#define PMIC_RG_INT_EN_FG_TIME_H_MASK 0x1
#define PMIC_RG_INT_EN_FG_TIME_H_SHIFT  10
#define PMIC_RG_INT_EN_FG_DISCHARGE_ADDR   MT6358_BM_TOP_INT_CON0
#define PMIC_RG_INT_EN_FG_DISCHARGE_MASK   0x1
#define PMIC_RG_INT_EN_FG_DISCHARGE_SHIFT   11
#define PMIC_RG_INT_EN_FG_CHARGE_ADDR MT6358_BM_TOP_INT_CON0
#define PMIC_RG_INT_EN_FG_CHARGE_MASK 0x1
#define PMIC_RG_INT_EN_FG_CHARGE_SHIFT  12
#define PMIC_RG_BM_INT_EN_CON0_RSV_ADDR MT6358_BM_TOP_INT_CON0
#define PMIC_RG_BM_INT_EN_CON0_RSV_MASK 0x1
#define PMIC_RG_BM_INT_EN_CON0_RSV_SHIFT   13
#define PMIC_BM_TOP_INT_CON0_SET_ADDR MT6358_BM_TOP_INT_CON0_SET
#define PMIC_BM_TOP_INT_CON0_SET_MASK 0xFFFF
#define PMIC_BM_TOP_INT_CON0_SET_SHIFT  0
#define PMIC_BM_TOP_INT_CON0_CLR_ADDR MT6358_BM_TOP_INT_CON0_CLR
#define PMIC_BM_TOP_INT_CON0_CLR_MASK 0xFFFF
#define PMIC_BM_TOP_INT_CON0_CLR_SHIFT  0
#define PMIC_RG_INT_EN_BATON_LV_ADDR  MT6358_BM_TOP_INT_CON1
#define PMIC_RG_INT_EN_BATON_LV_MASK  0x1
#define PMIC_RG_INT_EN_BATON_LV_SHIFT 0
#define PMIC_RG_INT_EN_BATON_HT_ADDR  MT6358_BM_TOP_INT_CON1
#define PMIC_RG_INT_EN_BATON_HT_MASK  0x1
#define PMIC_RG_INT_EN_BATON_HT_SHIFT 1
#define PMIC_RG_INT_EN_BATON_BAT_IN_ADDR   MT6358_BM_TOP_INT_CON1
#define PMIC_RG_INT_EN_BATON_BAT_IN_MASK   0x1
#define PMIC_RG_INT_EN_BATON_BAT_IN_SHIFT   2
#define PMIC_RG_INT_EN_BATON_BAT_OUT_ADDR   MT6358_BM_TOP_INT_CON1
#define PMIC_RG_INT_EN_BATON_BAT_OUT_MASK   0x1
#define PMIC_RG_INT_EN_BATON_BAT_OUT_SHIFT  3
#define PMIC_RG_INT_EN_BIF_ADDR MT6358_BM_TOP_INT_CON1
#define PMIC_RG_INT_EN_BIF_MASK 0x1
#define PMIC_RG_INT_EN_BIF_SHIFT  4
#define PMIC_BM_TOP_INT_CON1_SET_ADDR MT6358_BM_TOP_INT_CON1_SET
#define PMIC_BM_TOP_INT_CON1_SET_MASK 0xFFFF
#define PMIC_BM_TOP_INT_CON1_SET_SHIFT  0
#define PMIC_BM_TOP_INT_CON1_CLR_ADDR MT6358_BM_TOP_INT_CON1_CLR
#define PMIC_BM_TOP_INT_CON1_CLR_MASK 0xFFFF
#define PMIC_BM_TOP_INT_CON1_CLR_SHIFT  0
#define PMIC_RG_INT_MASK_FG_BAT0_H_ADDR MT6358_BM_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_FG_BAT0_H_MASK 0x1
#define PMIC_RG_INT_MASK_FG_BAT0_H_SHIFT   0
#define PMIC_RG_INT_MASK_FG_BAT0_L_ADDR MT6358_BM_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_FG_BAT0_L_MASK 0x1
#define PMIC_RG_INT_MASK_FG_BAT0_L_SHIFT   1
#define PMIC_RG_INT_MASK_FG_CUR_H_ADDR  MT6358_BM_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_FG_CUR_H_MASK  0x1
#define PMIC_RG_INT_MASK_FG_CUR_H_SHIFT 2
#define PMIC_RG_INT_MASK_FG_CUR_L_ADDR  MT6358_BM_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_FG_CUR_L_MASK  0x1
#define PMIC_RG_INT_MASK_FG_CUR_L_SHIFT 3
#define PMIC_RG_INT_MASK_FG_ZCV_ADDR  MT6358_BM_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_FG_ZCV_MASK  0x1
#define PMIC_RG_INT_MASK_FG_ZCV_SHIFT 4
#define PMIC_RG_INT_MASK_FG_BAT1_H_ADDR MT6358_BM_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_FG_BAT1_H_MASK 0x1
#define PMIC_RG_INT_MASK_FG_BAT1_H_SHIFT   5
#define PMIC_RG_INT_MASK_FG_BAT1_L_ADDR MT6358_BM_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_FG_BAT1_L_MASK 0x1
#define PMIC_RG_INT_MASK_FG_BAT1_L_SHIFT   6
#define PMIC_RG_INT_MASK_FG_N_CHARGE_L_ADDR MT6358_BM_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_FG_N_CHARGE_L_MASK 0x1
#define PMIC_RG_INT_MASK_FG_N_CHARGE_L_SHIFT  7
#define PMIC_RG_INT_MASK_FG_IAVG_H_ADDR MT6358_BM_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_FG_IAVG_H_MASK 0x1
#define PMIC_RG_INT_MASK_FG_IAVG_H_SHIFT   8
#define PMIC_RG_INT_MASK_FG_IAVG_L_ADDR MT6358_BM_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_FG_IAVG_L_MASK 0x1
#define PMIC_RG_INT_MASK_FG_IAVG_L_SHIFT   9
#define PMIC_RG_INT_MASK_FG_TIME_H_ADDR MT6358_BM_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_FG_TIME_H_MASK 0x1
#define PMIC_RG_INT_MASK_FG_TIME_H_SHIFT   10
#define PMIC_RG_INT_MASK_FG_DISCHARGE_ADDR  MT6358_BM_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_FG_DISCHARGE_MASK  0x1
#define PMIC_RG_INT_MASK_FG_DISCHARGE_SHIFT 11
#define PMIC_RG_INT_MASK_FG_CHARGE_ADDR MT6358_BM_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_FG_CHARGE_MASK 0x1
#define PMIC_RG_INT_MASK_FG_CHARGE_SHIFT   12
#define PMIC_RG_BM_INT_MASK_CON0_RSV_ADDR   MT6358_BM_TOP_INT_MASK_CON0
#define PMIC_RG_BM_INT_MASK_CON0_RSV_MASK   0x1
#define PMIC_RG_BM_INT_MASK_CON0_RSV_SHIFT  13
#define PMIC_BM_TOP_INT_MASK_CON0_SET_ADDR  MT6358_BM_TOP_INT_MASK_CON0_SET
#define PMIC_BM_TOP_INT_MASK_CON0_SET_MASK  0xFFFF
#define PMIC_BM_TOP_INT_MASK_CON0_SET_SHIFT 0
#define PMIC_BM_TOP_INT_MASK_CON0_CLR_ADDR  MT6358_BM_TOP_INT_MASK_CON0_CLR
#define PMIC_BM_TOP_INT_MASK_CON0_CLR_MASK  0xFFFF
#define PMIC_BM_TOP_INT_MASK_CON0_CLR_SHIFT 0
#define PMIC_RG_INT_MASK_BATON_LV_ADDR  MT6358_BM_TOP_INT_MASK_CON1
#define PMIC_RG_INT_MASK_BATON_LV_MASK  0x1
#define PMIC_RG_INT_MASK_BATON_LV_SHIFT 0
#define PMIC_RG_INT_MASK_BATON_HT_ADDR  MT6358_BM_TOP_INT_MASK_CON1
#define PMIC_RG_INT_MASK_BATON_HT_MASK  0x1
#define PMIC_RG_INT_MASK_BATON_HT_SHIFT 1
#define PMIC_RG_INT_MASK_BATON_BAT_IN_ADDR  MT6358_BM_TOP_INT_MASK_CON1
#define PMIC_RG_INT_MASK_BATON_BAT_IN_MASK  0x1
#define PMIC_RG_INT_MASK_BATON_BAT_IN_SHIFT 2
#define PMIC_RG_INT_MASK_BATON_BAT_OUT_ADDR MT6358_BM_TOP_INT_MASK_CON1
#define PMIC_RG_INT_MASK_BATON_BAT_OUT_MASK 0x1
#define PMIC_RG_INT_MASK_BATON_BAT_OUT_SHIFT  3
#define PMIC_RG_INT_MASK_BIF_ADDR MT6358_BM_TOP_INT_MASK_CON1
#define PMIC_RG_INT_MASK_BIF_MASK 0x1
#define PMIC_RG_INT_MASK_BIF_SHIFT 4
#define PMIC_BM_TOP_INT_MASK_CON1_SET_ADDR  MT6358_BM_TOP_INT_MASK_CON1_SET
#define PMIC_BM_TOP_INT_MASK_CON1_SET_MASK  0xFFFF
#define PMIC_BM_TOP_INT_MASK_CON1_SET_SHIFT 0
#define PMIC_BM_TOP_INT_MASK_CON1_CLR_ADDR  MT6358_BM_TOP_INT_MASK_CON1_CLR
#define PMIC_BM_TOP_INT_MASK_CON1_CLR_MASK  0xFFFF
#define PMIC_BM_TOP_INT_MASK_CON1_CLR_SHIFT 0
#define PMIC_RG_INT_STATUS_FG_BAT0_H_ADDR   MT6358_BM_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_FG_BAT0_H_MASK   0x1
#define PMIC_RG_INT_STATUS_FG_BAT0_H_SHIFT  0
#define PMIC_RG_INT_STATUS_FG_BAT0_L_ADDR   MT6358_BM_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_FG_BAT0_L_MASK   0x1
#define PMIC_RG_INT_STATUS_FG_BAT0_L_SHIFT  1
#define PMIC_RG_INT_STATUS_FG_CUR_H_ADDR   MT6358_BM_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_FG_CUR_H_MASK   0x1
#define PMIC_RG_INT_STATUS_FG_CUR_H_SHIFT   2
#define PMIC_RG_INT_STATUS_FG_CUR_L_ADDR   MT6358_BM_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_FG_CUR_L_MASK   0x1
#define PMIC_RG_INT_STATUS_FG_CUR_L_SHIFT   3
#define PMIC_RG_INT_STATUS_FG_ZCV_ADDR  MT6358_BM_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_FG_ZCV_MASK  0x1
#define PMIC_RG_INT_STATUS_FG_ZCV_SHIFT 4
#define PMIC_RG_INT_STATUS_FG_BAT1_H_ADDR   MT6358_BM_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_FG_BAT1_H_MASK   0x1
#define PMIC_RG_INT_STATUS_FG_BAT1_H_SHIFT  5
#define PMIC_RG_INT_STATUS_FG_BAT1_L_ADDR   MT6358_BM_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_FG_BAT1_L_MASK   0x1
#define PMIC_RG_INT_STATUS_FG_BAT1_L_SHIFT  6
#define PMIC_RG_INT_STATUS_FG_N_CHARGE_L_ADDR MT6358_BM_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_FG_N_CHARGE_L_MASK 0x1
#define PMIC_RG_INT_STATUS_FG_N_CHARGE_L_SHIFT   7
#define PMIC_RG_INT_STATUS_FG_IAVG_H_ADDR   MT6358_BM_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_FG_IAVG_H_MASK   0x1
#define PMIC_RG_INT_STATUS_FG_IAVG_H_SHIFT  8
#define PMIC_RG_INT_STATUS_FG_IAVG_L_ADDR   MT6358_BM_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_FG_IAVG_L_MASK   0x1
#define PMIC_RG_INT_STATUS_FG_IAVG_L_SHIFT  9
#define PMIC_RG_INT_STATUS_FG_TIME_H_ADDR   MT6358_BM_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_FG_TIME_H_MASK   0x1
#define PMIC_RG_INT_STATUS_FG_TIME_H_SHIFT  10
#define PMIC_RG_INT_STATUS_FG_DISCHARGE_ADDR  MT6358_BM_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_FG_DISCHARGE_MASK  0x1
#define PMIC_RG_INT_STATUS_FG_DISCHARGE_SHIFT 11
#define PMIC_RG_INT_STATUS_FG_CHARGE_ADDR   MT6358_BM_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_FG_CHARGE_MASK   0x1
#define PMIC_RG_INT_STATUS_FG_CHARGE_SHIFT  12
#define PMIC_RG_BM_INT_STATUS0_RSV_ADDR MT6358_BM_TOP_INT_STATUS0
#define PMIC_RG_BM_INT_STATUS0_RSV_MASK 0x1
#define PMIC_RG_BM_INT_STATUS0_RSV_SHIFT   13
#define PMIC_RG_INT_STATUS_BATON_LV_ADDR   MT6358_BM_TOP_INT_STATUS1
#define PMIC_RG_INT_STATUS_BATON_LV_MASK   0x1
#define PMIC_RG_INT_STATUS_BATON_LV_SHIFT   0
#define PMIC_RG_INT_STATUS_BATON_HT_ADDR   MT6358_BM_TOP_INT_STATUS1
#define PMIC_RG_INT_STATUS_BATON_HT_MASK   0x1
#define PMIC_RG_INT_STATUS_BATON_HT_SHIFT   1
#define PMIC_RG_INT_STATUS_BATON_BAT_IN_ADDR  MT6358_BM_TOP_INT_STATUS1
#define PMIC_RG_INT_STATUS_BATON_BAT_IN_MASK  0x1
#define PMIC_RG_INT_STATUS_BATON_BAT_IN_SHIFT 2
#define PMIC_RG_INT_STATUS_BATON_BAT_OUT_ADDR MT6358_BM_TOP_INT_STATUS1
#define PMIC_RG_INT_STATUS_BATON_BAT_OUT_MASK 0x1
#define PMIC_RG_INT_STATUS_BATON_BAT_OUT_SHIFT   3
#define PMIC_RG_INT_STATUS_BIF_ADDR   MT6358_BM_TOP_INT_STATUS1
#define PMIC_RG_INT_STATUS_BIF_MASK   0x1
#define PMIC_RG_INT_STATUS_BIF_SHIFT  4
#define PMIC_RG_INT_RAW_STATUS_FG_BAT0_H_ADDR MT6358_BM_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_FG_BAT0_H_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_FG_BAT0_H_SHIFT   0
#define PMIC_RG_INT_RAW_STATUS_FG_BAT0_L_ADDR MT6358_BM_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_FG_BAT0_L_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_FG_BAT0_L_SHIFT   1
#define PMIC_RG_INT_RAW_STATUS_FG_CUR_H_ADDR  MT6358_BM_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_FG_CUR_H_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_FG_CUR_H_SHIFT 2
#define PMIC_RG_INT_RAW_STATUS_FG_CUR_L_ADDR  MT6358_BM_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_FG_CUR_L_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_FG_CUR_L_SHIFT 3
#define PMIC_RG_INT_RAW_STATUS_FG_ZCV_ADDR  MT6358_BM_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_FG_ZCV_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_FG_ZCV_SHIFT 4
#define PMIC_RG_INT_RAW_STATUS_FG_BAT1_H_ADDR MT6358_BM_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_FG_BAT1_H_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_FG_BAT1_H_SHIFT   5
#define PMIC_RG_INT_RAW_STATUS_FG_BAT1_L_ADDR MT6358_BM_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_FG_BAT1_L_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_FG_BAT1_L_SHIFT   6
#define PMIC_RG_INT_RAW_STATUS_FG_N_CHARGE_L_ADDR MT6358_BM_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_FG_N_CHARGE_L_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_FG_N_CHARGE_L_SHIFT  7
#define PMIC_RG_INT_RAW_STATUS_FG_IAVG_H_ADDR MT6358_BM_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_FG_IAVG_H_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_FG_IAVG_H_SHIFT   8
#define PMIC_RG_INT_RAW_STATUS_FG_IAVG_L_ADDR MT6358_BM_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_FG_IAVG_L_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_FG_IAVG_L_SHIFT   9
#define PMIC_RG_INT_RAW_STATUS_FG_TIME_H_ADDR MT6358_BM_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_FG_TIME_H_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_FG_TIME_H_SHIFT   10
#define PMIC_RG_INT_RAW_STATUS_FG_DISCHARGE_ADDR  MT6358_BM_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_FG_DISCHARGE_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_FG_DISCHARGE_SHIFT 11
#define PMIC_RG_INT_RAW_STATUS_FG_CHARGE_ADDR MT6358_BM_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_FG_CHARGE_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_FG_CHARGE_SHIFT   12
#define PMIC_RG_BM_INT_RAW_STATUS_RSV_ADDR  MT6358_BM_TOP_INT_RAW_STATUS0
#define PMIC_RG_BM_INT_RAW_STATUS_RSV_MASK  0x1
#define PMIC_RG_BM_INT_RAW_STATUS_RSV_SHIFT 13
#define PMIC_RG_INT_RAW_STATUS_BATON_LV_ADDR  MT6358_BM_TOP_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_BATON_LV_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_BATON_LV_SHIFT 0
#define PMIC_RG_INT_RAW_STATUS_BATON_HT_ADDR  MT6358_BM_TOP_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_BATON_HT_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_BATON_HT_SHIFT 1
#define PMIC_RG_INT_RAW_STATUS_BATON_BAT_IN_ADDR  MT6358_BM_TOP_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_BATON_BAT_IN_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_BATON_BAT_IN_SHIFT 2
#define PMIC_RG_INT_RAW_STATUS_BATON_BAT_OUT_ADDR MT6358_BM_TOP_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_BATON_BAT_OUT_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_BATON_BAT_OUT_SHIFT  3
#define PMIC_RG_INT_RAW_STATUS_BIF_ADDR MT6358_BM_TOP_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_BIF_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_BIF_SHIFT   4
#define PMIC_POLARITY_ADDR  MT6358_BM_TOP_INT_MISC_CON
#define PMIC_POLARITY_MASK  0x1
#define PMIC_POLARITY_SHIFT  0
#define PMIC_RG_BM_MON_FLAG_SEL_ADDR  MT6358_BM_TOP_DBG_CON
#define PMIC_RG_BM_MON_FLAG_SEL_MASK  0xFF
#define PMIC_RG_BM_MON_FLAG_SEL_SHIFT 0
#define PMIC_RG_BM_MON_GRP_SEL_ADDR   MT6358_BM_TOP_DBG_CON
#define PMIC_RG_BM_MON_GRP_SEL_MASK   0x7
#define PMIC_RG_BM_MON_GRP_SEL_SHIFT  8
#define PMIC_RG_BM_TOP_RSV0_ADDR  MT6358_BM_TOP_RSV0
#define PMIC_RG_BM_TOP_RSV0_MASK  0x3
#define PMIC_RG_BM_TOP_RSV0_SHIFT 0
#define PMIC_FGADC_ANA_ANA_ID_ADDR MT6358_FGADC_ANA_DSN_ID
#define PMIC_FGADC_ANA_ANA_ID_MASK 0xFF
#define PMIC_FGADC_ANA_ANA_ID_SHIFT   0
#define PMIC_FGADC_ANA_DIG_ID_ADDR MT6358_FGADC_ANA_DSN_ID
#define PMIC_FGADC_ANA_DIG_ID_MASK 0xFF
#define PMIC_FGADC_ANA_DIG_ID_SHIFT   8
#define PMIC_FGADC_ANA_ANA_MINOR_REV_ADDR   MT6358_FGADC_ANA_DSN_REV0
#define PMIC_FGADC_ANA_ANA_MINOR_REV_MASK   0xF
#define PMIC_FGADC_ANA_ANA_MINOR_REV_SHIFT  0
#define PMIC_FGADC_ANA_ANA_MAJOR_REV_ADDR   MT6358_FGADC_ANA_DSN_REV0
#define PMIC_FGADC_ANA_ANA_MAJOR_REV_MASK   0xF
#define PMIC_FGADC_ANA_ANA_MAJOR_REV_SHIFT  4
#define PMIC_FGADC_ANA_DIG_MINOR_REV_ADDR   MT6358_FGADC_ANA_DSN_REV0
#define PMIC_FGADC_ANA_DIG_MINOR_REV_MASK   0xF
#define PMIC_FGADC_ANA_DIG_MINOR_REV_SHIFT  8
#define PMIC_FGADC_ANA_DIG_MAJOR_REV_ADDR   MT6358_FGADC_ANA_DSN_REV0
#define PMIC_FGADC_ANA_DIG_MAJOR_REV_MASK   0xF
#define PMIC_FGADC_ANA_DIG_MAJOR_REV_SHIFT  12
#define PMIC_FGADC_ANA_DSN_CBS_ADDR   MT6358_FGADC_ANA_DSN_DBI
#define PMIC_FGADC_ANA_DSN_CBS_MASK   0x3
#define PMIC_FGADC_ANA_DSN_CBS_SHIFT  0
#define PMIC_FGADC_ANA_DSN_BIX_ADDR   MT6358_FGADC_ANA_DSN_DBI
#define PMIC_FGADC_ANA_DSN_BIX_MASK   0x3
#define PMIC_FGADC_ANA_DSN_BIX_SHIFT  2
#define PMIC_FGADC_ANA_DSN_ESP_ADDR   MT6358_FGADC_ANA_DSN_DBI
#define PMIC_FGADC_ANA_DSN_ESP_MASK   0xFF
#define PMIC_FGADC_ANA_DSN_ESP_SHIFT  8
#define PMIC_FGADC_ANA_DSN_FPI_ADDR   MT6358_FGADC_ANA_DSN_DXI
#define PMIC_FGADC_ANA_DSN_FPI_MASK   0xFF
#define PMIC_FGADC_ANA_DSN_FPI_SHIFT  0
#define PMIC_RG_FGANALOGTEST_ADDR MT6358_FGADC_ANA_CON0
#define PMIC_RG_FGANALOGTEST_MASK 0x7
#define PMIC_RG_FGANALOGTEST_SHIFT 0
#define PMIC_RG_FGINTMODE_ADDR  MT6358_FGADC_ANA_CON0
#define PMIC_RG_FGINTMODE_MASK  0x1
#define PMIC_RG_FGINTMODE_SHIFT 4
#define PMIC_RG_SPARE_ADDR  MT6358_FGADC_ANA_CON0
#define PMIC_RG_SPARE_MASK  0xFF
#define PMIC_RG_SPARE_SHIFT  5
#define PMIC_FG_RNG_BIT_MODE_ADDR MT6358_FGADC_ANA_TEST_CON0
#define PMIC_FG_RNG_BIT_MODE_MASK 0x1
#define PMIC_FG_RNG_BIT_MODE_SHIFT 0
#define PMIC_FG_RNG_BIT_SW_ADDR MT6358_FGADC_ANA_TEST_CON0
#define PMIC_FG_RNG_BIT_SW_MASK 0x1
#define PMIC_FG_RNG_BIT_SW_SHIFT  1
#define PMIC_FG_RNG_EN_MODE_ADDR  MT6358_FGADC_ANA_TEST_CON0
#define PMIC_FG_RNG_EN_MODE_MASK  0x1
#define PMIC_FG_RNG_EN_MODE_SHIFT 2
#define PMIC_FG_RNG_EN_SW_ADDR  MT6358_FGADC_ANA_TEST_CON0
#define PMIC_FG_RNG_EN_SW_MASK  0x1
#define PMIC_FG_RNG_EN_SW_SHIFT 3
#define PMIC_DA_FG_RNG_EN_ADDR  MT6358_FGADC_ANA_TEST_CON0
#define PMIC_DA_FG_RNG_EN_MASK  0x1
#define PMIC_DA_FG_RNG_EN_SHIFT 6
#define PMIC_DA_FG_RNG_BIT_ADDR MT6358_FGADC_ANA_TEST_CON0
#define PMIC_DA_FG_RNG_BIT_MASK 0x1
#define PMIC_DA_FG_RNG_BIT_SHIFT  7
#define PMIC_FG_DWA_T0_ADDR  MT6358_FGADC_ANA_TEST_CON0
#define PMIC_FG_DWA_T0_MASK  0x3
#define PMIC_FG_DWA_T0_SHIFT 8
#define PMIC_FG_DWA_T1_ADDR  MT6358_FGADC_ANA_TEST_CON0
#define PMIC_FG_DWA_T1_MASK  0x3
#define PMIC_FG_DWA_T1_SHIFT 10
#define PMIC_FG_DWA_RST_MODE_ADDR MT6358_FGADC_ANA_TEST_CON0
#define PMIC_FG_DWA_RST_MODE_MASK 0x1
#define PMIC_FG_DWA_RST_MODE_SHIFT 12
#define PMIC_FG_DWA_RST_SW_ADDR MT6358_FGADC_ANA_TEST_CON0
#define PMIC_FG_DWA_RST_SW_MASK 0x1
#define PMIC_FG_DWA_RST_SW_SHIFT  13
#define PMIC_DA_DWA_RST_ADDR MT6358_FGADC_ANA_TEST_CON0
#define PMIC_DA_DWA_RST_MASK 0x1
#define PMIC_DA_DWA_RST_SHIFT   15
#define PMIC_FGADC_ANA_ELR_LEN_ADDR   MT6358_FGADC_ANA_ELR_NUM
#define PMIC_FGADC_ANA_ELR_LEN_MASK   0xFF
#define PMIC_FGADC_ANA_ELR_LEN_SHIFT  0
#define PMIC_RG_FGADC_GAINERROR_CAL_ADDR   MT6358_FGADC_ANA_ELR0
#define PMIC_RG_FGADC_GAINERROR_CAL_MASK   0x1FFF
#define PMIC_RG_FGADC_GAINERROR_CAL_SHIFT   0
#define PMIC_RG_FG_OFFSET_SWAP_ADDR   MT6358_FGADC_ANA_ELR1
#define PMIC_RG_FG_OFFSET_SWAP_MASK   0x7
#define PMIC_RG_FG_OFFSET_SWAP_SHIFT  0
#define PMIC_FGADC0_ANA_ID_ADDR MT6358_FGADC0_DSN_ID
#define PMIC_FGADC0_ANA_ID_MASK 0xFF
#define PMIC_FGADC0_ANA_ID_SHIFT  0
#define PMIC_FGADC0_DIG_ID_ADDR MT6358_FGADC0_DSN_ID
#define PMIC_FGADC0_DIG_ID_MASK 0xFF
#define PMIC_FGADC0_DIG_ID_SHIFT  8
#define PMIC_FGADC0_ANA_MINOR_REV_ADDR  MT6358_FGADC0_DSN_REV0
#define PMIC_FGADC0_ANA_MINOR_REV_MASK  0xF
#define PMIC_FGADC0_ANA_MINOR_REV_SHIFT 0
#define PMIC_FGADC0_ANA_MAJOR_REV_ADDR  MT6358_FGADC0_DSN_REV0
#define PMIC_FGADC0_ANA_MAJOR_REV_MASK  0xF
#define PMIC_FGADC0_ANA_MAJOR_REV_SHIFT 4
#define PMIC_FGADC0_DIG_MINOR_REV_ADDR  MT6358_FGADC0_DSN_REV0
#define PMIC_FGADC0_DIG_MINOR_REV_MASK  0xF
#define PMIC_FGADC0_DIG_MINOR_REV_SHIFT 8
#define PMIC_FGADC0_DIG_MAJOR_REV_ADDR  MT6358_FGADC0_DSN_REV0
#define PMIC_FGADC0_DIG_MAJOR_REV_MASK  0xF
#define PMIC_FGADC0_DIG_MAJOR_REV_SHIFT 12
#define PMIC_FGADC0_DSN_CBS_ADDR  MT6358_FGADC0_DSN_DBI
#define PMIC_FGADC0_DSN_CBS_MASK  0x3
#define PMIC_FGADC0_DSN_CBS_SHIFT 0
#define PMIC_FGADC0_DSN_BIX_ADDR  MT6358_FGADC0_DSN_DBI
#define PMIC_FGADC0_DSN_BIX_MASK  0x3
#define PMIC_FGADC0_DSN_BIX_SHIFT 2
#define PMIC_FGADC0_DSN_ESP_ADDR  MT6358_FGADC0_DSN_DBI
#define PMIC_FGADC0_DSN_ESP_MASK  0xFF
#define PMIC_FGADC0_DSN_ESP_SHIFT 8
#define PMIC_FGADC0_DSN_FPI_ADDR  MT6358_FGADC0_DSN_DXI
#define PMIC_FGADC0_DSN_FPI_MASK  0xFF
#define PMIC_FGADC0_DSN_FPI_SHIFT 0
#define PMIC_FG_ON_ADDR   MT6358_FGADC_CON0
#define PMIC_FG_ON_MASK   0x1
#define PMIC_FG_ON_SHIFT  0
#define PMIC_FG_CAL_ADDR  MT6358_FGADC_CON0
#define PMIC_FG_CAL_MASK  0x3
#define PMIC_FG_CAL_SHIFT 2
#define PMIC_FG_AUTOCALRATE_ADDR  MT6358_FGADC_CON0
#define PMIC_FG_AUTOCALRATE_MASK  0x7
#define PMIC_FG_AUTOCALRATE_SHIFT 4
#define PMIC_FG_SON_SLP_EN_ADDR MT6358_FGADC_CON0
#define PMIC_FG_SON_SLP_EN_MASK 0x1
#define PMIC_FG_SON_SLP_EN_SHIFT  8
#define PMIC_FG_SOFF_SLP_EN_ADDR  MT6358_FGADC_CON0
#define PMIC_FG_SOFF_SLP_EN_MASK  0x1
#define PMIC_FG_SOFF_SLP_EN_SHIFT 9
#define PMIC_FG_ZCV_DET_EN_ADDR MT6358_FGADC_CON0
#define PMIC_FG_ZCV_DET_EN_MASK 0x1
#define PMIC_FG_ZCV_DET_EN_SHIFT  10
#define PMIC_FG_AUXADC_R_ADDR   MT6358_FGADC_CON0
#define PMIC_FG_AUXADC_R_MASK   0x1
#define PMIC_FG_AUXADC_R_SHIFT  11
#define PMIC_FG_IAVG_MODE_ADDR  MT6358_FGADC_CON0
#define PMIC_FG_IAVG_MODE_MASK  0xF
#define PMIC_FG_IAVG_MODE_SHIFT 12
#define PMIC_FG_SW_READ_PRE_ADDR  MT6358_FGADC_CON1
#define PMIC_FG_SW_READ_PRE_MASK  0x1
#define PMIC_FG_SW_READ_PRE_SHIFT 0
#define PMIC_FG_SW_RSTCLR_ADDR  MT6358_FGADC_CON1
#define PMIC_FG_SW_RSTCLR_MASK  0x1
#define PMIC_FG_SW_RSTCLR_SHIFT 1
#define PMIC_FG_SW_CR_ADDR  MT6358_FGADC_CON1
#define PMIC_FG_SW_CR_MASK  0x1
#define PMIC_FG_SW_CR_SHIFT  2
#define PMIC_FG_SW_CLEAR_ADDR   MT6358_FGADC_CON1
#define PMIC_FG_SW_CLEAR_MASK   0x1
#define PMIC_FG_SW_CLEAR_SHIFT  3
#define PMIC_FG_OFFSET_RST_ADDR MT6358_FGADC_CON1
#define PMIC_FG_OFFSET_RST_MASK 0x1
#define PMIC_FG_OFFSET_RST_SHIFT  8
#define PMIC_FG_TIME_RST_ADDR   MT6358_FGADC_CON1
#define PMIC_FG_TIME_RST_MASK   0x1
#define PMIC_FG_TIME_RST_SHIFT  9
#define PMIC_FG_CHARGE_RST_ADDR MT6358_FGADC_CON1
#define PMIC_FG_CHARGE_RST_MASK 0x1
#define PMIC_FG_CHARGE_RST_SHIFT  10
#define PMIC_FG_N_CHARGE_RST_ADDR MT6358_FGADC_CON1
#define PMIC_FG_N_CHARGE_RST_MASK 0x1
#define PMIC_FG_N_CHARGE_RST_SHIFT 11
#define PMIC_FG_SOFF_RST_ADDR   MT6358_FGADC_CON1
#define PMIC_FG_SOFF_RST_MASK   0x1
#define PMIC_FG_SOFF_RST_SHIFT  12
#define PMIC_FG_LATCHDATA_ST_ADDR MT6358_FGADC_CON1
#define PMIC_FG_LATCHDATA_ST_MASK 0x1
#define PMIC_FG_LATCHDATA_ST_SHIFT 15
#define PMIC_EVENT_FG_BAT0_H_ADDR MT6358_FGADC_CON2
#define PMIC_EVENT_FG_BAT0_H_MASK 0x1
#define PMIC_EVENT_FG_BAT0_H_SHIFT 0
#define PMIC_EVENT_FG_BAT0_L_ADDR MT6358_FGADC_CON2
#define PMIC_EVENT_FG_BAT0_L_MASK 0x1
#define PMIC_EVENT_FG_BAT0_L_SHIFT 1
#define PMIC_EVENT_FG_CUR_H_ADDR  MT6358_FGADC_CON2
#define PMIC_EVENT_FG_CUR_H_MASK  0x1
#define PMIC_EVENT_FG_CUR_H_SHIFT 2
#define PMIC_EVENT_FG_CUR_L_ADDR  MT6358_FGADC_CON2
#define PMIC_EVENT_FG_CUR_L_MASK  0x1
#define PMIC_EVENT_FG_CUR_L_SHIFT 3
#define PMIC_EVENT_FG_ZCV_ADDR  MT6358_FGADC_CON2
#define PMIC_EVENT_FG_ZCV_MASK  0x1
#define PMIC_EVENT_FG_ZCV_SHIFT 4
#define PMIC_EVENT_FG_BAT1_H_ADDR MT6358_FGADC_CON2
#define PMIC_EVENT_FG_BAT1_H_MASK 0x1
#define PMIC_EVENT_FG_BAT1_H_SHIFT 6
#define PMIC_EVENT_FG_BAT1_L_ADDR MT6358_FGADC_CON2
#define PMIC_EVENT_FG_BAT1_L_MASK 0x1
#define PMIC_EVENT_FG_BAT1_L_SHIFT 7
#define PMIC_EVENT_FG_N_CHARGE_L_ADDR MT6358_FGADC_CON2
#define PMIC_EVENT_FG_N_CHARGE_L_MASK 0x1
#define PMIC_EVENT_FG_N_CHARGE_L_SHIFT  9
#define PMIC_EVENT_FG_IAVG_H_ADDR MT6358_FGADC_CON2
#define PMIC_EVENT_FG_IAVG_H_MASK 0x1
#define PMIC_EVENT_FG_IAVG_H_SHIFT 10
#define PMIC_EVENT_FG_IAVG_L_ADDR MT6358_FGADC_CON2
#define PMIC_EVENT_FG_IAVG_L_MASK 0x1
#define PMIC_EVENT_FG_IAVG_L_SHIFT 11
#define PMIC_EVENT_FG_TIME_H_ADDR MT6358_FGADC_CON2
#define PMIC_EVENT_FG_TIME_H_MASK 0x1
#define PMIC_EVENT_FG_TIME_H_SHIFT 12
#define PMIC_EVENT_FG_DISCHARGE_ADDR  MT6358_FGADC_CON2
#define PMIC_EVENT_FG_DISCHARGE_MASK  0x1
#define PMIC_EVENT_FG_DISCHARGE_SHIFT 14
#define PMIC_EVENT_FG_CHARGE_ADDR MT6358_FGADC_CON2
#define PMIC_EVENT_FG_CHARGE_MASK 0x1
#define PMIC_EVENT_FG_CHARGE_SHIFT 15
#define PMIC_FG_OSR1_ADDR MT6358_FGADC_CON3
#define PMIC_FG_OSR1_MASK 0xF
#define PMIC_FG_OSR1_SHIFT  0
#define PMIC_FG_OSR2_ADDR MT6358_FGADC_CON3
#define PMIC_FG_OSR2_MASK 0x3
#define PMIC_FG_OSR2_SHIFT  8
#define PMIC_FG_ADJ_OFFSET_EN_ADDR MT6358_FGADC_CON4
#define PMIC_FG_ADJ_OFFSET_EN_MASK 0x1
#define PMIC_FG_ADJ_OFFSET_EN_SHIFT   2
#define PMIC_FG_ADC_AUTORST_ADDR  MT6358_FGADC_CON4
#define PMIC_FG_ADC_AUTORST_MASK  0x1
#define PMIC_FG_ADC_AUTORST_SHIFT 3
#define PMIC_FG_ADC_RSTDETECT_ADDR MT6358_FGADC_CON4
#define PMIC_FG_ADC_RSTDETECT_MASK 0x1
#define PMIC_FG_ADC_RSTDETECT_SHIFT   4
#define PMIC_FG_VA_AON_ADDR  MT6358_FGADC_CON4
#define PMIC_FG_VA_AON_MASK  0x1
#define PMIC_FG_VA_AON_SHIFT 5
#define PMIC_FG_VA_AOFF_ADDR MT6358_FGADC_CON4
#define PMIC_FG_VA_AOFF_MASK 0x1
#define PMIC_FG_VA_AOFF_SHIFT   6
#define PMIC_FG_SON_SW_ADDR  MT6358_FGADC_CON4
#define PMIC_FG_SON_SW_MASK  0x1
#define PMIC_FG_SON_SW_SHIFT 7
#define PMIC_FG_SON_SW_MODE_ADDR  MT6358_FGADC_CON4
#define PMIC_FG_SON_SW_MODE_MASK  0x1
#define PMIC_FG_SON_SW_MODE_SHIFT 8
#define PMIC_FGADC_CON4_RSV_ADDR  MT6358_FGADC_CON4
#define PMIC_FGADC_CON4_RSV_MASK  0x7
#define PMIC_FGADC_CON4_RSV_SHIFT 9
#define PMIC_FG_RSTB_STATUS_ADDR  MT6358_FGADC_RST_CON0
#define PMIC_FG_RSTB_STATUS_MASK  0x1
#define PMIC_FG_RSTB_STATUS_SHIFT 0
#define PMIC_FG_CAR_15_00_ADDR  MT6358_FGADC_CAR_CON0
#define PMIC_FG_CAR_15_00_MASK  0xFFFF
#define PMIC_FG_CAR_15_00_SHIFT 0
#define PMIC_FG_CAR_31_16_ADDR  MT6358_FGADC_CAR_CON1
#define PMIC_FG_CAR_31_16_MASK  0xFFFF
#define PMIC_FG_CAR_31_16_SHIFT 0
#define PMIC_FG_BAT0_LTH_15_00_ADDR   MT6358_FGADC_CARTH_CON0
#define PMIC_FG_BAT0_LTH_15_00_MASK   0xFFFF
#define PMIC_FG_BAT0_LTH_15_00_SHIFT  0
#define PMIC_FG_BAT0_LTH_31_16_ADDR   MT6358_FGADC_CARTH_CON1
#define PMIC_FG_BAT0_LTH_31_16_MASK   0xFFFF
#define PMIC_FG_BAT0_LTH_31_16_SHIFT  0
#define PMIC_FG_BAT0_HTH_15_00_ADDR   MT6358_FGADC_CARTH_CON2
#define PMIC_FG_BAT0_HTH_15_00_MASK   0xFFFF
#define PMIC_FG_BAT0_HTH_15_00_SHIFT  0
#define PMIC_FG_BAT0_HTH_31_16_ADDR   MT6358_FGADC_CARTH_CON3
#define PMIC_FG_BAT0_HTH_31_16_MASK   0xFFFF
#define PMIC_FG_BAT0_HTH_31_16_SHIFT  0
#define PMIC_FG_BAT1_LTH_15_00_ADDR   MT6358_FGADC_CARTH_CON4
#define PMIC_FG_BAT1_LTH_15_00_MASK   0xFFFF
#define PMIC_FG_BAT1_LTH_15_00_SHIFT  0
#define PMIC_FG_BAT1_LTH_31_16_ADDR   MT6358_FGADC_CARTH_CON5
#define PMIC_FG_BAT1_LTH_31_16_MASK   0xFFFF
#define PMIC_FG_BAT1_LTH_31_16_SHIFT  0
#define PMIC_FG_BAT1_HTH_15_00_ADDR   MT6358_FGADC_CARTH_CON6
#define PMIC_FG_BAT1_HTH_15_00_MASK   0xFFFF
#define PMIC_FG_BAT1_HTH_15_00_SHIFT  0
#define PMIC_FG_BAT1_HTH_31_16_ADDR   MT6358_FGADC_CARTH_CON7
#define PMIC_FG_BAT1_HTH_31_16_MASK   0xFFFF
#define PMIC_FG_BAT1_HTH_31_16_SHIFT  0
#define PMIC_FG_NCAR_15_00_ADDR MT6358_FGADC_NCAR_CON0
#define PMIC_FG_NCAR_15_00_MASK 0xFFFF
#define PMIC_FG_NCAR_15_00_SHIFT  0
#define PMIC_FG_NCAR_31_16_ADDR MT6358_FGADC_NCAR_CON1
#define PMIC_FG_NCAR_31_16_MASK 0xFFFF
#define PMIC_FG_NCAR_31_16_SHIFT  0
#define PMIC_FG_N_CHARGE_LTH_15_00_ADDR MT6358_FGADC_NCAR_CON2
#define PMIC_FG_N_CHARGE_LTH_15_00_MASK 0xFFFF
#define PMIC_FG_N_CHARGE_LTH_15_00_SHIFT   0
#define PMIC_FG_N_CHARGE_LTH_31_16_ADDR MT6358_FGADC_NCAR_CON3
#define PMIC_FG_N_CHARGE_LTH_31_16_MASK 0xFFFF
#define PMIC_FG_N_CHARGE_LTH_31_16_SHIFT   0
#define PMIC_FG_IAVG_15_00_ADDR MT6358_FGADC_IAVG_CON0
#define PMIC_FG_IAVG_15_00_MASK 0xFFFF
#define PMIC_FG_IAVG_15_00_SHIFT  0
#define PMIC_FG_IAVG_27_16_ADDR MT6358_FGADC_IAVG_CON1
#define PMIC_FG_IAVG_27_16_MASK 0xFFF
#define PMIC_FG_IAVG_27_16_SHIFT  0
#define PMIC_FG_IAVG_VLD_ADDR   MT6358_FGADC_IAVG_CON1
#define PMIC_FG_IAVG_VLD_MASK   0x1
#define PMIC_FG_IAVG_VLD_SHIFT  15
#define PMIC_FG_IAVG_LTH_15_00_ADDR   MT6358_FGADC_IAVG_CON2
#define PMIC_FG_IAVG_LTH_15_00_MASK   0xFFFF
#define PMIC_FG_IAVG_LTH_15_00_SHIFT  0
#define PMIC_FG_IAVG_LTH_28_16_ADDR   MT6358_FGADC_IAVG_CON3
#define PMIC_FG_IAVG_LTH_28_16_MASK   0x1FFF
#define PMIC_FG_IAVG_LTH_28_16_SHIFT  0
#define PMIC_FG_IAVG_HTH_15_00_ADDR   MT6358_FGADC_IAVG_CON4
#define PMIC_FG_IAVG_HTH_15_00_MASK   0xFFFF
#define PMIC_FG_IAVG_HTH_15_00_SHIFT  0
#define PMIC_FG_IAVG_HTH_28_16_ADDR   MT6358_FGADC_IAVG_CON5
#define PMIC_FG_IAVG_HTH_28_16_MASK   0x1FFF
#define PMIC_FG_IAVG_HTH_28_16_SHIFT  0
#define PMIC_FG_NTER_15_00_ADDR MT6358_FGADC_NTER_CON0
#define PMIC_FG_NTER_15_00_MASK 0xFFFF
#define PMIC_FG_NTER_15_00_SHIFT  0
#define PMIC_FG_NTER_29_16_ADDR MT6358_FGADC_NTER_CON1
#define PMIC_FG_NTER_29_16_MASK 0x3FFF
#define PMIC_FG_NTER_29_16_SHIFT  0
#define PMIC_FG_TIME_HTH_15_00_ADDR   MT6358_FGADC_NTERTH_CON0
#define PMIC_FG_TIME_HTH_15_00_MASK   0xFFFF
#define PMIC_FG_TIME_HTH_15_00_SHIFT  0
#define PMIC_FG_TIME_HTH_29_16_ADDR   MT6358_FGADC_NTERTH_CON1
#define PMIC_FG_TIME_HTH_29_16_MASK   0x3FFF
#define PMIC_FG_TIME_HTH_29_16_SHIFT  0
#define PMIC_FG_SON_SLP_CUR_TH_ADDR   MT6358_FGADC_SON_CON0
#define PMIC_FG_SON_SLP_CUR_TH_MASK   0xFFFF
#define PMIC_FG_SON_SLP_CUR_TH_SHIFT  0
#define PMIC_FG_SON_SLP_TIME_ADDR MT6358_FGADC_SON_CON1
#define PMIC_FG_SON_SLP_TIME_MASK 0x3FF
#define PMIC_FG_SON_SLP_TIME_SHIFT 0
#define PMIC_FG_SON_DET_TIME_ADDR MT6358_FGADC_SON_CON2
#define PMIC_FG_SON_DET_TIME_MASK 0x3FF
#define PMIC_FG_SON_DET_TIME_SHIFT 0
#define PMIC_FG_FP_FTIME_ADDR   MT6358_FGADC_SON_CON3
#define PMIC_FG_FP_FTIME_MASK   0xFF
#define PMIC_FG_FP_FTIME_SHIFT  0
#define PMIC_FG_SOFF_SLP_CUR_TH_ADDR  MT6358_FGADC_SOFF_CON0
#define PMIC_FG_SOFF_SLP_CUR_TH_MASK  0xFFFF
#define PMIC_FG_SOFF_SLP_CUR_TH_SHIFT 0
#define PMIC_FG_SOFF_SLP_TIME_ADDR MT6358_FGADC_SOFF_CON1
#define PMIC_FG_SOFF_SLP_TIME_MASK 0x3FF
#define PMIC_FG_SOFF_SLP_TIME_SHIFT   0
#define PMIC_FG_SOFF_DET_TIME_ADDR MT6358_FGADC_SOFF_CON2
#define PMIC_FG_SOFF_DET_TIME_MASK 0x3FF
#define PMIC_FG_SOFF_DET_TIME_SHIFT   0
#define PMIC_FG_SOFF_TIME_15_00_ADDR  MT6358_FGADC_SOFF_CON3
#define PMIC_FG_SOFF_TIME_15_00_MASK  0xFFFF
#define PMIC_FG_SOFF_TIME_15_00_SHIFT 0
#define PMIC_FG_SOFF_TIME_29_16_ADDR  MT6358_FGADC_SOFF_CON4
#define PMIC_FG_SOFF_TIME_29_16_MASK  0x3FFF
#define PMIC_FG_SOFF_TIME_29_16_SHIFT 0
#define PMIC_FG_SOFF_ADDR MT6358_FGADC_SOFF_CON4
#define PMIC_FG_SOFF_MASK 0x1
#define PMIC_FG_SOFF_SHIFT  15
#define PMIC_FG_PWR_TIME0_ADDR  MT6358_FGADC_PWR_CON0
#define PMIC_FG_PWR_TIME0_MASK  0xFF
#define PMIC_FG_PWR_TIME0_SHIFT 0
#define PMIC_FG_PWR_TIME1_ADDR  MT6358_FGADC_PWR_CON0
#define PMIC_FG_PWR_TIME1_MASK  0xFF
#define PMIC_FG_PWR_TIME1_SHIFT 8
#define PMIC_FG_PWR_TIME2_ADDR  MT6358_FGADC_PWR_CON1
#define PMIC_FG_PWR_TIME2_MASK  0xFF
#define PMIC_FG_PWR_TIME2_SHIFT 0
#define PMIC_FG_ZCV_DET_IV_ADDR MT6358_FGADC_ZCV_CON0
#define PMIC_FG_ZCV_DET_IV_MASK 0xF
#define PMIC_FG_ZCV_DET_IV_SHIFT  0
#define PMIC_FG_ZCV_CURR_ADDR   MT6358_FGADC_ZCV_CON1
#define PMIC_FG_ZCV_CURR_MASK   0xFFFF
#define PMIC_FG_ZCV_CURR_SHIFT  0
#define PMIC_FG_ZCV_CAR_15_00_ADDR MT6358_FGADC_ZCV_CON2
#define PMIC_FG_ZCV_CAR_15_00_MASK 0xFFFF
#define PMIC_FG_ZCV_CAR_15_00_SHIFT   0
#define PMIC_FG_ZCV_CAR_31_16_ADDR MT6358_FGADC_ZCV_CON3
#define PMIC_FG_ZCV_CAR_31_16_MASK 0xFFFF
#define PMIC_FG_ZCV_CAR_31_16_SHIFT   0
#define PMIC_FG_ZCV_CAR_TH_15_00_ADDR MT6358_FGADC_ZCVTH_CON0
#define PMIC_FG_ZCV_CAR_TH_15_00_MASK 0xFFFF
#define PMIC_FG_ZCV_CAR_TH_15_00_SHIFT  0
#define PMIC_FG_ZCV_CAR_TH_30_16_ADDR MT6358_FGADC_ZCVTH_CON1
#define PMIC_FG_ZCV_CAR_TH_30_16_MASK 0x7FFF
#define PMIC_FG_ZCV_CAR_TH_30_16_SHIFT  0
#define PMIC_FGADC1_ANA_ID_ADDR MT6358_FGADC1_DSN_ID
#define PMIC_FGADC1_ANA_ID_MASK 0xFF
#define PMIC_FGADC1_ANA_ID_SHIFT  0
#define PMIC_FGADC1_DIG_ID_ADDR MT6358_FGADC1_DSN_ID
#define PMIC_FGADC1_DIG_ID_MASK 0xFF
#define PMIC_FGADC1_DIG_ID_SHIFT  8
#define PMIC_FGADC1_ANA_MINOR_REV_ADDR  MT6358_FGADC1_DSN_REV0
#define PMIC_FGADC1_ANA_MINOR_REV_MASK  0xF
#define PMIC_FGADC1_ANA_MINOR_REV_SHIFT 0
#define PMIC_FGADC1_ANA_MAJOR_REV_ADDR  MT6358_FGADC1_DSN_REV0
#define PMIC_FGADC1_ANA_MAJOR_REV_MASK  0xF
#define PMIC_FGADC1_ANA_MAJOR_REV_SHIFT 4
#define PMIC_FGADC1_DIG_MINOR_REV_ADDR  MT6358_FGADC1_DSN_REV0
#define PMIC_FGADC1_DIG_MINOR_REV_MASK  0xF
#define PMIC_FGADC1_DIG_MINOR_REV_SHIFT 8
#define PMIC_FGADC1_DIG_MAJOR_REV_ADDR  MT6358_FGADC1_DSN_REV0
#define PMIC_FGADC1_DIG_MAJOR_REV_MASK  0xF
#define PMIC_FGADC1_DIG_MAJOR_REV_SHIFT 12
#define PMIC_FGADC1_DSN_CBS_ADDR  MT6358_FGADC1_DSN_DBI
#define PMIC_FGADC1_DSN_CBS_MASK  0x3
#define PMIC_FGADC1_DSN_CBS_SHIFT 0
#define PMIC_FGADC1_DSN_BIX_ADDR  MT6358_FGADC1_DSN_DBI
#define PMIC_FGADC1_DSN_BIX_MASK  0x3
#define PMIC_FGADC1_DSN_BIX_SHIFT 2
#define PMIC_FGADC1_DSN_ESP_ADDR  MT6358_FGADC1_DSN_DBI
#define PMIC_FGADC1_DSN_ESP_MASK  0xFF
#define PMIC_FGADC1_DSN_ESP_SHIFT 8
#define PMIC_FGADC1_DSN_FPI_ADDR  MT6358_FGADC1_DSN_DXI
#define PMIC_FGADC1_DSN_FPI_MASK  0xFF
#define PMIC_FGADC1_DSN_FPI_SHIFT 0
#define PMIC_FG_R_CURR_ADDR  MT6358_FGADC_R_CON0
#define PMIC_FG_R_CURR_MASK  0xFFFF
#define PMIC_FG_R_CURR_SHIFT 0
#define PMIC_FG_CURRENT_OUT_ADDR  MT6358_FGADC_CUR_CON0
#define PMIC_FG_CURRENT_OUT_MASK  0xFFFF
#define PMIC_FG_CURRENT_OUT_SHIFT 0
#define PMIC_FG_CUR_LTH_ADDR MT6358_FGADC_CUR_CON1
#define PMIC_FG_CUR_LTH_MASK 0xFFFF
#define PMIC_FG_CUR_LTH_SHIFT   0
#define PMIC_FG_CUR_HTH_ADDR MT6358_FGADC_CUR_CON2
#define PMIC_FG_CUR_HTH_MASK 0xFFFF
#define PMIC_FG_CUR_HTH_SHIFT   0
#define PMIC_FG_CIC2_ADDR MT6358_FGADC_CUR_CON3
#define PMIC_FG_CIC2_MASK 0xFFFF
#define PMIC_FG_CIC2_SHIFT  0
#define PMIC_FG_OFFSET_ADDR  MT6358_FGADC_OFFSET_CON0
#define PMIC_FG_OFFSET_MASK  0xFFFF
#define PMIC_FG_OFFSET_SHIFT 0
#define PMIC_FG_ADJUST_OFFSET_VALUE_ADDR   MT6358_FGADC_OFFSET_CON1
#define PMIC_FG_ADJUST_OFFSET_VALUE_MASK   0xFFFF
#define PMIC_FG_ADJUST_OFFSET_VALUE_SHIFT   0
#define PMIC_FG_GAIN_ADDR MT6358_FGADC_GAIN_CON0
#define PMIC_FG_GAIN_MASK 0x1FFF
#define PMIC_FG_GAIN_SHIFT  0
#define PMIC_FG_MODE_ADDR MT6358_FGADC_TEST_CON0
#define PMIC_FG_MODE_MASK 0x1
#define PMIC_FG_MODE_SHIFT  0
#define PMIC_FG_RST_SW_ADDR  MT6358_FGADC_TEST_CON0
#define PMIC_FG_RST_SW_MASK  0x1
#define PMIC_FG_RST_SW_SHIFT 1
#define PMIC_FG_FGCAL_EN_SW_ADDR  MT6358_FGADC_TEST_CON0
#define PMIC_FG_FGCAL_EN_SW_MASK  0x1
#define PMIC_FG_FGCAL_EN_SW_SHIFT 2
#define PMIC_FG_FGADC_EN_SW_ADDR  MT6358_FGADC_TEST_CON0
#define PMIC_FG_FGADC_EN_SW_MASK  0x1
#define PMIC_FG_FGADC_EN_SW_SHIFT 3
#define PMIC_RG_SYSTEM_INFO_CON0_ADDR MT6358_SYSTEM_INFO_CON0
#define PMIC_RG_SYSTEM_INFO_CON0_MASK 0xFFFF
#define PMIC_RG_SYSTEM_INFO_CON0_SHIFT  0
#define PMIC_BATON_ANA_ANA_ID_ADDR MT6358_BATON_ANA_DSN_ID
#define PMIC_BATON_ANA_ANA_ID_MASK 0xFF
#define PMIC_BATON_ANA_ANA_ID_SHIFT   0
#define PMIC_BATON_ANA_DIG_ID_ADDR MT6358_BATON_ANA_DSN_ID
#define PMIC_BATON_ANA_DIG_ID_MASK 0xFF
#define PMIC_BATON_ANA_DIG_ID_SHIFT   8
#define PMIC_BATON_ANA_ANA_MINOR_REV_ADDR   MT6358_BATON_ANA_DSN_REV0
#define PMIC_BATON_ANA_ANA_MINOR_REV_MASK   0xF
#define PMIC_BATON_ANA_ANA_MINOR_REV_SHIFT  0
#define PMIC_BATON_ANA_ANA_MAJOR_REV_ADDR   MT6358_BATON_ANA_DSN_REV0
#define PMIC_BATON_ANA_ANA_MAJOR_REV_MASK   0xF
#define PMIC_BATON_ANA_ANA_MAJOR_REV_SHIFT  4
#define PMIC_BATON_ANA_DIG_MINOR_REV_ADDR   MT6358_BATON_ANA_DSN_REV0
#define PMIC_BATON_ANA_DIG_MINOR_REV_MASK   0xF
#define PMIC_BATON_ANA_DIG_MINOR_REV_SHIFT  8
#define PMIC_BATON_ANA_DIG_MAJOR_REV_ADDR   MT6358_BATON_ANA_DSN_REV0
#define PMIC_BATON_ANA_DIG_MAJOR_REV_MASK   0xF
#define PMIC_BATON_ANA_DIG_MAJOR_REV_SHIFT  12
#define PMIC_BATON_ANA_DSN_CBS_ADDR   MT6358_BATON_ANA_DSN_DBI
#define PMIC_BATON_ANA_DSN_CBS_MASK   0x3
#define PMIC_BATON_ANA_DSN_CBS_SHIFT  0
#define PMIC_BATON_ANA_DSN_BIX_ADDR   MT6358_BATON_ANA_DSN_DBI
#define PMIC_BATON_ANA_DSN_BIX_MASK   0x3
#define PMIC_BATON_ANA_DSN_BIX_SHIFT  2
#define PMIC_BATON_ANA_DSN_ESP_ADDR   MT6358_BATON_ANA_DSN_DBI
#define PMIC_BATON_ANA_DSN_ESP_MASK   0xFF
#define PMIC_BATON_ANA_DSN_ESP_SHIFT  8
#define PMIC_BATON_ANA_DSN_FPI_ADDR   MT6358_BATON_ANA_DSN_DXI
#define PMIC_BATON_ANA_DSN_FPI_MASK   0xFF
#define PMIC_BATON_ANA_DSN_FPI_SHIFT  0
#define PMIC_RG_BATON_EN_ADDR   MT6358_BATON_ANA_CON0
#define PMIC_RG_BATON_EN_MASK   0x1
#define PMIC_RG_BATON_EN_SHIFT  0
#define PMIC_RG_BIF_BATID_SW_EN_ADDR  MT6358_BATON_ANA_CON0
#define PMIC_RG_BIF_BATID_SW_EN_MASK  0x1
#define PMIC_RG_BIF_BATID_SW_EN_SHIFT 1
#define PMIC_RG_QI_BATON_LT_EN_ADDR   MT6358_BATON_ANA_CON0
#define PMIC_RG_QI_BATON_LT_EN_MASK   0x1
#define PMIC_RG_QI_BATON_LT_EN_SHIFT  2
#define PMIC_RG_BATON_HT_EN_ADDR  MT6358_BATON_ANA_CON0
#define PMIC_RG_BATON_HT_EN_MASK  0x1
#define PMIC_RG_BATON_HT_EN_SHIFT 3
#define PMIC_RG_BATON_HT_VTH_ADDR MT6358_BATON_ANA_CON0
#define PMIC_RG_BATON_HT_VTH_MASK 0x3
#define PMIC_RG_BATON_HT_VTH_SHIFT 4
#define PMIC_RG_HW_VTH1_ADDR MT6358_BATON_ANA_CON0
#define PMIC_RG_HW_VTH1_MASK 0x3
#define PMIC_RG_HW_VTH1_SHIFT   8
#define PMIC_RG_HW_VTH2_ADDR MT6358_BATON_ANA_CON0
#define PMIC_RG_HW_VTH2_MASK 0x3
#define PMIC_RG_HW_VTH2_SHIFT   10
#define PMIC_RG_HW_VTH_CTRL_ADDR  MT6358_BATON_ANA_CON0
#define PMIC_RG_HW_VTH_CTRL_MASK  0x1
#define PMIC_RG_HW_VTH_CTRL_SHIFT 12
#define PMIC_DA_BATON_HT_EN_ADDR  MT6358_BATON_ANA_MON0
#define PMIC_DA_BATON_HT_EN_MASK  0x1
#define PMIC_DA_BATON_HT_EN_SHIFT 0
#define PMIC_AD_BATON_UNDET_ADDR  MT6358_BATON_ANA_MON0
#define PMIC_AD_BATON_UNDET_MASK  0x1
#define PMIC_AD_BATON_UNDET_SHIFT 1
#define PMIC_AD_BATON_UNDET_RAW_ADDR  MT6358_BATON_ANA_MON0
#define PMIC_AD_BATON_UNDET_RAW_MASK  0x1
#define PMIC_AD_BATON_UNDET_RAW_SHIFT 2
#define PMIC_AD_BATON_HV_ADDR   MT6358_BATON_ANA_MON0
#define PMIC_AD_BATON_HV_MASK   0x1
#define PMIC_AD_BATON_HV_SHIFT  3
#define PMIC_DA_BIF_TX_EN_ADDR  MT6358_BIF_ANA_MON0
#define PMIC_DA_BIF_TX_EN_MASK  0x1
#define PMIC_DA_BIF_TX_EN_SHIFT 0
#define PMIC_DA_BIF_TX_DATA_ADDR  MT6358_BIF_ANA_MON0
#define PMIC_DA_BIF_TX_DATA_MASK  0x1
#define PMIC_DA_BIF_TX_DATA_SHIFT 1
#define PMIC_DA_BIF_RX_EN_ADDR  MT6358_BIF_ANA_MON0
#define PMIC_DA_BIF_RX_EN_MASK  0x1
#define PMIC_DA_BIF_RX_EN_SHIFT 2
#define PMIC_AD_BIF_RX_DATA_ADDR  MT6358_BIF_ANA_MON0
#define PMIC_AD_BIF_RX_DATA_MASK  0x1
#define PMIC_AD_BIF_RX_DATA_SHIFT 3
#define PMIC_BATON_ANA_ELR_LEN_ADDR   MT6358_BATON_ANA_ELR_NUM
#define PMIC_BATON_ANA_ELR_LEN_MASK   0xFF
#define PMIC_BATON_ANA_ELR_LEN_SHIFT  0
#define PMIC_RG_BATON_HT_TRIM_ADDR MT6358_BATON_ANA_ELR0
#define PMIC_RG_BATON_HT_TRIM_MASK 0x7
#define PMIC_RG_BATON_HT_TRIM_SHIFT   0
#define PMIC_BATON_ANA_ID_ADDR  MT6358_BATON_DSN_ID
#define PMIC_BATON_ANA_ID_MASK  0xFF
#define PMIC_BATON_ANA_ID_SHIFT 0
#define PMIC_BATON_DIG_ID_ADDR  MT6358_BATON_DSN_ID
#define PMIC_BATON_DIG_ID_MASK  0xFF
#define PMIC_BATON_DIG_ID_SHIFT 8
#define PMIC_BATON_ANA_MINOR_REV_ADDR MT6358_BATON_DSN_REV0
#define PMIC_BATON_ANA_MINOR_REV_MASK 0xF
#define PMIC_BATON_ANA_MINOR_REV_SHIFT  0
#define PMIC_BATON_ANA_MAJOR_REV_ADDR MT6358_BATON_DSN_REV0
#define PMIC_BATON_ANA_MAJOR_REV_MASK 0xF
#define PMIC_BATON_ANA_MAJOR_REV_SHIFT  4
#define PMIC_BATON_DIG_MINOR_REV_ADDR MT6358_BATON_DSN_REV0
#define PMIC_BATON_DIG_MINOR_REV_MASK 0xF
#define PMIC_BATON_DIG_MINOR_REV_SHIFT  8
#define PMIC_BATON_DIG_MAJOR_REV_ADDR MT6358_BATON_DSN_REV0
#define PMIC_BATON_DIG_MAJOR_REV_MASK 0xF
#define PMIC_BATON_DIG_MAJOR_REV_SHIFT  12
#define PMIC_BATON_DSN_CBS_ADDR MT6358_BATON_DSN_DBI
#define PMIC_BATON_DSN_CBS_MASK 0x3
#define PMIC_BATON_DSN_CBS_SHIFT  0
#define PMIC_BATON_DSN_BIX_ADDR MT6358_BATON_DSN_DBI
#define PMIC_BATON_DSN_BIX_MASK 0x3
#define PMIC_BATON_DSN_BIX_SHIFT  2
#define PMIC_BATON_DSN_ESP_ADDR MT6358_BATON_DSN_DBI
#define PMIC_BATON_DSN_ESP_MASK 0xFF
#define PMIC_BATON_DSN_ESP_SHIFT  8
#define PMIC_BATON_DSN_FPI_ADDR MT6358_BATON_DSN_DXI
#define PMIC_BATON_DSN_FPI_MASK 0xFF
#define PMIC_BATON_DSN_FPI_SHIFT  0
#define PMIC_RG_BATON_DEBOUNCE_WND_ADDR MT6358_BATON_CON0
#define PMIC_RG_BATON_DEBOUNCE_WND_MASK 0x3
#define PMIC_RG_BATON_DEBOUNCE_WND_SHIFT   0
#define PMIC_RG_BATON_DEBOUNCE_THD_ADDR MT6358_BATON_CON0
#define PMIC_RG_BATON_DEBOUNCE_THD_MASK 0x3
#define PMIC_RG_BATON_DEBOUNCE_THD_SHIFT   2
#define PMIC_RG_BATON_CHRDET_TEST_MODE_ADDR MT6358_BATON_CON1
#define PMIC_RG_BATON_CHRDET_TEST_MODE_MASK 0x1
#define PMIC_RG_BATON_CHRDET_TEST_MODE_SHIFT  0
#define PMIC_RG_BATON_UNDET_TEST_MODE_ADDR  MT6358_BATON_CON1
#define PMIC_RG_BATON_UNDET_TEST_MODE_MASK  0x1
#define PMIC_RG_BATON_UNDET_TEST_MODE_SHIFT 1
#define PMIC_RG_BATON_AUXADC_TEST_MODE_ADDR MT6358_BATON_CON1
#define PMIC_RG_BATON_AUXADC_TEST_MODE_MASK 0x1
#define PMIC_RG_BATON_AUXADC_TEST_MODE_SHIFT  2
#define PMIC_RG_BATON_FGADC_TEST_MODE_ADDR  MT6358_BATON_CON1
#define PMIC_RG_BATON_FGADC_TEST_MODE_MASK  0x1
#define PMIC_RG_BATON_FGADC_TEST_MODE_SHIFT 3
#define PMIC_RG_BATON_RTC_TEST_MODE_ADDR   MT6358_BATON_CON1
#define PMIC_RG_BATON_RTC_TEST_MODE_MASK   0x1
#define PMIC_RG_BATON_RTC_TEST_MODE_SHIFT   4
#define PMIC_RG_BATON_BIF_TEST_MODE_ADDR   MT6358_BATON_CON1
#define PMIC_RG_BATON_BIF_TEST_MODE_MASK   0x1
#define PMIC_RG_BATON_BIF_TEST_MODE_SHIFT   5
#define PMIC_RG_BATON_RSV_ADDR  MT6358_BATON_CON1
#define PMIC_RG_BATON_RSV_MASK  0x3
#define PMIC_RG_BATON_RSV_SHIFT 6
#define PMIC_RG_BATON_CHRDET_SW_ADDR  MT6358_BATON_CON1
#define PMIC_RG_BATON_CHRDET_SW_MASK  0x1
#define PMIC_RG_BATON_CHRDET_SW_SHIFT 8
#define PMIC_RG_BATON_UNDET_SW_ADDR   MT6358_BATON_CON1
#define PMIC_RG_BATON_UNDET_SW_MASK   0x1
#define PMIC_RG_BATON_UNDET_SW_SHIFT  9
#define PMIC_RG_BATON_AUXADC_SW_ADDR  MT6358_BATON_CON1
#define PMIC_RG_BATON_AUXADC_SW_MASK  0x1
#define PMIC_RG_BATON_AUXADC_SW_SHIFT 10
#define PMIC_RG_BATON_FGADC_SW_ADDR   MT6358_BATON_CON1
#define PMIC_RG_BATON_FGADC_SW_MASK   0x1
#define PMIC_RG_BATON_FGADC_SW_SHIFT  11
#define PMIC_RG_BATON_RTC_SW_ADDR MT6358_BATON_CON1
#define PMIC_RG_BATON_RTC_SW_MASK 0x1
#define PMIC_RG_BATON_RTC_SW_SHIFT 12
#define PMIC_RG_BATON_BIF_SW_ADDR MT6358_BATON_CON1
#define PMIC_RG_BATON_BIF_SW_MASK 0x1
#define PMIC_RG_BATON_BIF_SW_SHIFT 13
#define PMIC_RG_BATON_RSV_SW_ADDR MT6358_BATON_CON1
#define PMIC_RG_BATON_RSV_SW_MASK 0x3
#define PMIC_RG_BATON_RSV_SW_SHIFT 14
#define PMIC_BATON_STATUS_ADDR  MT6358_BATON_CON2
#define PMIC_BATON_STATUS_MASK  0x1
#define PMIC_BATON_STATUS_SHIFT 0
#define PMIC_BATON_AUXADC_SET_ADDR MT6358_BATON_CON2
#define PMIC_BATON_AUXADC_SET_MASK 0x1
#define PMIC_BATON_AUXADC_SET_SHIFT   1
#define PMIC_BATON_DEB_VALID_ADDR MT6358_BATON_CON2
#define PMIC_BATON_DEB_VALID_MASK 0x1
#define PMIC_BATON_DEB_VALID_SHIFT 2
#define PMIC_BATON_BIF_STATUS_ADDR MT6358_BATON_CON2
#define PMIC_BATON_BIF_STATUS_MASK 0x1
#define PMIC_BATON_BIF_STATUS_SHIFT   3
#define PMIC_BATON_RTC_STATUS_ADDR MT6358_BATON_CON2
#define PMIC_BATON_RTC_STATUS_MASK 0x1
#define PMIC_BATON_RTC_STATUS_SHIFT   4
#define PMIC_BATON_FGADC_STATUS_ADDR  MT6358_BATON_CON2
#define PMIC_BATON_FGADC_STATUS_MASK  0x1
#define PMIC_BATON_FGADC_STATUS_SHIFT 5
#define PMIC_BATON_AUXADC_TRIG_ADDR   MT6358_BATON_CON2
#define PMIC_BATON_AUXADC_TRIG_MASK   0x1
#define PMIC_BATON_AUXADC_TRIG_SHIFT  6
#define PMIC_BATON_CHRDET_DEB_ADDR MT6358_BATON_CON2
#define PMIC_BATON_CHRDET_DEB_MASK 0x1
#define PMIC_BATON_CHRDET_DEB_SHIFT   7
#define PMIC_BATON_IVGEN_ENB_ADDR MT6358_BATON_CON2
#define PMIC_BATON_IVGEN_ENB_MASK 0x1
#define PMIC_BATON_IVGEN_ENB_SHIFT 8
#define PMIC_BATON_VBIF28_STB_ADDR MT6358_BATON_CON2
#define PMIC_BATON_VBIF28_STB_MASK 0x1
#define PMIC_BATON_VBIF28_STB_SHIFT   9
#define PMIC_BATON_VBIF28_EN_ADDR MT6358_BATON_CON2
#define PMIC_BATON_VBIF28_EN_MASK 0x1
#define PMIC_BATON_VBIF28_EN_SHIFT 10
#define PMIC_BATON_RSV_0_ADDR   MT6358_BATON_CON2
#define PMIC_BATON_RSV_0_MASK   0x1F
#define PMIC_BATON_RSV_0_SHIFT  11
#define PMIC_RG_BATON_PWR_TIME0_ADDR  MT6358_BATON_CON3
#define PMIC_RG_BATON_PWR_TIME0_MASK  0xFF
#define PMIC_RG_BATON_PWR_TIME0_SHIFT 0
#define PMIC_RG_BATON_PWR_TIME1_ADDR  MT6358_BATON_CON3
#define PMIC_RG_BATON_PWR_TIME1_MASK  0xFF
#define PMIC_RG_BATON_PWR_TIME1_SHIFT 8
#define PMIC_BATON_ELR_LEN_ADDR MT6358_BATON_ELR_NUM
#define PMIC_BATON_ELR_LEN_MASK 0xFF
#define PMIC_BATON_ELR_LEN_SHIFT  0
#define PMIC_RG_BATON_CHRDET_DEB_TD_ADDR   MT6358_BATON_ELR0
#define PMIC_RG_BATON_CHRDET_DEB_TD_MASK   0x1
#define PMIC_RG_BATON_CHRDET_DEB_TD_SHIFT   0
#define PMIC_BIF_ANA_ID_ADDR MT6358_BIF_DSN_ID
#define PMIC_BIF_ANA_ID_MASK 0xFF
#define PMIC_BIF_ANA_ID_SHIFT   0
#define PMIC_BIF_DIG_ID_ADDR MT6358_BIF_DSN_ID
#define PMIC_BIF_DIG_ID_MASK 0xFF
#define PMIC_BIF_DIG_ID_SHIFT   8
#define PMIC_BIF_ANA_MINOR_REV_ADDR   MT6358_BIF_DSN_REV0
#define PMIC_BIF_ANA_MINOR_REV_MASK   0xF
#define PMIC_BIF_ANA_MINOR_REV_SHIFT  0
#define PMIC_BIF_ANA_MAJOR_REV_ADDR   MT6358_BIF_DSN_REV0
#define PMIC_BIF_ANA_MAJOR_REV_MASK   0xF
#define PMIC_BIF_ANA_MAJOR_REV_SHIFT  4
#define PMIC_BIF_DIG_MINOR_REV_ADDR   MT6358_BIF_DSN_REV0
#define PMIC_BIF_DIG_MINOR_REV_MASK   0xF
#define PMIC_BIF_DIG_MINOR_REV_SHIFT  8
#define PMIC_BIF_DIG_MAJOR_REV_ADDR   MT6358_BIF_DSN_REV0
#define PMIC_BIF_DIG_MAJOR_REV_MASK   0xF
#define PMIC_BIF_DIG_MAJOR_REV_SHIFT  12
#define PMIC_BIF_DSN_CBS_ADDR   MT6358_BIF_DSN_DBI
#define PMIC_BIF_DSN_CBS_MASK   0x3
#define PMIC_BIF_DSN_CBS_SHIFT  0
#define PMIC_BIF_DSN_BIX_ADDR   MT6358_BIF_DSN_DBI
#define PMIC_BIF_DSN_BIX_MASK   0x3
#define PMIC_BIF_DSN_BIX_SHIFT  2
#define PMIC_BIF_ESP_ADDR MT6358_BIF_DSN_DBI
#define PMIC_BIF_ESP_MASK 0xFF
#define PMIC_BIF_ESP_SHIFT  8
#define PMIC_BIF_DSN_FPI_ADDR   MT6358_BIF_DSN_DXI
#define PMIC_BIF_DSN_FPI_MASK   0xFF
#define PMIC_BIF_DSN_FPI_SHIFT  0
#define PMIC_BIF_COMMAND_0_ADDR MT6358_BIF_CON0
#define PMIC_BIF_COMMAND_0_MASK 0x7FF
#define PMIC_BIF_COMMAND_0_SHIFT  0
#define PMIC_BIF_COMMAND_1_ADDR MT6358_BIF_CON1
#define PMIC_BIF_COMMAND_1_MASK 0x7FF
#define PMIC_BIF_COMMAND_1_SHIFT  0
#define PMIC_BIF_COMMAND_2_ADDR MT6358_BIF_CON2
#define PMIC_BIF_COMMAND_2_MASK 0x7FF
#define PMIC_BIF_COMMAND_2_SHIFT  0
#define PMIC_BIF_COMMAND_3_ADDR MT6358_BIF_CON3
#define PMIC_BIF_COMMAND_3_MASK 0x7FF
#define PMIC_BIF_COMMAND_3_SHIFT  0
#define PMIC_BIF_COMMAND_4_ADDR MT6358_BIF_CON4
#define PMIC_BIF_COMMAND_4_MASK 0x7FF
#define PMIC_BIF_COMMAND_4_SHIFT  0
#define PMIC_BIF_COMMAND_5_ADDR MT6358_BIF_CON5
#define PMIC_BIF_COMMAND_5_MASK 0x7FF
#define PMIC_BIF_COMMAND_5_SHIFT  0
#define PMIC_BIF_COMMAND_6_ADDR MT6358_BIF_CON6
#define PMIC_BIF_COMMAND_6_MASK 0x7FF
#define PMIC_BIF_COMMAND_6_SHIFT  0
#define PMIC_BIF_COMMAND_7_ADDR MT6358_BIF_CON7
#define PMIC_BIF_COMMAND_7_MASK 0x7FF
#define PMIC_BIF_COMMAND_7_SHIFT  0
#define PMIC_BIF_COMMAND_8_ADDR MT6358_BIF_CON8
#define PMIC_BIF_COMMAND_8_MASK 0x7FF
#define PMIC_BIF_COMMAND_8_SHIFT  0
#define PMIC_BIF_COMMAND_9_ADDR MT6358_BIF_CON9
#define PMIC_BIF_COMMAND_9_MASK 0x7FF
#define PMIC_BIF_COMMAND_9_SHIFT  0
#define PMIC_BIF_COMMAND_10_ADDR  MT6358_BIF_CON10
#define PMIC_BIF_COMMAND_10_MASK  0x7FF
#define PMIC_BIF_COMMAND_10_SHIFT 0
#define PMIC_BIF_COMMAND_11_ADDR  MT6358_BIF_CON11
#define PMIC_BIF_COMMAND_11_MASK  0x7FF
#define PMIC_BIF_COMMAND_11_SHIFT 0
#define PMIC_BIF_COMMAND_12_ADDR  MT6358_BIF_CON12
#define PMIC_BIF_COMMAND_12_MASK  0x7FF
#define PMIC_BIF_COMMAND_12_SHIFT 0
#define PMIC_BIF_COMMAND_13_ADDR  MT6358_BIF_CON13
#define PMIC_BIF_COMMAND_13_MASK  0x7FF
#define PMIC_BIF_COMMAND_13_SHIFT 0
#define PMIC_BIF_COMMAND_14_ADDR  MT6358_BIF_CON14
#define PMIC_BIF_COMMAND_14_MASK  0x7FF
#define PMIC_BIF_COMMAND_14_SHIFT 0
#define PMIC_BIF_RSV_ADDR MT6358_BIF_CON15
#define PMIC_BIF_RSV_MASK 0x7F
#define PMIC_BIF_RSV_SHIFT  0
#define PMIC_BIF_COMMAND_TYPE_ADDR MT6358_BIF_CON15
#define PMIC_BIF_COMMAND_TYPE_MASK 0x3
#define PMIC_BIF_COMMAND_TYPE_SHIFT   8
#define PMIC_BIF_TRASFER_NUM_ADDR MT6358_BIF_CON15
#define PMIC_BIF_TRASFER_NUM_MASK 0xF
#define PMIC_BIF_TRASFER_NUM_SHIFT 12
#define PMIC_BIF_LOGIC_0_SET_ADDR MT6358_BIF_CON16
#define PMIC_BIF_LOGIC_0_SET_MASK 0xF
#define PMIC_BIF_LOGIC_0_SET_SHIFT 0
#define PMIC_BIF_LOGIC_1_SET_ADDR MT6358_BIF_CON16
#define PMIC_BIF_LOGIC_1_SET_MASK 0x1F
#define PMIC_BIF_LOGIC_1_SET_SHIFT 4
#define PMIC_BIF_STOP_SET_ADDR  MT6358_BIF_CON16
#define PMIC_BIF_STOP_SET_MASK  0x3F
#define PMIC_BIF_STOP_SET_SHIFT 10
#define PMIC_BIF_DEBOUNCE_EN_ADDR MT6358_BIF_CON17
#define PMIC_BIF_DEBOUNCE_EN_MASK 0x1
#define PMIC_BIF_DEBOUNCE_EN_SHIFT 4
#define PMIC_BIF_READ_EXPECT_NUM_ADDR MT6358_BIF_CON17
#define PMIC_BIF_READ_EXPECT_NUM_MASK 0xF
#define PMIC_BIF_READ_EXPECT_NUM_SHIFT  12
#define PMIC_BIF_TRASACT_TRIGGER_ADDR MT6358_BIF_CON18
#define PMIC_BIF_TRASACT_TRIGGER_MASK 0x1
#define PMIC_BIF_TRASACT_TRIGGER_SHIFT  0
#define PMIC_BIF_DATA_NUM_ADDR  MT6358_BIF_CON19
#define PMIC_BIF_DATA_NUM_MASK  0xF
#define PMIC_BIF_DATA_NUM_SHIFT 0
#define PMIC_BIF_RESPONSE_ADDR  MT6358_BIF_CON19
#define PMIC_BIF_RESPONSE_MASK  0x1
#define PMIC_BIF_RESPONSE_SHIFT 12
#define PMIC_BIF_DATA_0_ADDR MT6358_BIF_CON20
#define PMIC_BIF_DATA_0_MASK 0xFF
#define PMIC_BIF_DATA_0_SHIFT   0
#define PMIC_BIF_ACK_0_ADDR  MT6358_BIF_CON20
#define PMIC_BIF_ACK_0_MASK  0x1
#define PMIC_BIF_ACK_0_SHIFT 8
#define PMIC_BIF_ERROR_0_ADDR   MT6358_BIF_CON20
#define PMIC_BIF_ERROR_0_MASK   0x1
#define PMIC_BIF_ERROR_0_SHIFT  15
#define PMIC_BIF_DATA_1_ADDR MT6358_BIF_CON21
#define PMIC_BIF_DATA_1_MASK 0xFF
#define PMIC_BIF_DATA_1_SHIFT   0
#define PMIC_BIF_ACK_1_ADDR  MT6358_BIF_CON21
#define PMIC_BIF_ACK_1_MASK  0x1
#define PMIC_BIF_ACK_1_SHIFT 8
#define PMIC_BIF_ERROR_1_ADDR   MT6358_BIF_CON21
#define PMIC_BIF_ERROR_1_MASK   0x1
#define PMIC_BIF_ERROR_1_SHIFT  15
#define PMIC_BIF_DATA_2_ADDR MT6358_BIF_CON22
#define PMIC_BIF_DATA_2_MASK 0xFF
#define PMIC_BIF_DATA_2_SHIFT   0
#define PMIC_BIF_ACK_2_ADDR  MT6358_BIF_CON22
#define PMIC_BIF_ACK_2_MASK  0x1
#define PMIC_BIF_ACK_2_SHIFT 8
#define PMIC_BIF_ERROR_2_ADDR   MT6358_BIF_CON22
#define PMIC_BIF_ERROR_2_MASK   0x1
#define PMIC_BIF_ERROR_2_SHIFT  15
#define PMIC_BIF_DATA_3_ADDR MT6358_BIF_CON23
#define PMIC_BIF_DATA_3_MASK 0xFF
#define PMIC_BIF_DATA_3_SHIFT   0
#define PMIC_BIF_ACK_3_ADDR  MT6358_BIF_CON23
#define PMIC_BIF_ACK_3_MASK  0x1
#define PMIC_BIF_ACK_3_SHIFT 8
#define PMIC_BIF_ERROR_3_ADDR   MT6358_BIF_CON23
#define PMIC_BIF_ERROR_3_MASK   0x1
#define PMIC_BIF_ERROR_3_SHIFT  15
#define PMIC_BIF_DATA_4_ADDR MT6358_BIF_CON24
#define PMIC_BIF_DATA_4_MASK 0xFF
#define PMIC_BIF_DATA_4_SHIFT   0
#define PMIC_BIF_ACK_4_ADDR  MT6358_BIF_CON24
#define PMIC_BIF_ACK_4_MASK  0x1
#define PMIC_BIF_ACK_4_SHIFT 8
#define PMIC_BIF_ERROR_4_ADDR   MT6358_BIF_CON24
#define PMIC_BIF_ERROR_4_MASK   0x1
#define PMIC_BIF_ERROR_4_SHIFT  15
#define PMIC_BIF_DATA_5_ADDR MT6358_BIF_CON25
#define PMIC_BIF_DATA_5_MASK 0xFF
#define PMIC_BIF_DATA_5_SHIFT   0
#define PMIC_BIF_ACK_5_ADDR  MT6358_BIF_CON25
#define PMIC_BIF_ACK_5_MASK  0x1
#define PMIC_BIF_ACK_5_SHIFT 8
#define PMIC_BIF_ERROR_5_ADDR   MT6358_BIF_CON25
#define PMIC_BIF_ERROR_5_MASK   0x1
#define PMIC_BIF_ERROR_5_SHIFT  15
#define PMIC_BIF_DATA_6_ADDR MT6358_BIF_CON26
#define PMIC_BIF_DATA_6_MASK 0xFF
#define PMIC_BIF_DATA_6_SHIFT   0
#define PMIC_BIF_ACK_6_ADDR  MT6358_BIF_CON26
#define PMIC_BIF_ACK_6_MASK  0x1
#define PMIC_BIF_ACK_6_SHIFT 8
#define PMIC_BIF_ERROR_6_ADDR   MT6358_BIF_CON26
#define PMIC_BIF_ERROR_6_MASK   0x1
#define PMIC_BIF_ERROR_6_SHIFT  15
#define PMIC_BIF_DATA_7_ADDR MT6358_BIF_CON27
#define PMIC_BIF_DATA_7_MASK 0xFF
#define PMIC_BIF_DATA_7_SHIFT   0
#define PMIC_BIF_ACK_7_ADDR  MT6358_BIF_CON27
#define PMIC_BIF_ACK_7_MASK  0x1
#define PMIC_BIF_ACK_7_SHIFT 8
#define PMIC_BIF_ERROR_7_ADDR   MT6358_BIF_CON27
#define PMIC_BIF_ERROR_7_MASK   0x1
#define PMIC_BIF_ERROR_7_SHIFT  15
#define PMIC_BIF_DATA_8_ADDR MT6358_BIF_CON28
#define PMIC_BIF_DATA_8_MASK 0xFF
#define PMIC_BIF_DATA_8_SHIFT   0
#define PMIC_BIF_ACK_8_ADDR  MT6358_BIF_CON28
#define PMIC_BIF_ACK_8_MASK  0x1
#define PMIC_BIF_ACK_8_SHIFT 8
#define PMIC_BIF_ERROR_8_ADDR   MT6358_BIF_CON28
#define PMIC_BIF_ERROR_8_MASK   0x1
#define PMIC_BIF_ERROR_8_SHIFT  15
#define PMIC_BIF_DATA_9_ADDR MT6358_BIF_CON29
#define PMIC_BIF_DATA_9_MASK 0xFF
#define PMIC_BIF_DATA_9_SHIFT   0
#define PMIC_BIF_ACK_9_ADDR  MT6358_BIF_CON29
#define PMIC_BIF_ACK_9_MASK  0x1
#define PMIC_BIF_ACK_9_SHIFT 8
#define PMIC_BIF_ERROR_9_ADDR   MT6358_BIF_CON29
#define PMIC_BIF_ERROR_9_MASK   0x1
#define PMIC_BIF_ERROR_9_SHIFT  15
#define PMIC_BIF_TEST_MODE0_ADDR  MT6358_BIF_CON30
#define PMIC_BIF_TEST_MODE0_MASK  0x1
#define PMIC_BIF_TEST_MODE0_SHIFT 0
#define PMIC_BIF_TEST_MODE1_ADDR  MT6358_BIF_CON30
#define PMIC_BIF_TEST_MODE1_MASK  0x1
#define PMIC_BIF_TEST_MODE1_SHIFT 1
#define PMIC_BIF_TEST_MODE2_ADDR  MT6358_BIF_CON30
#define PMIC_BIF_TEST_MODE2_MASK  0x1
#define PMIC_BIF_TEST_MODE2_SHIFT 2
#define PMIC_BIF_TEST_MODE3_ADDR  MT6358_BIF_CON30
#define PMIC_BIF_TEST_MODE3_MASK  0x1
#define PMIC_BIF_TEST_MODE3_SHIFT 3
#define PMIC_BIF_TEST_MODE4_ADDR  MT6358_BIF_CON30
#define PMIC_BIF_TEST_MODE4_MASK  0x1
#define PMIC_BIF_TEST_MODE4_SHIFT 4
#define PMIC_BIF_TEST_MODE5_ADDR  MT6358_BIF_CON30
#define PMIC_BIF_TEST_MODE5_MASK  0x1
#define PMIC_BIF_TEST_MODE5_SHIFT 5
#define PMIC_BIF_TEST_MODE6_ADDR  MT6358_BIF_CON30
#define PMIC_BIF_TEST_MODE6_MASK  0x1
#define PMIC_BIF_TEST_MODE6_SHIFT 6
#define PMIC_BIF_TEST_MODE7_ADDR  MT6358_BIF_CON30
#define PMIC_BIF_TEST_MODE7_MASK  0x1
#define PMIC_BIF_TEST_MODE7_SHIFT 7
#define PMIC_BIF_TEST_MODE8_ADDR  MT6358_BIF_CON30
#define PMIC_BIF_TEST_MODE8_MASK  0x1
#define PMIC_BIF_TEST_MODE8_SHIFT 8
#define PMIC_BIF_BAT_LOST_SW_ADDR MT6358_BIF_CON30
#define PMIC_BIF_BAT_LOST_SW_MASK 0x1
#define PMIC_BIF_BAT_LOST_SW_SHIFT 11
#define PMIC_BIF_RX_DATA_SW_ADDR  MT6358_BIF_CON30
#define PMIC_BIF_RX_DATA_SW_MASK  0x1
#define PMIC_BIF_RX_DATA_SW_SHIFT 12
#define PMIC_BIF_TX_DATA_SW_ADDR  MT6358_BIF_CON30
#define PMIC_BIF_TX_DATA_SW_MASK  0x1
#define PMIC_BIF_TX_DATA_SW_SHIFT 13
#define PMIC_BIF_RX_EN_SW_ADDR  MT6358_BIF_CON30
#define PMIC_BIF_RX_EN_SW_MASK  0x1
#define PMIC_BIF_RX_EN_SW_SHIFT 14
#define PMIC_BIF_TX_EN_SW_ADDR  MT6358_BIF_CON30
#define PMIC_BIF_TX_EN_SW_MASK  0x1
#define PMIC_BIF_TX_EN_SW_SHIFT 15
#define PMIC_BIF_BACK_NORMAL_ADDR MT6358_BIF_CON31
#define PMIC_BIF_BACK_NORMAL_MASK 0x1
#define PMIC_BIF_BACK_NORMAL_SHIFT 0
#define PMIC_BIF_IRQ_CLR_ADDR   MT6358_BIF_CON31
#define PMIC_BIF_IRQ_CLR_MASK   0x1
#define PMIC_BIF_IRQ_CLR_SHIFT  1
#define PMIC_BIF_IRQ_ADDR MT6358_BIF_CON31
#define PMIC_BIF_IRQ_MASK 0x1
#define PMIC_BIF_IRQ_SHIFT  11
#define PMIC_BIF_TIMEOUT_ADDR   MT6358_BIF_CON31
#define PMIC_BIF_TIMEOUT_MASK   0x1
#define PMIC_BIF_TIMEOUT_SHIFT  12
#define PMIC_BIF_BAT_UNDET_ADDR MT6358_BIF_CON31
#define PMIC_BIF_BAT_UNDET_MASK 0x1
#define PMIC_BIF_BAT_UNDET_SHIFT  13
#define PMIC_BIF_TOTAL_VALID_ADDR MT6358_BIF_CON31
#define PMIC_BIF_TOTAL_VALID_MASK 0x1
#define PMIC_BIF_TOTAL_VALID_SHIFT 14
#define PMIC_BIF_BUS_STATUS_ADDR  MT6358_BIF_CON31
#define PMIC_BIF_BUS_STATUS_MASK  0x1
#define PMIC_BIF_BUS_STATUS_SHIFT 15
#define PMIC_BIF_POWER_UP_COUNT_ADDR  MT6358_BIF_CON32
#define PMIC_BIF_POWER_UP_COUNT_MASK  0x1F
#define PMIC_BIF_POWER_UP_COUNT_SHIFT 0
#define PMIC_BIF_POWER_UP_ADDR  MT6358_BIF_CON32
#define PMIC_BIF_POWER_UP_MASK  0x1
#define PMIC_BIF_POWER_UP_SHIFT 15
#define PMIC_BIF_RX_ERROR_UNKNOWN_ADDR  MT6358_BIF_CON33
#define PMIC_BIF_RX_ERROR_UNKNOWN_MASK  0x1
#define PMIC_BIF_RX_ERROR_UNKNOWN_SHIFT 2
#define PMIC_BIF_RX_ERROR_INSUFF_ADDR MT6358_BIF_CON33
#define PMIC_BIF_RX_ERROR_INSUFF_MASK 0x1
#define PMIC_BIF_RX_ERROR_INSUFF_SHIFT  3
#define PMIC_BIF_RX_ERROR_LOWPHASE_ADDR MT6358_BIF_CON33
#define PMIC_BIF_RX_ERROR_LOWPHASE_MASK 0x1
#define PMIC_BIF_RX_ERROR_LOWPHASE_SHIFT   4
#define PMIC_BIF_RX_STATE_ADDR  MT6358_BIF_CON33
#define PMIC_BIF_RX_STATE_MASK  0x7
#define PMIC_BIF_RX_STATE_SHIFT 5
#define PMIC_BIF_FLOW_CTL_STATE_ADDR  MT6358_BIF_CON33
#define PMIC_BIF_FLOW_CTL_STATE_MASK  0x3
#define PMIC_BIF_FLOW_CTL_STATE_SHIFT 8
#define PMIC_BIF_TX_STATE_ADDR  MT6358_BIF_CON33
#define PMIC_BIF_TX_STATE_MASK  0x3
#define PMIC_BIF_TX_STATE_SHIFT 10
#define PMIC_BIF_TX_DATA_FIANL_ADDR   MT6358_BIF_CON34
#define PMIC_BIF_TX_DATA_FIANL_MASK   0xFFFF
#define PMIC_BIF_TX_DATA_FIANL_SHIFT  0
#define PMIC_BIF_RX_DATA_SAMPLING_ADDR  MT6358_BIF_CON35
#define PMIC_BIF_RX_DATA_SAMPLING_MASK  0xFFFF
#define PMIC_BIF_RX_DATA_SAMPLING_SHIFT 0
#define PMIC_BIF_RX_DATA_RECOVERY_ADDR  MT6358_BIF_CON36
#define PMIC_BIF_RX_DATA_RECOVERY_MASK  0x3FFF
#define PMIC_BIF_RX_DATA_RECOVERY_SHIFT 0
#define PMIC_RG_BATON_HT_EN_PRE_ADDR  MT6358_BIF_CON36
#define PMIC_RG_BATON_HT_EN_PRE_MASK  0x1
#define PMIC_RG_BATON_HT_EN_PRE_SHIFT 14
#define PMIC_RG_BATON_HT_EN_DLY_TIME_ADDR   MT6358_BIF_CON36
#define PMIC_RG_BATON_HT_EN_DLY_TIME_MASK   0x1
#define PMIC_RG_BATON_HT_EN_DLY_TIME_SHIFT  15
#define PMIC_BIF_TIMEOUT_SET_ADDR MT6358_BIF_CON37
#define PMIC_BIF_TIMEOUT_SET_MASK 0xFFFF
#define PMIC_BIF_TIMEOUT_SET_SHIFT 0
#define PMIC_BIF_RX_DEG_WND_ADDR  MT6358_BIF_CON38
#define PMIC_BIF_RX_DEG_WND_MASK  0x7FF
#define PMIC_BIF_RX_DEG_WND_SHIFT 0
#define PMIC_BIF_RX_DEG_EN_ADDR MT6358_BIF_CON38
#define PMIC_BIF_RX_DEG_EN_MASK 0x1
#define PMIC_BIF_RX_DEG_EN_SHIFT  15
#define PMIC_BIF_RSV1_ADDR  MT6358_BIF_CON39
#define PMIC_BIF_RSV1_MASK  0xFF
#define PMIC_BIF_RSV1_SHIFT  0
#define PMIC_BIF_RSV0_ADDR  MT6358_BIF_CON39
#define PMIC_BIF_RSV0_MASK  0xFF
#define PMIC_BIF_RSV0_SHIFT  8
#define PMIC_HK_TOP_ANA_ID_ADDR MT6358_HK_TOP_ID
#define PMIC_HK_TOP_ANA_ID_MASK 0xFF
#define PMIC_HK_TOP_ANA_ID_SHIFT  0
#define PMIC_HK_TOP_DIG_ID_ADDR MT6358_HK_TOP_ID
#define PMIC_HK_TOP_DIG_ID_MASK 0xFF
#define PMIC_HK_TOP_DIG_ID_SHIFT  8
#define PMIC_HK_TOP_ANA_MINOR_REV_ADDR  MT6358_HK_TOP_REV0
#define PMIC_HK_TOP_ANA_MINOR_REV_MASK  0xF
#define PMIC_HK_TOP_ANA_MINOR_REV_SHIFT 0
#define PMIC_HK_TOP_ANA_MAJOR_REV_ADDR  MT6358_HK_TOP_REV0
#define PMIC_HK_TOP_ANA_MAJOR_REV_MASK  0xF
#define PMIC_HK_TOP_ANA_MAJOR_REV_SHIFT 4
#define PMIC_HK_TOP_DIG_MINOR_REV_ADDR  MT6358_HK_TOP_REV0
#define PMIC_HK_TOP_DIG_MINOR_REV_MASK  0xF
#define PMIC_HK_TOP_DIG_MINOR_REV_SHIFT 8
#define PMIC_HK_TOP_DIG_MAJOR_REV_ADDR  MT6358_HK_TOP_REV0
#define PMIC_HK_TOP_DIG_MAJOR_REV_MASK  0xF
#define PMIC_HK_TOP_DIG_MAJOR_REV_SHIFT 12
#define PMIC_HK_TOP_CBS_ADDR MT6358_HK_TOP_DBI
#define PMIC_HK_TOP_CBS_MASK 0x3
#define PMIC_HK_TOP_CBS_SHIFT   0
#define PMIC_HK_TOP_BIX_ADDR MT6358_HK_TOP_DBI
#define PMIC_HK_TOP_BIX_MASK 0x3
#define PMIC_HK_TOP_BIX_SHIFT   2
#define PMIC_HK_TOP_ESP_ADDR MT6358_HK_TOP_DBI
#define PMIC_HK_TOP_ESP_MASK 0xFF
#define PMIC_HK_TOP_ESP_SHIFT   8
#define PMIC_HK_TOP_FPI_ADDR MT6358_HK_TOP_DXI
#define PMIC_HK_TOP_FPI_MASK 0xFF
#define PMIC_HK_TOP_FPI_SHIFT   0
#define PMIC_HK_CLK_OFFSET_ADDR MT6358_HK_TPM0
#define PMIC_HK_CLK_OFFSET_MASK 0xFF
#define PMIC_HK_CLK_OFFSET_SHIFT  0
#define PMIC_HK_RST_OFFSET_ADDR MT6358_HK_TPM0
#define PMIC_HK_RST_OFFSET_MASK 0xFF
#define PMIC_HK_RST_OFFSET_SHIFT  8
#define PMIC_HK_INT_OFFSET_ADDR MT6358_HK_TPM1
#define PMIC_HK_INT_OFFSET_MASK 0xFF
#define PMIC_HK_INT_OFFSET_SHIFT  0
#define PMIC_HK_INT_LEN_ADDR MT6358_HK_TPM1
#define PMIC_HK_INT_LEN_MASK 0xFF
#define PMIC_HK_INT_LEN_SHIFT   8
#define PMIC_RG_AUXADC_AO_1M_CK_PDN_ADDR   MT6358_HK_TOP_CLK_CON0
#define PMIC_RG_AUXADC_AO_1M_CK_PDN_MASK   0x1
#define PMIC_RG_AUXADC_AO_1M_CK_PDN_SHIFT   0
#define PMIC_RG_AUXADC_1M_CK_PDN_HWEN_ADDR  MT6358_HK_TOP_CLK_CON0
#define PMIC_RG_AUXADC_1M_CK_PDN_HWEN_MASK  0x1
#define PMIC_RG_AUXADC_1M_CK_PDN_HWEN_SHIFT 1
#define PMIC_RG_AUXADC_1M_CK_PDN_ADDR MT6358_HK_TOP_CLK_CON0
#define PMIC_RG_AUXADC_1M_CK_PDN_MASK 0x1
#define PMIC_RG_AUXADC_1M_CK_PDN_SHIFT  2
#define PMIC_RG_AUXADC_CK_PDN_HWEN_ADDR MT6358_HK_TOP_CLK_CON0
#define PMIC_RG_AUXADC_CK_PDN_HWEN_MASK 0x1
#define PMIC_RG_AUXADC_CK_PDN_HWEN_SHIFT   3
#define PMIC_RG_AUXADC_CK_PDN_ADDR MT6358_HK_TOP_CLK_CON0
#define PMIC_RG_AUXADC_CK_PDN_MASK 0x1
#define PMIC_RG_AUXADC_CK_PDN_SHIFT   4
#define PMIC_RG_AUXADC_RNG_CK_PDN_HWEN_ADDR MT6358_HK_TOP_CLK_CON0
#define PMIC_RG_AUXADC_RNG_CK_PDN_HWEN_MASK 0x1
#define PMIC_RG_AUXADC_RNG_CK_PDN_HWEN_SHIFT  5
#define PMIC_RG_AUXADC_RNG_CK_PDN_ADDR  MT6358_HK_TOP_CLK_CON0
#define PMIC_RG_AUXADC_RNG_CK_PDN_MASK  0x1
#define PMIC_RG_AUXADC_RNG_CK_PDN_SHIFT 6
#define PMIC_RG_AUXADC_32K_CK_PDN_HWEN_ADDR MT6358_HK_TOP_CLK_CON0
#define PMIC_RG_AUXADC_32K_CK_PDN_HWEN_MASK 0x1
#define PMIC_RG_AUXADC_32K_CK_PDN_HWEN_SHIFT  7
#define PMIC_RG_AUXADC_32K_CK_PDN_ADDR  MT6358_HK_TOP_CLK_CON0
#define PMIC_RG_AUXADC_32K_CK_PDN_MASK  0x1
#define PMIC_RG_AUXADC_32K_CK_PDN_SHIFT 8
#define PMIC_RG_AUXADC_1K_CK_PDN_HWEN_ADDR  MT6358_HK_TOP_CLK_CON0
#define PMIC_RG_AUXADC_1K_CK_PDN_HWEN_MASK  0x1
#define PMIC_RG_AUXADC_1K_CK_PDN_HWEN_SHIFT 9
#define PMIC_RG_AUXADC_1K_CK_PDN_ADDR MT6358_HK_TOP_CLK_CON0
#define PMIC_RG_AUXADC_1K_CK_PDN_MASK 0x1
#define PMIC_RG_AUXADC_1K_CK_PDN_SHIFT  10
#define PMIC_RG_HK_INTRP_CK_PDN_HWEN_ADDR   MT6358_HK_TOP_CLK_CON0
#define PMIC_RG_HK_INTRP_CK_PDN_HWEN_MASK   0x1
#define PMIC_RG_HK_INTRP_CK_PDN_HWEN_SHIFT  11
#define PMIC_RG_HK_INTRP_CK_PDN_ADDR  MT6358_HK_TOP_CLK_CON0
#define PMIC_RG_HK_INTRP_CK_PDN_MASK  0x1
#define PMIC_RG_HK_INTRP_CK_PDN_SHIFT 12
#define PMIC_RG_AUXADC_CK_DIVSEL_ADDR MT6358_HK_TOP_CLK_CON1
#define PMIC_RG_AUXADC_CK_DIVSEL_MASK 0x1
#define PMIC_RG_AUXADC_CK_DIVSEL_SHIFT  0
#define PMIC_RG_AUXADC_CK_TSTSEL_ADDR MT6358_HK_TOP_CLK_CON1
#define PMIC_RG_AUXADC_CK_TSTSEL_MASK 0x1
#define PMIC_RG_AUXADC_CK_TSTSEL_SHIFT  1
#define PMIC_RG_AUXADC_RST_ADDR MT6358_HK_TOP_RST_CON0
#define PMIC_RG_AUXADC_RST_MASK 0x1
#define PMIC_RG_AUXADC_RST_SHIFT  0
#define PMIC_RG_AUXADC_REG_RST_ADDR   MT6358_HK_TOP_RST_CON0
#define PMIC_RG_AUXADC_REG_RST_MASK   0x1
#define PMIC_RG_AUXADC_REG_RST_SHIFT  1
#define PMIC_BANK_HK_TOP_SWRST_ADDR   MT6358_HK_TOP_RST_CON0
#define PMIC_BANK_HK_TOP_SWRST_MASK   0x1
#define PMIC_BANK_HK_TOP_SWRST_SHIFT  2
#define PMIC_BANK_AUXADC_SWRST_ADDR   MT6358_HK_TOP_RST_CON0
#define PMIC_BANK_AUXADC_SWRST_MASK   0x1
#define PMIC_BANK_AUXADC_SWRST_SHIFT  3
#define PMIC_BANK_AUXADC_DIG_1_SWRST_ADDR   MT6358_HK_TOP_RST_CON0
#define PMIC_BANK_AUXADC_DIG_1_SWRST_MASK   0x1
#define PMIC_BANK_AUXADC_DIG_1_SWRST_SHIFT  4
#define PMIC_BANK_AUXADC_DIG_2_SWRST_ADDR   MT6358_HK_TOP_RST_CON0
#define PMIC_BANK_AUXADC_DIG_2_SWRST_MASK   0x1
#define PMIC_BANK_AUXADC_DIG_2_SWRST_SHIFT  5
#define PMIC_BANK_AUXADC_DIG_3_SWRST_ADDR   MT6358_HK_TOP_RST_CON0
#define PMIC_BANK_AUXADC_DIG_3_SWRST_MASK   0x1
#define PMIC_BANK_AUXADC_DIG_3_SWRST_SHIFT  6
#define PMIC_BANK_AUXADC_DIG_4_SWRST_ADDR   MT6358_HK_TOP_RST_CON0
#define PMIC_BANK_AUXADC_DIG_4_SWRST_MASK   0x1
#define PMIC_BANK_AUXADC_DIG_4_SWRST_SHIFT  7
#define PMIC_RG_INT_EN_BAT_H_ADDR MT6358_HK_TOP_INT_CON0
#define PMIC_RG_INT_EN_BAT_H_MASK 0x1
#define PMIC_RG_INT_EN_BAT_H_SHIFT 0
#define PMIC_RG_INT_EN_BAT_L_ADDR MT6358_HK_TOP_INT_CON0
#define PMIC_RG_INT_EN_BAT_L_MASK 0x1
#define PMIC_RG_INT_EN_BAT_L_SHIFT 1
#define PMIC_RG_INT_EN_BAT2_H_ADDR MT6358_HK_TOP_INT_CON0
#define PMIC_RG_INT_EN_BAT2_H_MASK 0x1
#define PMIC_RG_INT_EN_BAT2_H_SHIFT   2
#define PMIC_RG_INT_EN_BAT2_L_ADDR MT6358_HK_TOP_INT_CON0
#define PMIC_RG_INT_EN_BAT2_L_MASK 0x1
#define PMIC_RG_INT_EN_BAT2_L_SHIFT   3
#define PMIC_RG_INT_EN_BAT_TEMP_H_ADDR  MT6358_HK_TOP_INT_CON0
#define PMIC_RG_INT_EN_BAT_TEMP_H_MASK  0x1
#define PMIC_RG_INT_EN_BAT_TEMP_H_SHIFT 4
#define PMIC_RG_INT_EN_BAT_TEMP_L_ADDR  MT6358_HK_TOP_INT_CON0
#define PMIC_RG_INT_EN_BAT_TEMP_L_MASK  0x1
#define PMIC_RG_INT_EN_BAT_TEMP_L_SHIFT 5
#define PMIC_RG_INT_EN_AUXADC_IMP_ADDR  MT6358_HK_TOP_INT_CON0
#define PMIC_RG_INT_EN_AUXADC_IMP_MASK  0x1
#define PMIC_RG_INT_EN_AUXADC_IMP_SHIFT 6
#define PMIC_RG_INT_EN_NAG_C_DLTV_ADDR  MT6358_HK_TOP_INT_CON0
#define PMIC_RG_INT_EN_NAG_C_DLTV_MASK  0x1
#define PMIC_RG_INT_EN_NAG_C_DLTV_SHIFT 7
#define PMIC_HK_INT_CON0_SET_ADDR MT6358_HK_TOP_INT_CON0_SET
#define PMIC_HK_INT_CON0_SET_MASK 0xFFFF
#define PMIC_HK_INT_CON0_SET_SHIFT 0
#define PMIC_HK_INT_CON0_CLR_ADDR MT6358_HK_TOP_INT_CON0_CLR
#define PMIC_HK_INT_CON0_CLR_MASK 0xFFFF
#define PMIC_HK_INT_CON0_CLR_SHIFT 0
#define PMIC_RG_INT_MASK_BAT_H_ADDR   MT6358_HK_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_BAT_H_MASK   0x1
#define PMIC_RG_INT_MASK_BAT_H_SHIFT  0
#define PMIC_RG_INT_MASK_BAT_L_ADDR   MT6358_HK_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_BAT_L_MASK   0x1
#define PMIC_RG_INT_MASK_BAT_L_SHIFT  1
#define PMIC_RG_INT_MASK_BAT2_H_ADDR  MT6358_HK_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_BAT2_H_MASK  0x1
#define PMIC_RG_INT_MASK_BAT2_H_SHIFT 2
#define PMIC_RG_INT_MASK_BAT2_L_ADDR  MT6358_HK_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_BAT2_L_MASK  0x1
#define PMIC_RG_INT_MASK_BAT2_L_SHIFT 3
#define PMIC_RG_INT_MASK_BAT_TEMP_H_ADDR   MT6358_HK_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_BAT_TEMP_H_MASK   0x1
#define PMIC_RG_INT_MASK_BAT_TEMP_H_SHIFT   4
#define PMIC_RG_INT_MASK_BAT_TEMP_L_ADDR   MT6358_HK_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_BAT_TEMP_L_MASK   0x1
#define PMIC_RG_INT_MASK_BAT_TEMP_L_SHIFT   5
#define PMIC_RG_INT_MASK_AUXADC_IMP_ADDR   MT6358_HK_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_AUXADC_IMP_MASK   0x1
#define PMIC_RG_INT_MASK_AUXADC_IMP_SHIFT   6
#define PMIC_RG_INT_MASK_NAG_C_DLTV_ADDR   MT6358_HK_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_NAG_C_DLTV_MASK   0x1
#define PMIC_RG_INT_MASK_NAG_C_DLTV_SHIFT   7
#define PMIC_HK_INT_MASK_CON0_SET_ADDR  MT6358_HK_TOP_INT_MASK_CON0_SET
#define PMIC_HK_INT_MASK_CON0_SET_MASK  0xFFFF
#define PMIC_HK_INT_MASK_CON0_SET_SHIFT 0
#define PMIC_HK_INT_MASK_CON0_CLR_ADDR  MT6358_HK_TOP_INT_MASK_CON0_CLR
#define PMIC_HK_INT_MASK_CON0_CLR_MASK  0xFFFF
#define PMIC_HK_INT_MASK_CON0_CLR_SHIFT 0
#define PMIC_RG_INT_STATUS_BAT_H_ADDR MT6358_HK_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_BAT_H_MASK 0x1
#define PMIC_RG_INT_STATUS_BAT_H_SHIFT  0
#define PMIC_RG_INT_STATUS_BAT_L_ADDR MT6358_HK_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_BAT_L_MASK 0x1
#define PMIC_RG_INT_STATUS_BAT_L_SHIFT  1
#define PMIC_RG_INT_STATUS_BAT2_H_ADDR  MT6358_HK_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_BAT2_H_MASK  0x1
#define PMIC_RG_INT_STATUS_BAT2_H_SHIFT 2
#define PMIC_RG_INT_STATUS_BAT2_L_ADDR  MT6358_HK_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_BAT2_L_MASK  0x1
#define PMIC_RG_INT_STATUS_BAT2_L_SHIFT 3
#define PMIC_RG_INT_STATUS_BAT_TEMP_H_ADDR  MT6358_HK_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_BAT_TEMP_H_MASK  0x1
#define PMIC_RG_INT_STATUS_BAT_TEMP_H_SHIFT 4
#define PMIC_RG_INT_STATUS_BAT_TEMP_L_ADDR  MT6358_HK_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_BAT_TEMP_L_MASK  0x1
#define PMIC_RG_INT_STATUS_BAT_TEMP_L_SHIFT 5
#define PMIC_RG_INT_STATUS_AUXADC_IMP_ADDR  MT6358_HK_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_AUXADC_IMP_MASK  0x1
#define PMIC_RG_INT_STATUS_AUXADC_IMP_SHIFT 6
#define PMIC_RG_INT_STATUS_NAG_C_DLTV_ADDR  MT6358_HK_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_NAG_C_DLTV_MASK  0x1
#define PMIC_RG_INT_STATUS_NAG_C_DLTV_SHIFT 7
#define PMIC_RG_INT_RAW_STATUS_BAT_H_ADDR   MT6358_HK_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_BAT_H_MASK   0x1
#define PMIC_RG_INT_RAW_STATUS_BAT_H_SHIFT  0
#define PMIC_RG_INT_RAW_STATUS_BAT_L_ADDR   MT6358_HK_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_BAT_L_MASK   0x1
#define PMIC_RG_INT_RAW_STATUS_BAT_L_SHIFT  1
#define PMIC_RG_INT_RAW_STATUS_BAT2_H_ADDR  MT6358_HK_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_BAT2_H_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_BAT2_H_SHIFT 2
#define PMIC_RG_INT_RAW_STATUS_BAT2_L_ADDR  MT6358_HK_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_BAT2_L_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_BAT2_L_SHIFT 3
#define PMIC_RG_INT_RAW_STATUS_BAT_TEMP_H_ADDR   MT6358_HK_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_BAT_TEMP_H_MASK   0x1
#define PMIC_RG_INT_RAW_STATUS_BAT_TEMP_H_SHIFT  4
#define PMIC_RG_INT_RAW_STATUS_BAT_TEMP_L_ADDR   MT6358_HK_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_BAT_TEMP_L_MASK   0x1
#define PMIC_RG_INT_RAW_STATUS_BAT_TEMP_L_SHIFT  5
#define PMIC_RG_INT_RAW_STATUS_AUXADC_IMP_ADDR   MT6358_HK_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_AUXADC_IMP_MASK   0x1
#define PMIC_RG_INT_RAW_STATUS_AUXADC_IMP_SHIFT  6
#define PMIC_RG_INT_RAW_STATUS_NAG_C_DLTV_ADDR   MT6358_HK_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_NAG_C_DLTV_MASK   0x1
#define PMIC_RG_INT_RAW_STATUS_NAG_C_DLTV_SHIFT  7
#define PMIC_RG_CLK_MON_FLAG_EN_ADDR  MT6358_HK_TOP_MON_CON0
#define PMIC_RG_CLK_MON_FLAG_EN_MASK  0x1
#define PMIC_RG_CLK_MON_FLAG_EN_SHIFT 0
#define PMIC_RG_CLK_MON_FLAG_SEL_ADDR MT6358_HK_TOP_MON_CON0
#define PMIC_RG_CLK_MON_FLAG_SEL_MASK 0xFF
#define PMIC_RG_CLK_MON_FLAG_SEL_SHIFT  1
#define PMIC_RG_INT_MON_FLAG_EN_ADDR  MT6358_HK_TOP_MON_CON1
#define PMIC_RG_INT_MON_FLAG_EN_MASK  0x1
#define PMIC_RG_INT_MON_FLAG_EN_SHIFT 0
#define PMIC_RG_INT_MON_FLAG_SEL_ADDR MT6358_HK_TOP_MON_CON1
#define PMIC_RG_INT_MON_FLAG_SEL_MASK 0xFF
#define PMIC_RG_INT_MON_FLAG_SEL_SHIFT  1
#define PMIC_RG_HK_MON_FLAG_SEL_ADDR  MT6358_HK_TOP_MON_CON2
#define PMIC_RG_HK_MON_FLAG_SEL_MASK  0xFF
#define PMIC_RG_HK_MON_FLAG_SEL_SHIFT 0
#define PMIC_RG_MON_FLAG_SEL_AUXADC_ADDR   MT6358_HK_TOP_MON_CON2
#define PMIC_RG_MON_FLAG_SEL_AUXADC_MASK   0x1
#define PMIC_RG_MON_FLAG_SEL_AUXADC_SHIFT   8
#define PMIC_RG_ADCIN_VSEN_MUX_EN_ADDR  MT6358_HK_TOP_CHR_CON
#define PMIC_RG_ADCIN_VSEN_MUX_EN_MASK  0x1
#define PMIC_RG_ADCIN_VSEN_MUX_EN_SHIFT 0
#define PMIC_RG_BATON_TDET_EN_ADDR MT6358_HK_TOP_CHR_CON
#define PMIC_RG_BATON_TDET_EN_MASK 0x1
#define PMIC_RG_BATON_TDET_EN_SHIFT   1
#define PMIC_RG_ADCIN_VSEN_EXT_BATON_EN_ADDR  MT6358_HK_TOP_CHR_CON
#define PMIC_RG_ADCIN_VSEN_EXT_BATON_EN_MASK  0x1
#define PMIC_RG_ADCIN_VSEN_EXT_BATON_EN_SHIFT 2
#define PMIC_RG_ADCIN_VBAT_EN_ADDR MT6358_HK_TOP_CHR_CON
#define PMIC_RG_ADCIN_VBAT_EN_MASK 0x1
#define PMIC_RG_ADCIN_VBAT_EN_SHIFT   3
#define PMIC_RG_ADCIN_VSEN_EN_ADDR MT6358_HK_TOP_CHR_CON
#define PMIC_RG_ADCIN_VSEN_EN_MASK 0x1
#define PMIC_RG_ADCIN_VSEN_EN_SHIFT   4
#define PMIC_RG_ADCIN_CHR_EN_ADDR MT6358_HK_TOP_CHR_CON
#define PMIC_RG_ADCIN_CHR_EN_MASK 0x1
#define PMIC_RG_ADCIN_CHR_EN_SHIFT 5
#define PMIC_DA_ADCIN_VBAT_EN_ADDR MT6358_HK_TOP_AUXADC_ANA
#define PMIC_DA_ADCIN_VBAT_EN_MASK 0x1
#define PMIC_DA_ADCIN_VBAT_EN_SHIFT   0
#define PMIC_DA_AUXADC_VBAT_EN_ADDR   MT6358_HK_TOP_AUXADC_ANA
#define PMIC_DA_AUXADC_VBAT_EN_MASK   0x1
#define PMIC_DA_AUXADC_VBAT_EN_SHIFT  1
#define PMIC_DA_ADCIN_VSEN_MUX_EN_ADDR  MT6358_HK_TOP_AUXADC_ANA
#define PMIC_DA_ADCIN_VSEN_MUX_EN_MASK  0x1
#define PMIC_DA_ADCIN_VSEN_MUX_EN_SHIFT 2
#define PMIC_DA_ADCIN_VSEN_EN_ADDR MT6358_HK_TOP_AUXADC_ANA
#define PMIC_DA_ADCIN_VSEN_EN_MASK 0x1
#define PMIC_DA_ADCIN_VSEN_EN_SHIFT   3
#define PMIC_DA_ADCIN_CHR_EN_ADDR MT6358_HK_TOP_AUXADC_ANA
#define PMIC_DA_ADCIN_CHR_EN_MASK 0x1
#define PMIC_DA_ADCIN_CHR_EN_SHIFT 4
#define PMIC_DA_BATON_TDET_EN_ADDR MT6358_HK_TOP_AUXADC_ANA
#define PMIC_DA_BATON_TDET_EN_MASK 0x1
#define PMIC_DA_BATON_TDET_EN_SHIFT   5
#define PMIC_DA_ADCIN_BATID_SW_EN_ADDR  MT6358_HK_TOP_AUXADC_ANA
#define PMIC_DA_ADCIN_BATID_SW_EN_MASK  0x1
#define PMIC_DA_ADCIN_BATID_SW_EN_SHIFT 6
#define PMIC_AUXADC_ANA_ID_ADDR MT6358_AUXADC_DSN_ID
#define PMIC_AUXADC_ANA_ID_MASK 0xFF
#define PMIC_AUXADC_ANA_ID_SHIFT  0
#define PMIC_AUXADC_DIG_ID_ADDR MT6358_AUXADC_DSN_ID
#define PMIC_AUXADC_DIG_ID_MASK 0xFF
#define PMIC_AUXADC_DIG_ID_SHIFT  8
#define PMIC_AUXADC_ANA_MINOR_REV_ADDR  MT6358_AUXADC_DSN_REV0
#define PMIC_AUXADC_ANA_MINOR_REV_MASK  0xF
#define PMIC_AUXADC_ANA_MINOR_REV_SHIFT 0
#define PMIC_AUXADC_ANA_MAJOR_REV_ADDR  MT6358_AUXADC_DSN_REV0
#define PMIC_AUXADC_ANA_MAJOR_REV_MASK  0xF
#define PMIC_AUXADC_ANA_MAJOR_REV_SHIFT 4
#define PMIC_AUXADC_DIG_MINOR_REV_ADDR  MT6358_AUXADC_DSN_REV0
#define PMIC_AUXADC_DIG_MINOR_REV_MASK  0xF
#define PMIC_AUXADC_DIG_MINOR_REV_SHIFT 8
#define PMIC_AUXADC_DIG_MAJOR_REV_ADDR  MT6358_AUXADC_DSN_REV0
#define PMIC_AUXADC_DIG_MAJOR_REV_MASK  0xF
#define PMIC_AUXADC_DIG_MAJOR_REV_SHIFT 12
#define PMIC_AUXADC_DSN_CBS_ADDR  MT6358_AUXADC_DSN_DBI
#define PMIC_AUXADC_DSN_CBS_MASK  0x3
#define PMIC_AUXADC_DSN_CBS_SHIFT 0
#define PMIC_AUXADC_DSN_BIX_ADDR  MT6358_AUXADC_DSN_DBI
#define PMIC_AUXADC_DSN_BIX_MASK  0x3
#define PMIC_AUXADC_DSN_BIX_SHIFT 2
#define PMIC_AUXADC_DSN_ESP_ADDR  MT6358_AUXADC_DSN_DBI
#define PMIC_AUXADC_DSN_ESP_MASK  0xFF
#define PMIC_AUXADC_DSN_ESP_SHIFT 8
#define PMIC_AUXADC_DSN_FPI_ADDR  MT6358_AUXADC_DSN_FPI
#define PMIC_AUXADC_DSN_FPI_MASK  0xFF
#define PMIC_AUXADC_DSN_FPI_SHIFT 0
#define PMIC_RG_AUXADC_CALI_ADDR  MT6358_AUXADC_ANA_CON0
#define PMIC_RG_AUXADC_CALI_MASK  0xF
#define PMIC_RG_AUXADC_CALI_SHIFT 0
#define PMIC_RG_AUX_RSV_ADDR MT6358_AUXADC_ANA_CON0
#define PMIC_RG_AUX_RSV_MASK 0xF
#define PMIC_RG_AUX_RSV_SHIFT   4
#define PMIC_RG_VBUF_BYP_ADDR   MT6358_AUXADC_ANA_CON0
#define PMIC_RG_VBUF_BYP_MASK   0x1
#define PMIC_RG_VBUF_BYP_SHIFT  8
#define PMIC_RG_VBUF_CALEN_ADDR MT6358_AUXADC_ANA_CON0
#define PMIC_RG_VBUF_CALEN_MASK 0x1
#define PMIC_RG_VBUF_CALEN_SHIFT  9
#define PMIC_RG_VBUF_EXTEN_ADDR MT6358_AUXADC_ANA_CON0
#define PMIC_RG_VBUF_EXTEN_MASK 0x1
#define PMIC_RG_VBUF_EXTEN_SHIFT  10
#define PMIC_AUXADC_DIG_1_ANA_ID_ADDR MT6358_AUXADC_DIG_1_DSN_ID
#define PMIC_AUXADC_DIG_1_ANA_ID_MASK 0xFF
#define PMIC_AUXADC_DIG_1_ANA_ID_SHIFT  0
#define PMIC_AUXADC_DIG_1_DIG_ID_ADDR MT6358_AUXADC_DIG_1_DSN_ID
#define PMIC_AUXADC_DIG_1_DIG_ID_MASK 0xFF
#define PMIC_AUXADC_DIG_1_DIG_ID_SHIFT  8
#define PMIC_AUXADC_DIG_1_ANA_MINOR_REV_ADDR  MT6358_AUXADC_DIG_1_DSN_REV0
#define PMIC_AUXADC_DIG_1_ANA_MINOR_REV_MASK  0xF
#define PMIC_AUXADC_DIG_1_ANA_MINOR_REV_SHIFT 0
#define PMIC_AUXADC_DIG_1_ANA_MAJOR_REV_ADDR  MT6358_AUXADC_DIG_1_DSN_REV0
#define PMIC_AUXADC_DIG_1_ANA_MAJOR_REV_MASK  0xF
#define PMIC_AUXADC_DIG_1_ANA_MAJOR_REV_SHIFT 4
#define PMIC_AUXADC_DIG_1_DIG_MINOR_REV_ADDR  MT6358_AUXADC_DIG_1_DSN_REV0
#define PMIC_AUXADC_DIG_1_DIG_MINOR_REV_MASK  0xF
#define PMIC_AUXADC_DIG_1_DIG_MINOR_REV_SHIFT 8
#define PMIC_AUXADC_DIG_1_DIG_MAJOR_REV_ADDR  MT6358_AUXADC_DIG_1_DSN_REV0
#define PMIC_AUXADC_DIG_1_DIG_MAJOR_REV_MASK  0xF
#define PMIC_AUXADC_DIG_1_DIG_MAJOR_REV_SHIFT 12
#define PMIC_AUXADC_DIG_1_DSN_CBS_ADDR  MT6358_AUXADC_DIG_1_DSN_DBI
#define PMIC_AUXADC_DIG_1_DSN_CBS_MASK  0x3
#define PMIC_AUXADC_DIG_1_DSN_CBS_SHIFT 0
#define PMIC_AUXADC_DIG_1_DSN_BIX_ADDR  MT6358_AUXADC_DIG_1_DSN_DBI
#define PMIC_AUXADC_DIG_1_DSN_BIX_MASK  0x3
#define PMIC_AUXADC_DIG_1_DSN_BIX_SHIFT 2
#define PMIC_AUXADC_DIG_1_DSN_ESP_ADDR  MT6358_AUXADC_DIG_1_DSN_DBI
#define PMIC_AUXADC_DIG_1_DSN_ESP_MASK  0xFF
#define PMIC_AUXADC_DIG_1_DSN_ESP_SHIFT 8
#define PMIC_AUXADC_DIG_1_DSN_FPI_ADDR  MT6358_AUXADC_DIG_1_DSN_DXI
#define PMIC_AUXADC_DIG_1_DSN_FPI_MASK  0xFF
#define PMIC_AUXADC_DIG_1_DSN_FPI_SHIFT 0
#define PMIC_AUXADC_ADC_OUT_CH0_ADDR  MT6358_AUXADC_ADC0
#define PMIC_AUXADC_ADC_OUT_CH0_MASK  0x7FFF
#define PMIC_AUXADC_ADC_OUT_CH0_SHIFT 0
#define PMIC_AUXADC_ADC_RDY_CH0_ADDR  MT6358_AUXADC_ADC0
#define PMIC_AUXADC_ADC_RDY_CH0_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_CH0_SHIFT 15
#define PMIC_AUXADC_ADC_OUT_CH1_ADDR  MT6358_AUXADC_ADC1
#define PMIC_AUXADC_ADC_OUT_CH1_MASK  0x7FFF
#define PMIC_AUXADC_ADC_OUT_CH1_SHIFT 0
#define PMIC_AUXADC_ADC_RDY_CH1_ADDR  MT6358_AUXADC_ADC1
#define PMIC_AUXADC_ADC_RDY_CH1_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_CH1_SHIFT 15
#define PMIC_AUXADC_ADC_OUT_CH2_ADDR  MT6358_AUXADC_ADC2
#define PMIC_AUXADC_ADC_OUT_CH2_MASK  0xFFF
#define PMIC_AUXADC_ADC_OUT_CH2_SHIFT 0
#define PMIC_AUXADC_ADC_RDY_CH2_ADDR  MT6358_AUXADC_ADC2
#define PMIC_AUXADC_ADC_RDY_CH2_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_CH2_SHIFT 15
#define PMIC_AUXADC_ADC_OUT_CH3_ADDR  MT6358_AUXADC_ADC3
#define PMIC_AUXADC_ADC_OUT_CH3_MASK  0xFFF
#define PMIC_AUXADC_ADC_OUT_CH3_SHIFT 0
#define PMIC_AUXADC_ADC_RDY_CH3_ADDR  MT6358_AUXADC_ADC3
#define PMIC_AUXADC_ADC_RDY_CH3_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_CH3_SHIFT 15
#define PMIC_AUXADC_ADC_OUT_CH4_ADDR  MT6358_AUXADC_ADC4
#define PMIC_AUXADC_ADC_OUT_CH4_MASK  0xFFF
#define PMIC_AUXADC_ADC_OUT_CH4_SHIFT 0
#define PMIC_AUXADC_ADC_RDY_CH4_ADDR  MT6358_AUXADC_ADC4
#define PMIC_AUXADC_ADC_RDY_CH4_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_CH4_SHIFT 15
#define PMIC_AUXADC_ADC_OUT_CH5_ADDR  MT6358_AUXADC_ADC5
#define PMIC_AUXADC_ADC_OUT_CH5_MASK  0xFFF
#define PMIC_AUXADC_ADC_OUT_CH5_SHIFT 0
#define PMIC_AUXADC_ADC_RDY_CH5_ADDR  MT6358_AUXADC_ADC5
#define PMIC_AUXADC_ADC_RDY_CH5_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_CH5_SHIFT 15
#define PMIC_AUXADC_ADC_OUT_CH6_ADDR  MT6358_AUXADC_ADC6
#define PMIC_AUXADC_ADC_OUT_CH6_MASK  0xFFF
#define PMIC_AUXADC_ADC_OUT_CH6_SHIFT 0
#define PMIC_AUXADC_ADC_RDY_CH6_ADDR  MT6358_AUXADC_ADC6
#define PMIC_AUXADC_ADC_RDY_CH6_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_CH6_SHIFT 15
#define PMIC_AUXADC_ADC_OUT_CH7_ADDR  MT6358_AUXADC_ADC7
#define PMIC_AUXADC_ADC_OUT_CH7_MASK  0x7FFF
#define PMIC_AUXADC_ADC_OUT_CH7_SHIFT 0
#define PMIC_AUXADC_ADC_RDY_CH7_ADDR  MT6358_AUXADC_ADC7
#define PMIC_AUXADC_ADC_RDY_CH7_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_CH7_SHIFT 15
#define PMIC_AUXADC_ADC_OUT_CH8_ADDR  MT6358_AUXADC_ADC8
#define PMIC_AUXADC_ADC_OUT_CH8_MASK  0xFFF
#define PMIC_AUXADC_ADC_OUT_CH8_SHIFT 0
#define PMIC_AUXADC_ADC_RDY_CH8_ADDR  MT6358_AUXADC_ADC8
#define PMIC_AUXADC_ADC_RDY_CH8_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_CH8_SHIFT 15
#define PMIC_AUXADC_ADC_OUT_CH9_ADDR  MT6358_AUXADC_ADC9
#define PMIC_AUXADC_ADC_OUT_CH9_MASK  0x7FFF
#define PMIC_AUXADC_ADC_OUT_CH9_SHIFT 0
#define PMIC_AUXADC_ADC_RDY_CH9_ADDR  MT6358_AUXADC_ADC9
#define PMIC_AUXADC_ADC_RDY_CH9_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_CH9_SHIFT 15
#define PMIC_AUXADC_ADC_OUT_CH10_ADDR MT6358_AUXADC_ADC10
#define PMIC_AUXADC_ADC_OUT_CH10_MASK 0x7FFF
#define PMIC_AUXADC_ADC_OUT_CH10_SHIFT  0
#define PMIC_AUXADC_ADC_RDY_CH10_ADDR MT6358_AUXADC_ADC10
#define PMIC_AUXADC_ADC_RDY_CH10_MASK 0x1
#define PMIC_AUXADC_ADC_RDY_CH10_SHIFT  15
#define PMIC_AUXADC_ADC_OUT_CH11_ADDR MT6358_AUXADC_ADC11
#define PMIC_AUXADC_ADC_OUT_CH11_MASK 0xFFF
#define PMIC_AUXADC_ADC_OUT_CH11_SHIFT  0
#define PMIC_AUXADC_ADC_RDY_CH11_ADDR MT6358_AUXADC_ADC11
#define PMIC_AUXADC_ADC_RDY_CH11_MASK 0x1
#define PMIC_AUXADC_ADC_RDY_CH11_SHIFT  15
#define PMIC_AUXADC_ADC_OUT_CH12_15_ADDR   MT6358_AUXADC_ADC12
#define PMIC_AUXADC_ADC_OUT_CH12_15_MASK   0x7FFF
#define PMIC_AUXADC_ADC_OUT_CH12_15_SHIFT   0
#define PMIC_AUXADC_ADC_RDY_CH12_15_ADDR   MT6358_AUXADC_ADC12
#define PMIC_AUXADC_ADC_RDY_CH12_15_MASK   0x1
#define PMIC_AUXADC_ADC_RDY_CH12_15_SHIFT   15
#define PMIC_AUXADC_ADC_OUT_LBAT_ADDR MT6358_AUXADC_ADC13
#define PMIC_AUXADC_ADC_OUT_LBAT_MASK 0xFFF
#define PMIC_AUXADC_ADC_OUT_LBAT_SHIFT  0
#define PMIC_AUXADC_ADC_RDY_LBAT_ADDR MT6358_AUXADC_ADC13
#define PMIC_AUXADC_ADC_RDY_LBAT_MASK 0x1
#define PMIC_AUXADC_ADC_RDY_LBAT_SHIFT  15
#define PMIC_AUXADC_ADC_OUT_LBAT2_ADDR  MT6358_AUXADC_ADC14
#define PMIC_AUXADC_ADC_OUT_LBAT2_MASK  0xFFF
#define PMIC_AUXADC_ADC_OUT_LBAT2_SHIFT 0
#define PMIC_AUXADC_ADC_RDY_LBAT2_ADDR  MT6358_AUXADC_ADC14
#define PMIC_AUXADC_ADC_RDY_LBAT2_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_LBAT2_SHIFT 15
#define PMIC_AUXADC_ADC_OUT_CH7_BY_GPS_ADDR MT6358_AUXADC_ADC15
#define PMIC_AUXADC_ADC_OUT_CH7_BY_GPS_MASK 0x7FFF
#define PMIC_AUXADC_ADC_OUT_CH7_BY_GPS_SHIFT  0
#define PMIC_AUXADC_ADC_RDY_CH7_BY_GPS_ADDR MT6358_AUXADC_ADC15
#define PMIC_AUXADC_ADC_RDY_CH7_BY_GPS_MASK 0x1
#define PMIC_AUXADC_ADC_RDY_CH7_BY_GPS_SHIFT  15
#define PMIC_AUXADC_ADC_OUT_CH7_BY_MD_ADDR  MT6358_AUXADC_ADC16
#define PMIC_AUXADC_ADC_OUT_CH7_BY_MD_MASK  0x7FFF
#define PMIC_AUXADC_ADC_OUT_CH7_BY_MD_SHIFT 0
#define PMIC_AUXADC_ADC_RDY_CH7_BY_MD_ADDR  MT6358_AUXADC_ADC16
#define PMIC_AUXADC_ADC_RDY_CH7_BY_MD_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_CH7_BY_MD_SHIFT 15
#define PMIC_AUXADC_ADC_OUT_CH7_BY_AP_ADDR  MT6358_AUXADC_ADC17
#define PMIC_AUXADC_ADC_OUT_CH7_BY_AP_MASK  0x7FFF
#define PMIC_AUXADC_ADC_OUT_CH7_BY_AP_SHIFT 0
#define PMIC_AUXADC_ADC_RDY_CH7_BY_AP_ADDR  MT6358_AUXADC_ADC17
#define PMIC_AUXADC_ADC_RDY_CH7_BY_AP_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_CH7_BY_AP_SHIFT 15
#define PMIC_AUXADC_ADC_OUT_CH4_BY_MD_ADDR  MT6358_AUXADC_ADC18
#define PMIC_AUXADC_ADC_OUT_CH4_BY_MD_MASK  0xFFF
#define PMIC_AUXADC_ADC_OUT_CH4_BY_MD_SHIFT 0
#define PMIC_AUXADC_ADC_RDY_CH4_BY_MD_ADDR  MT6358_AUXADC_ADC18
#define PMIC_AUXADC_ADC_RDY_CH4_BY_MD_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_CH4_BY_MD_SHIFT 15
#define PMIC_AUXADC_ADC_OUT_PWRON_PCHR_ADDR MT6358_AUXADC_ADC19
#define PMIC_AUXADC_ADC_OUT_PWRON_PCHR_MASK 0x7FFF
#define PMIC_AUXADC_ADC_OUT_PWRON_PCHR_SHIFT  0
#define PMIC_AUXADC_ADC_RDY_PWRON_PCHR_ADDR MT6358_AUXADC_ADC19
#define PMIC_AUXADC_ADC_RDY_PWRON_PCHR_MASK 0x1
#define PMIC_AUXADC_ADC_RDY_PWRON_PCHR_SHIFT  15
#define PMIC_AUXADC_ADC_OUT_WAKEUP_PCHR_ADDR  MT6358_AUXADC_ADC20
#define PMIC_AUXADC_ADC_OUT_WAKEUP_PCHR_MASK  0x7FFF
#define PMIC_AUXADC_ADC_OUT_WAKEUP_PCHR_SHIFT 0
#define PMIC_AUXADC_ADC_RDY_WAKEUP_PCHR_ADDR  MT6358_AUXADC_ADC20
#define PMIC_AUXADC_ADC_RDY_WAKEUP_PCHR_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_WAKEUP_PCHR_SHIFT 15
#define PMIC_AUXADC_ADC_OUT_CH0_BY_MD_ADDR  MT6358_AUXADC_ADC21
#define PMIC_AUXADC_ADC_OUT_CH0_BY_MD_MASK  0x7FFF
#define PMIC_AUXADC_ADC_OUT_CH0_BY_MD_SHIFT 0
#define PMIC_AUXADC_ADC_RDY_CH0_BY_MD_ADDR  MT6358_AUXADC_ADC21
#define PMIC_AUXADC_ADC_RDY_CH0_BY_MD_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_CH0_BY_MD_SHIFT 15
#define PMIC_AUXADC_ADC_OUT_CH0_BY_AP_ADDR  MT6358_AUXADC_ADC22
#define PMIC_AUXADC_ADC_OUT_CH0_BY_AP_MASK  0x7FFF
#define PMIC_AUXADC_ADC_OUT_CH0_BY_AP_SHIFT 0
#define PMIC_AUXADC_ADC_RDY_CH0_BY_AP_ADDR  MT6358_AUXADC_ADC22
#define PMIC_AUXADC_ADC_RDY_CH0_BY_AP_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_CH0_BY_AP_SHIFT 15
#define PMIC_AUXADC_ADC_OUT_CH1_BY_MD_ADDR  MT6358_AUXADC_ADC23
#define PMIC_AUXADC_ADC_OUT_CH1_BY_MD_MASK  0x7FFF
#define PMIC_AUXADC_ADC_OUT_CH1_BY_MD_SHIFT 0
#define PMIC_AUXADC_ADC_RDY_CH1_BY_MD_ADDR  MT6358_AUXADC_ADC23
#define PMIC_AUXADC_ADC_RDY_CH1_BY_MD_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_CH1_BY_MD_SHIFT 15
#define PMIC_AUXADC_ADC_OUT_CH1_BY_AP_ADDR  MT6358_AUXADC_ADC24
#define PMIC_AUXADC_ADC_OUT_CH1_BY_AP_MASK  0x7FFF
#define PMIC_AUXADC_ADC_OUT_CH1_BY_AP_SHIFT 0
#define PMIC_AUXADC_ADC_RDY_CH1_BY_AP_ADDR  MT6358_AUXADC_ADC24
#define PMIC_AUXADC_ADC_RDY_CH1_BY_AP_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_CH1_BY_AP_SHIFT 15
#define PMIC_AUXADC_ADC_OUT_BAT_TEMP_ADDR   MT6358_AUXADC_ADC25
#define PMIC_AUXADC_ADC_OUT_BAT_TEMP_MASK   0xFFF
#define PMIC_AUXADC_ADC_OUT_BAT_TEMP_SHIFT  0
#define PMIC_AUXADC_ADC_RDY_BAT_TEMP_ADDR   MT6358_AUXADC_ADC25
#define PMIC_AUXADC_ADC_RDY_BAT_TEMP_MASK   0x1
#define PMIC_AUXADC_ADC_RDY_BAT_TEMP_SHIFT  15
#define PMIC_AUXADC_ADC_OUT_FGADC_PCHR_ADDR MT6358_AUXADC_ADC26
#define PMIC_AUXADC_ADC_OUT_FGADC_PCHR_MASK 0x7FFF
#define PMIC_AUXADC_ADC_OUT_FGADC_PCHR_SHIFT  0
#define PMIC_AUXADC_ADC_RDY_FGADC_PCHR_ADDR MT6358_AUXADC_ADC26
#define PMIC_AUXADC_ADC_RDY_FGADC_PCHR_MASK 0x1
#define PMIC_AUXADC_ADC_RDY_FGADC_PCHR_SHIFT  15
#define PMIC_AUXADC_ADC_OUT_BAT_PLUGIN_PCHR_ADDR  MT6358_AUXADC_ADC27
#define PMIC_AUXADC_ADC_OUT_BAT_PLUGIN_PCHR_MASK  0x7FFF
#define PMIC_AUXADC_ADC_OUT_BAT_PLUGIN_PCHR_SHIFT 0
#define PMIC_AUXADC_ADC_RDY_BAT_PLUGIN_PCHR_ADDR  MT6358_AUXADC_ADC27
#define PMIC_AUXADC_ADC_RDY_BAT_PLUGIN_PCHR_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_BAT_PLUGIN_PCHR_SHIFT 15
#define PMIC_AUXADC_ADC_OUT_IMP_ADDR  MT6358_AUXADC_ADC28
#define PMIC_AUXADC_ADC_OUT_IMP_MASK  0x7FFF
#define PMIC_AUXADC_ADC_OUT_IMP_SHIFT 0
#define PMIC_AUXADC_ADC_RDY_IMP_ADDR  MT6358_AUXADC_ADC28
#define PMIC_AUXADC_ADC_RDY_IMP_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_IMP_SHIFT 15
#define PMIC_AUXADC_ADC_OUT_IMP_AVG_ADDR   MT6358_AUXADC_ADC29
#define PMIC_AUXADC_ADC_OUT_IMP_AVG_MASK   0x7FFF
#define PMIC_AUXADC_ADC_OUT_IMP_AVG_SHIFT   0
#define PMIC_AUXADC_ADC_RDY_IMP_AVG_ADDR   MT6358_AUXADC_ADC29
#define PMIC_AUXADC_ADC_RDY_IMP_AVG_MASK   0x1
#define PMIC_AUXADC_ADC_RDY_IMP_AVG_SHIFT   15
#define PMIC_AUXADC_ADC_OUT_RAW_ADDR  MT6358_AUXADC_ADC30
#define PMIC_AUXADC_ADC_OUT_RAW_MASK  0x7FFF
#define PMIC_AUXADC_ADC_OUT_RAW_SHIFT 0
#define PMIC_AUXADC_ADC_OUT_MDRT_ADDR MT6358_AUXADC_ADC31
#define PMIC_AUXADC_ADC_OUT_MDRT_MASK 0x7FFF
#define PMIC_AUXADC_ADC_OUT_MDRT_SHIFT  0
#define PMIC_AUXADC_ADC_RDY_MDRT_ADDR MT6358_AUXADC_ADC31
#define PMIC_AUXADC_ADC_RDY_MDRT_MASK 0x1
#define PMIC_AUXADC_ADC_RDY_MDRT_SHIFT  15
#define PMIC_AUXADC_ADC_OUT_DCXO_BY_GPS_ADDR  MT6358_AUXADC_ADC32
#define PMIC_AUXADC_ADC_OUT_DCXO_BY_GPS_MASK  0x7FFF
#define PMIC_AUXADC_ADC_OUT_DCXO_BY_GPS_SHIFT 0
#define PMIC_AUXADC_ADC_RDY_DCXO_BY_GPS_ADDR  MT6358_AUXADC_ADC32
#define PMIC_AUXADC_ADC_RDY_DCXO_BY_GPS_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_DCXO_BY_GPS_SHIFT 15
#define PMIC_AUXADC_ADC_OUT_DCXO_BY_MD_ADDR MT6358_AUXADC_ADC33
#define PMIC_AUXADC_ADC_OUT_DCXO_BY_MD_MASK 0x7FFF
#define PMIC_AUXADC_ADC_OUT_DCXO_BY_MD_SHIFT  0
#define PMIC_AUXADC_ADC_RDY_DCXO_BY_MD_ADDR MT6358_AUXADC_ADC33
#define PMIC_AUXADC_ADC_RDY_DCXO_BY_MD_MASK 0x1
#define PMIC_AUXADC_ADC_RDY_DCXO_BY_MD_SHIFT  15
#define PMIC_AUXADC_ADC_OUT_DCXO_BY_AP_ADDR MT6358_AUXADC_ADC34
#define PMIC_AUXADC_ADC_OUT_DCXO_BY_AP_MASK 0x7FFF
#define PMIC_AUXADC_ADC_OUT_DCXO_BY_AP_SHIFT  0
#define PMIC_AUXADC_ADC_RDY_DCXO_BY_AP_ADDR MT6358_AUXADC_ADC34
#define PMIC_AUXADC_ADC_RDY_DCXO_BY_AP_MASK 0x1
#define PMIC_AUXADC_ADC_RDY_DCXO_BY_AP_SHIFT  15
#define PMIC_AUXADC_ADC_OUT_DCXO_MDRT_ADDR  MT6358_AUXADC_ADC35
#define PMIC_AUXADC_ADC_OUT_DCXO_MDRT_MASK  0x7FFF
#define PMIC_AUXADC_ADC_OUT_DCXO_MDRT_SHIFT 0
#define PMIC_AUXADC_ADC_RDY_DCXO_MDRT_ADDR  MT6358_AUXADC_ADC35
#define PMIC_AUXADC_ADC_RDY_DCXO_MDRT_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_DCXO_MDRT_SHIFT 15
#define PMIC_AUXADC_ADC_OUT_NAG_ADDR  MT6358_AUXADC_ADC36
#define PMIC_AUXADC_ADC_OUT_NAG_MASK  0x7FFF
#define PMIC_AUXADC_ADC_OUT_NAG_SHIFT 0
#define PMIC_AUXADC_ADC_RDY_NAG_ADDR  MT6358_AUXADC_ADC36
#define PMIC_AUXADC_ADC_RDY_NAG_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_NAG_SHIFT 15
#define PMIC_AUXADC_ADC_OUT_BATID_ADDR  MT6358_AUXADC_ADC37
#define PMIC_AUXADC_ADC_OUT_BATID_MASK  0xFFF
#define PMIC_AUXADC_ADC_OUT_BATID_SHIFT 0
#define PMIC_AUXADC_ADC_RDY_BATID_ADDR  MT6358_AUXADC_ADC37
#define PMIC_AUXADC_ADC_RDY_BATID_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_BATID_SHIFT 15
#define PMIC_AUXADC_ADC_OUT_CH4_BY_THR1_ADDR  MT6358_AUXADC_ADC38
#define PMIC_AUXADC_ADC_OUT_CH4_BY_THR1_MASK  0xFFF
#define PMIC_AUXADC_ADC_OUT_CH4_BY_THR1_SHIFT 0
#define PMIC_AUXADC_ADC_RDY_CH4_BY_THR1_ADDR  MT6358_AUXADC_ADC38
#define PMIC_AUXADC_ADC_RDY_CH4_BY_THR1_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_CH4_BY_THR1_SHIFT 15
#define PMIC_AUXADC_ADC_OUT_CH4_BY_THR2_ADDR  MT6358_AUXADC_ADC39
#define PMIC_AUXADC_ADC_OUT_CH4_BY_THR2_MASK  0xFFF
#define PMIC_AUXADC_ADC_OUT_CH4_BY_THR2_SHIFT 0
#define PMIC_AUXADC_ADC_RDY_CH4_BY_THR2_ADDR  MT6358_AUXADC_ADC39
#define PMIC_AUXADC_ADC_RDY_CH4_BY_THR2_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_CH4_BY_THR2_SHIFT 15
#define PMIC_AUXADC_ADC_OUT_CH4_BY_THR3_ADDR  MT6358_AUXADC_ADC40
#define PMIC_AUXADC_ADC_OUT_CH4_BY_THR3_MASK  0xFFF
#define PMIC_AUXADC_ADC_OUT_CH4_BY_THR3_SHIFT 0
#define PMIC_AUXADC_ADC_RDY_CH4_BY_THR3_ADDR  MT6358_AUXADC_ADC40
#define PMIC_AUXADC_ADC_RDY_CH4_BY_THR3_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_CH4_BY_THR3_SHIFT 15
#define PMIC_AUXADC_ADC_BUSY_IN_ADDR  MT6358_AUXADC_STA0
#define PMIC_AUXADC_ADC_BUSY_IN_MASK  0xFFF
#define PMIC_AUXADC_ADC_BUSY_IN_SHIFT 0
#define PMIC_AUXADC_ADC_BUSY_IN_LBAT_ADDR   MT6358_AUXADC_STA0
#define PMIC_AUXADC_ADC_BUSY_IN_LBAT_MASK   0x1
#define PMIC_AUXADC_ADC_BUSY_IN_LBAT_SHIFT  12
#define PMIC_AUXADC_ADC_BUSY_IN_LBAT2_ADDR  MT6358_AUXADC_STA0
#define PMIC_AUXADC_ADC_BUSY_IN_LBAT2_MASK  0x1
#define PMIC_AUXADC_ADC_BUSY_IN_LBAT2_SHIFT 13
#define PMIC_AUXADC_ADC_BUSY_IN_BAT_TEMP_ADDR MT6358_AUXADC_STA0
#define PMIC_AUXADC_ADC_BUSY_IN_BAT_TEMP_MASK 0x1
#define PMIC_AUXADC_ADC_BUSY_IN_BAT_TEMP_SHIFT   14
#define PMIC_AUXADC_ADC_BUSY_IN_WAKEUP_ADDR MT6358_AUXADC_STA0
#define PMIC_AUXADC_ADC_BUSY_IN_WAKEUP_MASK 0x1
#define PMIC_AUXADC_ADC_BUSY_IN_WAKEUP_SHIFT  15
#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_MDRT_ADDR   MT6358_AUXADC_STA1
#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_MDRT_MASK   0x1
#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_MDRT_SHIFT  0
#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_AP_ADDR  MT6358_AUXADC_STA1
#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_AP_MASK  0x1
#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_AP_SHIFT 1
#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_MD_ADDR  MT6358_AUXADC_STA1
#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_MD_MASK  0x1
#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_MD_SHIFT 2
#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_ADDR MT6358_AUXADC_STA1
#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_MASK 0x1
#define PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_SHIFT   3
#define PMIC_AUXADC_ADC_BUSY_IN_MDRT_ADDR   MT6358_AUXADC_STA1
#define PMIC_AUXADC_ADC_BUSY_IN_MDRT_MASK   0x1
#define PMIC_AUXADC_ADC_BUSY_IN_MDRT_SHIFT  5
#define PMIC_AUXADC_ADC_BUSY_IN_SHARE_ADDR  MT6358_AUXADC_STA1
#define PMIC_AUXADC_ADC_BUSY_IN_SHARE_MASK  0x1
#define PMIC_AUXADC_ADC_BUSY_IN_SHARE_SHIFT 7
#define PMIC_AUXADC_ADC_BUSY_IN_IMP_ADDR   MT6358_AUXADC_STA1
#define PMIC_AUXADC_ADC_BUSY_IN_IMP_MASK   0x1
#define PMIC_AUXADC_ADC_BUSY_IN_IMP_SHIFT   8
#define PMIC_AUXADC_ADC_BUSY_IN_FGADC_PCHR_ADDR  MT6358_AUXADC_STA1
#define PMIC_AUXADC_ADC_BUSY_IN_FGADC_PCHR_MASK  0x1
#define PMIC_AUXADC_ADC_BUSY_IN_FGADC_PCHR_SHIFT  9
#define PMIC_AUXADC_ADC_BUSY_IN_GPS_AP_ADDR MT6358_AUXADC_STA1
#define PMIC_AUXADC_ADC_BUSY_IN_GPS_AP_MASK 0x1
#define PMIC_AUXADC_ADC_BUSY_IN_GPS_AP_SHIFT  11
#define PMIC_AUXADC_ADC_BUSY_IN_GPS_MD_ADDR MT6358_AUXADC_STA1
#define PMIC_AUXADC_ADC_BUSY_IN_GPS_MD_MASK 0x1
#define PMIC_AUXADC_ADC_BUSY_IN_GPS_MD_SHIFT  12
#define PMIC_AUXADC_ADC_BUSY_IN_GPS_ADDR   MT6358_AUXADC_STA1
#define PMIC_AUXADC_ADC_BUSY_IN_GPS_MASK   0x1
#define PMIC_AUXADC_ADC_BUSY_IN_GPS_SHIFT   13
#define PMIC_AUXADC_ADC_BUSY_IN_THR_MD_ADDR MT6358_AUXADC_STA1
#define PMIC_AUXADC_ADC_BUSY_IN_THR_MD_MASK 0x1
#define PMIC_AUXADC_ADC_BUSY_IN_THR_MD_SHIFT  15
#define PMIC_AUXADC_ADC_BUSY_IN_BAT_PLUGIN_PCHR_ADDR   MT6358_AUXADC_STA2
#define PMIC_AUXADC_ADC_BUSY_IN_BAT_PLUGIN_PCHR_MASK   0x1
#define PMIC_AUXADC_ADC_BUSY_IN_BAT_PLUGIN_PCHR_SHIFT  0
#define PMIC_AUXADC_ADC_BUSY_IN_BATID_ADDR  MT6358_AUXADC_STA2
#define PMIC_AUXADC_ADC_BUSY_IN_BATID_MASK  0x1
#define PMIC_AUXADC_ADC_BUSY_IN_BATID_SHIFT 2
#define PMIC_AUXADC_ADC_BUSY_IN_PWRON_ADDR  MT6358_AUXADC_STA2
#define PMIC_AUXADC_ADC_BUSY_IN_PWRON_MASK  0x1
#define PMIC_AUXADC_ADC_BUSY_IN_PWRON_SHIFT 3
#define PMIC_AUXADC_ADC_BUSY_IN_THR1_ADDR   MT6358_AUXADC_STA2
#define PMIC_AUXADC_ADC_BUSY_IN_THR1_MASK   0x1
#define PMIC_AUXADC_ADC_BUSY_IN_THR1_SHIFT  11
#define PMIC_AUXADC_ADC_BUSY_IN_THR2_ADDR   MT6358_AUXADC_STA2
#define PMIC_AUXADC_ADC_BUSY_IN_THR2_MASK   0x1
#define PMIC_AUXADC_ADC_BUSY_IN_THR2_SHIFT  12
#define PMIC_AUXADC_ADC_BUSY_IN_THR3_ADDR   MT6358_AUXADC_STA2
#define PMIC_AUXADC_ADC_BUSY_IN_THR3_MASK   0x1
#define PMIC_AUXADC_ADC_BUSY_IN_THR3_SHIFT  13
#define PMIC_AUXADC_ADC_BUSY_IN_NAG_ADDR   MT6358_AUXADC_STA2
#define PMIC_AUXADC_ADC_BUSY_IN_NAG_MASK   0x1
#define PMIC_AUXADC_ADC_BUSY_IN_NAG_SHIFT   15
#define PMIC_AUXADC_DIG_2_ANA_ID_ADDR MT6358_AUXADC_DIG_2_DSN_ID
#define PMIC_AUXADC_DIG_2_ANA_ID_MASK 0xFF
#define PMIC_AUXADC_DIG_2_ANA_ID_SHIFT  0
#define PMIC_AUXADC_DIG_2_DIG_ID_ADDR MT6358_AUXADC_DIG_2_DSN_ID
#define PMIC_AUXADC_DIG_2_DIG_ID_MASK 0xFF
#define PMIC_AUXADC_DIG_2_DIG_ID_SHIFT  8
#define PMIC_AUXADC_DIG_2_ANA_MINOR_REV_ADDR  MT6358_AUXADC_DIG_2_DSN_REV0
#define PMIC_AUXADC_DIG_2_ANA_MINOR_REV_MASK  0xF
#define PMIC_AUXADC_DIG_2_ANA_MINOR_REV_SHIFT 0
#define PMIC_AUXADC_DIG_2_ANA_MAJOR_REV_ADDR  MT6358_AUXADC_DIG_2_DSN_REV0
#define PMIC_AUXADC_DIG_2_ANA_MAJOR_REV_MASK  0xF
#define PMIC_AUXADC_DIG_2_ANA_MAJOR_REV_SHIFT 4
#define PMIC_AUXADC_DIG_2_DIG_MINOR_REV_ADDR  MT6358_AUXADC_DIG_2_DSN_REV0
#define PMIC_AUXADC_DIG_2_DIG_MINOR_REV_MASK  0xF
#define PMIC_AUXADC_DIG_2_DIG_MINOR_REV_SHIFT 8
#define PMIC_AUXADC_DIG_2_DIG_MAJOR_REV_ADDR  MT6358_AUXADC_DIG_2_DSN_REV0
#define PMIC_AUXADC_DIG_2_DIG_MAJOR_REV_MASK  0xF
#define PMIC_AUXADC_DIG_2_DIG_MAJOR_REV_SHIFT 12
#define PMIC_AUXADC_DIG_2_DSN_CBS_ADDR  MT6358_AUXADC_DIG_2_DSN_DBI
#define PMIC_AUXADC_DIG_2_DSN_CBS_MASK  0x3
#define PMIC_AUXADC_DIG_2_DSN_CBS_SHIFT 0
#define PMIC_AUXADC_DIG_2_DSN_BIX_ADDR  MT6358_AUXADC_DIG_2_DSN_DBI
#define PMIC_AUXADC_DIG_2_DSN_BIX_MASK  0x3
#define PMIC_AUXADC_DIG_2_DSN_BIX_SHIFT 2
#define PMIC_AUXADC_DIG_2_DSN_ESP_ADDR  MT6358_AUXADC_DIG_2_DSN_DBI
#define PMIC_AUXADC_DIG_2_DSN_ESP_MASK  0xFF
#define PMIC_AUXADC_DIG_2_DSN_ESP_SHIFT 8
#define PMIC_AUXADC_DIG_2_DSN_FPI_ADDR  MT6358_AUXADC_DIG_2_DSN_DXI
#define PMIC_AUXADC_DIG_2_DSN_FPI_MASK  0xFF
#define PMIC_AUXADC_DIG_2_DSN_FPI_SHIFT 0
#define PMIC_AUXADC_RQST_CH0_ADDR MT6358_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH0_MASK 0x1
#define PMIC_AUXADC_RQST_CH0_SHIFT 0
#define PMIC_AUXADC_RQST_CH1_ADDR MT6358_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH1_MASK 0x1
#define PMIC_AUXADC_RQST_CH1_SHIFT 1
#define PMIC_AUXADC_RQST_CH2_ADDR MT6358_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH2_MASK 0x1
#define PMIC_AUXADC_RQST_CH2_SHIFT 2
#define PMIC_AUXADC_RQST_CH3_ADDR MT6358_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH3_MASK 0x1
#define PMIC_AUXADC_RQST_CH3_SHIFT 3
#define PMIC_AUXADC_RQST_CH4_ADDR MT6358_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH4_MASK 0x1
#define PMIC_AUXADC_RQST_CH4_SHIFT 4
#define PMIC_AUXADC_RQST_CH5_ADDR MT6358_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH5_MASK 0x1
#define PMIC_AUXADC_RQST_CH5_SHIFT 5
#define PMIC_AUXADC_RQST_CH6_ADDR MT6358_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH6_MASK 0x1
#define PMIC_AUXADC_RQST_CH6_SHIFT 6
#define PMIC_AUXADC_RQST_CH7_ADDR MT6358_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH7_MASK 0x1
#define PMIC_AUXADC_RQST_CH7_SHIFT 7
#define PMIC_AUXADC_RQST_CH8_ADDR MT6358_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH8_MASK 0x1
#define PMIC_AUXADC_RQST_CH8_SHIFT 8
#define PMIC_AUXADC_RQST_CH9_ADDR MT6358_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH9_MASK 0x1
#define PMIC_AUXADC_RQST_CH9_SHIFT 9
#define PMIC_AUXADC_RQST_CH10_ADDR MT6358_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH10_MASK 0x1
#define PMIC_AUXADC_RQST_CH10_SHIFT   10
#define PMIC_AUXADC_RQST_CH11_ADDR MT6358_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH11_MASK 0x1
#define PMIC_AUXADC_RQST_CH11_SHIFT   11
#define PMIC_AUXADC_RQST_CH12_ADDR MT6358_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH12_MASK 0x1
#define PMIC_AUXADC_RQST_CH12_SHIFT   12
#define PMIC_AUXADC_RQST_CH13_ADDR MT6358_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH13_MASK 0x1
#define PMIC_AUXADC_RQST_CH13_SHIFT   13
#define PMIC_AUXADC_RQST_CH14_ADDR MT6358_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH14_MASK 0x1
#define PMIC_AUXADC_RQST_CH14_SHIFT   14
#define PMIC_AUXADC_RQST_CH15_ADDR MT6358_AUXADC_RQST0
#define PMIC_AUXADC_RQST_CH15_MASK 0x1
#define PMIC_AUXADC_RQST_CH15_SHIFT   15
#define PMIC_AUXADC_RQST_CH0_BY_MD_ADDR MT6358_AUXADC_RQST1
#define PMIC_AUXADC_RQST_CH0_BY_MD_MASK 0x1
#define PMIC_AUXADC_RQST_CH0_BY_MD_SHIFT   0
#define PMIC_AUXADC_RQST_CH1_BY_MD_ADDR MT6358_AUXADC_RQST1
#define PMIC_AUXADC_RQST_CH1_BY_MD_MASK 0x1
#define PMIC_AUXADC_RQST_CH1_BY_MD_SHIFT   1
#define PMIC_AUXADC_RQST_CH4_BY_MD_ADDR MT6358_AUXADC_RQST1
#define PMIC_AUXADC_RQST_CH4_BY_MD_MASK 0x1
#define PMIC_AUXADC_RQST_CH4_BY_MD_SHIFT   2
#define PMIC_AUXADC_RQST_CH7_BY_MD_ADDR MT6358_AUXADC_RQST1
#define PMIC_AUXADC_RQST_CH7_BY_MD_MASK 0x1
#define PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT   3
#define PMIC_AUXADC_RQST_CH7_BY_GPS_ADDR   MT6358_AUXADC_RQST1
#define PMIC_AUXADC_RQST_CH7_BY_GPS_MASK   0x1
#define PMIC_AUXADC_RQST_CH7_BY_GPS_SHIFT   4
#define PMIC_AUXADC_RQST_DCXO_BY_MD_ADDR   MT6358_AUXADC_RQST1
#define PMIC_AUXADC_RQST_DCXO_BY_MD_MASK   0x1
#define PMIC_AUXADC_RQST_DCXO_BY_MD_SHIFT   5
#define PMIC_AUXADC_RQST_DCXO_BY_GPS_ADDR   MT6358_AUXADC_RQST1
#define PMIC_AUXADC_RQST_DCXO_BY_GPS_MASK   0x1
#define PMIC_AUXADC_RQST_DCXO_BY_GPS_SHIFT  6
#define PMIC_AUXADC_RQST_BATID_ADDR   MT6358_AUXADC_RQST1
#define PMIC_AUXADC_RQST_BATID_MASK   0x1
#define PMIC_AUXADC_RQST_BATID_SHIFT  7
#define PMIC_AUXADC_RQST_CH4_BY_THR1_ADDR   MT6358_AUXADC_RQST1
#define PMIC_AUXADC_RQST_CH4_BY_THR1_MASK   0x1
#define PMIC_AUXADC_RQST_CH4_BY_THR1_SHIFT  8
#define PMIC_AUXADC_RQST_CH4_BY_THR2_ADDR   MT6358_AUXADC_RQST1
#define PMIC_AUXADC_RQST_CH4_BY_THR2_MASK   0x1
#define PMIC_AUXADC_RQST_CH4_BY_THR2_SHIFT  9
#define PMIC_AUXADC_RQST_CH4_BY_THR3_ADDR   MT6358_AUXADC_RQST1
#define PMIC_AUXADC_RQST_CH4_BY_THR3_MASK   0x1
#define PMIC_AUXADC_RQST_CH4_BY_THR3_SHIFT  10
#define PMIC_AUXADC_RQST_RSV1_ADDR MT6358_AUXADC_RQST1
#define PMIC_AUXADC_RQST_RSV1_MASK 0x1
#define PMIC_AUXADC_RQST_RSV1_SHIFT   11
#define PMIC_AUXADC_DIG_3_ANA_ID_ADDR MT6358_AUXADC_DIG_3_DSN_ID
#define PMIC_AUXADC_DIG_3_ANA_ID_MASK 0xFF
#define PMIC_AUXADC_DIG_3_ANA_ID_SHIFT  0
#define PMIC_AUXADC_DIG_3_DIG_ID_ADDR MT6358_AUXADC_DIG_3_DSN_ID
#define PMIC_AUXADC_DIG_3_DIG_ID_MASK 0xFF
#define PMIC_AUXADC_DIG_3_DIG_ID_SHIFT  8
#define PMIC_AUXADC_DIG_3_ANA_MINOR_REV_ADDR  MT6358_AUXADC_DIG_3_DSN_REV0
#define PMIC_AUXADC_DIG_3_ANA_MINOR_REV_MASK  0xF
#define PMIC_AUXADC_DIG_3_ANA_MINOR_REV_SHIFT 0
#define PMIC_AUXADC_DIG_3_ANA_MAJOR_REV_ADDR  MT6358_AUXADC_DIG_3_DSN_REV0
#define PMIC_AUXADC_DIG_3_ANA_MAJOR_REV_MASK  0xF
#define PMIC_AUXADC_DIG_3_ANA_MAJOR_REV_SHIFT 4
#define PMIC_AUXADC_DIG_3_DIG_MINOR_REV_ADDR  MT6358_AUXADC_DIG_3_DSN_REV0
#define PMIC_AUXADC_DIG_3_DIG_MINOR_REV_MASK  0xF
#define PMIC_AUXADC_DIG_3_DIG_MINOR_REV_SHIFT 8
#define PMIC_AUXADC_DIG_3_DIG_MAJOR_REV_ADDR  MT6358_AUXADC_DIG_3_DSN_REV0
#define PMIC_AUXADC_DIG_3_DIG_MAJOR_REV_MASK  0xF
#define PMIC_AUXADC_DIG_3_DIG_MAJOR_REV_SHIFT 12
#define PMIC_AUXADC_DIG_3_DSN_CBS_ADDR  MT6358_AUXADC_DIG_3_DSN_DBI
#define PMIC_AUXADC_DIG_3_DSN_CBS_MASK  0x3
#define PMIC_AUXADC_DIG_3_DSN_CBS_SHIFT 0
#define PMIC_AUXADC_DIG_3_DSN_BIX_ADDR  MT6358_AUXADC_DIG_3_DSN_DBI
#define PMIC_AUXADC_DIG_3_DSN_BIX_MASK  0x3
#define PMIC_AUXADC_DIG_3_DSN_BIX_SHIFT 2
#define PMIC_AUXADC_DIG_3_DSN_ESP_ADDR  MT6358_AUXADC_DIG_3_DSN_DBI
#define PMIC_AUXADC_DIG_3_DSN_ESP_MASK  0xFF
#define PMIC_AUXADC_DIG_3_DSN_ESP_SHIFT 8
#define PMIC_AUXADC_DIG_3_DSN_FPI_ADDR  MT6358_AUXADC_DIG_3_DSN_DXI
#define PMIC_AUXADC_DIG_3_DSN_FPI_MASK  0xFF
#define PMIC_AUXADC_DIG_3_DSN_FPI_SHIFT 0
#define PMIC_AUXADC_CK_ON_EXTD_ADDR   MT6358_AUXADC_CON0
#define PMIC_AUXADC_CK_ON_EXTD_MASK   0x3F
#define PMIC_AUXADC_CK_ON_EXTD_SHIFT  0
#define PMIC_AUXADC_SRCLKEN_SRC_SEL_ADDR   MT6358_AUXADC_CON0
#define PMIC_AUXADC_SRCLKEN_SRC_SEL_MASK   0x3
#define PMIC_AUXADC_SRCLKEN_SRC_SEL_SHIFT   6
#define PMIC_AUXADC_ADC_PWDB_ADDR MT6358_AUXADC_CON0
#define PMIC_AUXADC_ADC_PWDB_MASK 0x1
#define PMIC_AUXADC_ADC_PWDB_SHIFT 8
#define PMIC_AUXADC_ADC_PWDB_SWCTRL_ADDR   MT6358_AUXADC_CON0
#define PMIC_AUXADC_ADC_PWDB_SWCTRL_MASK   0x1
#define PMIC_AUXADC_ADC_PWDB_SWCTRL_SHIFT   9
#define PMIC_AUXADC_STRUP_CK_ON_ENB_ADDR   MT6358_AUXADC_CON0
#define PMIC_AUXADC_STRUP_CK_ON_ENB_MASK   0x1
#define PMIC_AUXADC_STRUP_CK_ON_ENB_SHIFT   10
#define PMIC_AUXADC_SRCLKEN_CK_EN_ADDR  MT6358_AUXADC_CON0
#define PMIC_AUXADC_SRCLKEN_CK_EN_MASK  0x1
#define PMIC_AUXADC_SRCLKEN_CK_EN_SHIFT 12
#define PMIC_AUXADC_CK_AON_GPS_ADDR   MT6358_AUXADC_CON0
#define PMIC_AUXADC_CK_AON_GPS_MASK   0x1
#define PMIC_AUXADC_CK_AON_GPS_SHIFT  13
#define PMIC_AUXADC_CK_AON_MD_ADDR MT6358_AUXADC_CON0
#define PMIC_AUXADC_CK_AON_MD_MASK 0x1
#define PMIC_AUXADC_CK_AON_MD_SHIFT   14
#define PMIC_AUXADC_CK_AON_ADDR MT6358_AUXADC_CON0
#define PMIC_AUXADC_CK_AON_MASK 0x1
#define PMIC_AUXADC_CK_AON_SHIFT  15
#define PMIC_AUXADC_CON0_SET_ADDR MT6358_AUXADC_CON0_SET
#define PMIC_AUXADC_CON0_SET_MASK 0xFFFF
#define PMIC_AUXADC_CON0_SET_SHIFT 0
#define PMIC_AUXADC_CON0_CLR_ADDR MT6358_AUXADC_CON0_CLR
#define PMIC_AUXADC_CON0_CLR_MASK 0xFFFF
#define PMIC_AUXADC_CON0_CLR_SHIFT 0
#define PMIC_AUXADC_AVG_NUM_SMALL_ADDR  MT6358_AUXADC_CON1
#define PMIC_AUXADC_AVG_NUM_SMALL_MASK  0x7
#define PMIC_AUXADC_AVG_NUM_SMALL_SHIFT 0
#define PMIC_AUXADC_AVG_NUM_LARGE_ADDR  MT6358_AUXADC_CON1
#define PMIC_AUXADC_AVG_NUM_LARGE_MASK  0x7
#define PMIC_AUXADC_AVG_NUM_LARGE_SHIFT 3
#define PMIC_AUXADC_SPL_NUM_ADDR  MT6358_AUXADC_CON1
#define PMIC_AUXADC_SPL_NUM_MASK  0x3FF
#define PMIC_AUXADC_SPL_NUM_SHIFT 6
#define PMIC_AUXADC_AVG_NUM_SEL_ADDR  MT6358_AUXADC_CON2
#define PMIC_AUXADC_AVG_NUM_SEL_MASK  0xFFF
#define PMIC_AUXADC_AVG_NUM_SEL_SHIFT 0
#define PMIC_AUXADC_AVG_NUM_SEL_SHARE_ADDR  MT6358_AUXADC_CON2
#define PMIC_AUXADC_AVG_NUM_SEL_SHARE_MASK  0x1
#define PMIC_AUXADC_AVG_NUM_SEL_SHARE_SHIFT 12
#define PMIC_AUXADC_AVG_NUM_SEL_LBAT_ADDR   MT6358_AUXADC_CON2
#define PMIC_AUXADC_AVG_NUM_SEL_LBAT_MASK   0x1
#define PMIC_AUXADC_AVG_NUM_SEL_LBAT_SHIFT  13
#define PMIC_AUXADC_AVG_NUM_SEL_BAT_TEMP_ADDR MT6358_AUXADC_CON2
#define PMIC_AUXADC_AVG_NUM_SEL_BAT_TEMP_MASK 0x1
#define PMIC_AUXADC_AVG_NUM_SEL_BAT_TEMP_SHIFT   14
#define PMIC_AUXADC_AVG_NUM_SEL_WAKEUP_ADDR MT6358_AUXADC_CON2
#define PMIC_AUXADC_AVG_NUM_SEL_WAKEUP_MASK 0x1
#define PMIC_AUXADC_AVG_NUM_SEL_WAKEUP_SHIFT  15
#define PMIC_AUXADC_SPL_NUM_LARGE_ADDR  MT6358_AUXADC_CON3
#define PMIC_AUXADC_SPL_NUM_LARGE_MASK  0x3FF
#define PMIC_AUXADC_SPL_NUM_LARGE_SHIFT 0
#define PMIC_AUXADC_SPL_NUM_SLEEP_ADDR  MT6358_AUXADC_CON4
#define PMIC_AUXADC_SPL_NUM_SLEEP_MASK  0x3FF
#define PMIC_AUXADC_SPL_NUM_SLEEP_SHIFT 0
#define PMIC_AUXADC_SPL_NUM_SLEEP_SEL_ADDR  MT6358_AUXADC_CON4
#define PMIC_AUXADC_SPL_NUM_SLEEP_SEL_MASK  0x1
#define PMIC_AUXADC_SPL_NUM_SLEEP_SEL_SHIFT 15
#define PMIC_AUXADC_SPL_NUM_SEL_ADDR  MT6358_AUXADC_CON5
#define PMIC_AUXADC_SPL_NUM_SEL_MASK  0xFFF
#define PMIC_AUXADC_SPL_NUM_SEL_SHIFT 0
#define PMIC_AUXADC_SPL_NUM_SEL_SHARE_ADDR  MT6358_AUXADC_CON5
#define PMIC_AUXADC_SPL_NUM_SEL_SHARE_MASK  0x1
#define PMIC_AUXADC_SPL_NUM_SEL_SHARE_SHIFT 12
#define PMIC_AUXADC_SPL_NUM_SEL_LBAT_ADDR   MT6358_AUXADC_CON5
#define PMIC_AUXADC_SPL_NUM_SEL_LBAT_MASK   0x1
#define PMIC_AUXADC_SPL_NUM_SEL_LBAT_SHIFT  13
#define PMIC_AUXADC_SPL_NUM_SEL_BAT_TEMP_ADDR MT6358_AUXADC_CON5
#define PMIC_AUXADC_SPL_NUM_SEL_BAT_TEMP_MASK 0x1
#define PMIC_AUXADC_SPL_NUM_SEL_BAT_TEMP_SHIFT   14
#define PMIC_AUXADC_SPL_NUM_SEL_WAKEUP_ADDR MT6358_AUXADC_CON5
#define PMIC_AUXADC_SPL_NUM_SEL_WAKEUP_MASK 0x1
#define PMIC_AUXADC_SPL_NUM_SEL_WAKEUP_SHIFT  15
#define PMIC_AUXADC_SPL_NUM_CH0_ADDR  MT6358_AUXADC_CON6
#define PMIC_AUXADC_SPL_NUM_CH0_MASK  0x3FF
#define PMIC_AUXADC_SPL_NUM_CH0_SHIFT 0
#define PMIC_AUXADC_SPL_NUM_CH3_ADDR  MT6358_AUXADC_CON7
#define PMIC_AUXADC_SPL_NUM_CH3_MASK  0x3FF
#define PMIC_AUXADC_SPL_NUM_CH3_SHIFT 0
#define PMIC_AUXADC_SPL_NUM_CH7_ADDR  MT6358_AUXADC_CON8
#define PMIC_AUXADC_SPL_NUM_CH7_MASK  0x3FF
#define PMIC_AUXADC_SPL_NUM_CH7_SHIFT 0
#define PMIC_AUXADC_AVG_NUM_LBAT_ADDR MT6358_AUXADC_CON9
#define PMIC_AUXADC_AVG_NUM_LBAT_MASK 0x7
#define PMIC_AUXADC_AVG_NUM_LBAT_SHIFT  0
#define PMIC_AUXADC_AVG_NUM_CH7_ADDR  MT6358_AUXADC_CON9
#define PMIC_AUXADC_AVG_NUM_CH7_MASK  0x7
#define PMIC_AUXADC_AVG_NUM_CH7_SHIFT 4
#define PMIC_AUXADC_AVG_NUM_CH3_ADDR  MT6358_AUXADC_CON9
#define PMIC_AUXADC_AVG_NUM_CH3_MASK  0x7
#define PMIC_AUXADC_AVG_NUM_CH3_SHIFT 8
#define PMIC_AUXADC_AVG_NUM_CH0_ADDR  MT6358_AUXADC_CON9
#define PMIC_AUXADC_AVG_NUM_CH0_MASK  0x7
#define PMIC_AUXADC_AVG_NUM_CH0_SHIFT 12
#define PMIC_AUXADC_AVG_NUM_HPC_ADDR  MT6358_AUXADC_CON10
#define PMIC_AUXADC_AVG_NUM_HPC_MASK  0x7
#define PMIC_AUXADC_AVG_NUM_HPC_SHIFT 0
#define PMIC_AUXADC_AVG_NUM_DCXO_ADDR MT6358_AUXADC_CON10
#define PMIC_AUXADC_AVG_NUM_DCXO_MASK 0x7
#define PMIC_AUXADC_AVG_NUM_DCXO_SHIFT  4
#define PMIC_AUXADC_TRIM_CH0_SEL_ADDR MT6358_AUXADC_CON11
#define PMIC_AUXADC_TRIM_CH0_SEL_MASK 0x3
#define PMIC_AUXADC_TRIM_CH0_SEL_SHIFT  0
#define PMIC_AUXADC_TRIM_CH1_SEL_ADDR MT6358_AUXADC_CON11
#define PMIC_AUXADC_TRIM_CH1_SEL_MASK 0x3
#define PMIC_AUXADC_TRIM_CH1_SEL_SHIFT  2
#define PMIC_AUXADC_TRIM_CH2_SEL_ADDR MT6358_AUXADC_CON11
#define PMIC_AUXADC_TRIM_CH2_SEL_MASK 0x3
#define PMIC_AUXADC_TRIM_CH2_SEL_SHIFT  4
#define PMIC_AUXADC_TRIM_CH3_SEL_ADDR MT6358_AUXADC_CON11
#define PMIC_AUXADC_TRIM_CH3_SEL_MASK 0x3
#define PMIC_AUXADC_TRIM_CH3_SEL_SHIFT  6
#define PMIC_AUXADC_TRIM_CH4_SEL_ADDR MT6358_AUXADC_CON11
#define PMIC_AUXADC_TRIM_CH4_SEL_MASK 0x3
#define PMIC_AUXADC_TRIM_CH4_SEL_SHIFT  8
#define PMIC_AUXADC_TRIM_CH5_SEL_ADDR MT6358_AUXADC_CON11
#define PMIC_AUXADC_TRIM_CH5_SEL_MASK 0x3
#define PMIC_AUXADC_TRIM_CH5_SEL_SHIFT  10
#define PMIC_AUXADC_TRIM_CH6_SEL_ADDR MT6358_AUXADC_CON11
#define PMIC_AUXADC_TRIM_CH6_SEL_MASK 0x3
#define PMIC_AUXADC_TRIM_CH6_SEL_SHIFT  12
#define PMIC_AUXADC_TRIM_CH7_SEL_ADDR MT6358_AUXADC_CON11
#define PMIC_AUXADC_TRIM_CH7_SEL_MASK 0x3
#define PMIC_AUXADC_TRIM_CH7_SEL_SHIFT  14
#define PMIC_AUXADC_TRIM_CH8_SEL_ADDR MT6358_AUXADC_CON12
#define PMIC_AUXADC_TRIM_CH8_SEL_MASK 0x3
#define PMIC_AUXADC_TRIM_CH8_SEL_SHIFT  0
#define PMIC_AUXADC_TRIM_CH9_SEL_ADDR MT6358_AUXADC_CON12
#define PMIC_AUXADC_TRIM_CH9_SEL_MASK 0x3
#define PMIC_AUXADC_TRIM_CH9_SEL_SHIFT  2
#define PMIC_AUXADC_TRIM_CH10_SEL_ADDR  MT6358_AUXADC_CON12
#define PMIC_AUXADC_TRIM_CH10_SEL_MASK  0x3
#define PMIC_AUXADC_TRIM_CH10_SEL_SHIFT 4
#define PMIC_AUXADC_TRIM_CH11_SEL_ADDR  MT6358_AUXADC_CON12
#define PMIC_AUXADC_TRIM_CH11_SEL_MASK  0x3
#define PMIC_AUXADC_TRIM_CH11_SEL_SHIFT 6
#define PMIC_AUXADC_ADC_2S_COMP_ENB_ADDR   MT6358_AUXADC_CON12
#define PMIC_AUXADC_ADC_2S_COMP_ENB_MASK   0x1
#define PMIC_AUXADC_ADC_2S_COMP_ENB_SHIFT   14
#define PMIC_AUXADC_ADC_TRIM_COMP_ADDR  MT6358_AUXADC_CON12
#define PMIC_AUXADC_ADC_TRIM_COMP_MASK  0x1
#define PMIC_AUXADC_ADC_TRIM_COMP_SHIFT 15
#define PMIC_AUXADC_RNG_EN_ADDR MT6358_AUXADC_CON13
#define PMIC_AUXADC_RNG_EN_MASK 0x1
#define PMIC_AUXADC_RNG_EN_SHIFT  0
#define PMIC_AUXADC_TEST_MODE_ADDR MT6358_AUXADC_CON13
#define PMIC_AUXADC_TEST_MODE_MASK 0x1
#define PMIC_AUXADC_TEST_MODE_SHIFT   3
#define PMIC_AUXADC_BIT_SEL_ADDR  MT6358_AUXADC_CON13
#define PMIC_AUXADC_BIT_SEL_MASK  0x1
#define PMIC_AUXADC_BIT_SEL_SHIFT 4
#define PMIC_AUXADC_START_SW_ADDR MT6358_AUXADC_CON13
#define PMIC_AUXADC_START_SW_MASK 0x1
#define PMIC_AUXADC_START_SW_SHIFT 5
#define PMIC_AUXADC_START_SWCTRL_ADDR MT6358_AUXADC_CON13
#define PMIC_AUXADC_START_SWCTRL_MASK 0x1
#define PMIC_AUXADC_START_SWCTRL_SHIFT  6
#define PMIC_AUXADC_TS_VBE_SEL_ADDR   MT6358_AUXADC_CON13
#define PMIC_AUXADC_TS_VBE_SEL_MASK   0x7
#define PMIC_AUXADC_TS_VBE_SEL_SHIFT  7
#define PMIC_AUXADC_TS_VBE_SEL_SWCTRL_ADDR  MT6358_AUXADC_CON13
#define PMIC_AUXADC_TS_VBE_SEL_SWCTRL_MASK  0x1
#define PMIC_AUXADC_TS_VBE_SEL_SWCTRL_SHIFT 10
#define PMIC_AUXADC_VBUF_EN_ADDR  MT6358_AUXADC_CON13
#define PMIC_AUXADC_VBUF_EN_MASK  0x1
#define PMIC_AUXADC_VBUF_EN_SHIFT 11
#define PMIC_AUXADC_VBUF_EN_SWCTRL_ADDR MT6358_AUXADC_CON13
#define PMIC_AUXADC_VBUF_EN_SWCTRL_MASK 0x1
#define PMIC_AUXADC_VBUF_EN_SWCTRL_SHIFT   12
#define PMIC_AUXADC_OUT_SEL_ADDR  MT6358_AUXADC_CON13
#define PMIC_AUXADC_OUT_SEL_MASK  0x1
#define PMIC_AUXADC_OUT_SEL_SHIFT 13
#define PMIC_AUXADC_DA_DAC_ADDR MT6358_AUXADC_CON14
#define PMIC_AUXADC_DA_DAC_MASK 0xFFF
#define PMIC_AUXADC_DA_DAC_SHIFT  0
#define PMIC_AUXADC_DA_DAC_SWCTRL_ADDR  MT6358_AUXADC_CON14
#define PMIC_AUXADC_DA_DAC_SWCTRL_MASK  0x1
#define PMIC_AUXADC_DA_DAC_SWCTRL_SHIFT 12
#define PMIC_AD_AUXADC_COMP_ADDR  MT6358_AUXADC_CON14
#define PMIC_AD_AUXADC_COMP_MASK  0x1
#define PMIC_AD_AUXADC_COMP_SHIFT 15
#define PMIC_AUXADC_ADCIN_VSEN_EN_ADDR  MT6358_AUXADC_CON15
#define PMIC_AUXADC_ADCIN_VSEN_EN_MASK  0x1
#define PMIC_AUXADC_ADCIN_VSEN_EN_SHIFT 0
#define PMIC_AUXADC_ADCIN_VBAT_EN_ADDR  MT6358_AUXADC_CON15
#define PMIC_AUXADC_ADCIN_VBAT_EN_MASK  0x1
#define PMIC_AUXADC_ADCIN_VBAT_EN_SHIFT 1
#define PMIC_AUXADC_ADCIN_VSEN_MUX_EN_ADDR  MT6358_AUXADC_CON15
#define PMIC_AUXADC_ADCIN_VSEN_MUX_EN_MASK  0x1
#define PMIC_AUXADC_ADCIN_VSEN_MUX_EN_SHIFT 2
#define PMIC_AUXADC_ADCIN_VSEN_EXT_BATON_EN_ADDR  MT6358_AUXADC_CON15
#define PMIC_AUXADC_ADCIN_VSEN_EXT_BATON_EN_MASK  0x1
#define PMIC_AUXADC_ADCIN_VSEN_EXT_BATON_EN_SHIFT 3
#define PMIC_AUXADC_ADCIN_CHR_EN_ADDR MT6358_AUXADC_CON15
#define PMIC_AUXADC_ADCIN_CHR_EN_MASK 0x1
#define PMIC_AUXADC_ADCIN_CHR_EN_SHIFT  4
#define PMIC_AUXADC_ADCIN_BATON_TDET_EN_ADDR  MT6358_AUXADC_CON15
#define PMIC_AUXADC_ADCIN_BATON_TDET_EN_MASK  0x1
#define PMIC_AUXADC_ADCIN_BATON_TDET_EN_SHIFT 5
#define PMIC_AUXADC_ACCDET_ANASWCTRL_EN_ADDR  MT6358_AUXADC_CON15
#define PMIC_AUXADC_ACCDET_ANASWCTRL_EN_MASK  0x1
#define PMIC_AUXADC_ACCDET_ANASWCTRL_EN_SHIFT 6
#define PMIC_AUXADC_XO_THADC_EN_ADDR  MT6358_AUXADC_CON15
#define PMIC_AUXADC_XO_THADC_EN_MASK  0x1
#define PMIC_AUXADC_XO_THADC_EN_SHIFT 7
#define PMIC_AUXADC_ADCIN_BATID_SW_EN_ADDR  MT6358_AUXADC_CON15
#define PMIC_AUXADC_ADCIN_BATID_SW_EN_MASK  0x1
#define PMIC_AUXADC_ADCIN_BATID_SW_EN_SHIFT 8
#define PMIC_AUXADC_DIG0_RSV0_ADDR MT6358_AUXADC_CON15
#define PMIC_AUXADC_DIG0_RSV0_MASK 0x3
#define PMIC_AUXADC_DIG0_RSV0_SHIFT   9
#define PMIC_AUXADC_CHSEL_ADDR  MT6358_AUXADC_CON15
#define PMIC_AUXADC_CHSEL_MASK  0xF
#define PMIC_AUXADC_CHSEL_SHIFT 11
#define PMIC_AUXADC_SWCTRL_EN_ADDR MT6358_AUXADC_CON15
#define PMIC_AUXADC_SWCTRL_EN_MASK 0x1
#define PMIC_AUXADC_SWCTRL_EN_SHIFT   15
#define PMIC_AUXADC_SOURCE_LBAT_SEL_ADDR   MT6358_AUXADC_CON16
#define PMIC_AUXADC_SOURCE_LBAT_SEL_MASK   0x1
#define PMIC_AUXADC_SOURCE_LBAT_SEL_SHIFT   0
#define PMIC_AUXADC_SOURCE_LBAT2_SEL_ADDR   MT6358_AUXADC_CON16
#define PMIC_AUXADC_SOURCE_LBAT2_SEL_MASK   0x1
#define PMIC_AUXADC_SOURCE_LBAT2_SEL_SHIFT  1
#define PMIC_AUXADC_START_EXTD_ADDR   MT6358_AUXADC_CON16
#define PMIC_AUXADC_START_EXTD_MASK   0x7F
#define PMIC_AUXADC_START_EXTD_SHIFT  2
#define PMIC_AUXADC_DAC_EXTD_ADDR MT6358_AUXADC_CON16
#define PMIC_AUXADC_DAC_EXTD_MASK 0xF
#define PMIC_AUXADC_DAC_EXTD_SHIFT 11
#define PMIC_AUXADC_DAC_EXTD_EN_ADDR  MT6358_AUXADC_CON16
#define PMIC_AUXADC_DAC_EXTD_EN_MASK  0x1
#define PMIC_AUXADC_DAC_EXTD_EN_SHIFT 15
#define PMIC_AUXADC_DIG0_RSV1_ADDR MT6358_AUXADC_CON17
#define PMIC_AUXADC_DIG0_RSV1_MASK 0x7
#define PMIC_AUXADC_DIG0_RSV1_SHIFT   13
#define PMIC_AUXADC_START_SHADE_NUM_ADDR   MT6358_AUXADC_CON18
#define PMIC_AUXADC_START_SHADE_NUM_MASK   0x3FF
#define PMIC_AUXADC_START_SHADE_NUM_SHIFT   0
#define PMIC_AUXADC_START_SHADE_EN_ADDR MT6358_AUXADC_CON18
#define PMIC_AUXADC_START_SHADE_EN_MASK 0x1
#define PMIC_AUXADC_START_SHADE_EN_SHIFT   14
#define PMIC_AUXADC_START_SHADE_SEL_ADDR   MT6358_AUXADC_CON18
#define PMIC_AUXADC_START_SHADE_SEL_MASK   0x1
#define PMIC_AUXADC_START_SHADE_SEL_SHIFT   15
#define PMIC_AUXADC_ADC_RDY_WAKEUP_CLR_ADDR MT6358_AUXADC_CON19
#define PMIC_AUXADC_ADC_RDY_WAKEUP_CLR_MASK 0x1
#define PMIC_AUXADC_ADC_RDY_WAKEUP_CLR_SHIFT  0
#define PMIC_AUXADC_ADC_RDY_FGADC_CLR_ADDR  MT6358_AUXADC_CON19
#define PMIC_AUXADC_ADC_RDY_FGADC_CLR_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_FGADC_CLR_SHIFT 1
#define PMIC_AUXADC_ADC_RDY_BAT_PLUGIN_CLR_ADDR  MT6358_AUXADC_CON19
#define PMIC_AUXADC_ADC_RDY_BAT_PLUGIN_CLR_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_BAT_PLUGIN_CLR_SHIFT  2
#define PMIC_AUXADC_ADC_RDY_PWRON_CLR_ADDR  MT6358_AUXADC_CON19
#define PMIC_AUXADC_ADC_RDY_PWRON_CLR_MASK  0x1
#define PMIC_AUXADC_ADC_RDY_PWRON_CLR_SHIFT 3
#define PMIC_AUXADC_DATA_REUSE_SEL_ADDR MT6358_AUXADC_CON20
#define PMIC_AUXADC_DATA_REUSE_SEL_MASK 0x3
#define PMIC_AUXADC_DATA_REUSE_SEL_SHIFT   0
#define PMIC_AUXADC_CH0_DATA_REUSE_SEL_ADDR MT6358_AUXADC_CON20
#define PMIC_AUXADC_CH0_DATA_REUSE_SEL_MASK 0x3
#define PMIC_AUXADC_CH0_DATA_REUSE_SEL_SHIFT  2
#define PMIC_AUXADC_CH1_DATA_REUSE_SEL_ADDR MT6358_AUXADC_CON20
#define PMIC_AUXADC_CH1_DATA_REUSE_SEL_MASK 0x3
#define PMIC_AUXADC_CH1_DATA_REUSE_SEL_SHIFT  4
#define PMIC_AUXADC_DCXO_DATA_REUSE_SEL_ADDR  MT6358_AUXADC_CON20
#define PMIC_AUXADC_DCXO_DATA_REUSE_SEL_MASK  0x3
#define PMIC_AUXADC_DCXO_DATA_REUSE_SEL_SHIFT 6
#define PMIC_AUXADC_DATA_REUSE_EN_ADDR  MT6358_AUXADC_CON20
#define PMIC_AUXADC_DATA_REUSE_EN_MASK  0x1
#define PMIC_AUXADC_DATA_REUSE_EN_SHIFT 8
#define PMIC_AUXADC_CH0_DATA_REUSE_EN_ADDR  MT6358_AUXADC_CON20
#define PMIC_AUXADC_CH0_DATA_REUSE_EN_MASK  0x1
#define PMIC_AUXADC_CH0_DATA_REUSE_EN_SHIFT 9
#define PMIC_AUXADC_CH1_DATA_REUSE_EN_ADDR  MT6358_AUXADC_CON20
#define PMIC_AUXADC_CH1_DATA_REUSE_EN_MASK  0x1
#define PMIC_AUXADC_CH1_DATA_REUSE_EN_SHIFT 10
#define PMIC_AUXADC_DCXO_DATA_REUSE_EN_ADDR MT6358_AUXADC_CON20
#define PMIC_AUXADC_DCXO_DATA_REUSE_EN_MASK 0x1
#define PMIC_AUXADC_DCXO_DATA_REUSE_EN_SHIFT  11
#define PMIC_AUXADC_AUTORPT_PRD_ADDR  MT6358_AUXADC_AUTORPT0
#define PMIC_AUXADC_AUTORPT_PRD_MASK  0x3FF
#define PMIC_AUXADC_AUTORPT_PRD_SHIFT 0
#define PMIC_AUXADC_AUTORPT_EN_ADDR   MT6358_AUXADC_AUTORPT0
#define PMIC_AUXADC_AUTORPT_EN_MASK   0x1
#define PMIC_AUXADC_AUTORPT_EN_SHIFT  15
#define PMIC_AUXADC_ACCDET_AUTO_SPL_ADDR   MT6358_AUXADC_ACCDET
#define PMIC_AUXADC_ACCDET_AUTO_SPL_MASK   0x1
#define PMIC_AUXADC_ACCDET_AUTO_SPL_SHIFT   0
#define PMIC_AUXADC_ACCDET_AUTO_RQST_CLR_ADDR MT6358_AUXADC_ACCDET
#define PMIC_AUXADC_ACCDET_AUTO_RQST_CLR_MASK 0x1
#define PMIC_AUXADC_ACCDET_AUTO_RQST_CLR_SHIFT   1
#define PMIC_AUXADC_ACCDET_DIG1_RSV0_ADDR   MT6358_AUXADC_ACCDET
#define PMIC_AUXADC_ACCDET_DIG1_RSV0_MASK   0x3F
#define PMIC_AUXADC_ACCDET_DIG1_RSV0_SHIFT  2
#define PMIC_AUXADC_ACCDET_DIG0_RSV0_ADDR   MT6358_AUXADC_ACCDET
#define PMIC_AUXADC_ACCDET_DIG0_RSV0_MASK   0xFF
#define PMIC_AUXADC_ACCDET_DIG0_RSV0_SHIFT  8
#define PMIC_AUXADC_FGADC_START_SW_ADDR MT6358_AUXADC_DBG0
#define PMIC_AUXADC_FGADC_START_SW_MASK 0x1
#define PMIC_AUXADC_FGADC_START_SW_SHIFT   0
#define PMIC_AUXADC_FGADC_START_SEL_ADDR   MT6358_AUXADC_DBG0
#define PMIC_AUXADC_FGADC_START_SEL_MASK   0x1
#define PMIC_AUXADC_FGADC_START_SEL_SHIFT   1
#define PMIC_AUXADC_FGADC_R_SW_ADDR   MT6358_AUXADC_DBG0
#define PMIC_AUXADC_FGADC_R_SW_MASK   0x1
#define PMIC_AUXADC_FGADC_R_SW_SHIFT  2
#define PMIC_AUXADC_FGADC_R_SEL_ADDR  MT6358_AUXADC_DBG0
#define PMIC_AUXADC_FGADC_R_SEL_MASK  0x1
#define PMIC_AUXADC_FGADC_R_SEL_SHIFT 3
#define PMIC_AUXADC_BAT_PLUGIN_START_SW_ADDR  MT6358_AUXADC_DBG0
#define PMIC_AUXADC_BAT_PLUGIN_START_SW_MASK  0x1
#define PMIC_AUXADC_BAT_PLUGIN_START_SW_SHIFT 4
#define PMIC_AUXADC_BAT_PLUGIN_START_SEL_ADDR MT6358_AUXADC_DBG0
#define PMIC_AUXADC_BAT_PLUGIN_START_SEL_MASK 0x1
#define PMIC_AUXADC_BAT_PLUGIN_START_SEL_SHIFT   5
#define PMIC_AUXADC_DBG_DIG0_RSV2_ADDR  MT6358_AUXADC_DBG0
#define PMIC_AUXADC_DBG_DIG0_RSV2_MASK  0xF
#define PMIC_AUXADC_DBG_DIG0_RSV2_SHIFT 6
#define PMIC_AUXADC_DBG_DIG1_RSV2_ADDR  MT6358_AUXADC_DBG0
#define PMIC_AUXADC_DBG_DIG1_RSV2_MASK  0x3F
#define PMIC_AUXADC_DBG_DIG1_RSV2_SHIFT 10
#define PMIC_AUXADC_DIG_3_ELR_LEN_ADDR  MT6358_AUXADC_DIG_3_ELR_NUM
#define PMIC_AUXADC_DIG_3_ELR_LEN_MASK  0xFF
#define PMIC_AUXADC_DIG_3_ELR_LEN_SHIFT 0
#define PMIC_EFUSE_GAIN_CH7_TRIM_ADDR MT6358_AUXADC_DIG_3_ELR0
#define PMIC_EFUSE_GAIN_CH7_TRIM_MASK 0xFFF
#define PMIC_EFUSE_GAIN_CH7_TRIM_SHIFT  0
#define PMIC_EFUSE_OFFSET_CH7_TRIM_ADDR MT6358_AUXADC_DIG_3_ELR1
#define PMIC_EFUSE_OFFSET_CH7_TRIM_MASK 0x7FF
#define PMIC_EFUSE_OFFSET_CH7_TRIM_SHIFT   0
#define PMIC_EFUSE_GAIN_CH4_TRIM_ADDR MT6358_AUXADC_DIG_3_ELR2
#define PMIC_EFUSE_GAIN_CH4_TRIM_MASK 0xFFF
#define PMIC_EFUSE_GAIN_CH4_TRIM_SHIFT  0
#define PMIC_EFUSE_OFFSET_CH4_TRIM_ADDR MT6358_AUXADC_DIG_3_ELR3
#define PMIC_EFUSE_OFFSET_CH4_TRIM_MASK 0x7FF
#define PMIC_EFUSE_OFFSET_CH4_TRIM_SHIFT   0
#define PMIC_EFUSE_GAIN_CH0_TRIM_ADDR MT6358_AUXADC_DIG_3_ELR4
#define PMIC_EFUSE_GAIN_CH0_TRIM_MASK 0xFFF
#define PMIC_EFUSE_GAIN_CH0_TRIM_SHIFT  0
#define PMIC_EFUSE_OFFSET_CH0_TRIM_ADDR MT6358_AUXADC_DIG_3_ELR5
#define PMIC_EFUSE_OFFSET_CH0_TRIM_MASK 0x7FF
#define PMIC_EFUSE_OFFSET_CH0_TRIM_SHIFT   0
#define PMIC_AUXADC_SW_GAIN_TRIM_ADDR MT6358_AUXADC_DIG_3_ELR6
#define PMIC_AUXADC_SW_GAIN_TRIM_MASK 0x7FFF
#define PMIC_AUXADC_SW_GAIN_TRIM_SHIFT  0
#define PMIC_AUXADC_SW_OFFSET_TRIM_ADDR MT6358_AUXADC_DIG_3_ELR7
#define PMIC_AUXADC_SW_OFFSET_TRIM_MASK 0x7FFF
#define PMIC_AUXADC_SW_OFFSET_TRIM_SHIFT   0
#define PMIC_AUXADC_EFUSE_DEGC_CALI_ADDR   MT6358_AUXADC_DIG_3_ELR8
#define PMIC_AUXADC_EFUSE_DEGC_CALI_MASK   0x3F
#define PMIC_AUXADC_EFUSE_DEGC_CALI_SHIFT   0
#define PMIC_AUXADC_EFUSE_ADC_CALI_EN_ADDR  MT6358_AUXADC_DIG_3_ELR8
#define PMIC_AUXADC_EFUSE_ADC_CALI_EN_MASK  0x1
#define PMIC_AUXADC_EFUSE_ADC_CALI_EN_SHIFT 8
#define PMIC_AUXADC_EFUSE_1RSV0_ADDR  MT6358_AUXADC_DIG_3_ELR8
#define PMIC_AUXADC_EFUSE_1RSV0_MASK  0x7F
#define PMIC_AUXADC_EFUSE_1RSV0_SHIFT 9
#define PMIC_AUXADC_EFUSE_O_VTS_ADDR  MT6358_AUXADC_DIG_3_ELR9
#define PMIC_AUXADC_EFUSE_O_VTS_MASK  0x1FFF
#define PMIC_AUXADC_EFUSE_O_VTS_SHIFT 0
#define PMIC_AUXADC_EFUSE_2RSV0_ADDR  MT6358_AUXADC_DIG_3_ELR9
#define PMIC_AUXADC_EFUSE_2RSV0_MASK  0x7
#define PMIC_AUXADC_EFUSE_2RSV0_SHIFT 13
#define PMIC_AUXADC_EFUSE_O_SLOPE_ADDR  MT6358_AUXADC_DIG_3_ELR10
#define PMIC_AUXADC_EFUSE_O_SLOPE_MASK  0x3F
#define PMIC_AUXADC_EFUSE_O_SLOPE_SHIFT 0
#define PMIC_AUXADC_EFUSE_O_SLOPE_SIGN_ADDR MT6358_AUXADC_DIG_3_ELR10
#define PMIC_AUXADC_EFUSE_O_SLOPE_SIGN_MASK 0x1
#define PMIC_AUXADC_EFUSE_O_SLOPE_SIGN_SHIFT  8
#define PMIC_AUXADC_EFUSE_3RSV0_ADDR  MT6358_AUXADC_DIG_3_ELR10
#define PMIC_AUXADC_EFUSE_3RSV0_MASK  0x7F
#define PMIC_AUXADC_EFUSE_3RSV0_SHIFT 9
#define PMIC_AUXADC_EFUSE_AUXADC_RSV_ADDR   MT6358_AUXADC_DIG_3_ELR11
#define PMIC_AUXADC_EFUSE_AUXADC_RSV_MASK   0xF
#define PMIC_AUXADC_EFUSE_AUXADC_RSV_SHIFT  0
#define PMIC_AUXADC_EFUSE_ID_ADDR MT6358_AUXADC_DIG_3_ELR11
#define PMIC_AUXADC_EFUSE_ID_MASK 0x1
#define PMIC_AUXADC_EFUSE_ID_SHIFT 4
#define PMIC_AUXADC_EFUSE_4RSV0_ADDR  MT6358_AUXADC_DIG_3_ELR11
#define PMIC_AUXADC_EFUSE_4RSV0_MASK  0x7FF
#define PMIC_AUXADC_EFUSE_4RSV0_SHIFT 5
#define PMIC_AUXADC_EFUSE_O_VTS_2_ADDR  MT6358_AUXADC_DIG_3_ELR12
#define PMIC_AUXADC_EFUSE_O_VTS_2_MASK  0x1FFF
#define PMIC_AUXADC_EFUSE_O_VTS_2_SHIFT 0
#define PMIC_AUXADC_EFUSE_2RSV0_2_ADDR  MT6358_AUXADC_DIG_3_ELR12
#define PMIC_AUXADC_EFUSE_2RSV0_2_MASK  0x7
#define PMIC_AUXADC_EFUSE_2RSV0_2_SHIFT 13
#define PMIC_AUXADC_EFUSE_O_VTS_3_ADDR  MT6358_AUXADC_DIG_3_ELR13
#define PMIC_AUXADC_EFUSE_O_VTS_3_MASK  0x1FFF
#define PMIC_AUXADC_EFUSE_O_VTS_3_SHIFT 0
#define PMIC_AUXADC_EFUSE_2RSV0_3_ADDR  MT6358_AUXADC_DIG_3_ELR13
#define PMIC_AUXADC_EFUSE_2RSV0_3_MASK  0x7
#define PMIC_AUXADC_EFUSE_2RSV0_3_SHIFT 13
#define PMIC_AUXADC_DIG_4_ANA_ID_ADDR MT6358_AUXADC_DIG_4_DSN_ID
#define PMIC_AUXADC_DIG_4_ANA_ID_MASK 0xFF
#define PMIC_AUXADC_DIG_4_ANA_ID_SHIFT  0
#define PMIC_AUXADC_DIG_4_DIG_ID_ADDR MT6358_AUXADC_DIG_4_DSN_ID
#define PMIC_AUXADC_DIG_4_DIG_ID_MASK 0xFF
#define PMIC_AUXADC_DIG_4_DIG_ID_SHIFT  8
#define PMIC_AUXADC_DIG_4_ANA_MINOR_REV_ADDR  MT6358_AUXADC_DIG_4_DSN_REV0
#define PMIC_AUXADC_DIG_4_ANA_MINOR_REV_MASK  0xF
#define PMIC_AUXADC_DIG_4_ANA_MINOR_REV_SHIFT 0
#define PMIC_AUXADC_DIG_4_ANA_MAJOR_REV_ADDR  MT6358_AUXADC_DIG_4_DSN_REV0
#define PMIC_AUXADC_DIG_4_ANA_MAJOR_REV_MASK  0xF
#define PMIC_AUXADC_DIG_4_ANA_MAJOR_REV_SHIFT 4
#define PMIC_AUXADC_DIG_4_DIG_MINOR_REV_ADDR  MT6358_AUXADC_DIG_4_DSN_REV0
#define PMIC_AUXADC_DIG_4_DIG_MINOR_REV_MASK  0xF
#define PMIC_AUXADC_DIG_4_DIG_MINOR_REV_SHIFT 8
#define PMIC_AUXADC_DIG_4_DIG_MAJOR_REV_ADDR  MT6358_AUXADC_DIG_4_DSN_REV0
#define PMIC_AUXADC_DIG_4_DIG_MAJOR_REV_MASK  0xF
#define PMIC_AUXADC_DIG_4_DIG_MAJOR_REV_SHIFT 12
#define PMIC_AUXADC_DIG_4_DSN_CBS_ADDR  MT6358_AUXADC_DIG_4_DSN_DBI
#define PMIC_AUXADC_DIG_4_DSN_CBS_MASK  0x3
#define PMIC_AUXADC_DIG_4_DSN_CBS_SHIFT 0
#define PMIC_AUXADC_DIG_4_DSN_BIX_ADDR  MT6358_AUXADC_DIG_4_DSN_DBI
#define PMIC_AUXADC_DIG_4_DSN_BIX_MASK  0x3
#define PMIC_AUXADC_DIG_4_DSN_BIX_SHIFT 2
#define PMIC_AUXADC_DIG_4_DSN_ESP_ADDR  MT6358_AUXADC_DIG_4_DSN_DBI
#define PMIC_AUXADC_DIG_4_DSN_ESP_MASK  0xFF
#define PMIC_AUXADC_DIG_4_DSN_ESP_SHIFT 8
#define PMIC_AUXADC_DIG_4_DSN_FPI_ADDR  MT6358_AUXADC_DIG_4_DSN_DXI
#define PMIC_AUXADC_DIG_4_DSN_FPI_MASK  0xFF
#define PMIC_AUXADC_DIG_4_DSN_FPI_SHIFT 0
#define PMIC_AUXADC_IMPEDANCE_CNT_ADDR  MT6358_AUXADC_IMP0
#define PMIC_AUXADC_IMPEDANCE_CNT_MASK  0x3F
#define PMIC_AUXADC_IMPEDANCE_CNT_SHIFT 0
#define PMIC_AUXADC_IMPEDANCE_CHSEL_ADDR   MT6358_AUXADC_IMP0
#define PMIC_AUXADC_IMPEDANCE_CHSEL_MASK   0x1
#define PMIC_AUXADC_IMPEDANCE_CHSEL_SHIFT   6
#define PMIC_AUXADC_IMPEDANCE_IRQ_CLR_ADDR  MT6358_AUXADC_IMP0
#define PMIC_AUXADC_IMPEDANCE_IRQ_CLR_MASK  0x1
#define PMIC_AUXADC_IMPEDANCE_IRQ_CLR_SHIFT 7
#define PMIC_AUXADC_IMPEDANCE_IRQ_STATUS_ADDR MT6358_AUXADC_IMP0
#define PMIC_AUXADC_IMPEDANCE_IRQ_STATUS_MASK 0x1
#define PMIC_AUXADC_IMPEDANCE_IRQ_STATUS_SHIFT   8
#define PMIC_AUXADC_CLR_IMP_CNT_STOP_ADDR   MT6358_AUXADC_IMP0
#define PMIC_AUXADC_CLR_IMP_CNT_STOP_MASK   0x1
#define PMIC_AUXADC_CLR_IMP_CNT_STOP_SHIFT  14
#define PMIC_AUXADC_IMPEDANCE_MODE_ADDR MT6358_AUXADC_IMP0
#define PMIC_AUXADC_IMPEDANCE_MODE_MASK 0x1
#define PMIC_AUXADC_IMPEDANCE_MODE_SHIFT   15
#define PMIC_AUXADC_IMP_AUTORPT_PRD_ADDR   MT6358_AUXADC_IMP1
#define PMIC_AUXADC_IMP_AUTORPT_PRD_MASK   0x3FF
#define PMIC_AUXADC_IMP_AUTORPT_PRD_SHIFT   0
#define PMIC_AUXADC_IMP_AUTORPT_EN_ADDR MT6358_AUXADC_IMP1
#define PMIC_AUXADC_IMP_AUTORPT_EN_MASK 0x1
#define PMIC_AUXADC_IMP_AUTORPT_EN_SHIFT   15
#define PMIC_AUXADC_IMP_CNT_ADDR  MT6358_AUXADC_IMP2
#define PMIC_AUXADC_IMP_CNT_MASK  0x3F
#define PMIC_AUXADC_IMP_CNT_SHIFT 0
#define PMIC_AUXADC_IMP_CNT_STOP_STATE_ADDR MT6358_AUXADC_IMP2
#define PMIC_AUXADC_IMP_CNT_STOP_STATE_MASK 0x1
#define PMIC_AUXADC_IMP_CNT_STOP_STATE_SHIFT  15
#define PMIC_AUXADC_LBAT_DEBT_MAX_ADDR  MT6358_AUXADC_LBAT0
#define PMIC_AUXADC_LBAT_DEBT_MAX_MASK  0xFF
#define PMIC_AUXADC_LBAT_DEBT_MAX_SHIFT 0
#define PMIC_AUXADC_LBAT_DEBT_MIN_ADDR  MT6358_AUXADC_LBAT0
#define PMIC_AUXADC_LBAT_DEBT_MIN_MASK  0xFF
#define PMIC_AUXADC_LBAT_DEBT_MIN_SHIFT 8
#define PMIC_AUXADC_LBAT_DET_PRD_15_0_ADDR  MT6358_AUXADC_LBAT1
#define PMIC_AUXADC_LBAT_DET_PRD_15_0_MASK  0xFFFF
#define PMIC_AUXADC_LBAT_DET_PRD_15_0_SHIFT 0
#define PMIC_AUXADC_LBAT_DET_PRD_19_16_ADDR MT6358_AUXADC_LBAT2
#define PMIC_AUXADC_LBAT_DET_PRD_19_16_MASK 0xF
#define PMIC_AUXADC_LBAT_DET_PRD_19_16_SHIFT  0
#define PMIC_AUXADC_LBAT_VOLT_MAX_ADDR  MT6358_AUXADC_LBAT3
#define PMIC_AUXADC_LBAT_VOLT_MAX_MASK  0xFFF
#define PMIC_AUXADC_LBAT_VOLT_MAX_SHIFT 0
#define PMIC_AUXADC_LBAT_IRQ_EN_MAX_ADDR   MT6358_AUXADC_LBAT3
#define PMIC_AUXADC_LBAT_IRQ_EN_MAX_MASK   0x1
#define PMIC_AUXADC_LBAT_IRQ_EN_MAX_SHIFT   12
#define PMIC_AUXADC_LBAT_EN_MAX_ADDR  MT6358_AUXADC_LBAT3
#define PMIC_AUXADC_LBAT_EN_MAX_MASK  0x1
#define PMIC_AUXADC_LBAT_EN_MAX_SHIFT 13
#define PMIC_AUXADC_LBAT_MAX_IRQ_B_ADDR MT6358_AUXADC_LBAT3
#define PMIC_AUXADC_LBAT_MAX_IRQ_B_MASK 0x1
#define PMIC_AUXADC_LBAT_MAX_IRQ_B_SHIFT   15
#define PMIC_AUXADC_LBAT_VOLT_MIN_ADDR  MT6358_AUXADC_LBAT4
#define PMIC_AUXADC_LBAT_VOLT_MIN_MASK  0xFFF
#define PMIC_AUXADC_LBAT_VOLT_MIN_SHIFT 0
#define PMIC_AUXADC_LBAT_IRQ_EN_MIN_ADDR   MT6358_AUXADC_LBAT4
#define PMIC_AUXADC_LBAT_IRQ_EN_MIN_MASK   0x1
#define PMIC_AUXADC_LBAT_IRQ_EN_MIN_SHIFT   12
#define PMIC_AUXADC_LBAT_EN_MIN_ADDR  MT6358_AUXADC_LBAT4
#define PMIC_AUXADC_LBAT_EN_MIN_MASK  0x1
#define PMIC_AUXADC_LBAT_EN_MIN_SHIFT 13
#define PMIC_AUXADC_LBAT_MIN_IRQ_B_ADDR MT6358_AUXADC_LBAT4
#define PMIC_AUXADC_LBAT_MIN_IRQ_B_MASK 0x1
#define PMIC_AUXADC_LBAT_MIN_IRQ_B_SHIFT   15
#define PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MAX_ADDR  MT6358_AUXADC_LBAT5
#define PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MAX_MASK  0x1FF
#define PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MAX_SHIFT 0
#define PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MIN_ADDR  MT6358_AUXADC_LBAT6
#define PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MIN_MASK  0x1FF
#define PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MIN_SHIFT 0
#define PMIC_AUXADC_BAT_TEMP_FROZE_EN_ADDR  MT6358_AUXADC_BAT_TEMP_0
#define PMIC_AUXADC_BAT_TEMP_FROZE_EN_MASK  0x1
#define PMIC_AUXADC_BAT_TEMP_FROZE_EN_SHIFT 0
#define PMIC_AUXADC_BAT_TEMP_DEBT_MAX_ADDR  MT6358_AUXADC_BAT_TEMP_1
#define PMIC_AUXADC_BAT_TEMP_DEBT_MAX_MASK  0xFF
#define PMIC_AUXADC_BAT_TEMP_DEBT_MAX_SHIFT 0
#define PMIC_AUXADC_BAT_TEMP_DEBT_MIN_ADDR  MT6358_AUXADC_BAT_TEMP_1
#define PMIC_AUXADC_BAT_TEMP_DEBT_MIN_MASK  0xFF
#define PMIC_AUXADC_BAT_TEMP_DEBT_MIN_SHIFT 8
#define PMIC_AUXADC_BAT_TEMP_DET_PRD_15_0_ADDR   MT6358_AUXADC_BAT_TEMP_2
#define PMIC_AUXADC_BAT_TEMP_DET_PRD_15_0_MASK   0xFFFF
#define PMIC_AUXADC_BAT_TEMP_DET_PRD_15_0_SHIFT  0
#define PMIC_AUXADC_BAT_TEMP_DET_PRD_19_16_ADDR  MT6358_AUXADC_BAT_TEMP_3
#define PMIC_AUXADC_BAT_TEMP_DET_PRD_19_16_MASK  0xF
#define PMIC_AUXADC_BAT_TEMP_DET_PRD_19_16_SHIFT  0
#define PMIC_AUXADC_BAT_TEMP_VOLT_MAX_ADDR  MT6358_AUXADC_BAT_TEMP_4
#define PMIC_AUXADC_BAT_TEMP_VOLT_MAX_MASK  0xFFF
#define PMIC_AUXADC_BAT_TEMP_VOLT_MAX_SHIFT 0
#define PMIC_AUXADC_BAT_TEMP_IRQ_EN_MAX_ADDR  MT6358_AUXADC_BAT_TEMP_4
#define PMIC_AUXADC_BAT_TEMP_IRQ_EN_MAX_MASK  0x1
#define PMIC_AUXADC_BAT_TEMP_IRQ_EN_MAX_SHIFT 12
#define PMIC_AUXADC_BAT_TEMP_EN_MAX_ADDR   MT6358_AUXADC_BAT_TEMP_4
#define PMIC_AUXADC_BAT_TEMP_EN_MAX_MASK   0x1
#define PMIC_AUXADC_BAT_TEMP_EN_MAX_SHIFT   13
#define PMIC_AUXADC_BAT_TEMP_MAX_IRQ_B_ADDR MT6358_AUXADC_BAT_TEMP_4
#define PMIC_AUXADC_BAT_TEMP_MAX_IRQ_B_MASK 0x1
#define PMIC_AUXADC_BAT_TEMP_MAX_IRQ_B_SHIFT  15
#define PMIC_AUXADC_BAT_TEMP_VOLT_MIN_ADDR  MT6358_AUXADC_BAT_TEMP_5
#define PMIC_AUXADC_BAT_TEMP_VOLT_MIN_MASK  0xFFF
#define PMIC_AUXADC_BAT_TEMP_VOLT_MIN_SHIFT 0
#define PMIC_AUXADC_BAT_TEMP_IRQ_EN_MIN_ADDR  MT6358_AUXADC_BAT_TEMP_5
#define PMIC_AUXADC_BAT_TEMP_IRQ_EN_MIN_MASK  0x1
#define PMIC_AUXADC_BAT_TEMP_IRQ_EN_MIN_SHIFT 12
#define PMIC_AUXADC_BAT_TEMP_EN_MIN_ADDR   MT6358_AUXADC_BAT_TEMP_5
#define PMIC_AUXADC_BAT_TEMP_EN_MIN_MASK   0x1
#define PMIC_AUXADC_BAT_TEMP_EN_MIN_SHIFT   13
#define PMIC_AUXADC_BAT_TEMP_MIN_IRQ_B_ADDR MT6358_AUXADC_BAT_TEMP_5
#define PMIC_AUXADC_BAT_TEMP_MIN_IRQ_B_MASK 0x1
#define PMIC_AUXADC_BAT_TEMP_MIN_IRQ_B_SHIFT  15
#define PMIC_AUXADC_BAT_TEMP_DEBOUNCE_COUNT_MAX_ADDR   MT6358_AUXADC_BAT_TEMP_6
#define PMIC_AUXADC_BAT_TEMP_DEBOUNCE_COUNT_MAX_MASK   0x1FF
#define PMIC_AUXADC_BAT_TEMP_DEBOUNCE_COUNT_MAX_SHIFT  0
#define PMIC_AUXADC_BAT_TEMP_DEBOUNCE_COUNT_MIN_ADDR   MT6358_AUXADC_BAT_TEMP_7
#define PMIC_AUXADC_BAT_TEMP_DEBOUNCE_COUNT_MIN_MASK   0x1FF
#define PMIC_AUXADC_BAT_TEMP_DEBOUNCE_COUNT_MIN_SHIFT  0
#define PMIC_AUXADC_LBAT2_DEBT_MAX_ADDR MT6358_AUXADC_LBAT2_1
#define PMIC_AUXADC_LBAT2_DEBT_MAX_MASK 0xFF
#define PMIC_AUXADC_LBAT2_DEBT_MAX_SHIFT   0
#define PMIC_AUXADC_LBAT2_DEBT_MIN_ADDR MT6358_AUXADC_LBAT2_1
#define PMIC_AUXADC_LBAT2_DEBT_MIN_MASK 0xFF
#define PMIC_AUXADC_LBAT2_DEBT_MIN_SHIFT   8
#define PMIC_AUXADC_LBAT2_DET_PRD_15_0_ADDR MT6358_AUXADC_LBAT2_2
#define PMIC_AUXADC_LBAT2_DET_PRD_15_0_MASK 0xFFFF
#define PMIC_AUXADC_LBAT2_DET_PRD_15_0_SHIFT  0
#define PMIC_AUXADC_LBAT2_DET_PRD_19_16_ADDR  MT6358_AUXADC_LBAT2_3
#define PMIC_AUXADC_LBAT2_DET_PRD_19_16_MASK  0xF
#define PMIC_AUXADC_LBAT2_DET_PRD_19_16_SHIFT 0
#define PMIC_AUXADC_LBAT2_VOLT_MAX_ADDR MT6358_AUXADC_LBAT2_4
#define PMIC_AUXADC_LBAT2_VOLT_MAX_MASK 0xFFF
#define PMIC_AUXADC_LBAT2_VOLT_MAX_SHIFT   0
#define PMIC_AUXADC_LBAT2_IRQ_EN_MAX_ADDR   MT6358_AUXADC_LBAT2_4
#define PMIC_AUXADC_LBAT2_IRQ_EN_MAX_MASK   0x1
#define PMIC_AUXADC_LBAT2_IRQ_EN_MAX_SHIFT  12
#define PMIC_AUXADC_LBAT2_EN_MAX_ADDR MT6358_AUXADC_LBAT2_4
#define PMIC_AUXADC_LBAT2_EN_MAX_MASK 0x1
#define PMIC_AUXADC_LBAT2_EN_MAX_SHIFT  13
#define PMIC_AUXADC_LBAT2_MAX_IRQ_B_ADDR   MT6358_AUXADC_LBAT2_4
#define PMIC_AUXADC_LBAT2_MAX_IRQ_B_MASK   0x1
#define PMIC_AUXADC_LBAT2_MAX_IRQ_B_SHIFT   15
#define PMIC_AUXADC_LBAT2_VOLT_MIN_ADDR MT6358_AUXADC_LBAT2_5
#define PMIC_AUXADC_LBAT2_VOLT_MIN_MASK 0xFFF
#define PMIC_AUXADC_LBAT2_VOLT_MIN_SHIFT   0
#define PMIC_AUXADC_LBAT2_IRQ_EN_MIN_ADDR   MT6358_AUXADC_LBAT2_5
#define PMIC_AUXADC_LBAT2_IRQ_EN_MIN_MASK   0x1
#define PMIC_AUXADC_LBAT2_IRQ_EN_MIN_SHIFT  12
#define PMIC_AUXADC_LBAT2_EN_MIN_ADDR MT6358_AUXADC_LBAT2_5
#define PMIC_AUXADC_LBAT2_EN_MIN_MASK 0x1
#define PMIC_AUXADC_LBAT2_EN_MIN_SHIFT  13
#define PMIC_AUXADC_LBAT2_MIN_IRQ_B_ADDR   MT6358_AUXADC_LBAT2_5
#define PMIC_AUXADC_LBAT2_MIN_IRQ_B_MASK   0x1
#define PMIC_AUXADC_LBAT2_MIN_IRQ_B_SHIFT   15
#define PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MAX_ADDR MT6358_AUXADC_LBAT2_6
#define PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MAX_MASK 0x1FF
#define PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MAX_SHIFT  0
#define PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MIN_ADDR MT6358_AUXADC_LBAT2_7
#define PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MIN_MASK 0x1FF
#define PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MIN_SHIFT  0
#define PMIC_AUXADC_MDRT_DET_PRD_ADDR MT6358_AUXADC_MDRT_0
#define PMIC_AUXADC_MDRT_DET_PRD_MASK 0x3FF
#define PMIC_AUXADC_MDRT_DET_PRD_SHIFT  0
#define PMIC_AUXADC_MDRT_DET_EN_ADDR  MT6358_AUXADC_MDRT_0
#define PMIC_AUXADC_MDRT_DET_EN_MASK  0x1
#define PMIC_AUXADC_MDRT_DET_EN_SHIFT 15
#define PMIC_AUXADC_MDRT_DET_WKUP_START_CNT_ADDR  MT6358_AUXADC_MDRT_1
#define PMIC_AUXADC_MDRT_DET_WKUP_START_CNT_MASK  0xFFF
#define PMIC_AUXADC_MDRT_DET_WKUP_START_CNT_SHIFT 0
#define PMIC_AUXADC_MDRT_DET_WKUP_START_CLR_ADDR  MT6358_AUXADC_MDRT_1
#define PMIC_AUXADC_MDRT_DET_WKUP_START_CLR_MASK  0x1
#define PMIC_AUXADC_MDRT_DET_WKUP_START_CLR_SHIFT 15
#define PMIC_AUXADC_MDRT_DET_WKUP_START_ADDR  MT6358_AUXADC_MDRT_2
#define PMIC_AUXADC_MDRT_DET_WKUP_START_MASK  0x1
#define PMIC_AUXADC_MDRT_DET_WKUP_START_SHIFT 0
#define PMIC_AUXADC_MDRT_DET_WKUP_START_SEL_ADDR  MT6358_AUXADC_MDRT_2
#define PMIC_AUXADC_MDRT_DET_WKUP_START_SEL_MASK  0x1
#define PMIC_AUXADC_MDRT_DET_WKUP_START_SEL_SHIFT 1
#define PMIC_AUXADC_MDRT_DET_WKUP_EN_ADDR   MT6358_AUXADC_MDRT_2
#define PMIC_AUXADC_MDRT_DET_WKUP_EN_MASK   0x1
#define PMIC_AUXADC_MDRT_DET_WKUP_EN_SHIFT  2
#define PMIC_AUXADC_MDRT_DET_SRCLKEN_IND_ADDR MT6358_AUXADC_MDRT_2
#define PMIC_AUXADC_MDRT_DET_SRCLKEN_IND_MASK 0x1
#define PMIC_AUXADC_MDRT_DET_SRCLKEN_IND_SHIFT   3
#define PMIC_AUXADC_MDRT_DET_RDY_ST_PRD_ADDR  MT6358_AUXADC_MDRT_3
#define PMIC_AUXADC_MDRT_DET_RDY_ST_PRD_MASK  0x3FF
#define PMIC_AUXADC_MDRT_DET_RDY_ST_PRD_SHIFT 0
#define PMIC_AUXADC_MDRT_DET_RDY_ST_EN_ADDR MT6358_AUXADC_MDRT_3
#define PMIC_AUXADC_MDRT_DET_RDY_ST_EN_MASK 0x1
#define PMIC_AUXADC_MDRT_DET_RDY_ST_EN_SHIFT  15
#define PMIC_AUXADC_MDRT_DET_START_SEL_ADDR MT6358_AUXADC_MDRT_4
#define PMIC_AUXADC_MDRT_DET_START_SEL_MASK 0x1
#define PMIC_AUXADC_MDRT_DET_START_SEL_SHIFT  0
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CNT_ADDR  MT6358_AUXADC_DCXO_MDRT_1
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CNT_MASK  0xFFF
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CNT_SHIFT 0
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CLR_ADDR  MT6358_AUXADC_DCXO_MDRT_1
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CLR_MASK  0x1
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CLR_SHIFT 15
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_EN_ADDR   MT6358_AUXADC_DCXO_MDRT_2
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_EN_MASK   0x1
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_EN_SHIFT  0
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_SEL_ADDR  MT6358_AUXADC_DCXO_MDRT_2
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_SEL_MASK  0x1
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_SEL_SHIFT 1
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_ADDR MT6358_AUXADC_DCXO_MDRT_2
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_MASK 0x1
#define PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_SHIFT  2
#define PMIC_AUXADC_NAG_EN_ADDR MT6358_AUXADC_NAG_0
#define PMIC_AUXADC_NAG_EN_MASK 0x1
#define PMIC_AUXADC_NAG_EN_SHIFT  0
#define PMIC_AUXADC_NAG_CLR_ADDR  MT6358_AUXADC_NAG_0
#define PMIC_AUXADC_NAG_CLR_MASK  0x1
#define PMIC_AUXADC_NAG_CLR_SHIFT 1
#define PMIC_AUXADC_NAG_VBAT1_SEL_ADDR  MT6358_AUXADC_NAG_0
#define PMIC_AUXADC_NAG_VBAT1_SEL_MASK  0x1
#define PMIC_AUXADC_NAG_VBAT1_SEL_SHIFT 2
#define PMIC_AUXADC_NAG_PRD_ADDR  MT6358_AUXADC_NAG_0
#define PMIC_AUXADC_NAG_PRD_MASK  0x7F
#define PMIC_AUXADC_NAG_PRD_SHIFT 3
#define PMIC_AUXADC_NAG_IRQ_EN_ADDR   MT6358_AUXADC_NAG_0
#define PMIC_AUXADC_NAG_IRQ_EN_MASK   0x1
#define PMIC_AUXADC_NAG_IRQ_EN_SHIFT  10
#define PMIC_AUXADC_NAG_C_DLTV_IRQ_ADDR MT6358_AUXADC_NAG_0
#define PMIC_AUXADC_NAG_C_DLTV_IRQ_MASK 0x1
#define PMIC_AUXADC_NAG_C_DLTV_IRQ_SHIFT   15
#define PMIC_AUXADC_NAG_ZCV_ADDR  MT6358_AUXADC_NAG_1
#define PMIC_AUXADC_NAG_ZCV_MASK  0x7FFF
#define PMIC_AUXADC_NAG_ZCV_SHIFT 0
#define PMIC_AUXADC_NAG_C_DLTV_TH_15_0_ADDR MT6358_AUXADC_NAG_2
#define PMIC_AUXADC_NAG_C_DLTV_TH_15_0_MASK 0xFFFF
#define PMIC_AUXADC_NAG_C_DLTV_TH_15_0_SHIFT  0
#define PMIC_AUXADC_NAG_C_DLTV_TH_26_16_ADDR  MT6358_AUXADC_NAG_3
#define PMIC_AUXADC_NAG_C_DLTV_TH_26_16_MASK  0x7FF
#define PMIC_AUXADC_NAG_C_DLTV_TH_26_16_SHIFT 0
#define PMIC_AUXADC_NAG_CNT_15_0_ADDR MT6358_AUXADC_NAG_4
#define PMIC_AUXADC_NAG_CNT_15_0_MASK 0xFFFF
#define PMIC_AUXADC_NAG_CNT_15_0_SHIFT  0
#define PMIC_AUXADC_NAG_CNT_25_16_ADDR  MT6358_AUXADC_NAG_5
#define PMIC_AUXADC_NAG_CNT_25_16_MASK  0x3FF
#define PMIC_AUXADC_NAG_CNT_25_16_SHIFT 0
#define PMIC_AUXADC_NAG_DLTV_ADDR MT6358_AUXADC_NAG_6
#define PMIC_AUXADC_NAG_DLTV_MASK 0xFFFF
#define PMIC_AUXADC_NAG_DLTV_SHIFT 0
#define PMIC_AUXADC_NAG_C_DLTV_15_0_ADDR   MT6358_AUXADC_NAG_7
#define PMIC_AUXADC_NAG_C_DLTV_15_0_MASK   0xFFFF
#define PMIC_AUXADC_NAG_C_DLTV_15_0_SHIFT   0
#define PMIC_AUXADC_NAG_C_DLTV_26_16_ADDR   MT6358_AUXADC_NAG_8
#define PMIC_AUXADC_NAG_C_DLTV_26_16_MASK   0x7FF
#define PMIC_AUXADC_NAG_C_DLTV_26_16_SHIFT  0
#define PMIC_AUXADC_NAG_START_ADDR MT6358_AUXADC_NAG_9
#define PMIC_AUXADC_NAG_START_MASK 0x1
#define PMIC_AUXADC_NAG_START_SHIFT   0
#define PMIC_AUXADC_NAG_CK_ON_ADDR MT6358_AUXADC_NAG_9
#define PMIC_AUXADC_NAG_CK_ON_MASK 0x1
#define PMIC_AUXADC_NAG_CK_ON_SHIFT   1
#define PMIC_AUXADC_RSV_1RSV0_ADDR MT6358_AUXADC_RSV_1
#define PMIC_AUXADC_RSV_1RSV0_MASK 0xFFFF
#define PMIC_AUXADC_RSV_1RSV0_SHIFT   0
#define PMIC_AUXADC_NEW_PRIORITY_LIST_SEL_ADDR   MT6358_AUXADC_PRI_NEW
#define PMIC_AUXADC_NEW_PRIORITY_LIST_SEL_MASK   0x1
#define PMIC_AUXADC_NEW_PRIORITY_LIST_SEL_SHIFT  0
#define PMIC_AUXADC_IMP_CK_SW_MODE_ADDR MT6358_AUXADC_DCM_CON
#define PMIC_AUXADC_IMP_CK_SW_MODE_MASK 0x1
#define PMIC_AUXADC_IMP_CK_SW_MODE_SHIFT   0
#define PMIC_AUXADC_IMP_CK_SW_EN_ADDR MT6358_AUXADC_DCM_CON
#define PMIC_AUXADC_IMP_CK_SW_EN_MASK 0x1
#define PMIC_AUXADC_IMP_CK_SW_EN_SHIFT  1
#define PMIC_AUXADC_LBAT_CK_SW_MODE_ADDR   MT6358_AUXADC_DCM_CON
#define PMIC_AUXADC_LBAT_CK_SW_MODE_MASK   0x1
#define PMIC_AUXADC_LBAT_CK_SW_MODE_SHIFT   2
#define PMIC_AUXADC_LBAT_CK_SW_EN_ADDR  MT6358_AUXADC_DCM_CON
#define PMIC_AUXADC_LBAT_CK_SW_EN_MASK  0x1
#define PMIC_AUXADC_LBAT_CK_SW_EN_SHIFT 3
#define PMIC_AUXADC_BAT_TEMP_CK_SW_MODE_ADDR  MT6358_AUXADC_DCM_CON
#define PMIC_AUXADC_BAT_TEMP_CK_SW_MODE_MASK  0x1
#define PMIC_AUXADC_BAT_TEMP_CK_SW_MODE_SHIFT 4
#define PMIC_AUXADC_BAT_TEMP_CK_SW_EN_ADDR  MT6358_AUXADC_DCM_CON
#define PMIC_AUXADC_BAT_TEMP_CK_SW_EN_MASK  0x1
#define PMIC_AUXADC_BAT_TEMP_CK_SW_EN_SHIFT 5
#define PMIC_AUXADC_LBAT2_CK_SW_MODE_ADDR   MT6358_AUXADC_DCM_CON
#define PMIC_AUXADC_LBAT2_CK_SW_MODE_MASK   0x1
#define PMIC_AUXADC_LBAT2_CK_SW_MODE_SHIFT  6
#define PMIC_AUXADC_LBAT2_CK_SW_EN_ADDR MT6358_AUXADC_DCM_CON
#define PMIC_AUXADC_LBAT2_CK_SW_EN_MASK 0x1
#define PMIC_AUXADC_LBAT2_CK_SW_EN_SHIFT   7
#define PMIC_AUXADC_NAG_CK_SW_MODE_ADDR MT6358_AUXADC_DCM_CON
#define PMIC_AUXADC_NAG_CK_SW_MODE_MASK 0x1
#define PMIC_AUXADC_NAG_CK_SW_MODE_SHIFT   8
#define PMIC_AUXADC_NAG_CK_SW_EN_ADDR MT6358_AUXADC_DCM_CON
#define PMIC_AUXADC_NAG_CK_SW_EN_MASK 0x1
#define PMIC_AUXADC_NAG_CK_SW_EN_SHIFT  9
#define PMIC_AUXADC_SAMPLE_LIST_15_0_ADDR   MT6358_AUXADC_SPL_LIST_0
#define PMIC_AUXADC_SAMPLE_LIST_15_0_MASK   0xFFFF
#define PMIC_AUXADC_SAMPLE_LIST_15_0_SHIFT  0
#define PMIC_AUXADC_SAMPLE_LIST_31_16_ADDR  MT6358_AUXADC_SPL_LIST_1
#define PMIC_AUXADC_SAMPLE_LIST_31_16_MASK  0xFFFF
#define PMIC_AUXADC_SAMPLE_LIST_31_16_SHIFT 0
#define PMIC_AUXADC_SAMPLE_LIST_33_32_ADDR  MT6358_AUXADC_SPL_LIST_2
#define PMIC_AUXADC_SAMPLE_LIST_33_32_MASK  0x3
#define PMIC_AUXADC_SAMPLE_LIST_33_32_SHIFT 0
#define PMIC_BUCK_TOP_ANA_ID_ADDR MT6358_BUCK_TOP_DSN_ID
#define PMIC_BUCK_TOP_ANA_ID_MASK 0xFF
#define PMIC_BUCK_TOP_ANA_ID_SHIFT 0
#define PMIC_BUCK_TOP_DIG_ID_ADDR MT6358_BUCK_TOP_DSN_ID
#define PMIC_BUCK_TOP_DIG_ID_MASK 0xFF
#define PMIC_BUCK_TOP_DIG_ID_SHIFT 8
#define PMIC_BUCK_TOP_ANA_MINOR_REV_ADDR   MT6358_BUCK_TOP_DSN_REV0
#define PMIC_BUCK_TOP_ANA_MINOR_REV_MASK   0xF
#define PMIC_BUCK_TOP_ANA_MINOR_REV_SHIFT   0
#define PMIC_BUCK_TOP_ANA_MAJOR_REV_ADDR   MT6358_BUCK_TOP_DSN_REV0
#define PMIC_BUCK_TOP_ANA_MAJOR_REV_MASK   0xF
#define PMIC_BUCK_TOP_ANA_MAJOR_REV_SHIFT   4
#define PMIC_BUCK_TOP_DIG_MINOR_REV_ADDR   MT6358_BUCK_TOP_DSN_REV0
#define PMIC_BUCK_TOP_DIG_MINOR_REV_MASK   0xF
#define PMIC_BUCK_TOP_DIG_MINOR_REV_SHIFT   8
#define PMIC_BUCK_TOP_DIG_MAJOR_REV_ADDR   MT6358_BUCK_TOP_DSN_REV0
#define PMIC_BUCK_TOP_DIG_MAJOR_REV_MASK   0xF
#define PMIC_BUCK_TOP_DIG_MAJOR_REV_SHIFT   12
#define PMIC_BUCK_TOP_CBS_ADDR  MT6358_BUCK_TOP_DBI
#define PMIC_BUCK_TOP_CBS_MASK  0x3
#define PMIC_BUCK_TOP_CBS_SHIFT 0
#define PMIC_BUCK_TOP_BIX_ADDR  MT6358_BUCK_TOP_DBI
#define PMIC_BUCK_TOP_BIX_MASK  0x3
#define PMIC_BUCK_TOP_BIX_SHIFT 2
#define PMIC_BUCK_TOP_ESP_ADDR  MT6358_BUCK_TOP_DBI
#define PMIC_BUCK_TOP_ESP_MASK  0xFF
#define PMIC_BUCK_TOP_ESP_SHIFT 8
#define PMIC_BUCK_TOP_FPI_ADDR  MT6358_BUCK_TOP_DXI
#define PMIC_BUCK_TOP_FPI_MASK  0xFF
#define PMIC_BUCK_TOP_FPI_SHIFT 0
#define PMIC_BUCK_TOP_CLK_OFFSET_ADDR MT6358_BUCK_TOP_PAM0
#define PMIC_BUCK_TOP_CLK_OFFSET_MASK 0xFF
#define PMIC_BUCK_TOP_CLK_OFFSET_SHIFT  0
#define PMIC_BUCK_TOP_RST_OFFSET_ADDR MT6358_BUCK_TOP_PAM0
#define PMIC_BUCK_TOP_RST_OFFSET_MASK 0xFF
#define PMIC_BUCK_TOP_RST_OFFSET_SHIFT  8
#define PMIC_BUCK_TOP_INT_OFFSET_ADDR MT6358_BUCK_TOP_PAM1
#define PMIC_BUCK_TOP_INT_OFFSET_MASK 0xFF
#define PMIC_BUCK_TOP_INT_OFFSET_SHIFT  0
#define PMIC_BUCK_TOP_INT_LEN_ADDR MT6358_BUCK_TOP_PAM1
#define PMIC_BUCK_TOP_INT_LEN_MASK 0xFF
#define PMIC_BUCK_TOP_INT_LEN_SHIFT   8
#define PMIC_RG_BUCK32K_CK_PDN_ADDR   MT6358_BUCK_TOP_CLK_CON0
#define PMIC_RG_BUCK32K_CK_PDN_MASK   0x1
#define PMIC_RG_BUCK32K_CK_PDN_SHIFT  0
#define PMIC_RG_BUCK1M_CK_PDN_ADDR MT6358_BUCK_TOP_CLK_CON0
#define PMIC_RG_BUCK1M_CK_PDN_MASK 0x1
#define PMIC_RG_BUCK1M_CK_PDN_SHIFT   1
#define PMIC_RG_BUCK26M_CK_PDN_ADDR   MT6358_BUCK_TOP_CLK_CON0
#define PMIC_RG_BUCK26M_CK_PDN_MASK   0x1
#define PMIC_RG_BUCK26M_CK_PDN_SHIFT  2
#define PMIC_RG_BUCK_ANA_AUTO_OFF_DIS_ADDR  MT6358_BUCK_TOP_CLK_CON0
#define PMIC_RG_BUCK_ANA_AUTO_OFF_DIS_MASK  0x1
#define PMIC_RG_BUCK_ANA_AUTO_OFF_DIS_SHIFT 3
#define PMIC_RG_BUCK_ANA_CK_PDN_ADDR  MT6358_BUCK_TOP_CLK_CON0
#define PMIC_RG_BUCK_ANA_CK_PDN_MASK  0x1
#define PMIC_RG_BUCK_ANA_CK_PDN_SHIFT 4
#define PMIC_RG_BUCK_TOP_CLK_CON0_SET_ADDR  MT6358_BUCK_TOP_CLK_CON0_SET
#define PMIC_RG_BUCK_TOP_CLK_CON0_SET_MASK  0xFFFF
#define PMIC_RG_BUCK_TOP_CLK_CON0_SET_SHIFT 0
#define PMIC_RG_BUCK_TOP_CLK_CON0_CLR_ADDR  MT6358_BUCK_TOP_CLK_CON0_CLR
#define PMIC_RG_BUCK_TOP_CLK_CON0_CLR_MASK  0xFFFF
#define PMIC_RG_BUCK_TOP_CLK_CON0_CLR_SHIFT 0
#define PMIC_RG_BUCK32K_CK_PDN_HWEN_ADDR   MT6358_BUCK_TOP_CLK_HWEN_CON0
#define PMIC_RG_BUCK32K_CK_PDN_HWEN_MASK   0x1
#define PMIC_RG_BUCK32K_CK_PDN_HWEN_SHIFT   0
#define PMIC_RG_BUCK1M_CK_PDN_HWEN_ADDR MT6358_BUCK_TOP_CLK_HWEN_CON0
#define PMIC_RG_BUCK1M_CK_PDN_HWEN_MASK 0x1
#define PMIC_RG_BUCK1M_CK_PDN_HWEN_SHIFT   1
#define PMIC_RG_BUCK26M_CK_PDN_HWEN_ADDR   MT6358_BUCK_TOP_CLK_HWEN_CON0
#define PMIC_RG_BUCK26M_CK_PDN_HWEN_MASK   0x1
#define PMIC_RG_BUCK26M_CK_PDN_HWEN_SHIFT   2
#define PMIC_RG_BUCK_DCM_MODE_ADDR MT6358_BUCK_TOP_CLK_HWEN_CON0
#define PMIC_RG_BUCK_DCM_MODE_MASK 0x1
#define PMIC_RG_BUCK_DCM_MODE_SHIFT   3
#define PMIC_RG_BUCK_TOP_CLK_HWEN_CON0_SET_ADDR  \
MT6358_BUCK_TOP_CLK_HWEN_CON0_SET
#define PMIC_RG_BUCK_TOP_CLK_HWEN_CON0_SET_MASK  0xFFFF
#define PMIC_RG_BUCK_TOP_CLK_HWEN_CON0_SET_SHIFT  0
#define PMIC_RG_BUCK_TOP_CLK_HWEN_CON0_CLR_ADDR  \
MT6358_BUCK_TOP_CLK_HWEN_CON0_CLR
#define PMIC_RG_BUCK_TOP_CLK_HWEN_CON0_CLR_MASK  0xFFFF
#define PMIC_RG_BUCK_TOP_CLK_HWEN_CON0_CLR_SHIFT  0
#define PMIC_RG_INT_EN_VPROC11_OC_ADDR  MT6358_BUCK_TOP_INT_CON0
#define PMIC_RG_INT_EN_VPROC11_OC_MASK  0x1
#define PMIC_RG_INT_EN_VPROC11_OC_SHIFT 0
#define PMIC_RG_INT_EN_VPROC12_OC_ADDR  MT6358_BUCK_TOP_INT_CON0
#define PMIC_RG_INT_EN_VPROC12_OC_MASK  0x1
#define PMIC_RG_INT_EN_VPROC12_OC_SHIFT 1
#define PMIC_RG_INT_EN_VCORE_OC_ADDR  MT6358_BUCK_TOP_INT_CON0
#define PMIC_RG_INT_EN_VCORE_OC_MASK  0x1
#define PMIC_RG_INT_EN_VCORE_OC_SHIFT 2
#define PMIC_RG_INT_EN_VGPU_OC_ADDR   MT6358_BUCK_TOP_INT_CON0
#define PMIC_RG_INT_EN_VGPU_OC_MASK   0x1
#define PMIC_RG_INT_EN_VGPU_OC_SHIFT  3
#define PMIC_RG_INT_EN_VMODEM_OC_ADDR MT6358_BUCK_TOP_INT_CON0
#define PMIC_RG_INT_EN_VMODEM_OC_MASK 0x1
#define PMIC_RG_INT_EN_VMODEM_OC_SHIFT  4
#define PMIC_RG_INT_EN_VDRAM1_OC_ADDR MT6358_BUCK_TOP_INT_CON0
#define PMIC_RG_INT_EN_VDRAM1_OC_MASK 0x1
#define PMIC_RG_INT_EN_VDRAM1_OC_SHIFT  5
#define PMIC_RG_INT_EN_VS1_OC_ADDR MT6358_BUCK_TOP_INT_CON0
#define PMIC_RG_INT_EN_VS1_OC_MASK 0x1
#define PMIC_RG_INT_EN_VS1_OC_SHIFT   6
#define PMIC_RG_INT_EN_VS2_OC_ADDR MT6358_BUCK_TOP_INT_CON0
#define PMIC_RG_INT_EN_VS2_OC_MASK 0x1
#define PMIC_RG_INT_EN_VS2_OC_SHIFT   7
#define PMIC_RG_INT_EN_VPA_OC_ADDR MT6358_BUCK_TOP_INT_CON0
#define PMIC_RG_INT_EN_VPA_OC_MASK 0x1
#define PMIC_RG_INT_EN_VPA_OC_SHIFT   8
#define PMIC_RG_INT_EN_VCORE_PREOC_ADDR MT6358_BUCK_TOP_INT_CON0
#define PMIC_RG_INT_EN_VCORE_PREOC_MASK 0x1
#define PMIC_RG_INT_EN_VCORE_PREOC_SHIFT   9
#define PMIC_RG_BUCK_TOP_INT_EN_CON0_SET_ADDR MT6358_BUCK_TOP_INT_CON0_SET
#define PMIC_RG_BUCK_TOP_INT_EN_CON0_SET_MASK 0xFFFF
#define PMIC_RG_BUCK_TOP_INT_EN_CON0_SET_SHIFT   0
#define PMIC_RG_BUCK_TOP_INT_EN_CON0_CLR_ADDR MT6358_BUCK_TOP_INT_CON0_CLR
#define PMIC_RG_BUCK_TOP_INT_EN_CON0_CLR_MASK 0xFFFF
#define PMIC_RG_BUCK_TOP_INT_EN_CON0_CLR_SHIFT   0
#define PMIC_RG_INT_MASK_VPROC11_OC_ADDR   MT6358_BUCK_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_VPROC11_OC_MASK   0x1
#define PMIC_RG_INT_MASK_VPROC11_OC_SHIFT   0
#define PMIC_RG_INT_MASK_VPROC12_OC_ADDR   MT6358_BUCK_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_VPROC12_OC_MASK   0x1
#define PMIC_RG_INT_MASK_VPROC12_OC_SHIFT   1
#define PMIC_RG_INT_MASK_VCORE_OC_ADDR  MT6358_BUCK_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_VCORE_OC_MASK  0x1
#define PMIC_RG_INT_MASK_VCORE_OC_SHIFT 2
#define PMIC_RG_INT_MASK_VGPU_OC_ADDR MT6358_BUCK_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_VGPU_OC_MASK 0x1
#define PMIC_RG_INT_MASK_VGPU_OC_SHIFT  3
#define PMIC_RG_INT_MASK_VMODEM_OC_ADDR MT6358_BUCK_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_VMODEM_OC_MASK 0x1
#define PMIC_RG_INT_MASK_VMODEM_OC_SHIFT   4
#define PMIC_RG_INT_MASK_VDRAM1_OC_ADDR MT6358_BUCK_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_VDRAM1_OC_MASK 0x1
#define PMIC_RG_INT_MASK_VDRAM1_OC_SHIFT   5
#define PMIC_RG_INT_MASK_VS1_OC_ADDR  MT6358_BUCK_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_VS1_OC_MASK  0x1
#define PMIC_RG_INT_MASK_VS1_OC_SHIFT 6
#define PMIC_RG_INT_MASK_VS2_OC_ADDR  MT6358_BUCK_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_VS2_OC_MASK  0x1
#define PMIC_RG_INT_MASK_VS2_OC_SHIFT 7
#define PMIC_RG_INT_MASK_VPA_OC_ADDR  MT6358_BUCK_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_VPA_OC_MASK  0x1
#define PMIC_RG_INT_MASK_VPA_OC_SHIFT 8
#define PMIC_RG_INT_MASK_VCORE_PREOC_ADDR   MT6358_BUCK_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_VCORE_PREOC_MASK   0x1
#define PMIC_RG_INT_MASK_VCORE_PREOC_SHIFT  9
#define PMIC_RG_BUCK_TOP_INT_MASK_CON0_SET_ADDR  \
MT6358_BUCK_TOP_INT_MASK_CON0_SET
#define PMIC_RG_BUCK_TOP_INT_MASK_CON0_SET_MASK  0xFFFF
#define PMIC_RG_BUCK_TOP_INT_MASK_CON0_SET_SHIFT  0
#define PMIC_RG_BUCK_TOP_INT_MASK_CON0_CLR_ADDR  \
MT6358_BUCK_TOP_INT_MASK_CON0_CLR
#define PMIC_RG_BUCK_TOP_INT_MASK_CON0_CLR_MASK  0xFFFF
#define PMIC_RG_BUCK_TOP_INT_MASK_CON0_CLR_SHIFT  0
#define PMIC_RG_INT_STATUS_VPROC11_OC_ADDR  MT6358_BUCK_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_VPROC11_OC_MASK  0x1
#define PMIC_RG_INT_STATUS_VPROC11_OC_SHIFT 0
#define PMIC_RG_INT_STATUS_VPROC12_OC_ADDR  MT6358_BUCK_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_VPROC12_OC_MASK  0x1
#define PMIC_RG_INT_STATUS_VPROC12_OC_SHIFT 1
#define PMIC_RG_INT_STATUS_VCORE_OC_ADDR   MT6358_BUCK_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_VCORE_OC_MASK   0x1
#define PMIC_RG_INT_STATUS_VCORE_OC_SHIFT   2
#define PMIC_RG_INT_STATUS_VGPU_OC_ADDR MT6358_BUCK_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_VGPU_OC_MASK 0x1
#define PMIC_RG_INT_STATUS_VGPU_OC_SHIFT   3
#define PMIC_RG_INT_STATUS_VMODEM_OC_ADDR   MT6358_BUCK_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_VMODEM_OC_MASK   0x1
#define PMIC_RG_INT_STATUS_VMODEM_OC_SHIFT  4
#define PMIC_RG_INT_STATUS_VDRAM1_OC_ADDR   MT6358_BUCK_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_VDRAM1_OC_MASK   0x1
#define PMIC_RG_INT_STATUS_VDRAM1_OC_SHIFT  5
#define PMIC_RG_INT_STATUS_VS1_OC_ADDR  MT6358_BUCK_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_VS1_OC_MASK  0x1
#define PMIC_RG_INT_STATUS_VS1_OC_SHIFT 6
#define PMIC_RG_INT_STATUS_VS2_OC_ADDR  MT6358_BUCK_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_VS2_OC_MASK  0x1
#define PMIC_RG_INT_STATUS_VS2_OC_SHIFT 7
#define PMIC_RG_INT_STATUS_VPA_OC_ADDR  MT6358_BUCK_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_VPA_OC_MASK  0x1
#define PMIC_RG_INT_STATUS_VPA_OC_SHIFT 8
#define PMIC_RG_INT_STATUS_VCORE_PREOC_ADDR MT6358_BUCK_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_VCORE_PREOC_MASK 0x1
#define PMIC_RG_INT_STATUS_VCORE_PREOC_SHIFT  9
#define PMIC_RG_INT_RAW_STATUS_VPROC11_OC_ADDR   MT6358_BUCK_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_VPROC11_OC_MASK   0x1
#define PMIC_RG_INT_RAW_STATUS_VPROC11_OC_SHIFT  0
#define PMIC_RG_INT_RAW_STATUS_VPROC12_OC_ADDR   MT6358_BUCK_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_VPROC12_OC_MASK   0x1
#define PMIC_RG_INT_RAW_STATUS_VPROC12_OC_SHIFT  1
#define PMIC_RG_INT_RAW_STATUS_VCORE_OC_ADDR  MT6358_BUCK_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_VCORE_OC_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_VCORE_OC_SHIFT 2
#define PMIC_RG_INT_RAW_STATUS_VGPU_OC_ADDR MT6358_BUCK_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_VGPU_OC_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_VGPU_OC_SHIFT  3
#define PMIC_RG_INT_RAW_STATUS_VMODEM_OC_ADDR MT6358_BUCK_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_VMODEM_OC_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_VMODEM_OC_SHIFT   4
#define PMIC_RG_INT_RAW_STATUS_VDRAM1_OC_ADDR MT6358_BUCK_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_VDRAM1_OC_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_VDRAM1_OC_SHIFT   5
#define PMIC_RG_INT_RAW_STATUS_VS1_OC_ADDR  MT6358_BUCK_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_VS1_OC_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_VS1_OC_SHIFT 6
#define PMIC_RG_INT_RAW_STATUS_VS2_OC_ADDR  MT6358_BUCK_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_VS2_OC_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_VS2_OC_SHIFT 7
#define PMIC_RG_INT_RAW_STATUS_VPA_OC_ADDR  MT6358_BUCK_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_VPA_OC_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_VPA_OC_SHIFT 8
#define PMIC_RG_INT_RAW_STATUS_VCORE_PREOC_ADDR  MT6358_BUCK_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_VCORE_PREOC_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_VCORE_PREOC_SHIFT  9
#define PMIC_RG_BUCK_STB_MAX_ADDR MT6358_BUCK_TOP_STB_CON
#define PMIC_RG_BUCK_STB_MAX_MASK 0x1FF
#define PMIC_RG_BUCK_STB_MAX_SHIFT 0
#define PMIC_RG_BUCK_LP_PROT_DISABLE_ADDR   MT6358_BUCK_TOP_STB_CON
#define PMIC_RG_BUCK_LP_PROT_DISABLE_MASK   0x1
#define PMIC_RG_BUCK_LP_PROT_DISABLE_SHIFT  9
#define PMIC_RG_BUCK_VSLEEP_SRC0_ADDR MT6358_BUCK_TOP_SLP_CON0
#define PMIC_RG_BUCK_VSLEEP_SRC0_MASK 0x1FF
#define PMIC_RG_BUCK_VSLEEP_SRC0_SHIFT  0
#define PMIC_RG_BUCK_VSLEEP_SRC1_ADDR MT6358_BUCK_TOP_SLP_CON0
#define PMIC_RG_BUCK_VSLEEP_SRC1_MASK 0xF
#define PMIC_RG_BUCK_VSLEEP_SRC1_SHIFT  12
#define PMIC_RG_BUCK_R2R_SRC0_ADDR MT6358_BUCK_TOP_SLP_CON1
#define PMIC_RG_BUCK_R2R_SRC0_MASK 0x1FF
#define PMIC_RG_BUCK_R2R_SRC0_SHIFT   0
#define PMIC_RG_BUCK_R2R_SRC1_ADDR MT6358_BUCK_TOP_SLP_CON1
#define PMIC_RG_BUCK_R2R_SRC1_MASK 0xF
#define PMIC_RG_BUCK_R2R_SRC1_SHIFT   12
#define PMIC_RG_BUCK_LP_SEQ_COUNT_ADDR  MT6358_BUCK_TOP_SLP_CON2
#define PMIC_RG_BUCK_LP_SEQ_COUNT_MASK  0x1FF
#define PMIC_RG_BUCK_LP_SEQ_COUNT_SHIFT 0
#define PMIC_RG_BUCK_ON_SEQ_COUNT_ADDR  MT6358_BUCK_TOP_SLP_CON2
#define PMIC_RG_BUCK_ON_SEQ_COUNT_MASK  0xF
#define PMIC_RG_BUCK_ON_SEQ_COUNT_SHIFT 12
#define PMIC_RG_BUCK_MINFREQ_LATENCY_MAX_ADDR MT6358_BUCK_TOP_MINFREQ_CON
#define PMIC_RG_BUCK_MINFREQ_LATENCY_MAX_MASK 0xFF
#define PMIC_RG_BUCK_MINFREQ_LATENCY_MAX_SHIFT   0
#define PMIC_RG_BUCK_MINFREQ_DURATION_MAX_ADDR   MT6358_BUCK_TOP_MINFREQ_CON
#define PMIC_RG_BUCK_MINFREQ_DURATION_MAX_MASK   0x7
#define PMIC_RG_BUCK_MINFREQ_DURATION_MAX_SHIFT  8
#define PMIC_RG_BUCK_VPROC11_OC_SDN_STATUS_ADDR  MT6358_BUCK_TOP_OC_CON0
#define PMIC_RG_BUCK_VPROC11_OC_SDN_STATUS_MASK  0x1
#define PMIC_RG_BUCK_VPROC11_OC_SDN_STATUS_SHIFT  0
#define PMIC_RG_BUCK_VPROC12_OC_SDN_STATUS_ADDR  MT6358_BUCK_TOP_OC_CON0
#define PMIC_RG_BUCK_VPROC12_OC_SDN_STATUS_MASK  0x1
#define PMIC_RG_BUCK_VPROC12_OC_SDN_STATUS_SHIFT  1
#define PMIC_RG_BUCK_VCORE_OC_SDN_STATUS_ADDR MT6358_BUCK_TOP_OC_CON0
#define PMIC_RG_BUCK_VCORE_OC_SDN_STATUS_MASK 0x1
#define PMIC_RG_BUCK_VCORE_OC_SDN_STATUS_SHIFT   2
#define PMIC_RG_BUCK_VGPU_OC_SDN_STATUS_ADDR  MT6358_BUCK_TOP_OC_CON0
#define PMIC_RG_BUCK_VGPU_OC_SDN_STATUS_MASK  0x1
#define PMIC_RG_BUCK_VGPU_OC_SDN_STATUS_SHIFT 3
#define PMIC_RG_BUCK_VMODEM_OC_SDN_STATUS_ADDR   MT6358_BUCK_TOP_OC_CON0
#define PMIC_RG_BUCK_VMODEM_OC_SDN_STATUS_MASK   0x1
#define PMIC_RG_BUCK_VMODEM_OC_SDN_STATUS_SHIFT  4
#define PMIC_RG_BUCK_VDRAM1_OC_SDN_STATUS_ADDR   MT6358_BUCK_TOP_OC_CON0
#define PMIC_RG_BUCK_VDRAM1_OC_SDN_STATUS_MASK   0x1
#define PMIC_RG_BUCK_VDRAM1_OC_SDN_STATUS_SHIFT  5
#define PMIC_RG_BUCK_VS1_OC_SDN_STATUS_ADDR MT6358_BUCK_TOP_OC_CON0
#define PMIC_RG_BUCK_VS1_OC_SDN_STATUS_MASK 0x1
#define PMIC_RG_BUCK_VS1_OC_SDN_STATUS_SHIFT  6
#define PMIC_RG_BUCK_VS2_OC_SDN_STATUS_ADDR MT6358_BUCK_TOP_OC_CON0
#define PMIC_RG_BUCK_VS2_OC_SDN_STATUS_MASK 0x1
#define PMIC_RG_BUCK_VS2_OC_SDN_STATUS_SHIFT  7
#define PMIC_RG_BUCK_VPA_OC_SDN_STATUS_ADDR MT6358_BUCK_TOP_OC_CON0
#define PMIC_RG_BUCK_VPA_OC_SDN_STATUS_MASK 0x1
#define PMIC_RG_BUCK_VPA_OC_SDN_STATUS_SHIFT  8
#define PMIC_RG_BUCK_K_RST_DONE_ADDR  MT6358_BUCK_TOP_K_CON0
#define PMIC_RG_BUCK_K_RST_DONE_MASK  0x1
#define PMIC_RG_BUCK_K_RST_DONE_SHIFT 0
#define PMIC_RG_BUCK_K_MAP_SEL_ADDR   MT6358_BUCK_TOP_K_CON0
#define PMIC_RG_BUCK_K_MAP_SEL_MASK   0x1
#define PMIC_RG_BUCK_K_MAP_SEL_SHIFT  1
#define PMIC_RG_BUCK_K_ONCE_EN_ADDR   MT6358_BUCK_TOP_K_CON0
#define PMIC_RG_BUCK_K_ONCE_EN_MASK   0x1
#define PMIC_RG_BUCK_K_ONCE_EN_SHIFT  2
#define PMIC_RG_BUCK_K_ONCE_ADDR  MT6358_BUCK_TOP_K_CON0
#define PMIC_RG_BUCK_K_ONCE_MASK  0x1
#define PMIC_RG_BUCK_K_ONCE_SHIFT 3
#define PMIC_RG_BUCK_K_START_MANUAL_ADDR   MT6358_BUCK_TOP_K_CON0
#define PMIC_RG_BUCK_K_START_MANUAL_MASK   0x1
#define PMIC_RG_BUCK_K_START_MANUAL_SHIFT   4
#define PMIC_RG_BUCK_K_SRC_SEL_ADDR   MT6358_BUCK_TOP_K_CON0
#define PMIC_RG_BUCK_K_SRC_SEL_MASK   0x1
#define PMIC_RG_BUCK_K_SRC_SEL_SHIFT  5
#define PMIC_RG_BUCK_K_AUTO_EN_ADDR   MT6358_BUCK_TOP_K_CON0
#define PMIC_RG_BUCK_K_AUTO_EN_MASK   0x1
#define PMIC_RG_BUCK_K_AUTO_EN_SHIFT  6
#define PMIC_RG_BUCK_K_INV_ADDR MT6358_BUCK_TOP_K_CON0
#define PMIC_RG_BUCK_K_INV_MASK 0x1
#define PMIC_RG_BUCK_K_INV_SHIFT  7
#define PMIC_RG_BUCK_K_CK_EN_ADDR MT6358_BUCK_TOP_K_CON0
#define PMIC_RG_BUCK_K_CK_EN_MASK 0x1
#define PMIC_RG_BUCK_K_CK_EN_SHIFT 8
#define PMIC_BUCK_K_RESULT_ADDR MT6358_BUCK_TOP_K_CON1
#define PMIC_BUCK_K_RESULT_MASK 0x1
#define PMIC_BUCK_K_RESULT_SHIFT  0
#define PMIC_BUCK_K_DONE_ADDR   MT6358_BUCK_TOP_K_CON1
#define PMIC_BUCK_K_DONE_MASK   0x1
#define PMIC_BUCK_K_DONE_SHIFT  1
#define PMIC_BUCK_K_CONTROL_ADDR  MT6358_BUCK_TOP_K_CON1
#define PMIC_BUCK_K_CONTROL_MASK  0x3F
#define PMIC_BUCK_K_CONTROL_SHIFT 2
#define PMIC_DA_SMPS_OSC_CAL_ADDR MT6358_BUCK_TOP_K_CON1
#define PMIC_DA_SMPS_OSC_CAL_MASK 0x3F
#define PMIC_DA_SMPS_OSC_CAL_SHIFT 8
#define PMIC_RG_BUCK_K_BUCK_CK_CNT_ADDR MT6358_BUCK_TOP_K_CON2
#define PMIC_RG_BUCK_K_BUCK_CK_CNT_MASK 0x3FF
#define PMIC_RG_BUCK_K_BUCK_CK_CNT_SHIFT   0
#define PMIC_BUCK_VPROC11_WDTDBG_VOSEL_ADDR MT6358_BUCK_TOP_WDTDBG0
#define PMIC_BUCK_VPROC11_WDTDBG_VOSEL_MASK 0x7F
#define PMIC_BUCK_VPROC11_WDTDBG_VOSEL_SHIFT  0
#define PMIC_BUCK_VPROC12_WDTDBG_VOSEL_ADDR MT6358_BUCK_TOP_WDTDBG0
#define PMIC_BUCK_VPROC12_WDTDBG_VOSEL_MASK 0x7F
#define PMIC_BUCK_VPROC12_WDTDBG_VOSEL_SHIFT  8
#define PMIC_BUCK_VCORE_WDTDBG_VOSEL_ADDR   MT6358_BUCK_TOP_WDTDBG1
#define PMIC_BUCK_VCORE_WDTDBG_VOSEL_MASK   0x7F
#define PMIC_BUCK_VCORE_WDTDBG_VOSEL_SHIFT  0
#define PMIC_BUCK_VGPU_WDTDBG_VOSEL_ADDR   MT6358_BUCK_TOP_WDTDBG1
#define PMIC_BUCK_VGPU_WDTDBG_VOSEL_MASK   0x7F
#define PMIC_BUCK_VGPU_WDTDBG_VOSEL_SHIFT   8
#define PMIC_BUCK_VMODEM_WDTDBG_VOSEL_ADDR  MT6358_BUCK_TOP_WDTDBG2
#define PMIC_BUCK_VMODEM_WDTDBG_VOSEL_MASK  0x7F
#define PMIC_BUCK_VMODEM_WDTDBG_VOSEL_SHIFT 0
#define PMIC_BUCK_VDRAM1_WDTDBG_VOSEL_ADDR  MT6358_BUCK_TOP_WDTDBG2
#define PMIC_BUCK_VDRAM1_WDTDBG_VOSEL_MASK  0x7F
#define PMIC_BUCK_VDRAM1_WDTDBG_VOSEL_SHIFT 8
#define PMIC_BUCK_VS1_WDTDBG_VOSEL_ADDR MT6358_BUCK_TOP_WDTDBG3
#define PMIC_BUCK_VS1_WDTDBG_VOSEL_MASK 0x7F
#define PMIC_BUCK_VS1_WDTDBG_VOSEL_SHIFT   0
#define PMIC_BUCK_VS2_WDTDBG_VOSEL_ADDR MT6358_BUCK_TOP_WDTDBG3
#define PMIC_BUCK_VS2_WDTDBG_VOSEL_MASK 0x7F
#define PMIC_BUCK_VS2_WDTDBG_VOSEL_SHIFT   8
#define PMIC_BUCK_VPA_WDTDBG_VOSEL_ADDR MT6358_BUCK_TOP_WDTDBG4
#define PMIC_BUCK_VPA_WDTDBG_VOSEL_MASK 0x3F
#define PMIC_BUCK_VPA_WDTDBG_VOSEL_SHIFT   0
#define PMIC_BUCK_TOP_ELR_LEN_ADDR MT6358_BUCK_TOP_ELR_NUM
#define PMIC_BUCK_TOP_ELR_LEN_MASK 0xFF
#define PMIC_BUCK_TOP_ELR_LEN_SHIFT   0
#define PMIC_RG_BUCK_VPROC11_OC_SDN_EN_ADDR MT6358_BUCK_TOP_ELR0
#define PMIC_RG_BUCK_VPROC11_OC_SDN_EN_MASK 0x1
#define PMIC_RG_BUCK_VPROC11_OC_SDN_EN_SHIFT  0
#define PMIC_RG_BUCK_VPROC12_OC_SDN_EN_ADDR MT6358_BUCK_TOP_ELR0
#define PMIC_RG_BUCK_VPROC12_OC_SDN_EN_MASK 0x1
#define PMIC_RG_BUCK_VPROC12_OC_SDN_EN_SHIFT  1
#define PMIC_RG_BUCK_VCORE_OC_SDN_EN_ADDR   MT6358_BUCK_TOP_ELR0
#define PMIC_RG_BUCK_VCORE_OC_SDN_EN_MASK   0x1
#define PMIC_RG_BUCK_VCORE_OC_SDN_EN_SHIFT  2
#define PMIC_RG_BUCK_VGPU_OC_SDN_EN_ADDR   MT6358_BUCK_TOP_ELR0
#define PMIC_RG_BUCK_VGPU_OC_SDN_EN_MASK   0x1
#define PMIC_RG_BUCK_VGPU_OC_SDN_EN_SHIFT   3
#define PMIC_RG_BUCK_VMODEM_OC_SDN_EN_ADDR  MT6358_BUCK_TOP_ELR0
#define PMIC_RG_BUCK_VMODEM_OC_SDN_EN_MASK  0x1
#define PMIC_RG_BUCK_VMODEM_OC_SDN_EN_SHIFT 4
#define PMIC_RG_BUCK_VDRAM1_OC_SDN_EN_ADDR  MT6358_BUCK_TOP_ELR0
#define PMIC_RG_BUCK_VDRAM1_OC_SDN_EN_MASK  0x1
#define PMIC_RG_BUCK_VDRAM1_OC_SDN_EN_SHIFT 5
#define PMIC_RG_BUCK_VS1_OC_SDN_EN_ADDR MT6358_BUCK_TOP_ELR0
#define PMIC_RG_BUCK_VS1_OC_SDN_EN_MASK 0x1
#define PMIC_RG_BUCK_VS1_OC_SDN_EN_SHIFT   6
#define PMIC_RG_BUCK_VS2_OC_SDN_EN_ADDR MT6358_BUCK_TOP_ELR0
#define PMIC_RG_BUCK_VS2_OC_SDN_EN_MASK 0x1
#define PMIC_RG_BUCK_VS2_OC_SDN_EN_SHIFT   7
#define PMIC_RG_BUCK_VPA_OC_SDN_EN_ADDR MT6358_BUCK_TOP_ELR0
#define PMIC_RG_BUCK_VPA_OC_SDN_EN_MASK 0x1
#define PMIC_RG_BUCK_VPA_OC_SDN_EN_SHIFT   8
#define PMIC_RG_BUCK_OC_SDN_EN_SEL_ADDR MT6358_BUCK_TOP_ELR0
#define PMIC_RG_BUCK_OC_SDN_EN_SEL_MASK 0x1
#define PMIC_RG_BUCK_OC_SDN_EN_SEL_SHIFT   9
#define PMIC_RG_BUCK_K_CONTROL_SMPS_ADDR   MT6358_BUCK_TOP_ELR0
#define PMIC_RG_BUCK_K_CONTROL_SMPS_MASK   0x3F
#define PMIC_RG_BUCK_K_CONTROL_SMPS_SHIFT   10
#define PMIC_RG_BUCK_VPROC11_VOSEL_LIMIT_SEL_ADDR MT6358_BUCK_TOP_ELR1
#define PMIC_RG_BUCK_VPROC11_VOSEL_LIMIT_SEL_MASK 0x3
#define PMIC_RG_BUCK_VPROC11_VOSEL_LIMIT_SEL_SHIFT  0
#define PMIC_RG_BUCK_VPROC12_VOSEL_LIMIT_SEL_ADDR MT6358_BUCK_TOP_ELR1
#define PMIC_RG_BUCK_VPROC12_VOSEL_LIMIT_SEL_MASK 0x3
#define PMIC_RG_BUCK_VPROC12_VOSEL_LIMIT_SEL_SHIFT  2
#define PMIC_RG_BUCK_VCORE_VOSEL_LIMIT_SEL_ADDR  MT6358_BUCK_TOP_ELR1
#define PMIC_RG_BUCK_VCORE_VOSEL_LIMIT_SEL_MASK  0x3
#define PMIC_RG_BUCK_VCORE_VOSEL_LIMIT_SEL_SHIFT  4
#define PMIC_RG_BUCK_VGPU_VOSEL_LIMIT_SEL_ADDR   MT6358_BUCK_TOP_ELR1
#define PMIC_RG_BUCK_VGPU_VOSEL_LIMIT_SEL_MASK   0x3
#define PMIC_RG_BUCK_VGPU_VOSEL_LIMIT_SEL_SHIFT  6
#define PMIC_RG_BUCK_VMODEM_VOSEL_LIMIT_SEL_ADDR  MT6358_BUCK_TOP_ELR1
#define PMIC_RG_BUCK_VMODEM_VOSEL_LIMIT_SEL_MASK  0x3
#define PMIC_RG_BUCK_VMODEM_VOSEL_LIMIT_SEL_SHIFT 8
#define PMIC_RG_BUCK_VDRAM1_VOSEL_LIMIT_SEL_ADDR  MT6358_BUCK_TOP_ELR1
#define PMIC_RG_BUCK_VDRAM1_VOSEL_LIMIT_SEL_MASK  0x3
#define PMIC_RG_BUCK_VDRAM1_VOSEL_LIMIT_SEL_SHIFT 10
#define PMIC_RG_BUCK_VS1_VOSEL_LIMIT_SEL_ADDR MT6358_BUCK_TOP_ELR1
#define PMIC_RG_BUCK_VS1_VOSEL_LIMIT_SEL_MASK 0x3
#define PMIC_RG_BUCK_VS1_VOSEL_LIMIT_SEL_SHIFT   12
#define PMIC_RG_BUCK_VS2_VOSEL_LIMIT_SEL_ADDR MT6358_BUCK_TOP_ELR1
#define PMIC_RG_BUCK_VS2_VOSEL_LIMIT_SEL_MASK 0x3
#define PMIC_RG_BUCK_VS2_VOSEL_LIMIT_SEL_SHIFT   14
#define PMIC_RG_BUCK_VPA_VOSEL_LIMIT_SEL_ADDR MT6358_BUCK_TOP_ELR2
#define PMIC_RG_BUCK_VPA_VOSEL_LIMIT_SEL_MASK 0x3
#define PMIC_RG_BUCK_VPA_VOSEL_LIMIT_SEL_SHIFT   0
#define PMIC_RG_BUCK_VDRAM1_VOSEL_LP3_ADDR  MT6358_BUCK_TOP_ELR3
#define PMIC_RG_BUCK_VDRAM1_VOSEL_LP3_MASK  0x7F
#define PMIC_RG_BUCK_VDRAM1_VOSEL_LP3_SHIFT 0
#define PMIC_BUCK_VPROC11_ANA_ID_ADDR MT6358_BUCK_VPROC11_DSN_ID
#define PMIC_BUCK_VPROC11_ANA_ID_MASK 0xFF
#define PMIC_BUCK_VPROC11_ANA_ID_SHIFT  0
#define PMIC_BUCK_VPROC11_DIG_ID_ADDR MT6358_BUCK_VPROC11_DSN_ID
#define PMIC_BUCK_VPROC11_DIG_ID_MASK 0xFF
#define PMIC_BUCK_VPROC11_DIG_ID_SHIFT  8
#define PMIC_BUCK_VPROC11_ANA_MINOR_REV_ADDR  MT6358_BUCK_VPROC11_DSN_REV0
#define PMIC_BUCK_VPROC11_ANA_MINOR_REV_MASK  0xF
#define PMIC_BUCK_VPROC11_ANA_MINOR_REV_SHIFT 0
#define PMIC_BUCK_VPROC11_ANA_MAJOR_REV_ADDR  MT6358_BUCK_VPROC11_DSN_REV0
#define PMIC_BUCK_VPROC11_ANA_MAJOR_REV_MASK  0xF
#define PMIC_BUCK_VPROC11_ANA_MAJOR_REV_SHIFT 4
#define PMIC_BUCK_VPROC11_DIG_MINOR_REV_ADDR  MT6358_BUCK_VPROC11_DSN_REV0
#define PMIC_BUCK_VPROC11_DIG_MINOR_REV_MASK  0xF
#define PMIC_BUCK_VPROC11_DIG_MINOR_REV_SHIFT 8
#define PMIC_BUCK_VPROC11_DIG_MAJOR_REV_ADDR  MT6358_BUCK_VPROC11_DSN_REV0
#define PMIC_BUCK_VPROC11_DIG_MAJOR_REV_MASK  0xF
#define PMIC_BUCK_VPROC11_DIG_MAJOR_REV_SHIFT 12
#define PMIC_BUCK_VPROC11_DSN_CBS_ADDR  MT6358_BUCK_VPROC11_DSN_DBI
#define PMIC_BUCK_VPROC11_DSN_CBS_MASK  0x3
#define PMIC_BUCK_VPROC11_DSN_CBS_SHIFT 0
#define PMIC_BUCK_VPROC11_DSN_BIX_ADDR  MT6358_BUCK_VPROC11_DSN_DBI
#define PMIC_BUCK_VPROC11_DSN_BIX_MASK  0x3
#define PMIC_BUCK_VPROC11_DSN_BIX_SHIFT 2
#define PMIC_BUCK_VPROC11_DSN_ESP_ADDR  MT6358_BUCK_VPROC11_DSN_DBI
#define PMIC_BUCK_VPROC11_DSN_ESP_MASK  0xFF
#define PMIC_BUCK_VPROC11_DSN_ESP_SHIFT 8
#define PMIC_BUCK_VPROC11_DSN_FPI_SSHUB_ADDR  MT6358_BUCK_VPROC11_DSN_DXI
#define PMIC_BUCK_VPROC11_DSN_FPI_SSHUB_MASK  0x1
#define PMIC_BUCK_VPROC11_DSN_FPI_SSHUB_SHIFT 0
#define PMIC_BUCK_VPROC11_DSN_FPI_TRACKING_ADDR  MT6358_BUCK_VPROC11_DSN_DXI
#define PMIC_BUCK_VPROC11_DSN_FPI_TRACKING_MASK  0x1
#define PMIC_BUCK_VPROC11_DSN_FPI_TRACKING_SHIFT  1
#define PMIC_BUCK_VPROC11_DSN_FPI_PREOC_ADDR  MT6358_BUCK_VPROC11_DSN_DXI
#define PMIC_BUCK_VPROC11_DSN_FPI_PREOC_MASK  0x1
#define PMIC_BUCK_VPROC11_DSN_FPI_PREOC_SHIFT 2
#define PMIC_BUCK_VPROC11_DSN_FPI_VOTER_ADDR  MT6358_BUCK_VPROC11_DSN_DXI
#define PMIC_BUCK_VPROC11_DSN_FPI_VOTER_MASK  0x1
#define PMIC_BUCK_VPROC11_DSN_FPI_VOTER_SHIFT 3
#define PMIC_BUCK_VPROC11_DSN_FPI_ULTRASONIC_ADDR MT6358_BUCK_VPROC11_DSN_DXI
#define PMIC_BUCK_VPROC11_DSN_FPI_ULTRASONIC_MASK 0x1
#define PMIC_BUCK_VPROC11_DSN_FPI_ULTRASONIC_SHIFT  4
#define PMIC_BUCK_VPROC11_DSN_FPI_DLC_ADDR  MT6358_BUCK_VPROC11_DSN_DXI
#define PMIC_BUCK_VPROC11_DSN_FPI_DLC_MASK  0x1
#define PMIC_BUCK_VPROC11_DSN_FPI_DLC_SHIFT 5
#define PMIC_BUCK_VPROC11_DSN_FPI_TRAP_ADDR MT6358_BUCK_VPROC11_DSN_DXI
#define PMIC_BUCK_VPROC11_DSN_FPI_TRAP_MASK 0x1
#define PMIC_BUCK_VPROC11_DSN_FPI_TRAP_SHIFT  6
#define PMIC_RG_BUCK_VPROC11_EN_ADDR  MT6358_BUCK_VPROC11_CON0
#define PMIC_RG_BUCK_VPROC11_EN_MASK  0x1
#define PMIC_RG_BUCK_VPROC11_EN_SHIFT 0
#define PMIC_RG_BUCK_VPROC11_LP_ADDR  MT6358_BUCK_VPROC11_CON0
#define PMIC_RG_BUCK_VPROC11_LP_MASK  0x1
#define PMIC_RG_BUCK_VPROC11_LP_SHIFT 1
#define PMIC_RG_BUCK_VPROC11_VOSEL_SLEEP_ADDR MT6358_BUCK_VPROC11_CON1
#define PMIC_RG_BUCK_VPROC11_VOSEL_SLEEP_MASK 0x7F
#define PMIC_RG_BUCK_VPROC11_VOSEL_SLEEP_SHIFT   0
#define PMIC_RG_BUCK_VPROC11_SFCHG_FRATE_ADDR MT6358_BUCK_VPROC11_CFG0
#define PMIC_RG_BUCK_VPROC11_SFCHG_FRATE_MASK 0x7F
#define PMIC_RG_BUCK_VPROC11_SFCHG_FRATE_SHIFT   0
#define PMIC_RG_BUCK_VPROC11_SFCHG_FEN_ADDR MT6358_BUCK_VPROC11_CFG0
#define PMIC_RG_BUCK_VPROC11_SFCHG_FEN_MASK 0x1
#define PMIC_RG_BUCK_VPROC11_SFCHG_FEN_SHIFT  7
#define PMIC_RG_BUCK_VPROC11_SFCHG_RRATE_ADDR MT6358_BUCK_VPROC11_CFG0
#define PMIC_RG_BUCK_VPROC11_SFCHG_RRATE_MASK 0x7F
#define PMIC_RG_BUCK_VPROC11_SFCHG_RRATE_SHIFT   8
#define PMIC_RG_BUCK_VPROC11_SFCHG_REN_ADDR MT6358_BUCK_VPROC11_CFG0
#define PMIC_RG_BUCK_VPROC11_SFCHG_REN_MASK 0x1
#define PMIC_RG_BUCK_VPROC11_SFCHG_REN_SHIFT  15
#define PMIC_RG_BUCK_VPROC11_DVS_EN_TD_ADDR MT6358_BUCK_VPROC11_CFG1
#define PMIC_RG_BUCK_VPROC11_DVS_EN_TD_MASK 0x3
#define PMIC_RG_BUCK_VPROC11_DVS_EN_TD_SHIFT  0
#define PMIC_RG_BUCK_VPROC11_DVS_EN_CTRL_ADDR MT6358_BUCK_VPROC11_CFG1
#define PMIC_RG_BUCK_VPROC11_DVS_EN_CTRL_MASK 0x3
#define PMIC_RG_BUCK_VPROC11_DVS_EN_CTRL_SHIFT   4
#define PMIC_RG_BUCK_VPROC11_DVS_EN_ONCE_ADDR MT6358_BUCK_VPROC11_CFG1
#define PMIC_RG_BUCK_VPROC11_DVS_EN_ONCE_MASK 0x1
#define PMIC_RG_BUCK_VPROC11_DVS_EN_ONCE_SHIFT   6
#define PMIC_RG_BUCK_VPROC11_DVS_DOWN_TD_ADDR MT6358_BUCK_VPROC11_CFG1
#define PMIC_RG_BUCK_VPROC11_DVS_DOWN_TD_MASK 0x3
#define PMIC_RG_BUCK_VPROC11_DVS_DOWN_TD_SHIFT   8
#define PMIC_RG_BUCK_VPROC11_DVS_DOWN_CTRL_ADDR  MT6358_BUCK_VPROC11_CFG1
#define PMIC_RG_BUCK_VPROC11_DVS_DOWN_CTRL_MASK  0x3
#define PMIC_RG_BUCK_VPROC11_DVS_DOWN_CTRL_SHIFT  12
#define PMIC_RG_BUCK_VPROC11_DVS_DOWN_ONCE_ADDR  MT6358_BUCK_VPROC11_CFG1
#define PMIC_RG_BUCK_VPROC11_DVS_DOWN_ONCE_MASK  0x1
#define PMIC_RG_BUCK_VPROC11_DVS_DOWN_ONCE_SHIFT  14
#define PMIC_RG_BUCK_VPROC11_SW_OP_EN_ADDR  MT6358_BUCK_VPROC11_OP_EN
#define PMIC_RG_BUCK_VPROC11_SW_OP_EN_MASK  0x1
#define PMIC_RG_BUCK_VPROC11_SW_OP_EN_SHIFT 0
#define PMIC_RG_BUCK_VPROC11_HW0_OP_EN_ADDR MT6358_BUCK_VPROC11_OP_EN
#define PMIC_RG_BUCK_VPROC11_HW0_OP_EN_MASK 0x1
#define PMIC_RG_BUCK_VPROC11_HW0_OP_EN_SHIFT  1
#define PMIC_RG_BUCK_VPROC11_HW1_OP_EN_ADDR MT6358_BUCK_VPROC11_OP_EN
#define PMIC_RG_BUCK_VPROC11_HW1_OP_EN_MASK 0x1
#define PMIC_RG_BUCK_VPROC11_HW1_OP_EN_SHIFT  2
#define PMIC_RG_BUCK_VPROC11_HW2_OP_EN_ADDR MT6358_BUCK_VPROC11_OP_EN
#define PMIC_RG_BUCK_VPROC11_HW2_OP_EN_MASK 0x1
#define PMIC_RG_BUCK_VPROC11_HW2_OP_EN_SHIFT  3
#define PMIC_RG_BUCK_VPROC11_OP_EN_SET_ADDR MT6358_BUCK_VPROC11_OP_EN_SET
#define PMIC_RG_BUCK_VPROC11_OP_EN_SET_MASK 0xFFFF
#define PMIC_RG_BUCK_VPROC11_OP_EN_SET_SHIFT  0
#define PMIC_RG_BUCK_VPROC11_OP_EN_CLR_ADDR MT6358_BUCK_VPROC11_OP_EN_CLR
#define PMIC_RG_BUCK_VPROC11_OP_EN_CLR_MASK 0xFFFF
#define PMIC_RG_BUCK_VPROC11_OP_EN_CLR_SHIFT  0
#define PMIC_RG_BUCK_VPROC11_HW0_OP_CFG_ADDR  MT6358_BUCK_VPROC11_OP_CFG
#define PMIC_RG_BUCK_VPROC11_HW0_OP_CFG_MASK  0x1
#define PMIC_RG_BUCK_VPROC11_HW0_OP_CFG_SHIFT 1
#define PMIC_RG_BUCK_VPROC11_HW1_OP_CFG_ADDR  MT6358_BUCK_VPROC11_OP_CFG
#define PMIC_RG_BUCK_VPROC11_HW1_OP_CFG_MASK  0x1
#define PMIC_RG_BUCK_VPROC11_HW1_OP_CFG_SHIFT 2
#define PMIC_RG_BUCK_VPROC11_HW2_OP_CFG_ADDR  MT6358_BUCK_VPROC11_OP_CFG
#define PMIC_RG_BUCK_VPROC11_HW2_OP_CFG_MASK  0x1
#define PMIC_RG_BUCK_VPROC11_HW2_OP_CFG_SHIFT 3
#define PMIC_RG_BUCK_VPROC11_ON_OP_ADDR MT6358_BUCK_VPROC11_OP_CFG
#define PMIC_RG_BUCK_VPROC11_ON_OP_MASK 0x1
#define PMIC_RG_BUCK_VPROC11_ON_OP_SHIFT   8
#define PMIC_RG_BUCK_VPROC11_LP_OP_ADDR MT6358_BUCK_VPROC11_OP_CFG
#define PMIC_RG_BUCK_VPROC11_LP_OP_MASK 0x1
#define PMIC_RG_BUCK_VPROC11_LP_OP_SHIFT   9
#define PMIC_RG_BUCK_VPROC11_OP_CFG_SET_ADDR  MT6358_BUCK_VPROC11_OP_CFG_SET
#define PMIC_RG_BUCK_VPROC11_OP_CFG_SET_MASK  0xFFFF
#define PMIC_RG_BUCK_VPROC11_OP_CFG_SET_SHIFT 0
#define PMIC_RG_BUCK_VPROC11_OP_CFG_CLR_ADDR  MT6358_BUCK_VPROC11_OP_CFG_CLR
#define PMIC_RG_BUCK_VPROC11_OP_CFG_CLR_MASK  0xFFFF
#define PMIC_RG_BUCK_VPROC11_OP_CFG_CLR_SHIFT 0
#define PMIC_RG_BUCK_VPROC11_OC_DEG_EN_ADDR MT6358_BUCK_VPROC11_OC_CFG
#define PMIC_RG_BUCK_VPROC11_OC_DEG_EN_MASK 0x1
#define PMIC_RG_BUCK_VPROC11_OC_DEG_EN_SHIFT  1
#define PMIC_RG_BUCK_VPROC11_OC_WND_ADDR   MT6358_BUCK_VPROC11_OC_CFG
#define PMIC_RG_BUCK_VPROC11_OC_WND_MASK   0x3
#define PMIC_RG_BUCK_VPROC11_OC_WND_SHIFT   2
#define PMIC_RG_BUCK_VPROC11_OC_THD_ADDR   MT6358_BUCK_VPROC11_OC_CFG
#define PMIC_RG_BUCK_VPROC11_OC_THD_MASK   0x3
#define PMIC_RG_BUCK_VPROC11_OC_THD_SHIFT   6
#define PMIC_DA_VPROC11_VOSEL_ADDR MT6358_BUCK_VPROC11_DBG0
#define PMIC_DA_VPROC11_VOSEL_MASK 0x7F
#define PMIC_DA_VPROC11_VOSEL_SHIFT   0
#define PMIC_DA_VPROC11_VOSEL_GRAY_ADDR MT6358_BUCK_VPROC11_DBG0
#define PMIC_DA_VPROC11_VOSEL_GRAY_MASK 0x7F
#define PMIC_DA_VPROC11_VOSEL_GRAY_SHIFT   8
#define PMIC_DA_VPROC11_EN_ADDR MT6358_BUCK_VPROC11_DBG1
#define PMIC_DA_VPROC11_EN_MASK 0x1
#define PMIC_DA_VPROC11_EN_SHIFT  0
#define PMIC_DA_VPROC11_STB_ADDR  MT6358_BUCK_VPROC11_DBG1
#define PMIC_DA_VPROC11_STB_MASK  0x1
#define PMIC_DA_VPROC11_STB_SHIFT 1
#define PMIC_DA_VPROC11_LOOP_SEL_ADDR MT6358_BUCK_VPROC11_DBG1
#define PMIC_DA_VPROC11_LOOP_SEL_MASK 0x1
#define PMIC_DA_VPROC11_LOOP_SEL_SHIFT  2
#define PMIC_DA_VPROC11_R2R_PDN_ADDR  MT6358_BUCK_VPROC11_DBG1
#define PMIC_DA_VPROC11_R2R_PDN_MASK  0x1
#define PMIC_DA_VPROC11_R2R_PDN_SHIFT 3
#define PMIC_DA_VPROC11_DVS_EN_ADDR   MT6358_BUCK_VPROC11_DBG1
#define PMIC_DA_VPROC11_DVS_EN_MASK   0x1
#define PMIC_DA_VPROC11_DVS_EN_SHIFT  4
#define PMIC_DA_VPROC11_DVS_DOWN_ADDR MT6358_BUCK_VPROC11_DBG1
#define PMIC_DA_VPROC11_DVS_DOWN_MASK 0x1
#define PMIC_DA_VPROC11_DVS_DOWN_SHIFT  5
#define PMIC_DA_VPROC11_SSH_ADDR  MT6358_BUCK_VPROC11_DBG1
#define PMIC_DA_VPROC11_SSH_MASK  0x1
#define PMIC_DA_VPROC11_SSH_SHIFT 6
#define PMIC_DA_VPROC11_MINFREQ_DISCHARGE_ADDR   MT6358_BUCK_VPROC11_DBG1
#define PMIC_DA_VPROC11_MINFREQ_DISCHARGE_MASK   0x1
#define PMIC_DA_VPROC11_MINFREQ_DISCHARGE_SHIFT  8
#define PMIC_RG_BUCK_VPROC11_OC_FLAG_CLR_SEL_ADDR MT6358_BUCK_VPROC11_DBG2
#define PMIC_RG_BUCK_VPROC11_OC_FLAG_CLR_SEL_MASK 0x1
#define PMIC_RG_BUCK_VPROC11_OC_FLAG_CLR_SEL_SHIFT  4
#define PMIC_RG_BUCK_VPROC11_OSC_SEL_DIS_ADDR MT6358_BUCK_VPROC11_DBG2
#define PMIC_RG_BUCK_VPROC11_OSC_SEL_DIS_MASK 0x1
#define PMIC_RG_BUCK_VPROC11_OSC_SEL_DIS_SHIFT   5
#define PMIC_RG_BUCK_VPROC11_CK_SW_MODE_ADDR  MT6358_BUCK_VPROC11_DBG2
#define PMIC_RG_BUCK_VPROC11_CK_SW_MODE_MASK  0x1
#define PMIC_RG_BUCK_VPROC11_CK_SW_MODE_SHIFT 6
#define PMIC_RG_BUCK_VPROC11_CK_SW_EN_ADDR  MT6358_BUCK_VPROC11_DBG2
#define PMIC_RG_BUCK_VPROC11_CK_SW_EN_MASK  0x1
#define PMIC_RG_BUCK_VPROC11_CK_SW_EN_SHIFT 7
#define PMIC_BUCK_VPROC11_ELR_LEN_ADDR  MT6358_BUCK_VPROC11_ELR_NUM
#define PMIC_BUCK_VPROC11_ELR_LEN_MASK  0xFF
#define PMIC_BUCK_VPROC11_ELR_LEN_SHIFT 0
#define PMIC_RG_BUCK_VPROC11_VOSEL_ADDR MT6358_BUCK_VPROC11_ELR0
#define PMIC_RG_BUCK_VPROC11_VOSEL_MASK 0x7F
#define PMIC_RG_BUCK_VPROC11_VOSEL_SHIFT   0
#define PMIC_BUCK_VPROC12_ANA_ID_ADDR MT6358_BUCK_VPROC12_DSN_ID
#define PMIC_BUCK_VPROC12_ANA_ID_MASK 0xFF
#define PMIC_BUCK_VPROC12_ANA_ID_SHIFT  0
#define PMIC_BUCK_VPROC12_DIG_ID_ADDR MT6358_BUCK_VPROC12_DSN_ID
#define PMIC_BUCK_VPROC12_DIG_ID_MASK 0xFF
#define PMIC_BUCK_VPROC12_DIG_ID_SHIFT  8
#define PMIC_BUCK_VPROC12_ANA_MINOR_REV_ADDR  MT6358_BUCK_VPROC12_DSN_REV0
#define PMIC_BUCK_VPROC12_ANA_MINOR_REV_MASK  0xF
#define PMIC_BUCK_VPROC12_ANA_MINOR_REV_SHIFT 0
#define PMIC_BUCK_VPROC12_ANA_MAJOR_REV_ADDR  MT6358_BUCK_VPROC12_DSN_REV0
#define PMIC_BUCK_VPROC12_ANA_MAJOR_REV_MASK  0xF
#define PMIC_BUCK_VPROC12_ANA_MAJOR_REV_SHIFT 4
#define PMIC_BUCK_VPROC12_DIG_MINOR_REV_ADDR  MT6358_BUCK_VPROC12_DSN_REV0
#define PMIC_BUCK_VPROC12_DIG_MINOR_REV_MASK  0xF
#define PMIC_BUCK_VPROC12_DIG_MINOR_REV_SHIFT 8
#define PMIC_BUCK_VPROC12_DIG_MAJOR_REV_ADDR  MT6358_BUCK_VPROC12_DSN_REV0
#define PMIC_BUCK_VPROC12_DIG_MAJOR_REV_MASK  0xF
#define PMIC_BUCK_VPROC12_DIG_MAJOR_REV_SHIFT 12
#define PMIC_BUCK_VPROC12_DSN_CBS_ADDR  MT6358_BUCK_VPROC12_DSN_DBI
#define PMIC_BUCK_VPROC12_DSN_CBS_MASK  0x3
#define PMIC_BUCK_VPROC12_DSN_CBS_SHIFT 0
#define PMIC_BUCK_VPROC12_DSN_BIX_ADDR  MT6358_BUCK_VPROC12_DSN_DBI
#define PMIC_BUCK_VPROC12_DSN_BIX_MASK  0x3
#define PMIC_BUCK_VPROC12_DSN_BIX_SHIFT 2
#define PMIC_BUCK_VPROC12_DSN_ESP_ADDR  MT6358_BUCK_VPROC12_DSN_DBI
#define PMIC_BUCK_VPROC12_DSN_ESP_MASK  0xFF
#define PMIC_BUCK_VPROC12_DSN_ESP_SHIFT 8
#define PMIC_BUCK_VPROC12_DSN_FPI_SSHUB_ADDR  MT6358_BUCK_VPROC12_DSN_DXI
#define PMIC_BUCK_VPROC12_DSN_FPI_SSHUB_MASK  0x1
#define PMIC_BUCK_VPROC12_DSN_FPI_SSHUB_SHIFT 0
#define PMIC_BUCK_VPROC12_DSN_FPI_TRACKING_ADDR  MT6358_BUCK_VPROC12_DSN_DXI
#define PMIC_BUCK_VPROC12_DSN_FPI_TRACKING_MASK  0x1
#define PMIC_BUCK_VPROC12_DSN_FPI_TRACKING_SHIFT  1
#define PMIC_BUCK_VPROC12_DSN_FPI_PREOC_ADDR  MT6358_BUCK_VPROC12_DSN_DXI
#define PMIC_BUCK_VPROC12_DSN_FPI_PREOC_MASK  0x1
#define PMIC_BUCK_VPROC12_DSN_FPI_PREOC_SHIFT 2
#define PMIC_BUCK_VPROC12_DSN_FPI_VOTER_ADDR  MT6358_BUCK_VPROC12_DSN_DXI
#define PMIC_BUCK_VPROC12_DSN_FPI_VOTER_MASK  0x1
#define PMIC_BUCK_VPROC12_DSN_FPI_VOTER_SHIFT 3
#define PMIC_BUCK_VPROC12_DSN_FPI_ULTRASONIC_ADDR MT6358_BUCK_VPROC12_DSN_DXI
#define PMIC_BUCK_VPROC12_DSN_FPI_ULTRASONIC_MASK 0x1
#define PMIC_BUCK_VPROC12_DSN_FPI_ULTRASONIC_SHIFT  4
#define PMIC_BUCK_VPROC12_DSN_FPI_DLC_ADDR  MT6358_BUCK_VPROC12_DSN_DXI
#define PMIC_BUCK_VPROC12_DSN_FPI_DLC_MASK  0x1
#define PMIC_BUCK_VPROC12_DSN_FPI_DLC_SHIFT 5
#define PMIC_BUCK_VPROC12_DSN_FPI_TRAP_ADDR MT6358_BUCK_VPROC12_DSN_DXI
#define PMIC_BUCK_VPROC12_DSN_FPI_TRAP_MASK 0x1
#define PMIC_BUCK_VPROC12_DSN_FPI_TRAP_SHIFT  6
#define PMIC_RG_BUCK_VPROC12_EN_ADDR  MT6358_BUCK_VPROC12_CON0
#define PMIC_RG_BUCK_VPROC12_EN_MASK  0x1
#define PMIC_RG_BUCK_VPROC12_EN_SHIFT 0
#define PMIC_RG_BUCK_VPROC12_LP_ADDR  MT6358_BUCK_VPROC12_CON0
#define PMIC_RG_BUCK_VPROC12_LP_MASK  0x1
#define PMIC_RG_BUCK_VPROC12_LP_SHIFT 1
#define PMIC_RG_BUCK_VPROC12_VOSEL_SLEEP_ADDR MT6358_BUCK_VPROC12_CON1
#define PMIC_RG_BUCK_VPROC12_VOSEL_SLEEP_MASK 0x7F
#define PMIC_RG_BUCK_VPROC12_VOSEL_SLEEP_SHIFT   0
#define PMIC_RG_BUCK_VPROC12_SFCHG_FRATE_ADDR MT6358_BUCK_VPROC12_CFG0
#define PMIC_RG_BUCK_VPROC12_SFCHG_FRATE_MASK 0x7F
#define PMIC_RG_BUCK_VPROC12_SFCHG_FRATE_SHIFT   0
#define PMIC_RG_BUCK_VPROC12_SFCHG_FEN_ADDR MT6358_BUCK_VPROC12_CFG0
#define PMIC_RG_BUCK_VPROC12_SFCHG_FEN_MASK 0x1
#define PMIC_RG_BUCK_VPROC12_SFCHG_FEN_SHIFT  7
#define PMIC_RG_BUCK_VPROC12_SFCHG_RRATE_ADDR MT6358_BUCK_VPROC12_CFG0
#define PMIC_RG_BUCK_VPROC12_SFCHG_RRATE_MASK 0x7F
#define PMIC_RG_BUCK_VPROC12_SFCHG_RRATE_SHIFT   8
#define PMIC_RG_BUCK_VPROC12_SFCHG_REN_ADDR MT6358_BUCK_VPROC12_CFG0
#define PMIC_RG_BUCK_VPROC12_SFCHG_REN_MASK 0x1
#define PMIC_RG_BUCK_VPROC12_SFCHG_REN_SHIFT  15
#define PMIC_RG_BUCK_VPROC12_DVS_EN_TD_ADDR MT6358_BUCK_VPROC12_CFG1
#define PMIC_RG_BUCK_VPROC12_DVS_EN_TD_MASK 0x3
#define PMIC_RG_BUCK_VPROC12_DVS_EN_TD_SHIFT  0
#define PMIC_RG_BUCK_VPROC12_DVS_EN_CTRL_ADDR MT6358_BUCK_VPROC12_CFG1
#define PMIC_RG_BUCK_VPROC12_DVS_EN_CTRL_MASK 0x3
#define PMIC_RG_BUCK_VPROC12_DVS_EN_CTRL_SHIFT   4
#define PMIC_RG_BUCK_VPROC12_DVS_EN_ONCE_ADDR MT6358_BUCK_VPROC12_CFG1
#define PMIC_RG_BUCK_VPROC12_DVS_EN_ONCE_MASK 0x1
#define PMIC_RG_BUCK_VPROC12_DVS_EN_ONCE_SHIFT   6
#define PMIC_RG_BUCK_VPROC12_DVS_DOWN_TD_ADDR MT6358_BUCK_VPROC12_CFG1
#define PMIC_RG_BUCK_VPROC12_DVS_DOWN_TD_MASK 0x3
#define PMIC_RG_BUCK_VPROC12_DVS_DOWN_TD_SHIFT   8
#define PMIC_RG_BUCK_VPROC12_DVS_DOWN_CTRL_ADDR  MT6358_BUCK_VPROC12_CFG1
#define PMIC_RG_BUCK_VPROC12_DVS_DOWN_CTRL_MASK  0x3
#define PMIC_RG_BUCK_VPROC12_DVS_DOWN_CTRL_SHIFT  12
#define PMIC_RG_BUCK_VPROC12_DVS_DOWN_ONCE_ADDR  MT6358_BUCK_VPROC12_CFG1
#define PMIC_RG_BUCK_VPROC12_DVS_DOWN_ONCE_MASK  0x1
#define PMIC_RG_BUCK_VPROC12_DVS_DOWN_ONCE_SHIFT  14
#define PMIC_RG_BUCK_VPROC12_SW_OP_EN_ADDR  MT6358_BUCK_VPROC12_OP_EN
#define PMIC_RG_BUCK_VPROC12_SW_OP_EN_MASK  0x1
#define PMIC_RG_BUCK_VPROC12_SW_OP_EN_SHIFT 0
#define PMIC_RG_BUCK_VPROC12_HW0_OP_EN_ADDR MT6358_BUCK_VPROC12_OP_EN
#define PMIC_RG_BUCK_VPROC12_HW0_OP_EN_MASK 0x1
#define PMIC_RG_BUCK_VPROC12_HW0_OP_EN_SHIFT  1
#define PMIC_RG_BUCK_VPROC12_HW1_OP_EN_ADDR MT6358_BUCK_VPROC12_OP_EN
#define PMIC_RG_BUCK_VPROC12_HW1_OP_EN_MASK 0x1
#define PMIC_RG_BUCK_VPROC12_HW1_OP_EN_SHIFT  2
#define PMIC_RG_BUCK_VPROC12_HW2_OP_EN_ADDR MT6358_BUCK_VPROC12_OP_EN
#define PMIC_RG_BUCK_VPROC12_HW2_OP_EN_MASK 0x1
#define PMIC_RG_BUCK_VPROC12_HW2_OP_EN_SHIFT  3
#define PMIC_RG_BUCK_VPROC12_OP_EN_SET_ADDR MT6358_BUCK_VPROC12_OP_EN_SET
#define PMIC_RG_BUCK_VPROC12_OP_EN_SET_MASK 0xFFFF
#define PMIC_RG_BUCK_VPROC12_OP_EN_SET_SHIFT  0
#define PMIC_RG_BUCK_VPROC12_OP_EN_CLR_ADDR MT6358_BUCK_VPROC12_OP_EN_CLR
#define PMIC_RG_BUCK_VPROC12_OP_EN_CLR_MASK 0xFFFF
#define PMIC_RG_BUCK_VPROC12_OP_EN_CLR_SHIFT  0
#define PMIC_RG_BUCK_VPROC12_HW0_OP_CFG_ADDR  MT6358_BUCK_VPROC12_OP_CFG
#define PMIC_RG_BUCK_VPROC12_HW0_OP_CFG_MASK  0x1
#define PMIC_RG_BUCK_VPROC12_HW0_OP_CFG_SHIFT 1
#define PMIC_RG_BUCK_VPROC12_HW1_OP_CFG_ADDR  MT6358_BUCK_VPROC12_OP_CFG
#define PMIC_RG_BUCK_VPROC12_HW1_OP_CFG_MASK  0x1
#define PMIC_RG_BUCK_VPROC12_HW1_OP_CFG_SHIFT 2
#define PMIC_RG_BUCK_VPROC12_HW2_OP_CFG_ADDR  MT6358_BUCK_VPROC12_OP_CFG
#define PMIC_RG_BUCK_VPROC12_HW2_OP_CFG_MASK  0x1
#define PMIC_RG_BUCK_VPROC12_HW2_OP_CFG_SHIFT 3
#define PMIC_RG_BUCK_VPROC12_ON_OP_ADDR MT6358_BUCK_VPROC12_OP_CFG
#define PMIC_RG_BUCK_VPROC12_ON_OP_MASK 0x1
#define PMIC_RG_BUCK_VPROC12_ON_OP_SHIFT   8
#define PMIC_RG_BUCK_VPROC12_LP_OP_ADDR MT6358_BUCK_VPROC12_OP_CFG
#define PMIC_RG_BUCK_VPROC12_LP_OP_MASK 0x1
#define PMIC_RG_BUCK_VPROC12_LP_OP_SHIFT   9
#define PMIC_RG_BUCK_VPROC12_OP_CFG_SET_ADDR  MT6358_BUCK_VPROC12_OP_CFG_SET
#define PMIC_RG_BUCK_VPROC12_OP_CFG_SET_MASK  0xFFFF
#define PMIC_RG_BUCK_VPROC12_OP_CFG_SET_SHIFT 0
#define PMIC_RG_BUCK_VPROC12_OP_CFG_CLR_ADDR  MT6358_BUCK_VPROC12_OP_CFG_CLR
#define PMIC_RG_BUCK_VPROC12_OP_CFG_CLR_MASK  0xFFFF
#define PMIC_RG_BUCK_VPROC12_OP_CFG_CLR_SHIFT 0
#define PMIC_RG_BUCK_VPROC12_OC_DEG_EN_ADDR MT6358_BUCK_VPROC12_OC_CFG
#define PMIC_RG_BUCK_VPROC12_OC_DEG_EN_MASK 0x1
#define PMIC_RG_BUCK_VPROC12_OC_DEG_EN_SHIFT  1
#define PMIC_RG_BUCK_VPROC12_OC_WND_ADDR   MT6358_BUCK_VPROC12_OC_CFG
#define PMIC_RG_BUCK_VPROC12_OC_WND_MASK   0x3
#define PMIC_RG_BUCK_VPROC12_OC_WND_SHIFT   2
#define PMIC_RG_BUCK_VPROC12_OC_THD_ADDR   MT6358_BUCK_VPROC12_OC_CFG
#define PMIC_RG_BUCK_VPROC12_OC_THD_MASK   0x3
#define PMIC_RG_BUCK_VPROC12_OC_THD_SHIFT   6
#define PMIC_DA_VPROC12_VOSEL_ADDR MT6358_BUCK_VPROC12_DBG0
#define PMIC_DA_VPROC12_VOSEL_MASK 0x7F
#define PMIC_DA_VPROC12_VOSEL_SHIFT   0
#define PMIC_DA_VPROC12_VOSEL_GRAY_ADDR MT6358_BUCK_VPROC12_DBG0
#define PMIC_DA_VPROC12_VOSEL_GRAY_MASK 0x7F
#define PMIC_DA_VPROC12_VOSEL_GRAY_SHIFT   8
#define PMIC_DA_VPROC12_EN_ADDR MT6358_BUCK_VPROC12_DBG1
#define PMIC_DA_VPROC12_EN_MASK 0x1
#define PMIC_DA_VPROC12_EN_SHIFT  0
#define PMIC_DA_VPROC12_STB_ADDR  MT6358_BUCK_VPROC12_DBG1
#define PMIC_DA_VPROC12_STB_MASK  0x1
#define PMIC_DA_VPROC12_STB_SHIFT 1
#define PMIC_DA_VPROC12_LOOP_SEL_ADDR MT6358_BUCK_VPROC12_DBG1
#define PMIC_DA_VPROC12_LOOP_SEL_MASK 0x1
#define PMIC_DA_VPROC12_LOOP_SEL_SHIFT  2
#define PMIC_DA_VPROC12_R2R_PDN_ADDR  MT6358_BUCK_VPROC12_DBG1
#define PMIC_DA_VPROC12_R2R_PDN_MASK  0x1
#define PMIC_DA_VPROC12_R2R_PDN_SHIFT 3
#define PMIC_DA_VPROC12_DVS_EN_ADDR   MT6358_BUCK_VPROC12_DBG1
#define PMIC_DA_VPROC12_DVS_EN_MASK   0x1
#define PMIC_DA_VPROC12_DVS_EN_SHIFT  4
#define PMIC_DA_VPROC12_DVS_DOWN_ADDR MT6358_BUCK_VPROC12_DBG1
#define PMIC_DA_VPROC12_DVS_DOWN_MASK 0x1
#define PMIC_DA_VPROC12_DVS_DOWN_SHIFT  5
#define PMIC_DA_VPROC12_SSH_ADDR  MT6358_BUCK_VPROC12_DBG1
#define PMIC_DA_VPROC12_SSH_MASK  0x1
#define PMIC_DA_VPROC12_SSH_SHIFT 6
#define PMIC_DA_VPROC12_MINFREQ_DISCHARGE_ADDR   MT6358_BUCK_VPROC12_DBG1
#define PMIC_DA_VPROC12_MINFREQ_DISCHARGE_MASK   0x1
#define PMIC_DA_VPROC12_MINFREQ_DISCHARGE_SHIFT  8
#define PMIC_RG_BUCK_VPROC12_OC_FLAG_CLR_SEL_ADDR MT6358_BUCK_VPROC12_DBG2
#define PMIC_RG_BUCK_VPROC12_OC_FLAG_CLR_SEL_MASK 0x1
#define PMIC_RG_BUCK_VPROC12_OC_FLAG_CLR_SEL_SHIFT  4
#define PMIC_RG_BUCK_VPROC12_OSC_SEL_DIS_ADDR MT6358_BUCK_VPROC12_DBG2
#define PMIC_RG_BUCK_VPROC12_OSC_SEL_DIS_MASK 0x1
#define PMIC_RG_BUCK_VPROC12_OSC_SEL_DIS_SHIFT   5
#define PMIC_RG_BUCK_VPROC12_CK_SW_MODE_ADDR  MT6358_BUCK_VPROC12_DBG2
#define PMIC_RG_BUCK_VPROC12_CK_SW_MODE_MASK  0x1
#define PMIC_RG_BUCK_VPROC12_CK_SW_MODE_SHIFT 6
#define PMIC_RG_BUCK_VPROC12_CK_SW_EN_ADDR  MT6358_BUCK_VPROC12_DBG2
#define PMIC_RG_BUCK_VPROC12_CK_SW_EN_MASK  0x1
#define PMIC_RG_BUCK_VPROC12_CK_SW_EN_SHIFT 7
#define PMIC_BUCK_VPROC12_ELR_LEN_ADDR  MT6358_BUCK_VPROC12_ELR_NUM
#define PMIC_BUCK_VPROC12_ELR_LEN_MASK  0xFF
#define PMIC_BUCK_VPROC12_ELR_LEN_SHIFT 0
#define PMIC_RG_BUCK_VPROC12_VOSEL_ADDR MT6358_BUCK_VPROC12_ELR0
#define PMIC_RG_BUCK_VPROC12_VOSEL_MASK 0x7F
#define PMIC_RG_BUCK_VPROC12_VOSEL_SHIFT   0
#define PMIC_BUCK_VCORE_ANA_ID_ADDR   MT6358_BUCK_VCORE_DSN_ID
#define PMIC_BUCK_VCORE_ANA_ID_MASK   0xFF
#define PMIC_BUCK_VCORE_ANA_ID_SHIFT  0
#define PMIC_BUCK_VCORE_DIG_ID_ADDR   MT6358_BUCK_VCORE_DSN_ID
#define PMIC_BUCK_VCORE_DIG_ID_MASK   0xFF
#define PMIC_BUCK_VCORE_DIG_ID_SHIFT  8
#define PMIC_BUCK_VCORE_ANA_MINOR_REV_ADDR  MT6358_BUCK_VCORE_DSN_REV0
#define PMIC_BUCK_VCORE_ANA_MINOR_REV_MASK  0xF
#define PMIC_BUCK_VCORE_ANA_MINOR_REV_SHIFT 0
#define PMIC_BUCK_VCORE_ANA_MAJOR_REV_ADDR  MT6358_BUCK_VCORE_DSN_REV0
#define PMIC_BUCK_VCORE_ANA_MAJOR_REV_MASK  0xF
#define PMIC_BUCK_VCORE_ANA_MAJOR_REV_SHIFT 4
#define PMIC_BUCK_VCORE_DIG_MINOR_REV_ADDR  MT6358_BUCK_VCORE_DSN_REV0
#define PMIC_BUCK_VCORE_DIG_MINOR_REV_MASK  0xF
#define PMIC_BUCK_VCORE_DIG_MINOR_REV_SHIFT 8
#define PMIC_BUCK_VCORE_DIG_MAJOR_REV_ADDR  MT6358_BUCK_VCORE_DSN_REV0
#define PMIC_BUCK_VCORE_DIG_MAJOR_REV_MASK  0xF
#define PMIC_BUCK_VCORE_DIG_MAJOR_REV_SHIFT 12
#define PMIC_BUCK_VCORE_DSN_CBS_ADDR  MT6358_BUCK_VCORE_DSN_DBI
#define PMIC_BUCK_VCORE_DSN_CBS_MASK  0x3
#define PMIC_BUCK_VCORE_DSN_CBS_SHIFT 0
#define PMIC_BUCK_VCORE_DSN_BIX_ADDR  MT6358_BUCK_VCORE_DSN_DBI
#define PMIC_BUCK_VCORE_DSN_BIX_MASK  0x3
#define PMIC_BUCK_VCORE_DSN_BIX_SHIFT 2
#define PMIC_BUCK_VCORE_DSN_ESP_ADDR  MT6358_BUCK_VCORE_DSN_DBI
#define PMIC_BUCK_VCORE_DSN_ESP_MASK  0xFF
#define PMIC_BUCK_VCORE_DSN_ESP_SHIFT 8
#define PMIC_BUCK_VCORE_DSN_FPI_SSHUB_ADDR  MT6358_BUCK_VCORE_DSN_DXI
#define PMIC_BUCK_VCORE_DSN_FPI_SSHUB_MASK  0x1
#define PMIC_BUCK_VCORE_DSN_FPI_SSHUB_SHIFT 0
#define PMIC_BUCK_VCORE_DSN_FPI_TRACKING_ADDR MT6358_BUCK_VCORE_DSN_DXI
#define PMIC_BUCK_VCORE_DSN_FPI_TRACKING_MASK 0x1
#define PMIC_BUCK_VCORE_DSN_FPI_TRACKING_SHIFT   1
#define PMIC_BUCK_VCORE_DSN_FPI_PREOC_ADDR  MT6358_BUCK_VCORE_DSN_DXI
#define PMIC_BUCK_VCORE_DSN_FPI_PREOC_MASK  0x1
#define PMIC_BUCK_VCORE_DSN_FPI_PREOC_SHIFT 2
#define PMIC_BUCK_VCORE_DSN_FPI_VOTER_ADDR  MT6358_BUCK_VCORE_DSN_DXI
#define PMIC_BUCK_VCORE_DSN_FPI_VOTER_MASK  0x1
#define PMIC_BUCK_VCORE_DSN_FPI_VOTER_SHIFT 3
#define PMIC_BUCK_VCORE_DSN_FPI_ULTRASONIC_ADDR  MT6358_BUCK_VCORE_DSN_DXI
#define PMIC_BUCK_VCORE_DSN_FPI_ULTRASONIC_MASK  0x1
#define PMIC_BUCK_VCORE_DSN_FPI_ULTRASONIC_SHIFT  4
#define PMIC_BUCK_VCORE_DSN_FPI_DLC_ADDR   MT6358_BUCK_VCORE_DSN_DXI
#define PMIC_BUCK_VCORE_DSN_FPI_DLC_MASK   0x1
#define PMIC_BUCK_VCORE_DSN_FPI_DLC_SHIFT   5
#define PMIC_BUCK_VCORE_DSN_FPI_TRAP_ADDR   MT6358_BUCK_VCORE_DSN_DXI
#define PMIC_BUCK_VCORE_DSN_FPI_TRAP_MASK   0x1
#define PMIC_BUCK_VCORE_DSN_FPI_TRAP_SHIFT  6
#define PMIC_RG_BUCK_VCORE_EN_ADDR MT6358_BUCK_VCORE_CON0
#define PMIC_RG_BUCK_VCORE_EN_MASK 0x1
#define PMIC_RG_BUCK_VCORE_EN_SHIFT   0
#define PMIC_RG_BUCK_VCORE_LP_ADDR MT6358_BUCK_VCORE_CON0
#define PMIC_RG_BUCK_VCORE_LP_MASK 0x1
#define PMIC_RG_BUCK_VCORE_LP_SHIFT   1
#define PMIC_RG_BUCK_VCORE_VOSEL_SLEEP_ADDR MT6358_BUCK_VCORE_CON1
#define PMIC_RG_BUCK_VCORE_VOSEL_SLEEP_MASK 0x7F
#define PMIC_RG_BUCK_VCORE_VOSEL_SLEEP_SHIFT  0
#define PMIC_RG_BUCK_VCORE_SFCHG_FRATE_ADDR MT6358_BUCK_VCORE_CFG0
#define PMIC_RG_BUCK_VCORE_SFCHG_FRATE_MASK 0x7F
#define PMIC_RG_BUCK_VCORE_SFCHG_FRATE_SHIFT  0
#define PMIC_RG_BUCK_VCORE_SFCHG_FEN_ADDR   MT6358_BUCK_VCORE_CFG0
#define PMIC_RG_BUCK_VCORE_SFCHG_FEN_MASK   0x1
#define PMIC_RG_BUCK_VCORE_SFCHG_FEN_SHIFT  7
#define PMIC_RG_BUCK_VCORE_SFCHG_RRATE_ADDR MT6358_BUCK_VCORE_CFG0
#define PMIC_RG_BUCK_VCORE_SFCHG_RRATE_MASK 0x7F
#define PMIC_RG_BUCK_VCORE_SFCHG_RRATE_SHIFT  8
#define PMIC_RG_BUCK_VCORE_SFCHG_REN_ADDR   MT6358_BUCK_VCORE_CFG0
#define PMIC_RG_BUCK_VCORE_SFCHG_REN_MASK   0x1
#define PMIC_RG_BUCK_VCORE_SFCHG_REN_SHIFT  15
#define PMIC_RG_BUCK_VCORE_DVS_EN_TD_ADDR   MT6358_BUCK_VCORE_CFG1
#define PMIC_RG_BUCK_VCORE_DVS_EN_TD_MASK   0x3
#define PMIC_RG_BUCK_VCORE_DVS_EN_TD_SHIFT  0
#define PMIC_RG_BUCK_VCORE_DVS_EN_CTRL_ADDR MT6358_BUCK_VCORE_CFG1
#define PMIC_RG_BUCK_VCORE_DVS_EN_CTRL_MASK 0x3
#define PMIC_RG_BUCK_VCORE_DVS_EN_CTRL_SHIFT  4
#define PMIC_RG_BUCK_VCORE_DVS_EN_ONCE_ADDR MT6358_BUCK_VCORE_CFG1
#define PMIC_RG_BUCK_VCORE_DVS_EN_ONCE_MASK 0x1
#define PMIC_RG_BUCK_VCORE_DVS_EN_ONCE_SHIFT  6
#define PMIC_RG_BUCK_VCORE_DVS_DOWN_TD_ADDR MT6358_BUCK_VCORE_CFG1
#define PMIC_RG_BUCK_VCORE_DVS_DOWN_TD_MASK 0x3
#define PMIC_RG_BUCK_VCORE_DVS_DOWN_TD_SHIFT  8
#define PMIC_RG_BUCK_VCORE_DVS_DOWN_CTRL_ADDR MT6358_BUCK_VCORE_CFG1
#define PMIC_RG_BUCK_VCORE_DVS_DOWN_CTRL_MASK 0x3
#define PMIC_RG_BUCK_VCORE_DVS_DOWN_CTRL_SHIFT   12
#define PMIC_RG_BUCK_VCORE_DVS_DOWN_ONCE_ADDR MT6358_BUCK_VCORE_CFG1
#define PMIC_RG_BUCK_VCORE_DVS_DOWN_ONCE_MASK 0x1
#define PMIC_RG_BUCK_VCORE_DVS_DOWN_ONCE_SHIFT   14
#define PMIC_RG_BUCK_VCORE_SW_OP_EN_ADDR   MT6358_BUCK_VCORE_OP_EN
#define PMIC_RG_BUCK_VCORE_SW_OP_EN_MASK   0x1
#define PMIC_RG_BUCK_VCORE_SW_OP_EN_SHIFT   0
#define PMIC_RG_BUCK_VCORE_HW0_OP_EN_ADDR   MT6358_BUCK_VCORE_OP_EN
#define PMIC_RG_BUCK_VCORE_HW0_OP_EN_MASK   0x1
#define PMIC_RG_BUCK_VCORE_HW0_OP_EN_SHIFT  1
#define PMIC_RG_BUCK_VCORE_HW1_OP_EN_ADDR   MT6358_BUCK_VCORE_OP_EN
#define PMIC_RG_BUCK_VCORE_HW1_OP_EN_MASK   0x1
#define PMIC_RG_BUCK_VCORE_HW1_OP_EN_SHIFT  2
#define PMIC_RG_BUCK_VCORE_HW2_OP_EN_ADDR   MT6358_BUCK_VCORE_OP_EN
#define PMIC_RG_BUCK_VCORE_HW2_OP_EN_MASK   0x1
#define PMIC_RG_BUCK_VCORE_HW2_OP_EN_SHIFT  3
#define PMIC_RG_BUCK_VCORE_OP_EN_SET_ADDR   MT6358_BUCK_VCORE_OP_EN_SET
#define PMIC_RG_BUCK_VCORE_OP_EN_SET_MASK   0xFFFF
#define PMIC_RG_BUCK_VCORE_OP_EN_SET_SHIFT  0
#define PMIC_RG_BUCK_VCORE_OP_EN_CLR_ADDR   MT6358_BUCK_VCORE_OP_EN_CLR
#define PMIC_RG_BUCK_VCORE_OP_EN_CLR_MASK   0xFFFF
#define PMIC_RG_BUCK_VCORE_OP_EN_CLR_SHIFT  0
#define PMIC_RG_BUCK_VCORE_HW0_OP_CFG_ADDR  MT6358_BUCK_VCORE_OP_CFG
#define PMIC_RG_BUCK_VCORE_HW0_OP_CFG_MASK  0x1
#define PMIC_RG_BUCK_VCORE_HW0_OP_CFG_SHIFT 1
#define PMIC_RG_BUCK_VCORE_HW1_OP_CFG_ADDR  MT6358_BUCK_VCORE_OP_CFG
#define PMIC_RG_BUCK_VCORE_HW1_OP_CFG_MASK  0x1
#define PMIC_RG_BUCK_VCORE_HW1_OP_CFG_SHIFT 2
#define PMIC_RG_BUCK_VCORE_HW2_OP_CFG_ADDR  MT6358_BUCK_VCORE_OP_CFG
#define PMIC_RG_BUCK_VCORE_HW2_OP_CFG_MASK  0x1
#define PMIC_RG_BUCK_VCORE_HW2_OP_CFG_SHIFT 3
#define PMIC_RG_BUCK_VCORE_ON_OP_ADDR MT6358_BUCK_VCORE_OP_CFG
#define PMIC_RG_BUCK_VCORE_ON_OP_MASK 0x1
#define PMIC_RG_BUCK_VCORE_ON_OP_SHIFT  8
#define PMIC_RG_BUCK_VCORE_LP_OP_ADDR MT6358_BUCK_VCORE_OP_CFG
#define PMIC_RG_BUCK_VCORE_LP_OP_MASK 0x1
#define PMIC_RG_BUCK_VCORE_LP_OP_SHIFT  9
#define PMIC_RG_BUCK_VCORE_OP_CFG_SET_ADDR  MT6358_BUCK_VCORE_OP_CFG_SET
#define PMIC_RG_BUCK_VCORE_OP_CFG_SET_MASK  0xFFFF
#define PMIC_RG_BUCK_VCORE_OP_CFG_SET_SHIFT 0
#define PMIC_RG_BUCK_VCORE_OP_CFG_CLR_ADDR  MT6358_BUCK_VCORE_OP_CFG_CLR
#define PMIC_RG_BUCK_VCORE_OP_CFG_CLR_MASK  0xFFFF
#define PMIC_RG_BUCK_VCORE_OP_CFG_CLR_SHIFT 0
#define PMIC_RG_BUCK_VCORE_OC_DEG_EN_ADDR   MT6358_BUCK_VCORE_OC_CFG
#define PMIC_RG_BUCK_VCORE_OC_DEG_EN_MASK   0x1
#define PMIC_RG_BUCK_VCORE_OC_DEG_EN_SHIFT  1
#define PMIC_RG_BUCK_VCORE_OC_WND_ADDR  MT6358_BUCK_VCORE_OC_CFG
#define PMIC_RG_BUCK_VCORE_OC_WND_MASK  0x3
#define PMIC_RG_BUCK_VCORE_OC_WND_SHIFT 2
#define PMIC_RG_BUCK_VCORE_OC_THD_ADDR  MT6358_BUCK_VCORE_OC_CFG
#define PMIC_RG_BUCK_VCORE_OC_THD_MASK  0x3
#define PMIC_RG_BUCK_VCORE_OC_THD_SHIFT 6
#define PMIC_DA_VCORE_VOSEL_ADDR  MT6358_BUCK_VCORE_DBG0
#define PMIC_DA_VCORE_VOSEL_MASK  0x7F
#define PMIC_DA_VCORE_VOSEL_SHIFT 0
#define PMIC_DA_VCORE_VOSEL_GRAY_ADDR MT6358_BUCK_VCORE_DBG0
#define PMIC_DA_VCORE_VOSEL_GRAY_MASK 0x7F
#define PMIC_DA_VCORE_VOSEL_GRAY_SHIFT  8
#define PMIC_DA_VCORE_EN_ADDR   MT6358_BUCK_VCORE_DBG1
#define PMIC_DA_VCORE_EN_MASK   0x1
#define PMIC_DA_VCORE_EN_SHIFT  0
#define PMIC_DA_VCORE_STB_ADDR  MT6358_BUCK_VCORE_DBG1
#define PMIC_DA_VCORE_STB_MASK  0x1
#define PMIC_DA_VCORE_STB_SHIFT 1
#define PMIC_DA_VCORE_LOOP_SEL_ADDR   MT6358_BUCK_VCORE_DBG1
#define PMIC_DA_VCORE_LOOP_SEL_MASK   0x1
#define PMIC_DA_VCORE_LOOP_SEL_SHIFT  2
#define PMIC_DA_VCORE_R2R_PDN_ADDR MT6358_BUCK_VCORE_DBG1
#define PMIC_DA_VCORE_R2R_PDN_MASK 0x1
#define PMIC_DA_VCORE_R2R_PDN_SHIFT   3
#define PMIC_DA_VCORE_DVS_EN_ADDR MT6358_BUCK_VCORE_DBG1
#define PMIC_DA_VCORE_DVS_EN_MASK 0x1
#define PMIC_DA_VCORE_DVS_EN_SHIFT 4
#define PMIC_DA_VCORE_DVS_DOWN_ADDR   MT6358_BUCK_VCORE_DBG1
#define PMIC_DA_VCORE_DVS_DOWN_MASK   0x1
#define PMIC_DA_VCORE_DVS_DOWN_SHIFT  5
#define PMIC_DA_VCORE_SSH_ADDR  MT6358_BUCK_VCORE_DBG1
#define PMIC_DA_VCORE_SSH_MASK  0x1
#define PMIC_DA_VCORE_SSH_SHIFT 6
#define PMIC_DA_VCORE_MINFREQ_DISCHARGE_ADDR  MT6358_BUCK_VCORE_DBG1
#define PMIC_DA_VCORE_MINFREQ_DISCHARGE_MASK  0x1
#define PMIC_DA_VCORE_MINFREQ_DISCHARGE_SHIFT 8
#define PMIC_RG_BUCK_VCORE_OC_FLAG_CLR_SEL_ADDR  MT6358_BUCK_VCORE_DBG2
#define PMIC_RG_BUCK_VCORE_OC_FLAG_CLR_SEL_MASK  0x1
#define PMIC_RG_BUCK_VCORE_OC_FLAG_CLR_SEL_SHIFT  4
#define PMIC_RG_BUCK_VCORE_OSC_SEL_DIS_ADDR MT6358_BUCK_VCORE_DBG2
#define PMIC_RG_BUCK_VCORE_OSC_SEL_DIS_MASK 0x1
#define PMIC_RG_BUCK_VCORE_OSC_SEL_DIS_SHIFT  5
#define PMIC_RG_BUCK_VCORE_CK_SW_MODE_ADDR  MT6358_BUCK_VCORE_DBG2
#define PMIC_RG_BUCK_VCORE_CK_SW_MODE_MASK  0x1
#define PMIC_RG_BUCK_VCORE_CK_SW_MODE_SHIFT 6
#define PMIC_RG_BUCK_VCORE_CK_SW_EN_ADDR   MT6358_BUCK_VCORE_DBG2
#define PMIC_RG_BUCK_VCORE_CK_SW_EN_MASK   0x1
#define PMIC_RG_BUCK_VCORE_CK_SW_EN_SHIFT   7
#define PMIC_RG_BUCK_VCORE_SSHUB_EN_ADDR   MT6358_BUCK_VCORE_SSHUB_CON0
#define PMIC_RG_BUCK_VCORE_SSHUB_EN_MASK   0x1
#define PMIC_RG_BUCK_VCORE_SSHUB_EN_SHIFT   0
#define PMIC_RG_BUCK_VCORE_SSHUB_SLEEP_VOSEL_EN_ADDR   \
MT6358_BUCK_VCORE_SSHUB_CON0
#define PMIC_RG_BUCK_VCORE_SSHUB_SLEEP_VOSEL_EN_MASK   0x1
#define PMIC_RG_BUCK_VCORE_SSHUB_SLEEP_VOSEL_EN_SHIFT  1
#define PMIC_RG_BUCK_VCORE_SSHUB_VOSEL_ADDR MT6358_BUCK_VCORE_SSHUB_CON1
#define PMIC_RG_BUCK_VCORE_SSHUB_VOSEL_MASK 0x7F
#define PMIC_RG_BUCK_VCORE_SSHUB_VOSEL_SHIFT  0
#define PMIC_RG_BUCK_VCORE_SSHUB_VOSEL_SLEEP_ADDR MT6358_BUCK_VCORE_SSHUB_CON1
#define PMIC_RG_BUCK_VCORE_SSHUB_VOSEL_SLEEP_MASK 0x7F
#define PMIC_RG_BUCK_VCORE_SSHUB_VOSEL_SLEEP_SHIFT  8
#define PMIC_BUCK_VCORE_ELR_LEN_ADDR  MT6358_BUCK_VCORE_ELR_NUM
#define PMIC_BUCK_VCORE_ELR_LEN_MASK  0xFF
#define PMIC_BUCK_VCORE_ELR_LEN_SHIFT 0
#define PMIC_RG_BUCK_VCORE_VOSEL_ADDR MT6358_BUCK_VCORE_ELR0
#define PMIC_RG_BUCK_VCORE_VOSEL_MASK 0x7F
#define PMIC_RG_BUCK_VCORE_VOSEL_SHIFT  0
#define PMIC_BUCK_VGPU_ANA_ID_ADDR MT6358_BUCK_VGPU_DSN_ID
#define PMIC_BUCK_VGPU_ANA_ID_MASK 0xFF
#define PMIC_BUCK_VGPU_ANA_ID_SHIFT   0
#define PMIC_BUCK_VGPU_DIG_ID_ADDR MT6358_BUCK_VGPU_DSN_ID
#define PMIC_BUCK_VGPU_DIG_ID_MASK 0xFF
#define PMIC_BUCK_VGPU_DIG_ID_SHIFT   8
#define PMIC_BUCK_VGPU_ANA_MINOR_REV_ADDR   MT6358_BUCK_VGPU_DSN_REV0
#define PMIC_BUCK_VGPU_ANA_MINOR_REV_MASK   0xF
#define PMIC_BUCK_VGPU_ANA_MINOR_REV_SHIFT  0
#define PMIC_BUCK_VGPU_ANA_MAJOR_REV_ADDR   MT6358_BUCK_VGPU_DSN_REV0
#define PMIC_BUCK_VGPU_ANA_MAJOR_REV_MASK   0xF
#define PMIC_BUCK_VGPU_ANA_MAJOR_REV_SHIFT  4
#define PMIC_BUCK_VGPU_DIG_MINOR_REV_ADDR   MT6358_BUCK_VGPU_DSN_REV0
#define PMIC_BUCK_VGPU_DIG_MINOR_REV_MASK   0xF
#define PMIC_BUCK_VGPU_DIG_MINOR_REV_SHIFT  8
#define PMIC_BUCK_VGPU_DIG_MAJOR_REV_ADDR   MT6358_BUCK_VGPU_DSN_REV0
#define PMIC_BUCK_VGPU_DIG_MAJOR_REV_MASK   0xF
#define PMIC_BUCK_VGPU_DIG_MAJOR_REV_SHIFT  12
#define PMIC_BUCK_VGPU_DSN_CBS_ADDR   MT6358_BUCK_VGPU_DSN_DBI
#define PMIC_BUCK_VGPU_DSN_CBS_MASK   0x3
#define PMIC_BUCK_VGPU_DSN_CBS_SHIFT  0
#define PMIC_BUCK_VGPU_DSN_BIX_ADDR   MT6358_BUCK_VGPU_DSN_DBI
#define PMIC_BUCK_VGPU_DSN_BIX_MASK   0x3
#define PMIC_BUCK_VGPU_DSN_BIX_SHIFT  2
#define PMIC_BUCK_VGPU_DSN_ESP_ADDR   MT6358_BUCK_VGPU_DSN_DBI
#define PMIC_BUCK_VGPU_DSN_ESP_MASK   0xFF
#define PMIC_BUCK_VGPU_DSN_ESP_SHIFT  8
#define PMIC_BUCK_VGPU_DSN_FPI_SSHUB_ADDR   MT6358_BUCK_VGPU_DSN_DXI
#define PMIC_BUCK_VGPU_DSN_FPI_SSHUB_MASK   0x1
#define PMIC_BUCK_VGPU_DSN_FPI_SSHUB_SHIFT  0
#define PMIC_BUCK_VGPU_DSN_FPI_TRACKING_ADDR  MT6358_BUCK_VGPU_DSN_DXI
#define PMIC_BUCK_VGPU_DSN_FPI_TRACKING_MASK  0x1
#define PMIC_BUCK_VGPU_DSN_FPI_TRACKING_SHIFT 1
#define PMIC_BUCK_VGPU_DSN_FPI_PREOC_ADDR   MT6358_BUCK_VGPU_DSN_DXI
#define PMIC_BUCK_VGPU_DSN_FPI_PREOC_MASK   0x1
#define PMIC_BUCK_VGPU_DSN_FPI_PREOC_SHIFT  2
#define PMIC_BUCK_VGPU_DSN_FPI_VOTER_ADDR   MT6358_BUCK_VGPU_DSN_DXI
#define PMIC_BUCK_VGPU_DSN_FPI_VOTER_MASK   0x1
#define PMIC_BUCK_VGPU_DSN_FPI_VOTER_SHIFT  3
#define PMIC_BUCK_VGPU_DSN_FPI_ULTRASONIC_ADDR   MT6358_BUCK_VGPU_DSN_DXI
#define PMIC_BUCK_VGPU_DSN_FPI_ULTRASONIC_MASK   0x1
#define PMIC_BUCK_VGPU_DSN_FPI_ULTRASONIC_SHIFT  4
#define PMIC_BUCK_VGPU_DSN_FPI_DLC_ADDR MT6358_BUCK_VGPU_DSN_DXI
#define PMIC_BUCK_VGPU_DSN_FPI_DLC_MASK 0x1
#define PMIC_BUCK_VGPU_DSN_FPI_DLC_SHIFT   5
#define PMIC_BUCK_VGPU_DSN_FPI_TRAP_ADDR   MT6358_BUCK_VGPU_DSN_DXI
#define PMIC_BUCK_VGPU_DSN_FPI_TRAP_MASK   0x1
#define PMIC_BUCK_VGPU_DSN_FPI_TRAP_SHIFT   6
#define PMIC_RG_BUCK_VGPU_EN_ADDR MT6358_BUCK_VGPU_CON0
#define PMIC_RG_BUCK_VGPU_EN_MASK 0x1
#define PMIC_RG_BUCK_VGPU_EN_SHIFT 0
#define PMIC_RG_BUCK_VGPU_LP_ADDR MT6358_BUCK_VGPU_CON0
#define PMIC_RG_BUCK_VGPU_LP_MASK 0x1
#define PMIC_RG_BUCK_VGPU_LP_SHIFT 1
#define PMIC_RG_BUCK_VGPU_VOSEL_SLEEP_ADDR  MT6358_BUCK_VGPU_CON1
#define PMIC_RG_BUCK_VGPU_VOSEL_SLEEP_MASK  0x7F
#define PMIC_RG_BUCK_VGPU_VOSEL_SLEEP_SHIFT 0
#define PMIC_RG_BUCK_VGPU_SFCHG_FRATE_ADDR  MT6358_BUCK_VGPU_CFG0
#define PMIC_RG_BUCK_VGPU_SFCHG_FRATE_MASK  0x7F
#define PMIC_RG_BUCK_VGPU_SFCHG_FRATE_SHIFT 0
#define PMIC_RG_BUCK_VGPU_SFCHG_FEN_ADDR   MT6358_BUCK_VGPU_CFG0
#define PMIC_RG_BUCK_VGPU_SFCHG_FEN_MASK   0x1
#define PMIC_RG_BUCK_VGPU_SFCHG_FEN_SHIFT   7
#define PMIC_RG_BUCK_VGPU_SFCHG_RRATE_ADDR  MT6358_BUCK_VGPU_CFG0
#define PMIC_RG_BUCK_VGPU_SFCHG_RRATE_MASK  0x7F
#define PMIC_RG_BUCK_VGPU_SFCHG_RRATE_SHIFT 8
#define PMIC_RG_BUCK_VGPU_SFCHG_REN_ADDR   MT6358_BUCK_VGPU_CFG0
#define PMIC_RG_BUCK_VGPU_SFCHG_REN_MASK   0x1
#define PMIC_RG_BUCK_VGPU_SFCHG_REN_SHIFT   15
#define PMIC_RG_BUCK_VGPU_DVS_EN_TD_ADDR   MT6358_BUCK_VGPU_CFG1
#define PMIC_RG_BUCK_VGPU_DVS_EN_TD_MASK   0x3
#define PMIC_RG_BUCK_VGPU_DVS_EN_TD_SHIFT   0
#define PMIC_RG_BUCK_VGPU_DVS_EN_CTRL_ADDR  MT6358_BUCK_VGPU_CFG1
#define PMIC_RG_BUCK_VGPU_DVS_EN_CTRL_MASK  0x3
#define PMIC_RG_BUCK_VGPU_DVS_EN_CTRL_SHIFT 4
#define PMIC_RG_BUCK_VGPU_DVS_EN_ONCE_ADDR  MT6358_BUCK_VGPU_CFG1
#define PMIC_RG_BUCK_VGPU_DVS_EN_ONCE_MASK  0x1
#define PMIC_RG_BUCK_VGPU_DVS_EN_ONCE_SHIFT 6
#define PMIC_RG_BUCK_VGPU_DVS_DOWN_TD_ADDR  MT6358_BUCK_VGPU_CFG1
#define PMIC_RG_BUCK_VGPU_DVS_DOWN_TD_MASK  0x3
#define PMIC_RG_BUCK_VGPU_DVS_DOWN_TD_SHIFT 8
#define PMIC_RG_BUCK_VGPU_DVS_DOWN_CTRL_ADDR  MT6358_BUCK_VGPU_CFG1
#define PMIC_RG_BUCK_VGPU_DVS_DOWN_CTRL_MASK  0x3
#define PMIC_RG_BUCK_VGPU_DVS_DOWN_CTRL_SHIFT 12
#define PMIC_RG_BUCK_VGPU_DVS_DOWN_ONCE_ADDR  MT6358_BUCK_VGPU_CFG1
#define PMIC_RG_BUCK_VGPU_DVS_DOWN_ONCE_MASK  0x1
#define PMIC_RG_BUCK_VGPU_DVS_DOWN_ONCE_SHIFT 14
#define PMIC_RG_BUCK_VGPU_SW_OP_EN_ADDR MT6358_BUCK_VGPU_OP_EN
#define PMIC_RG_BUCK_VGPU_SW_OP_EN_MASK 0x1
#define PMIC_RG_BUCK_VGPU_SW_OP_EN_SHIFT   0
#define PMIC_RG_BUCK_VGPU_HW0_OP_EN_ADDR   MT6358_BUCK_VGPU_OP_EN
#define PMIC_RG_BUCK_VGPU_HW0_OP_EN_MASK   0x1
#define PMIC_RG_BUCK_VGPU_HW0_OP_EN_SHIFT   1
#define PMIC_RG_BUCK_VGPU_HW1_OP_EN_ADDR   MT6358_BUCK_VGPU_OP_EN
#define PMIC_RG_BUCK_VGPU_HW1_OP_EN_MASK   0x1
#define PMIC_RG_BUCK_VGPU_HW1_OP_EN_SHIFT   2
#define PMIC_RG_BUCK_VGPU_HW2_OP_EN_ADDR   MT6358_BUCK_VGPU_OP_EN
#define PMIC_RG_BUCK_VGPU_HW2_OP_EN_MASK   0x1
#define PMIC_RG_BUCK_VGPU_HW2_OP_EN_SHIFT   3
#define PMIC_RG_BUCK_VGPU_OP_EN_SET_ADDR   MT6358_BUCK_VGPU_OP_EN_SET
#define PMIC_RG_BUCK_VGPU_OP_EN_SET_MASK   0xFFFF
#define PMIC_RG_BUCK_VGPU_OP_EN_SET_SHIFT   0
#define PMIC_RG_BUCK_VGPU_OP_EN_CLR_ADDR   MT6358_BUCK_VGPU_OP_EN_CLR
#define PMIC_RG_BUCK_VGPU_OP_EN_CLR_MASK   0xFFFF
#define PMIC_RG_BUCK_VGPU_OP_EN_CLR_SHIFT   0
#define PMIC_RG_BUCK_VGPU_HW0_OP_CFG_ADDR   MT6358_BUCK_VGPU_OP_CFG
#define PMIC_RG_BUCK_VGPU_HW0_OP_CFG_MASK   0x1
#define PMIC_RG_BUCK_VGPU_HW0_OP_CFG_SHIFT  1
#define PMIC_RG_BUCK_VGPU_HW1_OP_CFG_ADDR   MT6358_BUCK_VGPU_OP_CFG
#define PMIC_RG_BUCK_VGPU_HW1_OP_CFG_MASK   0x1
#define PMIC_RG_BUCK_VGPU_HW1_OP_CFG_SHIFT  2
#define PMIC_RG_BUCK_VGPU_HW2_OP_CFG_ADDR   MT6358_BUCK_VGPU_OP_CFG
#define PMIC_RG_BUCK_VGPU_HW2_OP_CFG_MASK   0x1
#define PMIC_RG_BUCK_VGPU_HW2_OP_CFG_SHIFT  3
#define PMIC_RG_BUCK_VGPU_ON_OP_ADDR  MT6358_BUCK_VGPU_OP_CFG
#define PMIC_RG_BUCK_VGPU_ON_OP_MASK  0x1
#define PMIC_RG_BUCK_VGPU_ON_OP_SHIFT 8
#define PMIC_RG_BUCK_VGPU_LP_OP_ADDR  MT6358_BUCK_VGPU_OP_CFG
#define PMIC_RG_BUCK_VGPU_LP_OP_MASK  0x1
#define PMIC_RG_BUCK_VGPU_LP_OP_SHIFT 9
#define PMIC_RG_BUCK_VGPU_OP_CFG_SET_ADDR   MT6358_BUCK_VGPU_OP_CFG_SET
#define PMIC_RG_BUCK_VGPU_OP_CFG_SET_MASK   0xFFFF
#define PMIC_RG_BUCK_VGPU_OP_CFG_SET_SHIFT  0
#define PMIC_RG_BUCK_VGPU_OP_CFG_CLR_ADDR   MT6358_BUCK_VGPU_OP_CFG_CLR
#define PMIC_RG_BUCK_VGPU_OP_CFG_CLR_MASK   0xFFFF
#define PMIC_RG_BUCK_VGPU_OP_CFG_CLR_SHIFT  0
#define PMIC_RG_BUCK_VGPU_OC_DEG_EN_ADDR   MT6358_BUCK_VGPU_OC_CFG
#define PMIC_RG_BUCK_VGPU_OC_DEG_EN_MASK   0x1
#define PMIC_RG_BUCK_VGPU_OC_DEG_EN_SHIFT   1
#define PMIC_RG_BUCK_VGPU_OC_WND_ADDR MT6358_BUCK_VGPU_OC_CFG
#define PMIC_RG_BUCK_VGPU_OC_WND_MASK 0x3
#define PMIC_RG_BUCK_VGPU_OC_WND_SHIFT  2
#define PMIC_RG_BUCK_VGPU_OC_THD_ADDR MT6358_BUCK_VGPU_OC_CFG
#define PMIC_RG_BUCK_VGPU_OC_THD_MASK 0x3
#define PMIC_RG_BUCK_VGPU_OC_THD_SHIFT  6
#define PMIC_DA_VGPU_VOSEL_ADDR MT6358_BUCK_VGPU_DBG0
#define PMIC_DA_VGPU_VOSEL_MASK 0x7F
#define PMIC_DA_VGPU_VOSEL_SHIFT  0
#define PMIC_DA_VGPU_VOSEL_GRAY_ADDR  MT6358_BUCK_VGPU_DBG0
#define PMIC_DA_VGPU_VOSEL_GRAY_MASK  0x7F
#define PMIC_DA_VGPU_VOSEL_GRAY_SHIFT 8
#define PMIC_DA_VGPU_EN_ADDR MT6358_BUCK_VGPU_DBG1
#define PMIC_DA_VGPU_EN_MASK 0x1
#define PMIC_DA_VGPU_EN_SHIFT   0
#define PMIC_DA_VGPU_STB_ADDR   MT6358_BUCK_VGPU_DBG1
#define PMIC_DA_VGPU_STB_MASK   0x1
#define PMIC_DA_VGPU_STB_SHIFT  1
#define PMIC_DA_VGPU_LOOP_SEL_ADDR MT6358_BUCK_VGPU_DBG1
#define PMIC_DA_VGPU_LOOP_SEL_MASK 0x1
#define PMIC_DA_VGPU_LOOP_SEL_SHIFT   2
#define PMIC_DA_VGPU_R2R_PDN_ADDR MT6358_BUCK_VGPU_DBG1
#define PMIC_DA_VGPU_R2R_PDN_MASK 0x1
#define PMIC_DA_VGPU_R2R_PDN_SHIFT 3
#define PMIC_DA_VGPU_DVS_EN_ADDR  MT6358_BUCK_VGPU_DBG1
#define PMIC_DA_VGPU_DVS_EN_MASK  0x1
#define PMIC_DA_VGPU_DVS_EN_SHIFT 4
#define PMIC_DA_VGPU_DVS_DOWN_ADDR MT6358_BUCK_VGPU_DBG1
#define PMIC_DA_VGPU_DVS_DOWN_MASK 0x1
#define PMIC_DA_VGPU_DVS_DOWN_SHIFT   5
#define PMIC_DA_VGPU_SSH_ADDR   MT6358_BUCK_VGPU_DBG1
#define PMIC_DA_VGPU_SSH_MASK   0x1
#define PMIC_DA_VGPU_SSH_SHIFT  6
#define PMIC_DA_VGPU_MINFREQ_DISCHARGE_ADDR MT6358_BUCK_VGPU_DBG1
#define PMIC_DA_VGPU_MINFREQ_DISCHARGE_MASK 0x1
#define PMIC_DA_VGPU_MINFREQ_DISCHARGE_SHIFT  8
#define PMIC_RG_BUCK_VGPU_OC_FLAG_CLR_SEL_ADDR   MT6358_BUCK_VGPU_DBG2
#define PMIC_RG_BUCK_VGPU_OC_FLAG_CLR_SEL_MASK   0x1
#define PMIC_RG_BUCK_VGPU_OC_FLAG_CLR_SEL_SHIFT  4
#define PMIC_RG_BUCK_VGPU_OSC_SEL_DIS_ADDR  MT6358_BUCK_VGPU_DBG2
#define PMIC_RG_BUCK_VGPU_OSC_SEL_DIS_MASK  0x1
#define PMIC_RG_BUCK_VGPU_OSC_SEL_DIS_SHIFT 5
#define PMIC_RG_BUCK_VGPU_CK_SW_MODE_ADDR   MT6358_BUCK_VGPU_DBG2
#define PMIC_RG_BUCK_VGPU_CK_SW_MODE_MASK   0x1
#define PMIC_RG_BUCK_VGPU_CK_SW_MODE_SHIFT  6
#define PMIC_RG_BUCK_VGPU_CK_SW_EN_ADDR MT6358_BUCK_VGPU_DBG2
#define PMIC_RG_BUCK_VGPU_CK_SW_EN_MASK 0x1
#define PMIC_RG_BUCK_VGPU_CK_SW_EN_SHIFT   7
#define PMIC_BUCK_VGPU_ELR_LEN_ADDR   MT6358_BUCK_VGPU_ELR_NUM
#define PMIC_BUCK_VGPU_ELR_LEN_MASK   0xFF
#define PMIC_BUCK_VGPU_ELR_LEN_SHIFT  0
#define PMIC_RG_BUCK_VGPU_VOSEL_ADDR  MT6358_BUCK_VGPU_ELR0
#define PMIC_RG_BUCK_VGPU_VOSEL_MASK  0x7F
#define PMIC_RG_BUCK_VGPU_VOSEL_SHIFT 0
#define PMIC_BUCK_VMODEM_ANA_ID_ADDR  MT6358_BUCK_VMODEM_DSN_ID
#define PMIC_BUCK_VMODEM_ANA_ID_MASK  0xFF
#define PMIC_BUCK_VMODEM_ANA_ID_SHIFT 0
#define PMIC_BUCK_VMODEM_DIG_ID_ADDR  MT6358_BUCK_VMODEM_DSN_ID
#define PMIC_BUCK_VMODEM_DIG_ID_MASK  0xFF
#define PMIC_BUCK_VMODEM_DIG_ID_SHIFT 8
#define PMIC_BUCK_VMODEM_ANA_MINOR_REV_ADDR MT6358_BUCK_VMODEM_DSN_REV0
#define PMIC_BUCK_VMODEM_ANA_MINOR_REV_MASK 0xF
#define PMIC_BUCK_VMODEM_ANA_MINOR_REV_SHIFT  0
#define PMIC_BUCK_VMODEM_ANA_MAJOR_REV_ADDR MT6358_BUCK_VMODEM_DSN_REV0
#define PMIC_BUCK_VMODEM_ANA_MAJOR_REV_MASK 0xF
#define PMIC_BUCK_VMODEM_ANA_MAJOR_REV_SHIFT  4
#define PMIC_BUCK_VMODEM_DIG_MINOR_REV_ADDR MT6358_BUCK_VMODEM_DSN_REV0
#define PMIC_BUCK_VMODEM_DIG_MINOR_REV_MASK 0xF
#define PMIC_BUCK_VMODEM_DIG_MINOR_REV_SHIFT  8
#define PMIC_BUCK_VMODEM_DIG_MAJOR_REV_ADDR MT6358_BUCK_VMODEM_DSN_REV0
#define PMIC_BUCK_VMODEM_DIG_MAJOR_REV_MASK 0xF
#define PMIC_BUCK_VMODEM_DIG_MAJOR_REV_SHIFT  12
#define PMIC_BUCK_VMODEM_DSN_CBS_ADDR MT6358_BUCK_VMODEM_DSN_DBI
#define PMIC_BUCK_VMODEM_DSN_CBS_MASK 0x3
#define PMIC_BUCK_VMODEM_DSN_CBS_SHIFT  0
#define PMIC_BUCK_VMODEM_DSN_BIX_ADDR MT6358_BUCK_VMODEM_DSN_DBI
#define PMIC_BUCK_VMODEM_DSN_BIX_MASK 0x3
#define PMIC_BUCK_VMODEM_DSN_BIX_SHIFT  2
#define PMIC_BUCK_VMODEM_DSN_ESP_ADDR MT6358_BUCK_VMODEM_DSN_DBI
#define PMIC_BUCK_VMODEM_DSN_ESP_MASK 0xFF
#define PMIC_BUCK_VMODEM_DSN_ESP_SHIFT  8
#define PMIC_BUCK_VMODEM_DSN_FPI_SSHUB_ADDR MT6358_BUCK_VMODEM_DSN_DXI
#define PMIC_BUCK_VMODEM_DSN_FPI_SSHUB_MASK 0x1
#define PMIC_BUCK_VMODEM_DSN_FPI_SSHUB_SHIFT  0
#define PMIC_BUCK_VMODEM_DSN_FPI_TRACKING_ADDR   MT6358_BUCK_VMODEM_DSN_DXI
#define PMIC_BUCK_VMODEM_DSN_FPI_TRACKING_MASK   0x1
#define PMIC_BUCK_VMODEM_DSN_FPI_TRACKING_SHIFT  1
#define PMIC_BUCK_VMODEM_DSN_FPI_PREOC_ADDR MT6358_BUCK_VMODEM_DSN_DXI
#define PMIC_BUCK_VMODEM_DSN_FPI_PREOC_MASK 0x1
#define PMIC_BUCK_VMODEM_DSN_FPI_PREOC_SHIFT  2
#define PMIC_BUCK_VMODEM_DSN_FPI_VOTER_ADDR MT6358_BUCK_VMODEM_DSN_DXI
#define PMIC_BUCK_VMODEM_DSN_FPI_VOTER_MASK 0x1
#define PMIC_BUCK_VMODEM_DSN_FPI_VOTER_SHIFT  3
#define PMIC_BUCK_VMODEM_DSN_FPI_ULTRASONIC_ADDR  MT6358_BUCK_VMODEM_DSN_DXI
#define PMIC_BUCK_VMODEM_DSN_FPI_ULTRASONIC_MASK  0x1
#define PMIC_BUCK_VMODEM_DSN_FPI_ULTRASONIC_SHIFT 4
#define PMIC_BUCK_VMODEM_DSN_FPI_DLC_ADDR   MT6358_BUCK_VMODEM_DSN_DXI
#define PMIC_BUCK_VMODEM_DSN_FPI_DLC_MASK   0x1
#define PMIC_BUCK_VMODEM_DSN_FPI_DLC_SHIFT  5
#define PMIC_BUCK_VMODEM_DSN_FPI_TRAP_ADDR  MT6358_BUCK_VMODEM_DSN_DXI
#define PMIC_BUCK_VMODEM_DSN_FPI_TRAP_MASK  0x1
#define PMIC_BUCK_VMODEM_DSN_FPI_TRAP_SHIFT 6
#define PMIC_RG_BUCK_VMODEM_EN_ADDR   MT6358_BUCK_VMODEM_CON0
#define PMIC_RG_BUCK_VMODEM_EN_MASK   0x1
#define PMIC_RG_BUCK_VMODEM_EN_SHIFT  0
#define PMIC_RG_BUCK_VMODEM_LP_ADDR   MT6358_BUCK_VMODEM_CON0
#define PMIC_RG_BUCK_VMODEM_LP_MASK   0x1
#define PMIC_RG_BUCK_VMODEM_LP_SHIFT  1
#define PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_ADDR  MT6358_BUCK_VMODEM_CON1
#define PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_MASK  0x7F
#define PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_SHIFT 0
#define PMIC_RG_BUCK_VMODEM_SFCHG_FRATE_ADDR  MT6358_BUCK_VMODEM_CFG0
#define PMIC_RG_BUCK_VMODEM_SFCHG_FRATE_MASK  0x7F
#define PMIC_RG_BUCK_VMODEM_SFCHG_FRATE_SHIFT 0
#define PMIC_RG_BUCK_VMODEM_SFCHG_FEN_ADDR  MT6358_BUCK_VMODEM_CFG0
#define PMIC_RG_BUCK_VMODEM_SFCHG_FEN_MASK  0x1
#define PMIC_RG_BUCK_VMODEM_SFCHG_FEN_SHIFT 7
#define PMIC_RG_BUCK_VMODEM_SFCHG_RRATE_ADDR  MT6358_BUCK_VMODEM_CFG0
#define PMIC_RG_BUCK_VMODEM_SFCHG_RRATE_MASK  0x7F
#define PMIC_RG_BUCK_VMODEM_SFCHG_RRATE_SHIFT 8
#define PMIC_RG_BUCK_VMODEM_SFCHG_REN_ADDR  MT6358_BUCK_VMODEM_CFG0
#define PMIC_RG_BUCK_VMODEM_SFCHG_REN_MASK  0x1
#define PMIC_RG_BUCK_VMODEM_SFCHG_REN_SHIFT 15
#define PMIC_RG_BUCK_VMODEM_DVS_EN_TD_ADDR  MT6358_BUCK_VMODEM_CFG1
#define PMIC_RG_BUCK_VMODEM_DVS_EN_TD_MASK  0x3
#define PMIC_RG_BUCK_VMODEM_DVS_EN_TD_SHIFT 0
#define PMIC_RG_BUCK_VMODEM_DVS_EN_CTRL_ADDR  MT6358_BUCK_VMODEM_CFG1
#define PMIC_RG_BUCK_VMODEM_DVS_EN_CTRL_MASK  0x3
#define PMIC_RG_BUCK_VMODEM_DVS_EN_CTRL_SHIFT 4
#define PMIC_RG_BUCK_VMODEM_DVS_EN_ONCE_ADDR  MT6358_BUCK_VMODEM_CFG1
#define PMIC_RG_BUCK_VMODEM_DVS_EN_ONCE_MASK  0x1
#define PMIC_RG_BUCK_VMODEM_DVS_EN_ONCE_SHIFT 6
#define PMIC_RG_BUCK_VMODEM_DVS_DOWN_TD_ADDR  MT6358_BUCK_VMODEM_CFG1
#define PMIC_RG_BUCK_VMODEM_DVS_DOWN_TD_MASK  0x3
#define PMIC_RG_BUCK_VMODEM_DVS_DOWN_TD_SHIFT 8
#define PMIC_RG_BUCK_VMODEM_DVS_DOWN_CTRL_ADDR   MT6358_BUCK_VMODEM_CFG1
#define PMIC_RG_BUCK_VMODEM_DVS_DOWN_CTRL_MASK   0x3
#define PMIC_RG_BUCK_VMODEM_DVS_DOWN_CTRL_SHIFT  12
#define PMIC_RG_BUCK_VMODEM_DVS_DOWN_ONCE_ADDR   MT6358_BUCK_VMODEM_CFG1
#define PMIC_RG_BUCK_VMODEM_DVS_DOWN_ONCE_MASK   0x1
#define PMIC_RG_BUCK_VMODEM_DVS_DOWN_ONCE_SHIFT  14
#define PMIC_RG_BUCK_VMODEM_SW_OP_EN_ADDR   MT6358_BUCK_VMODEM_OP_EN
#define PMIC_RG_BUCK_VMODEM_SW_OP_EN_MASK   0x1
#define PMIC_RG_BUCK_VMODEM_SW_OP_EN_SHIFT  0
#define PMIC_RG_BUCK_VMODEM_HW0_OP_EN_ADDR  MT6358_BUCK_VMODEM_OP_EN
#define PMIC_RG_BUCK_VMODEM_HW0_OP_EN_MASK  0x1
#define PMIC_RG_BUCK_VMODEM_HW0_OP_EN_SHIFT 1
#define PMIC_RG_BUCK_VMODEM_HW1_OP_EN_ADDR  MT6358_BUCK_VMODEM_OP_EN
#define PMIC_RG_BUCK_VMODEM_HW1_OP_EN_MASK  0x1
#define PMIC_RG_BUCK_VMODEM_HW1_OP_EN_SHIFT 2
#define PMIC_RG_BUCK_VMODEM_HW2_OP_EN_ADDR  MT6358_BUCK_VMODEM_OP_EN
#define PMIC_RG_BUCK_VMODEM_HW2_OP_EN_MASK  0x1
#define PMIC_RG_BUCK_VMODEM_HW2_OP_EN_SHIFT 3
#define PMIC_RG_BUCK_VMODEM_OP_EN_SET_ADDR  MT6358_BUCK_VMODEM_OP_EN_SET
#define PMIC_RG_BUCK_VMODEM_OP_EN_SET_MASK  0xFFFF
#define PMIC_RG_BUCK_VMODEM_OP_EN_SET_SHIFT 0
#define PMIC_RG_BUCK_VMODEM_OP_EN_CLR_ADDR  MT6358_BUCK_VMODEM_OP_EN_CLR
#define PMIC_RG_BUCK_VMODEM_OP_EN_CLR_MASK  0xFFFF
#define PMIC_RG_BUCK_VMODEM_OP_EN_CLR_SHIFT 0
#define PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_ADDR MT6358_BUCK_VMODEM_OP_CFG
#define PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_MASK 0x1
#define PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_SHIFT  1
#define PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_ADDR MT6358_BUCK_VMODEM_OP_CFG
#define PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_MASK 0x1
#define PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_SHIFT  2
#define PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_ADDR MT6358_BUCK_VMODEM_OP_CFG
#define PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_MASK 0x1
#define PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_SHIFT  3
#define PMIC_RG_BUCK_VMODEM_ON_OP_ADDR  MT6358_BUCK_VMODEM_OP_CFG
#define PMIC_RG_BUCK_VMODEM_ON_OP_MASK  0x1
#define PMIC_RG_BUCK_VMODEM_ON_OP_SHIFT 8
#define PMIC_RG_BUCK_VMODEM_LP_OP_ADDR  MT6358_BUCK_VMODEM_OP_CFG
#define PMIC_RG_BUCK_VMODEM_LP_OP_MASK  0x1
#define PMIC_RG_BUCK_VMODEM_LP_OP_SHIFT 9
#define PMIC_RG_BUCK_VMODEM_OP_CFG_SET_ADDR MT6358_BUCK_VMODEM_OP_CFG_SET
#define PMIC_RG_BUCK_VMODEM_OP_CFG_SET_MASK 0xFFFF
#define PMIC_RG_BUCK_VMODEM_OP_CFG_SET_SHIFT  0
#define PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_ADDR MT6358_BUCK_VMODEM_OP_CFG_CLR
#define PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_MASK 0xFFFF
#define PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_SHIFT  0
#define PMIC_RG_BUCK_VMODEM_OC_DEG_EN_ADDR  MT6358_BUCK_VMODEM_OC_CFG
#define PMIC_RG_BUCK_VMODEM_OC_DEG_EN_MASK  0x1
#define PMIC_RG_BUCK_VMODEM_OC_DEG_EN_SHIFT 1
#define PMIC_RG_BUCK_VMODEM_OC_WND_ADDR MT6358_BUCK_VMODEM_OC_CFG
#define PMIC_RG_BUCK_VMODEM_OC_WND_MASK 0x3
#define PMIC_RG_BUCK_VMODEM_OC_WND_SHIFT   2
#define PMIC_RG_BUCK_VMODEM_OC_THD_ADDR MT6358_BUCK_VMODEM_OC_CFG
#define PMIC_RG_BUCK_VMODEM_OC_THD_MASK 0x3
#define PMIC_RG_BUCK_VMODEM_OC_THD_SHIFT   6
#define PMIC_DA_VMODEM_VOSEL_ADDR MT6358_BUCK_VMODEM_DBG0
#define PMIC_DA_VMODEM_VOSEL_MASK 0x7F
#define PMIC_DA_VMODEM_VOSEL_SHIFT 0
#define PMIC_DA_VMODEM_VOSEL_GRAY_ADDR  MT6358_BUCK_VMODEM_DBG0
#define PMIC_DA_VMODEM_VOSEL_GRAY_MASK  0x7F
#define PMIC_DA_VMODEM_VOSEL_GRAY_SHIFT 8
#define PMIC_DA_VMODEM_EN_ADDR  MT6358_BUCK_VMODEM_DBG1
#define PMIC_DA_VMODEM_EN_MASK  0x1
#define PMIC_DA_VMODEM_EN_SHIFT 0
#define PMIC_DA_VMODEM_STB_ADDR MT6358_BUCK_VMODEM_DBG1
#define PMIC_DA_VMODEM_STB_MASK 0x1
#define PMIC_DA_VMODEM_STB_SHIFT  1
#define PMIC_DA_VMODEM_LOOP_SEL_ADDR  MT6358_BUCK_VMODEM_DBG1
#define PMIC_DA_VMODEM_LOOP_SEL_MASK  0x1
#define PMIC_DA_VMODEM_LOOP_SEL_SHIFT 2
#define PMIC_DA_VMODEM_R2R_PDN_ADDR   MT6358_BUCK_VMODEM_DBG1
#define PMIC_DA_VMODEM_R2R_PDN_MASK   0x1
#define PMIC_DA_VMODEM_R2R_PDN_SHIFT  3
#define PMIC_DA_VMODEM_DVS_EN_ADDR MT6358_BUCK_VMODEM_DBG1
#define PMIC_DA_VMODEM_DVS_EN_MASK 0x1
#define PMIC_DA_VMODEM_DVS_EN_SHIFT   4
#define PMIC_DA_VMODEM_DVS_DOWN_ADDR  MT6358_BUCK_VMODEM_DBG1
#define PMIC_DA_VMODEM_DVS_DOWN_MASK  0x1
#define PMIC_DA_VMODEM_DVS_DOWN_SHIFT 5
#define PMIC_DA_VMODEM_SSH_ADDR MT6358_BUCK_VMODEM_DBG1
#define PMIC_DA_VMODEM_SSH_MASK 0x1
#define PMIC_DA_VMODEM_SSH_SHIFT  6
#define PMIC_DA_VMODEM_MINFREQ_DISCHARGE_ADDR MT6358_BUCK_VMODEM_DBG1
#define PMIC_DA_VMODEM_MINFREQ_DISCHARGE_MASK 0x1
#define PMIC_DA_VMODEM_MINFREQ_DISCHARGE_SHIFT   8
#define PMIC_RG_BUCK_VMODEM_OC_FLAG_CLR_SEL_ADDR  MT6358_BUCK_VMODEM_DBG2
#define PMIC_RG_BUCK_VMODEM_OC_FLAG_CLR_SEL_MASK  0x1
#define PMIC_RG_BUCK_VMODEM_OC_FLAG_CLR_SEL_SHIFT 4
#define PMIC_RG_BUCK_VMODEM_OSC_SEL_DIS_ADDR  MT6358_BUCK_VMODEM_DBG2
#define PMIC_RG_BUCK_VMODEM_OSC_SEL_DIS_MASK  0x1
#define PMIC_RG_BUCK_VMODEM_OSC_SEL_DIS_SHIFT 5
#define PMIC_RG_BUCK_VMODEM_CK_SW_MODE_ADDR MT6358_BUCK_VMODEM_DBG2
#define PMIC_RG_BUCK_VMODEM_CK_SW_MODE_MASK 0x1
#define PMIC_RG_BUCK_VMODEM_CK_SW_MODE_SHIFT  6
#define PMIC_RG_BUCK_VMODEM_CK_SW_EN_ADDR   MT6358_BUCK_VMODEM_DBG2
#define PMIC_RG_BUCK_VMODEM_CK_SW_EN_MASK   0x1
#define PMIC_RG_BUCK_VMODEM_CK_SW_EN_SHIFT  7
#define PMIC_BUCK_VMODEM_ELR_LEN_ADDR MT6358_BUCK_VMODEM_ELR_NUM
#define PMIC_BUCK_VMODEM_ELR_LEN_MASK 0xFF
#define PMIC_BUCK_VMODEM_ELR_LEN_SHIFT  0
#define PMIC_RG_BUCK_VMODEM_VOSEL_ADDR  MT6358_BUCK_VMODEM_ELR0
#define PMIC_RG_BUCK_VMODEM_VOSEL_MASK  0x7F
#define PMIC_RG_BUCK_VMODEM_VOSEL_SHIFT 0
#define PMIC_BUCK_VDRAM1_ANA_ID_ADDR  MT6358_BUCK_VDRAM1_DSN_ID
#define PMIC_BUCK_VDRAM1_ANA_ID_MASK  0xFF
#define PMIC_BUCK_VDRAM1_ANA_ID_SHIFT 0
#define PMIC_BUCK_VDRAM1_DIG_ID_ADDR  MT6358_BUCK_VDRAM1_DSN_ID
#define PMIC_BUCK_VDRAM1_DIG_ID_MASK  0xFF
#define PMIC_BUCK_VDRAM1_DIG_ID_SHIFT 8
#define PMIC_BUCK_VDRAM1_ANA_MINOR_REV_ADDR MT6358_BUCK_VDRAM1_DSN_REV0
#define PMIC_BUCK_VDRAM1_ANA_MINOR_REV_MASK 0xF
#define PMIC_BUCK_VDRAM1_ANA_MINOR_REV_SHIFT  0
#define PMIC_BUCK_VDRAM1_ANA_MAJOR_REV_ADDR MT6358_BUCK_VDRAM1_DSN_REV0
#define PMIC_BUCK_VDRAM1_ANA_MAJOR_REV_MASK 0xF
#define PMIC_BUCK_VDRAM1_ANA_MAJOR_REV_SHIFT  4
#define PMIC_BUCK_VDRAM1_DIG_MINOR_REV_ADDR MT6358_BUCK_VDRAM1_DSN_REV0
#define PMIC_BUCK_VDRAM1_DIG_MINOR_REV_MASK 0xF
#define PMIC_BUCK_VDRAM1_DIG_MINOR_REV_SHIFT  8
#define PMIC_BUCK_VDRAM1_DIG_MAJOR_REV_ADDR MT6358_BUCK_VDRAM1_DSN_REV0
#define PMIC_BUCK_VDRAM1_DIG_MAJOR_REV_MASK 0xF
#define PMIC_BUCK_VDRAM1_DIG_MAJOR_REV_SHIFT  12
#define PMIC_BUCK_VDRAM1_DSN_CBS_ADDR MT6358_BUCK_VDRAM1_DSN_DBI
#define PMIC_BUCK_VDRAM1_DSN_CBS_MASK 0x3
#define PMIC_BUCK_VDRAM1_DSN_CBS_SHIFT  0
#define PMIC_BUCK_VDRAM1_DSN_BIX_ADDR MT6358_BUCK_VDRAM1_DSN_DBI
#define PMIC_BUCK_VDRAM1_DSN_BIX_MASK 0x3
#define PMIC_BUCK_VDRAM1_DSN_BIX_SHIFT  2
#define PMIC_BUCK_VDRAM1_DSN_ESP_ADDR MT6358_BUCK_VDRAM1_DSN_DBI
#define PMIC_BUCK_VDRAM1_DSN_ESP_MASK 0xFF
#define PMIC_BUCK_VDRAM1_DSN_ESP_SHIFT  8
#define PMIC_BUCK_VDRAM1_DSN_FPI_SSHUB_ADDR MT6358_BUCK_VDRAM1_DSN_DXI
#define PMIC_BUCK_VDRAM1_DSN_FPI_SSHUB_MASK 0x1
#define PMIC_BUCK_VDRAM1_DSN_FPI_SSHUB_SHIFT  0
#define PMIC_BUCK_VDRAM1_DSN_FPI_TRACKING_ADDR   MT6358_BUCK_VDRAM1_DSN_DXI
#define PMIC_BUCK_VDRAM1_DSN_FPI_TRACKING_MASK   0x1
#define PMIC_BUCK_VDRAM1_DSN_FPI_TRACKING_SHIFT  1
#define PMIC_BUCK_VDRAM1_DSN_FPI_PREOC_ADDR MT6358_BUCK_VDRAM1_DSN_DXI
#define PMIC_BUCK_VDRAM1_DSN_FPI_PREOC_MASK 0x1
#define PMIC_BUCK_VDRAM1_DSN_FPI_PREOC_SHIFT  2
#define PMIC_BUCK_VDRAM1_DSN_FPI_VOTER_ADDR MT6358_BUCK_VDRAM1_DSN_DXI
#define PMIC_BUCK_VDRAM1_DSN_FPI_VOTER_MASK 0x1
#define PMIC_BUCK_VDRAM1_DSN_FPI_VOTER_SHIFT  3
#define PMIC_BUCK_VDRAM1_DSN_FPI_ULTRASONIC_ADDR  MT6358_BUCK_VDRAM1_DSN_DXI
#define PMIC_BUCK_VDRAM1_DSN_FPI_ULTRASONIC_MASK  0x1
#define PMIC_BUCK_VDRAM1_DSN_FPI_ULTRASONIC_SHIFT 4
#define PMIC_BUCK_VDRAM1_DSN_FPI_DLC_ADDR   MT6358_BUCK_VDRAM1_DSN_DXI
#define PMIC_BUCK_VDRAM1_DSN_FPI_DLC_MASK   0x1
#define PMIC_BUCK_VDRAM1_DSN_FPI_DLC_SHIFT  5
#define PMIC_BUCK_VDRAM1_DSN_FPI_TRAP_ADDR  MT6358_BUCK_VDRAM1_DSN_DXI
#define PMIC_BUCK_VDRAM1_DSN_FPI_TRAP_MASK  0x1
#define PMIC_BUCK_VDRAM1_DSN_FPI_TRAP_SHIFT 6
#define PMIC_RG_BUCK_VDRAM1_EN_ADDR   MT6358_BUCK_VDRAM1_CON0
#define PMIC_RG_BUCK_VDRAM1_EN_MASK   0x1
#define PMIC_RG_BUCK_VDRAM1_EN_SHIFT  0
#define PMIC_RG_BUCK_VDRAM1_LP_ADDR   MT6358_BUCK_VDRAM1_CON0
#define PMIC_RG_BUCK_VDRAM1_LP_MASK   0x1
#define PMIC_RG_BUCK_VDRAM1_LP_SHIFT  1
#define PMIC_RG_BUCK_VDRAM1_VOSEL_SLEEP_ADDR  MT6358_BUCK_VDRAM1_CON1
#define PMIC_RG_BUCK_VDRAM1_VOSEL_SLEEP_MASK  0x7F
#define PMIC_RG_BUCK_VDRAM1_VOSEL_SLEEP_SHIFT 0
#define PMIC_RG_BUCK_VDRAM1_SFCHG_FRATE_ADDR  MT6358_BUCK_VDRAM1_CFG0
#define PMIC_RG_BUCK_VDRAM1_SFCHG_FRATE_MASK  0x7F
#define PMIC_RG_BUCK_VDRAM1_SFCHG_FRATE_SHIFT 0
#define PMIC_RG_BUCK_VDRAM1_SFCHG_FEN_ADDR  MT6358_BUCK_VDRAM1_CFG0
#define PMIC_RG_BUCK_VDRAM1_SFCHG_FEN_MASK  0x1
#define PMIC_RG_BUCK_VDRAM1_SFCHG_FEN_SHIFT 7
#define PMIC_RG_BUCK_VDRAM1_SFCHG_RRATE_ADDR  MT6358_BUCK_VDRAM1_CFG0
#define PMIC_RG_BUCK_VDRAM1_SFCHG_RRATE_MASK  0x7F
#define PMIC_RG_BUCK_VDRAM1_SFCHG_RRATE_SHIFT 8
#define PMIC_RG_BUCK_VDRAM1_SFCHG_REN_ADDR  MT6358_BUCK_VDRAM1_CFG0
#define PMIC_RG_BUCK_VDRAM1_SFCHG_REN_MASK  0x1
#define PMIC_RG_BUCK_VDRAM1_SFCHG_REN_SHIFT 15
#define PMIC_RG_BUCK_VDRAM1_DVS_EN_TD_ADDR  MT6358_BUCK_VDRAM1_CFG1
#define PMIC_RG_BUCK_VDRAM1_DVS_EN_TD_MASK  0x3
#define PMIC_RG_BUCK_VDRAM1_DVS_EN_TD_SHIFT 0
#define PMIC_RG_BUCK_VDRAM1_DVS_EN_CTRL_ADDR  MT6358_BUCK_VDRAM1_CFG1
#define PMIC_RG_BUCK_VDRAM1_DVS_EN_CTRL_MASK  0x3
#define PMIC_RG_BUCK_VDRAM1_DVS_EN_CTRL_SHIFT 4
#define PMIC_RG_BUCK_VDRAM1_DVS_EN_ONCE_ADDR  MT6358_BUCK_VDRAM1_CFG1
#define PMIC_RG_BUCK_VDRAM1_DVS_EN_ONCE_MASK  0x1
#define PMIC_RG_BUCK_VDRAM1_DVS_EN_ONCE_SHIFT 6
#define PMIC_RG_BUCK_VDRAM1_DVS_DOWN_TD_ADDR  MT6358_BUCK_VDRAM1_CFG1
#define PMIC_RG_BUCK_VDRAM1_DVS_DOWN_TD_MASK  0x3
#define PMIC_RG_BUCK_VDRAM1_DVS_DOWN_TD_SHIFT 8
#define PMIC_RG_BUCK_VDRAM1_DVS_DOWN_CTRL_ADDR   MT6358_BUCK_VDRAM1_CFG1
#define PMIC_RG_BUCK_VDRAM1_DVS_DOWN_CTRL_MASK   0x3
#define PMIC_RG_BUCK_VDRAM1_DVS_DOWN_CTRL_SHIFT  12
#define PMIC_RG_BUCK_VDRAM1_DVS_DOWN_ONCE_ADDR   MT6358_BUCK_VDRAM1_CFG1
#define PMIC_RG_BUCK_VDRAM1_DVS_DOWN_ONCE_MASK   0x1
#define PMIC_RG_BUCK_VDRAM1_DVS_DOWN_ONCE_SHIFT  14
#define PMIC_RG_BUCK_VDRAM1_SW_OP_EN_ADDR   MT6358_BUCK_VDRAM1_OP_EN
#define PMIC_RG_BUCK_VDRAM1_SW_OP_EN_MASK   0x1
#define PMIC_RG_BUCK_VDRAM1_SW_OP_EN_SHIFT  0
#define PMIC_RG_BUCK_VDRAM1_HW0_OP_EN_ADDR  MT6358_BUCK_VDRAM1_OP_EN
#define PMIC_RG_BUCK_VDRAM1_HW0_OP_EN_MASK  0x1
#define PMIC_RG_BUCK_VDRAM1_HW0_OP_EN_SHIFT 1
#define PMIC_RG_BUCK_VDRAM1_HW1_OP_EN_ADDR  MT6358_BUCK_VDRAM1_OP_EN
#define PMIC_RG_BUCK_VDRAM1_HW1_OP_EN_MASK  0x1
#define PMIC_RG_BUCK_VDRAM1_HW1_OP_EN_SHIFT 2
#define PMIC_RG_BUCK_VDRAM1_HW2_OP_EN_ADDR  MT6358_BUCK_VDRAM1_OP_EN
#define PMIC_RG_BUCK_VDRAM1_HW2_OP_EN_MASK  0x1
#define PMIC_RG_BUCK_VDRAM1_HW2_OP_EN_SHIFT 3
#define PMIC_RG_BUCK_VDRAM1_OP_EN_SET_ADDR  MT6358_BUCK_VDRAM1_OP_EN_SET
#define PMIC_RG_BUCK_VDRAM1_OP_EN_SET_MASK  0xFFFF
#define PMIC_RG_BUCK_VDRAM1_OP_EN_SET_SHIFT 0
#define PMIC_RG_BUCK_VDRAM1_OP_EN_CLR_ADDR  MT6358_BUCK_VDRAM1_OP_EN_CLR
#define PMIC_RG_BUCK_VDRAM1_OP_EN_CLR_MASK  0xFFFF
#define PMIC_RG_BUCK_VDRAM1_OP_EN_CLR_SHIFT 0
#define PMIC_RG_BUCK_VDRAM1_HW0_OP_CFG_ADDR MT6358_BUCK_VDRAM1_OP_CFG
#define PMIC_RG_BUCK_VDRAM1_HW0_OP_CFG_MASK 0x1
#define PMIC_RG_BUCK_VDRAM1_HW0_OP_CFG_SHIFT  1
#define PMIC_RG_BUCK_VDRAM1_HW1_OP_CFG_ADDR MT6358_BUCK_VDRAM1_OP_CFG
#define PMIC_RG_BUCK_VDRAM1_HW1_OP_CFG_MASK 0x1
#define PMIC_RG_BUCK_VDRAM1_HW1_OP_CFG_SHIFT  2
#define PMIC_RG_BUCK_VDRAM1_HW2_OP_CFG_ADDR MT6358_BUCK_VDRAM1_OP_CFG
#define PMIC_RG_BUCK_VDRAM1_HW2_OP_CFG_MASK 0x1
#define PMIC_RG_BUCK_VDRAM1_HW2_OP_CFG_SHIFT  3
#define PMIC_RG_BUCK_VDRAM1_ON_OP_ADDR  MT6358_BUCK_VDRAM1_OP_CFG
#define PMIC_RG_BUCK_VDRAM1_ON_OP_MASK  0x1
#define PMIC_RG_BUCK_VDRAM1_ON_OP_SHIFT 8
#define PMIC_RG_BUCK_VDRAM1_LP_OP_ADDR  MT6358_BUCK_VDRAM1_OP_CFG
#define PMIC_RG_BUCK_VDRAM1_LP_OP_MASK  0x1
#define PMIC_RG_BUCK_VDRAM1_LP_OP_SHIFT 9
#define PMIC_RG_BUCK_VDRAM1_OP_CFG_SET_ADDR MT6358_BUCK_VDRAM1_OP_CFG_SET
#define PMIC_RG_BUCK_VDRAM1_OP_CFG_SET_MASK 0xFFFF
#define PMIC_RG_BUCK_VDRAM1_OP_CFG_SET_SHIFT  0
#define PMIC_RG_BUCK_VDRAM1_OP_CFG_CLR_ADDR MT6358_BUCK_VDRAM1_OP_CFG_CLR
#define PMIC_RG_BUCK_VDRAM1_OP_CFG_CLR_MASK 0xFFFF
#define PMIC_RG_BUCK_VDRAM1_OP_CFG_CLR_SHIFT  0
#define PMIC_RG_BUCK_VDRAM1_OC_DEG_EN_ADDR  MT6358_BUCK_VDRAM1_OC_CFG
#define PMIC_RG_BUCK_VDRAM1_OC_DEG_EN_MASK  0x1
#define PMIC_RG_BUCK_VDRAM1_OC_DEG_EN_SHIFT 1
#define PMIC_RG_BUCK_VDRAM1_OC_WND_ADDR MT6358_BUCK_VDRAM1_OC_CFG
#define PMIC_RG_BUCK_VDRAM1_OC_WND_MASK 0x3
#define PMIC_RG_BUCK_VDRAM1_OC_WND_SHIFT   2
#define PMIC_RG_BUCK_VDRAM1_OC_THD_ADDR MT6358_BUCK_VDRAM1_OC_CFG
#define PMIC_RG_BUCK_VDRAM1_OC_THD_MASK 0x3
#define PMIC_RG_BUCK_VDRAM1_OC_THD_SHIFT   6
#define PMIC_DA_VDRAM1_VOSEL_ADDR MT6358_BUCK_VDRAM1_DBG0
#define PMIC_DA_VDRAM1_VOSEL_MASK 0x7F
#define PMIC_DA_VDRAM1_VOSEL_SHIFT 0
#define PMIC_DA_VDRAM1_VOSEL_GRAY_ADDR  MT6358_BUCK_VDRAM1_DBG0
#define PMIC_DA_VDRAM1_VOSEL_GRAY_MASK  0x7F
#define PMIC_DA_VDRAM1_VOSEL_GRAY_SHIFT 8
#define PMIC_DA_VDRAM1_EN_ADDR  MT6358_BUCK_VDRAM1_DBG1
#define PMIC_DA_VDRAM1_EN_MASK  0x1
#define PMIC_DA_VDRAM1_EN_SHIFT 0
#define PMIC_DA_VDRAM1_STB_ADDR MT6358_BUCK_VDRAM1_DBG1
#define PMIC_DA_VDRAM1_STB_MASK 0x1
#define PMIC_DA_VDRAM1_STB_SHIFT  1
#define PMIC_DA_VDRAM1_LOOP_SEL_ADDR  MT6358_BUCK_VDRAM1_DBG1
#define PMIC_DA_VDRAM1_LOOP_SEL_MASK  0x1
#define PMIC_DA_VDRAM1_LOOP_SEL_SHIFT 2
#define PMIC_DA_VDRAM1_R2R_PDN_ADDR   MT6358_BUCK_VDRAM1_DBG1
#define PMIC_DA_VDRAM1_R2R_PDN_MASK   0x1
#define PMIC_DA_VDRAM1_R2R_PDN_SHIFT  3
#define PMIC_DA_VDRAM1_DVS_EN_ADDR MT6358_BUCK_VDRAM1_DBG1
#define PMIC_DA_VDRAM1_DVS_EN_MASK 0x1
#define PMIC_DA_VDRAM1_DVS_EN_SHIFT   4
#define PMIC_DA_VDRAM1_DVS_DOWN_ADDR  MT6358_BUCK_VDRAM1_DBG1
#define PMIC_DA_VDRAM1_DVS_DOWN_MASK  0x1
#define PMIC_DA_VDRAM1_DVS_DOWN_SHIFT 5
#define PMIC_DA_VDRAM1_SSH_ADDR MT6358_BUCK_VDRAM1_DBG1
#define PMIC_DA_VDRAM1_SSH_MASK 0x1
#define PMIC_DA_VDRAM1_SSH_SHIFT  6
#define PMIC_DA_VDRAM1_MINFREQ_DISCHARGE_ADDR MT6358_BUCK_VDRAM1_DBG1
#define PMIC_DA_VDRAM1_MINFREQ_DISCHARGE_MASK 0x1
#define PMIC_DA_VDRAM1_MINFREQ_DISCHARGE_SHIFT   8
#define PMIC_RG_BUCK_VDRAM1_OC_FLAG_CLR_SEL_ADDR  MT6358_BUCK_VDRAM1_DBG2
#define PMIC_RG_BUCK_VDRAM1_OC_FLAG_CLR_SEL_MASK  0x1
#define PMIC_RG_BUCK_VDRAM1_OC_FLAG_CLR_SEL_SHIFT 4
#define PMIC_RG_BUCK_VDRAM1_OSC_SEL_DIS_ADDR  MT6358_BUCK_VDRAM1_DBG2
#define PMIC_RG_BUCK_VDRAM1_OSC_SEL_DIS_MASK  0x1
#define PMIC_RG_BUCK_VDRAM1_OSC_SEL_DIS_SHIFT 5
#define PMIC_RG_BUCK_VDRAM1_CK_SW_MODE_ADDR MT6358_BUCK_VDRAM1_DBG2
#define PMIC_RG_BUCK_VDRAM1_CK_SW_MODE_MASK 0x1
#define PMIC_RG_BUCK_VDRAM1_CK_SW_MODE_SHIFT  6
#define PMIC_RG_BUCK_VDRAM1_CK_SW_EN_ADDR   MT6358_BUCK_VDRAM1_DBG2
#define PMIC_RG_BUCK_VDRAM1_CK_SW_EN_MASK   0x1
#define PMIC_RG_BUCK_VDRAM1_CK_SW_EN_SHIFT  7
#define PMIC_BUCK_VDRAM1_ELR_LEN_ADDR MT6358_BUCK_VDRAM1_ELR_NUM
#define PMIC_BUCK_VDRAM1_ELR_LEN_MASK 0xFF
#define PMIC_BUCK_VDRAM1_ELR_LEN_SHIFT  0
#define PMIC_RG_BUCK_VDRAM1_VOSEL_ADDR  MT6358_BUCK_VDRAM1_ELR0
#define PMIC_RG_BUCK_VDRAM1_VOSEL_MASK  0x7F
#define PMIC_RG_BUCK_VDRAM1_VOSEL_SHIFT 0
#define PMIC_BUCK_VS1_ANA_ID_ADDR MT6358_BUCK_VS1_DSN_ID
#define PMIC_BUCK_VS1_ANA_ID_MASK 0xFF
#define PMIC_BUCK_VS1_ANA_ID_SHIFT 0
#define PMIC_BUCK_VS1_DIG_ID_ADDR MT6358_BUCK_VS1_DSN_ID
#define PMIC_BUCK_VS1_DIG_ID_MASK 0xFF
#define PMIC_BUCK_VS1_DIG_ID_SHIFT 8
#define PMIC_BUCK_VS1_ANA_MINOR_REV_ADDR   MT6358_BUCK_VS1_DSN_REV0
#define PMIC_BUCK_VS1_ANA_MINOR_REV_MASK   0xF
#define PMIC_BUCK_VS1_ANA_MINOR_REV_SHIFT   0
#define PMIC_BUCK_VS1_ANA_MAJOR_REV_ADDR   MT6358_BUCK_VS1_DSN_REV0
#define PMIC_BUCK_VS1_ANA_MAJOR_REV_MASK   0xF
#define PMIC_BUCK_VS1_ANA_MAJOR_REV_SHIFT   4
#define PMIC_BUCK_VS1_DIG_MINOR_REV_ADDR   MT6358_BUCK_VS1_DSN_REV0
#define PMIC_BUCK_VS1_DIG_MINOR_REV_MASK   0xF
#define PMIC_BUCK_VS1_DIG_MINOR_REV_SHIFT   8
#define PMIC_BUCK_VS1_DIG_MAJOR_REV_ADDR   MT6358_BUCK_VS1_DSN_REV0
#define PMIC_BUCK_VS1_DIG_MAJOR_REV_MASK   0xF
#define PMIC_BUCK_VS1_DIG_MAJOR_REV_SHIFT   12
#define PMIC_BUCK_VS1_DSN_CBS_ADDR MT6358_BUCK_VS1_DSN_DBI
#define PMIC_BUCK_VS1_DSN_CBS_MASK 0x3
#define PMIC_BUCK_VS1_DSN_CBS_SHIFT   0
#define PMIC_BUCK_VS1_DSN_BIX_ADDR MT6358_BUCK_VS1_DSN_DBI
#define PMIC_BUCK_VS1_DSN_BIX_MASK 0x3
#define PMIC_BUCK_VS1_DSN_BIX_SHIFT   2
#define PMIC_BUCK_VS1_DSN_ESP_ADDR MT6358_BUCK_VS1_DSN_DBI
#define PMIC_BUCK_VS1_DSN_ESP_MASK 0xFF
#define PMIC_BUCK_VS1_DSN_ESP_SHIFT   8
#define PMIC_BUCK_VS1_DSN_FPI_SSHUB_ADDR   MT6358_BUCK_VS1_DSN_DXI
#define PMIC_BUCK_VS1_DSN_FPI_SSHUB_MASK   0x1
#define PMIC_BUCK_VS1_DSN_FPI_SSHUB_SHIFT   0
#define PMIC_BUCK_VS1_DSN_FPI_TRACKING_ADDR MT6358_BUCK_VS1_DSN_DXI
#define PMIC_BUCK_VS1_DSN_FPI_TRACKING_MASK 0x1
#define PMIC_BUCK_VS1_DSN_FPI_TRACKING_SHIFT  1
#define PMIC_BUCK_VS1_DSN_FPI_PREOC_ADDR   MT6358_BUCK_VS1_DSN_DXI
#define PMIC_BUCK_VS1_DSN_FPI_PREOC_MASK   0x1
#define PMIC_BUCK_VS1_DSN_FPI_PREOC_SHIFT   2
#define PMIC_BUCK_VS1_DSN_FPI_VOTER_ADDR   MT6358_BUCK_VS1_DSN_DXI
#define PMIC_BUCK_VS1_DSN_FPI_VOTER_MASK   0x1
#define PMIC_BUCK_VS1_DSN_FPI_VOTER_SHIFT   3
#define PMIC_BUCK_VS1_DSN_FPI_ULTRASONIC_ADDR MT6358_BUCK_VS1_DSN_DXI
#define PMIC_BUCK_VS1_DSN_FPI_ULTRASONIC_MASK 0x1
#define PMIC_BUCK_VS1_DSN_FPI_ULTRASONIC_SHIFT   4
#define PMIC_BUCK_VS1_DSN_FPI_DLC_ADDR  MT6358_BUCK_VS1_DSN_DXI
#define PMIC_BUCK_VS1_DSN_FPI_DLC_MASK  0x1
#define PMIC_BUCK_VS1_DSN_FPI_DLC_SHIFT 5
#define PMIC_BUCK_VS1_DSN_FPI_TRAP_ADDR MT6358_BUCK_VS1_DSN_DXI
#define PMIC_BUCK_VS1_DSN_FPI_TRAP_MASK 0x1
#define PMIC_BUCK_VS1_DSN_FPI_TRAP_SHIFT   6
#define PMIC_RG_BUCK_VS1_EN_ADDR  MT6358_BUCK_VS1_CON0
#define PMIC_RG_BUCK_VS1_EN_MASK  0x1
#define PMIC_RG_BUCK_VS1_EN_SHIFT 0
#define PMIC_RG_BUCK_VS1_LP_ADDR  MT6358_BUCK_VS1_CON0
#define PMIC_RG_BUCK_VS1_LP_MASK  0x1
#define PMIC_RG_BUCK_VS1_LP_SHIFT 1
#define PMIC_RG_BUCK_VS1_VOSEL_SLEEP_ADDR   MT6358_BUCK_VS1_CON1
#define PMIC_RG_BUCK_VS1_VOSEL_SLEEP_MASK   0x7F
#define PMIC_RG_BUCK_VS1_VOSEL_SLEEP_SHIFT  0
#define PMIC_RG_BUCK_VS1_SFCHG_FRATE_ADDR   MT6358_BUCK_VS1_CFG0
#define PMIC_RG_BUCK_VS1_SFCHG_FRATE_MASK   0x7F
#define PMIC_RG_BUCK_VS1_SFCHG_FRATE_SHIFT  0
#define PMIC_RG_BUCK_VS1_SFCHG_FEN_ADDR MT6358_BUCK_VS1_CFG0
#define PMIC_RG_BUCK_VS1_SFCHG_FEN_MASK 0x1
#define PMIC_RG_BUCK_VS1_SFCHG_FEN_SHIFT   7
#define PMIC_RG_BUCK_VS1_SFCHG_RRATE_ADDR   MT6358_BUCK_VS1_CFG0
#define PMIC_RG_BUCK_VS1_SFCHG_RRATE_MASK   0x7F
#define PMIC_RG_BUCK_VS1_SFCHG_RRATE_SHIFT  8
#define PMIC_RG_BUCK_VS1_SFCHG_REN_ADDR MT6358_BUCK_VS1_CFG0
#define PMIC_RG_BUCK_VS1_SFCHG_REN_MASK 0x1
#define PMIC_RG_BUCK_VS1_SFCHG_REN_SHIFT   15
#define PMIC_RG_BUCK_VS1_DVS_EN_TD_ADDR MT6358_BUCK_VS1_CFG1
#define PMIC_RG_BUCK_VS1_DVS_EN_TD_MASK 0x3
#define PMIC_RG_BUCK_VS1_DVS_EN_TD_SHIFT   0
#define PMIC_RG_BUCK_VS1_DVS_EN_CTRL_ADDR   MT6358_BUCK_VS1_CFG1
#define PMIC_RG_BUCK_VS1_DVS_EN_CTRL_MASK   0x3
#define PMIC_RG_BUCK_VS1_DVS_EN_CTRL_SHIFT  4
#define PMIC_RG_BUCK_VS1_DVS_EN_ONCE_ADDR   MT6358_BUCK_VS1_CFG1
#define PMIC_RG_BUCK_VS1_DVS_EN_ONCE_MASK   0x1
#define PMIC_RG_BUCK_VS1_DVS_EN_ONCE_SHIFT  6
#define PMIC_RG_BUCK_VS1_DVS_DOWN_TD_ADDR   MT6358_BUCK_VS1_CFG1
#define PMIC_RG_BUCK_VS1_DVS_DOWN_TD_MASK   0x3
#define PMIC_RG_BUCK_VS1_DVS_DOWN_TD_SHIFT  8
#define PMIC_RG_BUCK_VS1_DVS_DOWN_CTRL_ADDR MT6358_BUCK_VS1_CFG1
#define PMIC_RG_BUCK_VS1_DVS_DOWN_CTRL_MASK 0x3
#define PMIC_RG_BUCK_VS1_DVS_DOWN_CTRL_SHIFT  12
#define PMIC_RG_BUCK_VS1_DVS_DOWN_ONCE_ADDR MT6358_BUCK_VS1_CFG1
#define PMIC_RG_BUCK_VS1_DVS_DOWN_ONCE_MASK 0x1
#define PMIC_RG_BUCK_VS1_DVS_DOWN_ONCE_SHIFT  14
#define PMIC_RG_BUCK_VS1_SW_OP_EN_ADDR  MT6358_BUCK_VS1_OP_EN
#define PMIC_RG_BUCK_VS1_SW_OP_EN_MASK  0x1
#define PMIC_RG_BUCK_VS1_SW_OP_EN_SHIFT 0
#define PMIC_RG_BUCK_VS1_HW0_OP_EN_ADDR MT6358_BUCK_VS1_OP_EN
#define PMIC_RG_BUCK_VS1_HW0_OP_EN_MASK 0x1
#define PMIC_RG_BUCK_VS1_HW0_OP_EN_SHIFT   1
#define PMIC_RG_BUCK_VS1_HW1_OP_EN_ADDR MT6358_BUCK_VS1_OP_EN
#define PMIC_RG_BUCK_VS1_HW1_OP_EN_MASK 0x1
#define PMIC_RG_BUCK_VS1_HW1_OP_EN_SHIFT   2
#define PMIC_RG_BUCK_VS1_HW2_OP_EN_ADDR MT6358_BUCK_VS1_OP_EN
#define PMIC_RG_BUCK_VS1_HW2_OP_EN_MASK 0x1
#define PMIC_RG_BUCK_VS1_HW2_OP_EN_SHIFT   3
#define PMIC_RG_BUCK_VS1_OP_EN_SET_ADDR MT6358_BUCK_VS1_OP_EN_SET
#define PMIC_RG_BUCK_VS1_OP_EN_SET_MASK 0xFFFF
#define PMIC_RG_BUCK_VS1_OP_EN_SET_SHIFT   0
#define PMIC_RG_BUCK_VS1_OP_EN_CLR_ADDR MT6358_BUCK_VS1_OP_EN_CLR
#define PMIC_RG_BUCK_VS1_OP_EN_CLR_MASK 0xFFFF
#define PMIC_RG_BUCK_VS1_OP_EN_CLR_SHIFT   0
#define PMIC_RG_BUCK_VS1_HW0_OP_CFG_ADDR   MT6358_BUCK_VS1_OP_CFG
#define PMIC_RG_BUCK_VS1_HW0_OP_CFG_MASK   0x1
#define PMIC_RG_BUCK_VS1_HW0_OP_CFG_SHIFT   1
#define PMIC_RG_BUCK_VS1_HW1_OP_CFG_ADDR   MT6358_BUCK_VS1_OP_CFG
#define PMIC_RG_BUCK_VS1_HW1_OP_CFG_MASK   0x1
#define PMIC_RG_BUCK_VS1_HW1_OP_CFG_SHIFT   2
#define PMIC_RG_BUCK_VS1_HW2_OP_CFG_ADDR   MT6358_BUCK_VS1_OP_CFG
#define PMIC_RG_BUCK_VS1_HW2_OP_CFG_MASK   0x1
#define PMIC_RG_BUCK_VS1_HW2_OP_CFG_SHIFT   3
#define PMIC_RG_BUCK_VS1_ON_OP_ADDR   MT6358_BUCK_VS1_OP_CFG
#define PMIC_RG_BUCK_VS1_ON_OP_MASK   0x1
#define PMIC_RG_BUCK_VS1_ON_OP_SHIFT  8
#define PMIC_RG_BUCK_VS1_LP_OP_ADDR   MT6358_BUCK_VS1_OP_CFG
#define PMIC_RG_BUCK_VS1_LP_OP_MASK   0x1
#define PMIC_RG_BUCK_VS1_LP_OP_SHIFT  9
#define PMIC_RG_BUCK_VS1_OP_CFG_SET_ADDR   MT6358_BUCK_VS1_OP_CFG_SET
#define PMIC_RG_BUCK_VS1_OP_CFG_SET_MASK   0xFFFF
#define PMIC_RG_BUCK_VS1_OP_CFG_SET_SHIFT   0
#define PMIC_RG_BUCK_VS1_OP_CFG_CLR_ADDR   MT6358_BUCK_VS1_OP_CFG_CLR
#define PMIC_RG_BUCK_VS1_OP_CFG_CLR_MASK   0xFFFF
#define PMIC_RG_BUCK_VS1_OP_CFG_CLR_SHIFT   0
#define PMIC_RG_BUCK_VS1_OC_DEG_EN_ADDR MT6358_BUCK_VS1_OC_CFG
#define PMIC_RG_BUCK_VS1_OC_DEG_EN_MASK 0x1
#define PMIC_RG_BUCK_VS1_OC_DEG_EN_SHIFT   1
#define PMIC_RG_BUCK_VS1_OC_WND_ADDR  MT6358_BUCK_VS1_OC_CFG
#define PMIC_RG_BUCK_VS1_OC_WND_MASK  0x3
#define PMIC_RG_BUCK_VS1_OC_WND_SHIFT 2
#define PMIC_RG_BUCK_VS1_OC_THD_ADDR  MT6358_BUCK_VS1_OC_CFG
#define PMIC_RG_BUCK_VS1_OC_THD_MASK  0x3
#define PMIC_RG_BUCK_VS1_OC_THD_SHIFT 6
#define PMIC_DA_VS1_VOSEL_ADDR  MT6358_BUCK_VS1_DBG0
#define PMIC_DA_VS1_VOSEL_MASK  0x7F
#define PMIC_DA_VS1_VOSEL_SHIFT 0
#define PMIC_DA_VS1_VOSEL_GRAY_ADDR   MT6358_BUCK_VS1_DBG0
#define PMIC_DA_VS1_VOSEL_GRAY_MASK   0x7F
#define PMIC_DA_VS1_VOSEL_GRAY_SHIFT  8
#define PMIC_DA_VS1_EN_ADDR  MT6358_BUCK_VS1_DBG1
#define PMIC_DA_VS1_EN_MASK  0x1
#define PMIC_DA_VS1_EN_SHIFT 0
#define PMIC_DA_VS1_STB_ADDR MT6358_BUCK_VS1_DBG1
#define PMIC_DA_VS1_STB_MASK 0x1
#define PMIC_DA_VS1_STB_SHIFT   1
#define PMIC_DA_VS1_LOOP_SEL_ADDR MT6358_BUCK_VS1_DBG1
#define PMIC_DA_VS1_LOOP_SEL_MASK 0x1
#define PMIC_DA_VS1_LOOP_SEL_SHIFT 2
#define PMIC_DA_VS1_R2R_PDN_ADDR  MT6358_BUCK_VS1_DBG1
#define PMIC_DA_VS1_R2R_PDN_MASK  0x1
#define PMIC_DA_VS1_R2R_PDN_SHIFT 3
#define PMIC_DA_VS1_DVS_EN_ADDR MT6358_BUCK_VS1_DBG1
#define PMIC_DA_VS1_DVS_EN_MASK 0x1
#define PMIC_DA_VS1_DVS_EN_SHIFT  4
#define PMIC_DA_VS1_DVS_DOWN_ADDR MT6358_BUCK_VS1_DBG1
#define PMIC_DA_VS1_DVS_DOWN_MASK 0x1
#define PMIC_DA_VS1_DVS_DOWN_SHIFT 5
#define PMIC_DA_VS1_SSH_ADDR MT6358_BUCK_VS1_DBG1
#define PMIC_DA_VS1_SSH_MASK 0x1
#define PMIC_DA_VS1_SSH_SHIFT   6
#define PMIC_DA_VS1_MINFREQ_DISCHARGE_ADDR  MT6358_BUCK_VS1_DBG1
#define PMIC_DA_VS1_MINFREQ_DISCHARGE_MASK  0x1
#define PMIC_DA_VS1_MINFREQ_DISCHARGE_SHIFT 8
#define PMIC_RG_BUCK_VS1_OC_FLAG_CLR_SEL_ADDR MT6358_BUCK_VS1_DBG2
#define PMIC_RG_BUCK_VS1_OC_FLAG_CLR_SEL_MASK 0x1
#define PMIC_RG_BUCK_VS1_OC_FLAG_CLR_SEL_SHIFT   4
#define PMIC_RG_BUCK_VS1_OSC_SEL_DIS_ADDR   MT6358_BUCK_VS1_DBG2
#define PMIC_RG_BUCK_VS1_OSC_SEL_DIS_MASK   0x1
#define PMIC_RG_BUCK_VS1_OSC_SEL_DIS_SHIFT  5
#define PMIC_RG_BUCK_VS1_CK_SW_MODE_ADDR   MT6358_BUCK_VS1_DBG2
#define PMIC_RG_BUCK_VS1_CK_SW_MODE_MASK   0x1
#define PMIC_RG_BUCK_VS1_CK_SW_MODE_SHIFT   6
#define PMIC_RG_BUCK_VS1_CK_SW_EN_ADDR  MT6358_BUCK_VS1_DBG2
#define PMIC_RG_BUCK_VS1_CK_SW_EN_MASK  0x1
#define PMIC_RG_BUCK_VS1_CK_SW_EN_SHIFT 7
#define PMIC_RG_BUCK_VS1_VOTER_EN_ADDR  MT6358_BUCK_VS1_VOTER
#define PMIC_RG_BUCK_VS1_VOTER_EN_MASK  0xFFF
#define PMIC_RG_BUCK_VS1_VOTER_EN_SHIFT 0
#define PMIC_RG_BUCK_VS1_VOTER_EN_SET_ADDR  MT6358_BUCK_VS1_VOTER_SET
#define PMIC_RG_BUCK_VS1_VOTER_EN_SET_MASK  0xFFF
#define PMIC_RG_BUCK_VS1_VOTER_EN_SET_SHIFT 0
#define PMIC_RG_BUCK_VS1_VOTER_EN_CLR_ADDR  MT6358_BUCK_VS1_VOTER_CLR
#define PMIC_RG_BUCK_VS1_VOTER_EN_CLR_MASK  0xFFF
#define PMIC_RG_BUCK_VS1_VOTER_EN_CLR_SHIFT 0
#define PMIC_RG_BUCK_VS1_VOTER_VOSEL_ADDR   MT6358_BUCK_VS1_VOTER_CFG
#define PMIC_RG_BUCK_VS1_VOTER_VOSEL_MASK   0x7F
#define PMIC_RG_BUCK_VS1_VOTER_VOSEL_SHIFT  0
#define PMIC_BUCK_VS1_ELR_LEN_ADDR MT6358_BUCK_VS1_ELR_NUM
#define PMIC_BUCK_VS1_ELR_LEN_MASK 0xFF
#define PMIC_BUCK_VS1_ELR_LEN_SHIFT   0
#define PMIC_RG_BUCK_VS1_VOSEL_ADDR   MT6358_BUCK_VS1_ELR0
#define PMIC_RG_BUCK_VS1_VOSEL_MASK   0x7F
#define PMIC_RG_BUCK_VS1_VOSEL_SHIFT  0
#define PMIC_BUCK_VS2_ANA_ID_ADDR MT6358_BUCK_VS2_DSN_ID
#define PMIC_BUCK_VS2_ANA_ID_MASK 0xFF
#define PMIC_BUCK_VS2_ANA_ID_SHIFT 0
#define PMIC_BUCK_VS2_DIG_ID_ADDR MT6358_BUCK_VS2_DSN_ID
#define PMIC_BUCK_VS2_DIG_ID_MASK 0xFF
#define PMIC_BUCK_VS2_DIG_ID_SHIFT 8
#define PMIC_BUCK_VS2_ANA_MINOR_REV_ADDR   MT6358_BUCK_VS2_DSN_REV0
#define PMIC_BUCK_VS2_ANA_MINOR_REV_MASK   0xF
#define PMIC_BUCK_VS2_ANA_MINOR_REV_SHIFT   0
#define PMIC_BUCK_VS2_ANA_MAJOR_REV_ADDR   MT6358_BUCK_VS2_DSN_REV0
#define PMIC_BUCK_VS2_ANA_MAJOR_REV_MASK   0xF
#define PMIC_BUCK_VS2_ANA_MAJOR_REV_SHIFT   4
#define PMIC_BUCK_VS2_DIG_MINOR_REV_ADDR   MT6358_BUCK_VS2_DSN_REV0
#define PMIC_BUCK_VS2_DIG_MINOR_REV_MASK   0xF
#define PMIC_BUCK_VS2_DIG_MINOR_REV_SHIFT   8
#define PMIC_BUCK_VS2_DIG_MAJOR_REV_ADDR   MT6358_BUCK_VS2_DSN_REV0
#define PMIC_BUCK_VS2_DIG_MAJOR_REV_MASK   0xF
#define PMIC_BUCK_VS2_DIG_MAJOR_REV_SHIFT   12
#define PMIC_BUCK_VS2_DSN_CBS_ADDR MT6358_BUCK_VS2_DSN_DBI
#define PMIC_BUCK_VS2_DSN_CBS_MASK 0x3
#define PMIC_BUCK_VS2_DSN_CBS_SHIFT   0
#define PMIC_BUCK_VS2_DSN_BIX_ADDR MT6358_BUCK_VS2_DSN_DBI
#define PMIC_BUCK_VS2_DSN_BIX_MASK 0x3
#define PMIC_BUCK_VS2_DSN_BIX_SHIFT   2
#define PMIC_BUCK_VS2_DSN_ESP_ADDR MT6358_BUCK_VS2_DSN_DBI
#define PMIC_BUCK_VS2_DSN_ESP_MASK 0xFF
#define PMIC_BUCK_VS2_DSN_ESP_SHIFT   8
#define PMIC_BUCK_VS2_DSN_FPI_SSHUB_ADDR   MT6358_BUCK_VS2_DSN_DXI
#define PMIC_BUCK_VS2_DSN_FPI_SSHUB_MASK   0x1
#define PMIC_BUCK_VS2_DSN_FPI_SSHUB_SHIFT   0
#define PMIC_BUCK_VS2_DSN_FPI_TRACKING_ADDR MT6358_BUCK_VS2_DSN_DXI
#define PMIC_BUCK_VS2_DSN_FPI_TRACKING_MASK 0x1
#define PMIC_BUCK_VS2_DSN_FPI_TRACKING_SHIFT  1
#define PMIC_BUCK_VS2_DSN_FPI_PREOC_ADDR   MT6358_BUCK_VS2_DSN_DXI
#define PMIC_BUCK_VS2_DSN_FPI_PREOC_MASK   0x1
#define PMIC_BUCK_VS2_DSN_FPI_PREOC_SHIFT   2
#define PMIC_BUCK_VS2_DSN_FPI_VOTER_ADDR   MT6358_BUCK_VS2_DSN_DXI
#define PMIC_BUCK_VS2_DSN_FPI_VOTER_MASK   0x1
#define PMIC_BUCK_VS2_DSN_FPI_VOTER_SHIFT   3
#define PMIC_BUCK_VS2_DSN_FPI_ULTRASONIC_ADDR MT6358_BUCK_VS2_DSN_DXI
#define PMIC_BUCK_VS2_DSN_FPI_ULTRASONIC_MASK 0x1
#define PMIC_BUCK_VS2_DSN_FPI_ULTRASONIC_SHIFT   4
#define PMIC_BUCK_VS2_DSN_FPI_DLC_ADDR  MT6358_BUCK_VS2_DSN_DXI
#define PMIC_BUCK_VS2_DSN_FPI_DLC_MASK  0x1
#define PMIC_BUCK_VS2_DSN_FPI_DLC_SHIFT 5
#define PMIC_BUCK_VS2_DSN_FPI_TRAP_ADDR MT6358_BUCK_VS2_DSN_DXI
#define PMIC_BUCK_VS2_DSN_FPI_TRAP_MASK 0x1
#define PMIC_BUCK_VS2_DSN_FPI_TRAP_SHIFT   6
#define PMIC_RG_BUCK_VS2_EN_ADDR  MT6358_BUCK_VS2_CON0
#define PMIC_RG_BUCK_VS2_EN_MASK  0x1
#define PMIC_RG_BUCK_VS2_EN_SHIFT 0
#define PMIC_RG_BUCK_VS2_LP_ADDR  MT6358_BUCK_VS2_CON0
#define PMIC_RG_BUCK_VS2_LP_MASK  0x1
#define PMIC_RG_BUCK_VS2_LP_SHIFT 1
#define PMIC_RG_BUCK_VS2_VOSEL_SLEEP_ADDR   MT6358_BUCK_VS2_CON1
#define PMIC_RG_BUCK_VS2_VOSEL_SLEEP_MASK   0x7F
#define PMIC_RG_BUCK_VS2_VOSEL_SLEEP_SHIFT  0
#define PMIC_RG_BUCK_VS2_SFCHG_FRATE_ADDR   MT6358_BUCK_VS2_CFG0
#define PMIC_RG_BUCK_VS2_SFCHG_FRATE_MASK   0x7F
#define PMIC_RG_BUCK_VS2_SFCHG_FRATE_SHIFT  0
#define PMIC_RG_BUCK_VS2_SFCHG_FEN_ADDR MT6358_BUCK_VS2_CFG0
#define PMIC_RG_BUCK_VS2_SFCHG_FEN_MASK 0x1
#define PMIC_RG_BUCK_VS2_SFCHG_FEN_SHIFT   7
#define PMIC_RG_BUCK_VS2_SFCHG_RRATE_ADDR   MT6358_BUCK_VS2_CFG0
#define PMIC_RG_BUCK_VS2_SFCHG_RRATE_MASK   0x7F
#define PMIC_RG_BUCK_VS2_SFCHG_RRATE_SHIFT  8
#define PMIC_RG_BUCK_VS2_SFCHG_REN_ADDR MT6358_BUCK_VS2_CFG0
#define PMIC_RG_BUCK_VS2_SFCHG_REN_MASK 0x1
#define PMIC_RG_BUCK_VS2_SFCHG_REN_SHIFT   15
#define PMIC_RG_BUCK_VS2_DVS_EN_TD_ADDR MT6358_BUCK_VS2_CFG1
#define PMIC_RG_BUCK_VS2_DVS_EN_TD_MASK 0x3
#define PMIC_RG_BUCK_VS2_DVS_EN_TD_SHIFT   0
#define PMIC_RG_BUCK_VS2_DVS_EN_CTRL_ADDR   MT6358_BUCK_VS2_CFG1
#define PMIC_RG_BUCK_VS2_DVS_EN_CTRL_MASK   0x3
#define PMIC_RG_BUCK_VS2_DVS_EN_CTRL_SHIFT  4
#define PMIC_RG_BUCK_VS2_DVS_EN_ONCE_ADDR   MT6358_BUCK_VS2_CFG1
#define PMIC_RG_BUCK_VS2_DVS_EN_ONCE_MASK   0x1
#define PMIC_RG_BUCK_VS2_DVS_EN_ONCE_SHIFT  6
#define PMIC_RG_BUCK_VS2_DVS_DOWN_TD_ADDR   MT6358_BUCK_VS2_CFG1
#define PMIC_RG_BUCK_VS2_DVS_DOWN_TD_MASK   0x3
#define PMIC_RG_BUCK_VS2_DVS_DOWN_TD_SHIFT  8
#define PMIC_RG_BUCK_VS2_DVS_DOWN_CTRL_ADDR MT6358_BUCK_VS2_CFG1
#define PMIC_RG_BUCK_VS2_DVS_DOWN_CTRL_MASK 0x3
#define PMIC_RG_BUCK_VS2_DVS_DOWN_CTRL_SHIFT  12
#define PMIC_RG_BUCK_VS2_DVS_DOWN_ONCE_ADDR MT6358_BUCK_VS2_CFG1
#define PMIC_RG_BUCK_VS2_DVS_DOWN_ONCE_MASK 0x1
#define PMIC_RG_BUCK_VS2_DVS_DOWN_ONCE_SHIFT  14
#define PMIC_RG_BUCK_VS2_SW_OP_EN_ADDR  MT6358_BUCK_VS2_OP_EN
#define PMIC_RG_BUCK_VS2_SW_OP_EN_MASK  0x1
#define PMIC_RG_BUCK_VS2_SW_OP_EN_SHIFT 0
#define PMIC_RG_BUCK_VS2_HW0_OP_EN_ADDR MT6358_BUCK_VS2_OP_EN
#define PMIC_RG_BUCK_VS2_HW0_OP_EN_MASK 0x1
#define PMIC_RG_BUCK_VS2_HW0_OP_EN_SHIFT   1
#define PMIC_RG_BUCK_VS2_HW1_OP_EN_ADDR MT6358_BUCK_VS2_OP_EN
#define PMIC_RG_BUCK_VS2_HW1_OP_EN_MASK 0x1
#define PMIC_RG_BUCK_VS2_HW1_OP_EN_SHIFT   2
#define PMIC_RG_BUCK_VS2_HW2_OP_EN_ADDR MT6358_BUCK_VS2_OP_EN
#define PMIC_RG_BUCK_VS2_HW2_OP_EN_MASK 0x1
#define PMIC_RG_BUCK_VS2_HW2_OP_EN_SHIFT   3
#define PMIC_RG_BUCK_VS2_OP_EN_SET_ADDR MT6358_BUCK_VS2_OP_EN_SET
#define PMIC_RG_BUCK_VS2_OP_EN_SET_MASK 0xFFFF
#define PMIC_RG_BUCK_VS2_OP_EN_SET_SHIFT   0
#define PMIC_RG_BUCK_VS2_OP_EN_CLR_ADDR MT6358_BUCK_VS2_OP_EN_CLR
#define PMIC_RG_BUCK_VS2_OP_EN_CLR_MASK 0xFFFF
#define PMIC_RG_BUCK_VS2_OP_EN_CLR_SHIFT   0
#define PMIC_RG_BUCK_VS2_HW0_OP_CFG_ADDR   MT6358_BUCK_VS2_OP_CFG
#define PMIC_RG_BUCK_VS2_HW0_OP_CFG_MASK   0x1
#define PMIC_RG_BUCK_VS2_HW0_OP_CFG_SHIFT   1
#define PMIC_RG_BUCK_VS2_HW1_OP_CFG_ADDR   MT6358_BUCK_VS2_OP_CFG
#define PMIC_RG_BUCK_VS2_HW1_OP_CFG_MASK   0x1
#define PMIC_RG_BUCK_VS2_HW1_OP_CFG_SHIFT   2
#define PMIC_RG_BUCK_VS2_HW2_OP_CFG_ADDR   MT6358_BUCK_VS2_OP_CFG
#define PMIC_RG_BUCK_VS2_HW2_OP_CFG_MASK   0x1
#define PMIC_RG_BUCK_VS2_HW2_OP_CFG_SHIFT   3
#define PMIC_RG_BUCK_VS2_ON_OP_ADDR   MT6358_BUCK_VS2_OP_CFG
#define PMIC_RG_BUCK_VS2_ON_OP_MASK   0x1
#define PMIC_RG_BUCK_VS2_ON_OP_SHIFT  8
#define PMIC_RG_BUCK_VS2_LP_OP_ADDR   MT6358_BUCK_VS2_OP_CFG
#define PMIC_RG_BUCK_VS2_LP_OP_MASK   0x1
#define PMIC_RG_BUCK_VS2_LP_OP_SHIFT  9
#define PMIC_RG_BUCK_VS2_OP_CFG_SET_ADDR   MT6358_BUCK_VS2_OP_CFG_SET
#define PMIC_RG_BUCK_VS2_OP_CFG_SET_MASK   0xFFFF
#define PMIC_RG_BUCK_VS2_OP_CFG_SET_SHIFT   0
#define PMIC_RG_BUCK_VS2_OP_CFG_CLR_ADDR   MT6358_BUCK_VS2_OP_CFG_CLR
#define PMIC_RG_BUCK_VS2_OP_CFG_CLR_MASK   0xFFFF
#define PMIC_RG_BUCK_VS2_OP_CFG_CLR_SHIFT   0
#define PMIC_RG_BUCK_VS2_OC_DEG_EN_ADDR MT6358_BUCK_VS2_OC_CFG
#define PMIC_RG_BUCK_VS2_OC_DEG_EN_MASK 0x1
#define PMIC_RG_BUCK_VS2_OC_DEG_EN_SHIFT   1
#define PMIC_RG_BUCK_VS2_OC_WND_ADDR  MT6358_BUCK_VS2_OC_CFG
#define PMIC_RG_BUCK_VS2_OC_WND_MASK  0x3
#define PMIC_RG_BUCK_VS2_OC_WND_SHIFT 2
#define PMIC_RG_BUCK_VS2_OC_THD_ADDR  MT6358_BUCK_VS2_OC_CFG
#define PMIC_RG_BUCK_VS2_OC_THD_MASK  0x3
#define PMIC_RG_BUCK_VS2_OC_THD_SHIFT 6
#define PMIC_DA_VS2_VOSEL_ADDR  MT6358_BUCK_VS2_DBG0
#define PMIC_DA_VS2_VOSEL_MASK  0x7F
#define PMIC_DA_VS2_VOSEL_SHIFT 0
#define PMIC_DA_VS2_VOSEL_GRAY_ADDR   MT6358_BUCK_VS2_DBG0
#define PMIC_DA_VS2_VOSEL_GRAY_MASK   0x7F
#define PMIC_DA_VS2_VOSEL_GRAY_SHIFT  8
#define PMIC_DA_VS2_EN_ADDR  MT6358_BUCK_VS2_DBG1
#define PMIC_DA_VS2_EN_MASK  0x1
#define PMIC_DA_VS2_EN_SHIFT 0
#define PMIC_DA_VS2_STB_ADDR MT6358_BUCK_VS2_DBG1
#define PMIC_DA_VS2_STB_MASK 0x1
#define PMIC_DA_VS2_STB_SHIFT   1
#define PMIC_DA_VS2_LOOP_SEL_ADDR MT6358_BUCK_VS2_DBG1
#define PMIC_DA_VS2_LOOP_SEL_MASK 0x1
#define PMIC_DA_VS2_LOOP_SEL_SHIFT 2
#define PMIC_DA_VS2_R2R_PDN_ADDR  MT6358_BUCK_VS2_DBG1
#define PMIC_DA_VS2_R2R_PDN_MASK  0x1
#define PMIC_DA_VS2_R2R_PDN_SHIFT 3
#define PMIC_DA_VS2_DVS_EN_ADDR MT6358_BUCK_VS2_DBG1
#define PMIC_DA_VS2_DVS_EN_MASK 0x1
#define PMIC_DA_VS2_DVS_EN_SHIFT  4
#define PMIC_DA_VS2_DVS_DOWN_ADDR MT6358_BUCK_VS2_DBG1
#define PMIC_DA_VS2_DVS_DOWN_MASK 0x1
#define PMIC_DA_VS2_DVS_DOWN_SHIFT 5
#define PMIC_DA_VS2_SSH_ADDR MT6358_BUCK_VS2_DBG1
#define PMIC_DA_VS2_SSH_MASK 0x1
#define PMIC_DA_VS2_SSH_SHIFT   6
#define PMIC_DA_VS2_MINFREQ_DISCHARGE_ADDR  MT6358_BUCK_VS2_DBG1
#define PMIC_DA_VS2_MINFREQ_DISCHARGE_MASK  0x1
#define PMIC_DA_VS2_MINFREQ_DISCHARGE_SHIFT 8
#define PMIC_RG_BUCK_VS2_OC_FLAG_CLR_SEL_ADDR MT6358_BUCK_VS2_DBG2
#define PMIC_RG_BUCK_VS2_OC_FLAG_CLR_SEL_MASK 0x1
#define PMIC_RG_BUCK_VS2_OC_FLAG_CLR_SEL_SHIFT   4
#define PMIC_RG_BUCK_VS2_OSC_SEL_DIS_ADDR   MT6358_BUCK_VS2_DBG2
#define PMIC_RG_BUCK_VS2_OSC_SEL_DIS_MASK   0x1
#define PMIC_RG_BUCK_VS2_OSC_SEL_DIS_SHIFT  5
#define PMIC_RG_BUCK_VS2_CK_SW_MODE_ADDR   MT6358_BUCK_VS2_DBG2
#define PMIC_RG_BUCK_VS2_CK_SW_MODE_MASK   0x1
#define PMIC_RG_BUCK_VS2_CK_SW_MODE_SHIFT   6
#define PMIC_RG_BUCK_VS2_CK_SW_EN_ADDR  MT6358_BUCK_VS2_DBG2
#define PMIC_RG_BUCK_VS2_CK_SW_EN_MASK  0x1
#define PMIC_RG_BUCK_VS2_CK_SW_EN_SHIFT 7
#define PMIC_RG_BUCK_VS2_VOTER_EN_ADDR  MT6358_BUCK_VS2_VOTER
#define PMIC_RG_BUCK_VS2_VOTER_EN_MASK  0xFFF
#define PMIC_RG_BUCK_VS2_VOTER_EN_SHIFT 0
#define PMIC_RG_BUCK_VS2_VOTER_EN_SET_ADDR  MT6358_BUCK_VS2_VOTER_SET
#define PMIC_RG_BUCK_VS2_VOTER_EN_SET_MASK  0xFFF
#define PMIC_RG_BUCK_VS2_VOTER_EN_SET_SHIFT 0
#define PMIC_RG_BUCK_VS2_VOTER_EN_CLR_ADDR  MT6358_BUCK_VS2_VOTER_CLR
#define PMIC_RG_BUCK_VS2_VOTER_EN_CLR_MASK  0xFFF
#define PMIC_RG_BUCK_VS2_VOTER_EN_CLR_SHIFT 0
#define PMIC_RG_BUCK_VS2_VOTER_VOSEL_ADDR   MT6358_BUCK_VS2_VOTER_CFG
#define PMIC_RG_BUCK_VS2_VOTER_VOSEL_MASK   0x7F
#define PMIC_RG_BUCK_VS2_VOTER_VOSEL_SHIFT  0
#define PMIC_BUCK_VS2_ELR_LEN_ADDR MT6358_BUCK_VS2_ELR_NUM
#define PMIC_BUCK_VS2_ELR_LEN_MASK 0xFF
#define PMIC_BUCK_VS2_ELR_LEN_SHIFT   0
#define PMIC_RG_BUCK_VS2_VOSEL_ADDR   MT6358_BUCK_VS2_ELR0
#define PMIC_RG_BUCK_VS2_VOSEL_MASK   0x7F
#define PMIC_RG_BUCK_VS2_VOSEL_SHIFT  0
#define PMIC_BUCK_VPA_ANA_ID_ADDR MT6358_BUCK_VPA_DSN_ID
#define PMIC_BUCK_VPA_ANA_ID_MASK 0xFF
#define PMIC_BUCK_VPA_ANA_ID_SHIFT 0
#define PMIC_BUCK_VPA_DIG_ID_ADDR MT6358_BUCK_VPA_DSN_ID
#define PMIC_BUCK_VPA_DIG_ID_MASK 0xFF
#define PMIC_BUCK_VPA_DIG_ID_SHIFT 8
#define PMIC_BUCK_VPA_ANA_MINOR_REV_ADDR   MT6358_BUCK_VPA_DSN_REV0
#define PMIC_BUCK_VPA_ANA_MINOR_REV_MASK   0xF
#define PMIC_BUCK_VPA_ANA_MINOR_REV_SHIFT   0
#define PMIC_BUCK_VPA_ANA_MAJOR_REV_ADDR   MT6358_BUCK_VPA_DSN_REV0
#define PMIC_BUCK_VPA_ANA_MAJOR_REV_MASK   0xF
#define PMIC_BUCK_VPA_ANA_MAJOR_REV_SHIFT   4
#define PMIC_BUCK_VPA_DIG_MINOR_REV_ADDR   MT6358_BUCK_VPA_DSN_REV0
#define PMIC_BUCK_VPA_DIG_MINOR_REV_MASK   0xF
#define PMIC_BUCK_VPA_DIG_MINOR_REV_SHIFT   8
#define PMIC_BUCK_VPA_DIG_MAJOR_REV_ADDR   MT6358_BUCK_VPA_DSN_REV0
#define PMIC_BUCK_VPA_DIG_MAJOR_REV_MASK   0xF
#define PMIC_BUCK_VPA_DIG_MAJOR_REV_SHIFT   12
#define PMIC_BUCK_VPA_DSN_CBS_ADDR MT6358_BUCK_VPA_DSN_DBI
#define PMIC_BUCK_VPA_DSN_CBS_MASK 0x3
#define PMIC_BUCK_VPA_DSN_CBS_SHIFT   0
#define PMIC_BUCK_VPA_DSN_BIX_ADDR MT6358_BUCK_VPA_DSN_DBI
#define PMIC_BUCK_VPA_DSN_BIX_MASK 0x3
#define PMIC_BUCK_VPA_DSN_BIX_SHIFT   2
#define PMIC_BUCK_VPA_DSN_ESP_ADDR MT6358_BUCK_VPA_DSN_DBI
#define PMIC_BUCK_VPA_DSN_ESP_MASK 0xFF
#define PMIC_BUCK_VPA_DSN_ESP_SHIFT   8
#define PMIC_BUCK_VPA_DSN_FPI_SSHUB_ADDR   MT6358_BUCK_VPA_DSN_DXI
#define PMIC_BUCK_VPA_DSN_FPI_SSHUB_MASK   0x1
#define PMIC_BUCK_VPA_DSN_FPI_SSHUB_SHIFT   0
#define PMIC_BUCK_VPA_DSN_FPI_TRACKING_ADDR MT6358_BUCK_VPA_DSN_DXI
#define PMIC_BUCK_VPA_DSN_FPI_TRACKING_MASK 0x1
#define PMIC_BUCK_VPA_DSN_FPI_TRACKING_SHIFT  1
#define PMIC_BUCK_VPA_DSN_FPI_PREOC_ADDR   MT6358_BUCK_VPA_DSN_DXI
#define PMIC_BUCK_VPA_DSN_FPI_PREOC_MASK   0x1
#define PMIC_BUCK_VPA_DSN_FPI_PREOC_SHIFT   2
#define PMIC_BUCK_VPA_DSN_FPI_VOTER_ADDR   MT6358_BUCK_VPA_DSN_DXI
#define PMIC_BUCK_VPA_DSN_FPI_VOTER_MASK   0x1
#define PMIC_BUCK_VPA_DSN_FPI_VOTER_SHIFT   3
#define PMIC_BUCK_VPA_DSN_FPI_ULTRASONIC_ADDR MT6358_BUCK_VPA_DSN_DXI
#define PMIC_BUCK_VPA_DSN_FPI_ULTRASONIC_MASK 0x1
#define PMIC_BUCK_VPA_DSN_FPI_ULTRASONIC_SHIFT   4
#define PMIC_BUCK_VPA_DSN_FPI_DLC_ADDR  MT6358_BUCK_VPA_DSN_DXI
#define PMIC_BUCK_VPA_DSN_FPI_DLC_MASK  0x1
#define PMIC_BUCK_VPA_DSN_FPI_DLC_SHIFT 5
#define PMIC_BUCK_VPA_DSN_FPI_TRAP_ADDR MT6358_BUCK_VPA_DSN_DXI
#define PMIC_BUCK_VPA_DSN_FPI_TRAP_MASK 0x1
#define PMIC_BUCK_VPA_DSN_FPI_TRAP_SHIFT   6
#define PMIC_RG_BUCK_VPA_EN_ADDR  MT6358_BUCK_VPA_CON0
#define PMIC_RG_BUCK_VPA_EN_MASK  0x1
#define PMIC_RG_BUCK_VPA_EN_SHIFT 0
#define PMIC_RG_BUCK_VPA_VOSEL_ADDR   MT6358_BUCK_VPA_CON1
#define PMIC_RG_BUCK_VPA_VOSEL_MASK   0x3F
#define PMIC_RG_BUCK_VPA_VOSEL_SHIFT  0
#define PMIC_RG_BUCK_VPA_SFCHG_FRATE_ADDR   MT6358_BUCK_VPA_CFG0
#define PMIC_RG_BUCK_VPA_SFCHG_FRATE_MASK   0x7F
#define PMIC_RG_BUCK_VPA_SFCHG_FRATE_SHIFT  0
#define PMIC_RG_BUCK_VPA_SFCHG_FEN_ADDR MT6358_BUCK_VPA_CFG0
#define PMIC_RG_BUCK_VPA_SFCHG_FEN_MASK 0x1
#define PMIC_RG_BUCK_VPA_SFCHG_FEN_SHIFT   7
#define PMIC_RG_BUCK_VPA_SFCHG_RRATE_ADDR   MT6358_BUCK_VPA_CFG0
#define PMIC_RG_BUCK_VPA_SFCHG_RRATE_MASK   0x7F
#define PMIC_RG_BUCK_VPA_SFCHG_RRATE_SHIFT  8
#define PMIC_RG_BUCK_VPA_SFCHG_REN_ADDR MT6358_BUCK_VPA_CFG0
#define PMIC_RG_BUCK_VPA_SFCHG_REN_MASK 0x1
#define PMIC_RG_BUCK_VPA_SFCHG_REN_SHIFT   15
#define PMIC_RG_BUCK_VPA_DVS_TRANST_TD_ADDR MT6358_BUCK_VPA_CFG1
#define PMIC_RG_BUCK_VPA_DVS_TRANST_TD_MASK 0x3
#define PMIC_RG_BUCK_VPA_DVS_TRANST_TD_SHIFT  0
#define PMIC_RG_BUCK_VPA_DVS_TRANST_CTRL_ADDR MT6358_BUCK_VPA_CFG1
#define PMIC_RG_BUCK_VPA_DVS_TRANST_CTRL_MASK 0x3
#define PMIC_RG_BUCK_VPA_DVS_TRANST_CTRL_SHIFT   4
#define PMIC_RG_BUCK_VPA_DVS_TRANST_ONCE_ADDR MT6358_BUCK_VPA_CFG1
#define PMIC_RG_BUCK_VPA_DVS_TRANST_ONCE_MASK 0x1
#define PMIC_RG_BUCK_VPA_DVS_TRANST_ONCE_SHIFT   6
#define PMIC_RG_BUCK_VPA_DVS_BW_TD_ADDR MT6358_BUCK_VPA_CFG1
#define PMIC_RG_BUCK_VPA_DVS_BW_TD_MASK 0x3
#define PMIC_RG_BUCK_VPA_DVS_BW_TD_SHIFT   8
#define PMIC_RG_BUCK_VPA_DVS_BW_CTRL_ADDR   MT6358_BUCK_VPA_CFG1
#define PMIC_RG_BUCK_VPA_DVS_BW_CTRL_MASK   0x3
#define PMIC_RG_BUCK_VPA_DVS_BW_CTRL_SHIFT  12
#define PMIC_RG_BUCK_VPA_DVS_BW_ONCE_ADDR   MT6358_BUCK_VPA_CFG1
#define PMIC_RG_BUCK_VPA_DVS_BW_ONCE_MASK   0x1
#define PMIC_RG_BUCK_VPA_DVS_BW_ONCE_SHIFT  14
#define PMIC_RG_BUCK_VPA_OC_DEG_EN_ADDR MT6358_BUCK_VPA_OC_CFG
#define PMIC_RG_BUCK_VPA_OC_DEG_EN_MASK 0x1
#define PMIC_RG_BUCK_VPA_OC_DEG_EN_SHIFT   1
#define PMIC_RG_BUCK_VPA_OC_WND_ADDR  MT6358_BUCK_VPA_OC_CFG
#define PMIC_RG_BUCK_VPA_OC_WND_MASK  0x3
#define PMIC_RG_BUCK_VPA_OC_WND_SHIFT 2
#define PMIC_RG_BUCK_VPA_OC_THD_ADDR  MT6358_BUCK_VPA_OC_CFG
#define PMIC_RG_BUCK_VPA_OC_THD_MASK  0x3
#define PMIC_RG_BUCK_VPA_OC_THD_SHIFT 6
#define PMIC_DA_VPA_VOSEL_ADDR  MT6358_BUCK_VPA_DBG0
#define PMIC_DA_VPA_VOSEL_MASK  0x3F
#define PMIC_DA_VPA_VOSEL_SHIFT 0
#define PMIC_DA_VPA_VOSEL_GRAY_ADDR   MT6358_BUCK_VPA_DBG0
#define PMIC_DA_VPA_VOSEL_GRAY_MASK   0x3F
#define PMIC_DA_VPA_VOSEL_GRAY_SHIFT  8
#define PMIC_DA_VPA_EN_ADDR  MT6358_BUCK_VPA_DBG1
#define PMIC_DA_VPA_EN_MASK  0x1
#define PMIC_DA_VPA_EN_SHIFT 0
#define PMIC_DA_VPA_STB_ADDR MT6358_BUCK_VPA_DBG1
#define PMIC_DA_VPA_STB_MASK 0x1
#define PMIC_DA_VPA_STB_SHIFT   1
#define PMIC_DA_VPA_DVS_TRANST_ADDR   MT6358_BUCK_VPA_DBG1
#define PMIC_DA_VPA_DVS_TRANST_MASK   0x1
#define PMIC_DA_VPA_DVS_TRANST_SHIFT  5
#define PMIC_DA_VPA_DVS_BW_ADDR MT6358_BUCK_VPA_DBG1
#define PMIC_DA_VPA_DVS_BW_MASK 0x1
#define PMIC_DA_VPA_DVS_BW_SHIFT  6
#define PMIC_RG_BUCK_VPA_OC_FLAG_CLR_SEL_ADDR MT6358_BUCK_VPA_DBG2
#define PMIC_RG_BUCK_VPA_OC_FLAG_CLR_SEL_MASK 0x1
#define PMIC_RG_BUCK_VPA_OC_FLAG_CLR_SEL_SHIFT   4
#define PMIC_RG_BUCK_VPA_OSC_SEL_DIS_ADDR   MT6358_BUCK_VPA_DBG2
#define PMIC_RG_BUCK_VPA_OSC_SEL_DIS_MASK   0x1
#define PMIC_RG_BUCK_VPA_OSC_SEL_DIS_SHIFT  5
#define PMIC_RG_BUCK_VPA_CK_SW_MODE_ADDR   MT6358_BUCK_VPA_DBG2
#define PMIC_RG_BUCK_VPA_CK_SW_MODE_MASK   0x1
#define PMIC_RG_BUCK_VPA_CK_SW_MODE_SHIFT   6
#define PMIC_RG_BUCK_VPA_CK_SW_EN_ADDR  MT6358_BUCK_VPA_DBG2
#define PMIC_RG_BUCK_VPA_CK_SW_EN_MASK  0x1
#define PMIC_RG_BUCK_VPA_CK_SW_EN_SHIFT 7
#define PMIC_RG_BUCK_VPA_VOSEL_DLC011_ADDR  MT6358_BUCK_VPA_DLC_CON0
#define PMIC_RG_BUCK_VPA_VOSEL_DLC011_MASK  0x3F
#define PMIC_RG_BUCK_VPA_VOSEL_DLC011_SHIFT 0
#define PMIC_RG_BUCK_VPA_VOSEL_DLC111_ADDR  MT6358_BUCK_VPA_DLC_CON0
#define PMIC_RG_BUCK_VPA_VOSEL_DLC111_MASK  0x3F
#define PMIC_RG_BUCK_VPA_VOSEL_DLC111_SHIFT 8
#define PMIC_RG_BUCK_VPA_VOSEL_DLC001_ADDR  MT6358_BUCK_VPA_DLC_CON1
#define PMIC_RG_BUCK_VPA_VOSEL_DLC001_MASK  0x3F
#define PMIC_RG_BUCK_VPA_VOSEL_DLC001_SHIFT 8
#define PMIC_RG_BUCK_VPA_DLC_MAP_EN_ADDR   MT6358_BUCK_VPA_DLC_CON2
#define PMIC_RG_BUCK_VPA_DLC_MAP_EN_MASK   0x1
#define PMIC_RG_BUCK_VPA_DLC_MAP_EN_SHIFT   0
#define PMIC_RG_BUCK_VPA_DLC_ADDR MT6358_BUCK_VPA_DLC_CON2
#define PMIC_RG_BUCK_VPA_DLC_MASK 0x7
#define PMIC_RG_BUCK_VPA_DLC_SHIFT 8
#define PMIC_DA_VPA_DLC_ADDR MT6358_BUCK_VPA_DLC_CON2
#define PMIC_DA_VPA_DLC_MASK 0x7
#define PMIC_DA_VPA_DLC_SHIFT   12
#define PMIC_RG_BUCK_VPA_MSFG_EN_ADDR MT6358_BUCK_VPA_MSFG_CON0
#define PMIC_RG_BUCK_VPA_MSFG_EN_MASK 0x1
#define PMIC_RG_BUCK_VPA_MSFG_EN_SHIFT  0
#define PMIC_RG_BUCK_VPA_MSFG_RDELTA2GO_ADDR  MT6358_BUCK_VPA_MSFG_CON1
#define PMIC_RG_BUCK_VPA_MSFG_RDELTA2GO_MASK  0x3F
#define PMIC_RG_BUCK_VPA_MSFG_RDELTA2GO_SHIFT 0
#define PMIC_RG_BUCK_VPA_MSFG_FDELTA2GO_ADDR  MT6358_BUCK_VPA_MSFG_CON1
#define PMIC_RG_BUCK_VPA_MSFG_FDELTA2GO_MASK  0x3F
#define PMIC_RG_BUCK_VPA_MSFG_FDELTA2GO_SHIFT 8
#define PMIC_RG_BUCK_VPA_MSFG_RRATE0_ADDR   MT6358_BUCK_VPA_MSFG_RRATE0
#define PMIC_RG_BUCK_VPA_MSFG_RRATE0_MASK   0x3F
#define PMIC_RG_BUCK_VPA_MSFG_RRATE0_SHIFT  0
#define PMIC_RG_BUCK_VPA_MSFG_RRATE1_ADDR   MT6358_BUCK_VPA_MSFG_RRATE0
#define PMIC_RG_BUCK_VPA_MSFG_RRATE1_MASK   0x3F
#define PMIC_RG_BUCK_VPA_MSFG_RRATE1_SHIFT  8
#define PMIC_RG_BUCK_VPA_MSFG_RRATE2_ADDR   MT6358_BUCK_VPA_MSFG_RRATE1
#define PMIC_RG_BUCK_VPA_MSFG_RRATE2_MASK   0x3F
#define PMIC_RG_BUCK_VPA_MSFG_RRATE2_SHIFT  0
#define PMIC_RG_BUCK_VPA_MSFG_RRATE3_ADDR   MT6358_BUCK_VPA_MSFG_RRATE1
#define PMIC_RG_BUCK_VPA_MSFG_RRATE3_MASK   0x3F
#define PMIC_RG_BUCK_VPA_MSFG_RRATE3_SHIFT  8
#define PMIC_RG_BUCK_VPA_MSFG_RRATE4_ADDR   MT6358_BUCK_VPA_MSFG_RRATE2
#define PMIC_RG_BUCK_VPA_MSFG_RRATE4_MASK   0x3F
#define PMIC_RG_BUCK_VPA_MSFG_RRATE4_SHIFT  0
#define PMIC_RG_BUCK_VPA_MSFG_RRATE5_ADDR   MT6358_BUCK_VPA_MSFG_RRATE2
#define PMIC_RG_BUCK_VPA_MSFG_RRATE5_MASK   0x3F
#define PMIC_RG_BUCK_VPA_MSFG_RRATE5_SHIFT  8
#define PMIC_RG_BUCK_VPA_MSFG_RTHD0_ADDR   MT6358_BUCK_VPA_MSFG_RTHD0
#define PMIC_RG_BUCK_VPA_MSFG_RTHD0_MASK   0x3F
#define PMIC_RG_BUCK_VPA_MSFG_RTHD0_SHIFT   0
#define PMIC_RG_BUCK_VPA_MSFG_RTHD1_ADDR   MT6358_BUCK_VPA_MSFG_RTHD0
#define PMIC_RG_BUCK_VPA_MSFG_RTHD1_MASK   0x3F
#define PMIC_RG_BUCK_VPA_MSFG_RTHD1_SHIFT   8
#define PMIC_RG_BUCK_VPA_MSFG_RTHD2_ADDR   MT6358_BUCK_VPA_MSFG_RTHD1
#define PMIC_RG_BUCK_VPA_MSFG_RTHD2_MASK   0x3F
#define PMIC_RG_BUCK_VPA_MSFG_RTHD2_SHIFT   0
#define PMIC_RG_BUCK_VPA_MSFG_RTHD3_ADDR   MT6358_BUCK_VPA_MSFG_RTHD1
#define PMIC_RG_BUCK_VPA_MSFG_RTHD3_MASK   0x3F
#define PMIC_RG_BUCK_VPA_MSFG_RTHD3_SHIFT   8
#define PMIC_RG_BUCK_VPA_MSFG_RTHD4_ADDR   MT6358_BUCK_VPA_MSFG_RTHD2
#define PMIC_RG_BUCK_VPA_MSFG_RTHD4_MASK   0x3F
#define PMIC_RG_BUCK_VPA_MSFG_RTHD4_SHIFT   0
#define PMIC_RG_BUCK_VPA_MSFG_FRATE0_ADDR   MT6358_BUCK_VPA_MSFG_FRATE0
#define PMIC_RG_BUCK_VPA_MSFG_FRATE0_MASK   0x3F
#define PMIC_RG_BUCK_VPA_MSFG_FRATE0_SHIFT  0
#define PMIC_RG_BUCK_VPA_MSFG_FRATE1_ADDR   MT6358_BUCK_VPA_MSFG_FRATE0
#define PMIC_RG_BUCK_VPA_MSFG_FRATE1_MASK   0x3F
#define PMIC_RG_BUCK_VPA_MSFG_FRATE1_SHIFT  8
#define PMIC_RG_BUCK_VPA_MSFG_FRATE2_ADDR   MT6358_BUCK_VPA_MSFG_FRATE1
#define PMIC_RG_BUCK_VPA_MSFG_FRATE2_MASK   0x3F
#define PMIC_RG_BUCK_VPA_MSFG_FRATE2_SHIFT  0
#define PMIC_RG_BUCK_VPA_MSFG_FRATE3_ADDR   MT6358_BUCK_VPA_MSFG_FRATE1
#define PMIC_RG_BUCK_VPA_MSFG_FRATE3_MASK   0x3F
#define PMIC_RG_BUCK_VPA_MSFG_FRATE3_SHIFT  8
#define PMIC_RG_BUCK_VPA_MSFG_FRATE4_ADDR   MT6358_BUCK_VPA_MSFG_FRATE2
#define PMIC_RG_BUCK_VPA_MSFG_FRATE4_MASK   0x3F
#define PMIC_RG_BUCK_VPA_MSFG_FRATE4_SHIFT  0
#define PMIC_RG_BUCK_VPA_MSFG_FRATE5_ADDR   MT6358_BUCK_VPA_MSFG_FRATE2
#define PMIC_RG_BUCK_VPA_MSFG_FRATE5_MASK   0x3F
#define PMIC_RG_BUCK_VPA_MSFG_FRATE5_SHIFT  8
#define PMIC_RG_BUCK_VPA_MSFG_FTHD0_ADDR   MT6358_BUCK_VPA_MSFG_FTHD0
#define PMIC_RG_BUCK_VPA_MSFG_FTHD0_MASK   0x3F
#define PMIC_RG_BUCK_VPA_MSFG_FTHD0_SHIFT   0
#define PMIC_RG_BUCK_VPA_MSFG_FTHD1_ADDR   MT6358_BUCK_VPA_MSFG_FTHD0
#define PMIC_RG_BUCK_VPA_MSFG_FTHD1_MASK   0x3F
#define PMIC_RG_BUCK_VPA_MSFG_FTHD1_SHIFT   8
#define PMIC_RG_BUCK_VPA_MSFG_FTHD2_ADDR   MT6358_BUCK_VPA_MSFG_FTHD1
#define PMIC_RG_BUCK_VPA_MSFG_FTHD2_MASK   0x3F
#define PMIC_RG_BUCK_VPA_MSFG_FTHD2_SHIFT   0
#define PMIC_RG_BUCK_VPA_MSFG_FTHD3_ADDR   MT6358_BUCK_VPA_MSFG_FTHD1
#define PMIC_RG_BUCK_VPA_MSFG_FTHD3_MASK   0x3F
#define PMIC_RG_BUCK_VPA_MSFG_FTHD3_SHIFT   8
#define PMIC_RG_BUCK_VPA_MSFG_FTHD4_ADDR   MT6358_BUCK_VPA_MSFG_FTHD2
#define PMIC_RG_BUCK_VPA_MSFG_FTHD4_MASK   0x3F
#define PMIC_RG_BUCK_VPA_MSFG_FTHD4_SHIFT   0
#define PMIC_BUCK_ANA0_ANA_ID_ADDR MT6358_BUCK_ANA0_DSN_ID
#define PMIC_BUCK_ANA0_ANA_ID_MASK 0xFF
#define PMIC_BUCK_ANA0_ANA_ID_SHIFT   0
#define PMIC_BUCK_ANA0_DIG_ID_ADDR MT6358_BUCK_ANA0_DSN_ID
#define PMIC_BUCK_ANA0_DIG_ID_MASK 0xFF
#define PMIC_BUCK_ANA0_DIG_ID_SHIFT   8
#define PMIC_BUCK_ANA0_ANA_MINOR_REV_ADDR   MT6358_BUCK_ANA0_DSN_REV0
#define PMIC_BUCK_ANA0_ANA_MINOR_REV_MASK   0xF
#define PMIC_BUCK_ANA0_ANA_MINOR_REV_SHIFT  0
#define PMIC_BUCK_ANA0_ANA_MAJOR_REV_ADDR   MT6358_BUCK_ANA0_DSN_REV0
#define PMIC_BUCK_ANA0_ANA_MAJOR_REV_MASK   0xF
#define PMIC_BUCK_ANA0_ANA_MAJOR_REV_SHIFT  4
#define PMIC_BUCK_ANA0_DIG_MINOR_REV_ADDR   MT6358_BUCK_ANA0_DSN_REV0
#define PMIC_BUCK_ANA0_DIG_MINOR_REV_MASK   0xF
#define PMIC_BUCK_ANA0_DIG_MINOR_REV_SHIFT  8
#define PMIC_BUCK_ANA0_DIG_MAJOR_REV_ADDR   MT6358_BUCK_ANA0_DSN_REV0
#define PMIC_BUCK_ANA0_DIG_MAJOR_REV_MASK   0xF
#define PMIC_BUCK_ANA0_DIG_MAJOR_REV_SHIFT  12
#define PMIC_BUCK_ANA0_DSN_CBS_ADDR   MT6358_BUCK_ANA0_DSN_DBI
#define PMIC_BUCK_ANA0_DSN_CBS_MASK   0x3
#define PMIC_BUCK_ANA0_DSN_CBS_SHIFT  0
#define PMIC_BUCK_ANA0_DSN_BIX_ADDR   MT6358_BUCK_ANA0_DSN_DBI
#define PMIC_BUCK_ANA0_DSN_BIX_MASK   0x3
#define PMIC_BUCK_ANA0_DSN_BIX_SHIFT  2
#define PMIC_BUCK_ANA0_DSN_ESP_ADDR   MT6358_BUCK_ANA0_DSN_DBI
#define PMIC_BUCK_ANA0_DSN_ESP_MASK   0xFF
#define PMIC_BUCK_ANA0_DSN_ESP_SHIFT  8
#define PMIC_BUCK_ANA0_DSN_FPI_ADDR   MT6358_BUCK_ANA0_DSN_FPI
#define PMIC_BUCK_ANA0_DSN_FPI_MASK   0xFF
#define PMIC_BUCK_ANA0_DSN_FPI_SHIFT  0
#define PMIC_RG_SMPS_TESTMODE_B_ADDR  MT6358_SMPS_ANA_CON0
#define PMIC_RG_SMPS_TESTMODE_B_MASK  0xFFF
#define PMIC_RG_SMPS_TESTMODE_B_SHIFT 0
#define PMIC_RG_VPA_BURSTH_ADDR MT6358_SMPS_ANA_CON0
#define PMIC_RG_VPA_BURSTH_MASK 0x3
#define PMIC_RG_VPA_BURSTH_SHIFT  12
#define PMIC_RG_VPA_BURSTL_ADDR MT6358_SMPS_ANA_CON0
#define PMIC_RG_VPA_BURSTL_MASK 0x3
#define PMIC_RG_VPA_BURSTL_SHIFT  14
#define PMIC_RG_SMPS_IVGD_DET_ADDR MT6358_SMPS_ANA_CON1
#define PMIC_RG_SMPS_IVGD_DET_MASK 0x1
#define PMIC_RG_SMPS_IVGD_DET_SHIFT   0
#define PMIC_RG_AUTOK_RST_ADDR  MT6358_SMPS_ANA_CON1
#define PMIC_RG_AUTOK_RST_MASK  0x1
#define PMIC_RG_AUTOK_RST_SHIFT 1
#define PMIC_RG_VMODEM_SLEEP_VOLTAGE_ADDR   MT6358_SMPS_ANA_CON1
#define PMIC_RG_VMODEM_SLEEP_VOLTAGE_MASK   0x7
#define PMIC_RG_VMODEM_SLEEP_VOLTAGE_SHIFT  2
#define PMIC_RG_VPROC11_FPWM_ADDR MT6358_VPROC_ANA_CON0
#define PMIC_RG_VPROC11_FPWM_MASK 0x1
#define PMIC_RG_VPROC11_FPWM_SHIFT 1
#define PMIC_RG_VPROC12_FPWM_ADDR MT6358_VPROC_ANA_CON0
#define PMIC_RG_VPROC12_FPWM_MASK 0x1
#define PMIC_RG_VPROC12_FPWM_SHIFT 2
#define PMIC_RG_VPROC11_NDIS_EN_ADDR  MT6358_VPROC_ANA_CON0
#define PMIC_RG_VPROC11_NDIS_EN_MASK  0x1
#define PMIC_RG_VPROC11_NDIS_EN_SHIFT 3
#define PMIC_RG_VPROC12_NDIS_EN_ADDR  MT6358_VPROC_ANA_CON0
#define PMIC_RG_VPROC12_NDIS_EN_MASK  0x1
#define PMIC_RG_VPROC12_NDIS_EN_SHIFT 4
#define PMIC_RG_VPROC11_FCOT_ADDR MT6358_VPROC_ANA_CON0
#define PMIC_RG_VPROC11_FCOT_MASK 0x1
#define PMIC_RG_VPROC11_FCOT_SHIFT 5
#define PMIC_RG_VPROC12_FCOT_ADDR MT6358_VPROC_ANA_CON0
#define PMIC_RG_VPROC12_FCOT_MASK 0x1
#define PMIC_RG_VPROC12_FCOT_SHIFT 6
#define PMIC_RG_VPROC11VPROC12_TMDL_ADDR   MT6358_VPROC_ANA_CON0
#define PMIC_RG_VPROC11VPROC12_TMDL_MASK   0x1
#define PMIC_RG_VPROC11VPROC12_TMDL_SHIFT   7
#define PMIC_RG_VPROC11_TBDIS_ADDR MT6358_VPROC_ANA_CON0
#define PMIC_RG_VPROC11_TBDIS_MASK 0x1
#define PMIC_RG_VPROC11_TBDIS_SHIFT   8
#define PMIC_RG_VPROC12_TBDIS_ADDR MT6358_VPROC_ANA_CON0
#define PMIC_RG_VPROC12_TBDIS_MASK 0x1
#define PMIC_RG_VPROC12_TBDIS_SHIFT   9
#define PMIC_RG_VPROC11_VDIFFOFF_ADDR MT6358_VPROC_ANA_CON0
#define PMIC_RG_VPROC11_VDIFFOFF_MASK 0x1
#define PMIC_RG_VPROC11_VDIFFOFF_SHIFT  10
#define PMIC_RG_VPROC12_VDIFFOFF_ADDR MT6358_VPROC_ANA_CON0
#define PMIC_RG_VPROC12_VDIFFOFF_MASK 0x1
#define PMIC_RG_VPROC12_VDIFFOFF_SHIFT  11
#define PMIC_RG_VPROC11_RCOMP0_ADDR   MT6358_VPROC_ANA_CON1
#define PMIC_RG_VPROC11_RCOMP0_MASK   0xF
#define PMIC_RG_VPROC11_RCOMP0_SHIFT  0
#define PMIC_RG_VPROC11_RCOMP1_ADDR   MT6358_VPROC_ANA_CON1
#define PMIC_RG_VPROC11_RCOMP1_MASK   0x7
#define PMIC_RG_VPROC11_RCOMP1_SHIFT  4
#define PMIC_RG_VPROC11_CCOMP0_ADDR   MT6358_VPROC_ANA_CON1
#define PMIC_RG_VPROC11_CCOMP0_MASK   0x3
#define PMIC_RG_VPROC11_CCOMP0_SHIFT  7
#define PMIC_RG_VPROC11_CCOMP1_ADDR   MT6358_VPROC_ANA_CON1
#define PMIC_RG_VPROC11_CCOMP1_MASK   0x3
#define PMIC_RG_VPROC11_CCOMP1_SHIFT  9
#define PMIC_RG_VPROC11_RAMP_SLP_ADDR MT6358_VPROC_ANA_CON1
#define PMIC_RG_VPROC11_RAMP_SLP_MASK 0x7
#define PMIC_RG_VPROC11_RAMP_SLP_SHIFT  11
#define PMIC_RG_VPROC12_RCOMP0_ADDR   MT6358_VPROC_ANA_CON2
#define PMIC_RG_VPROC12_RCOMP0_MASK   0xF
#define PMIC_RG_VPROC12_RCOMP0_SHIFT  0
#define PMIC_RG_VPROC12_RCOMP1_ADDR   MT6358_VPROC_ANA_CON2
#define PMIC_RG_VPROC12_RCOMP1_MASK   0x7
#define PMIC_RG_VPROC12_RCOMP1_SHIFT  4
#define PMIC_RG_VPROC12_CCOMP0_ADDR   MT6358_VPROC_ANA_CON2
#define PMIC_RG_VPROC12_CCOMP0_MASK   0x3
#define PMIC_RG_VPROC12_CCOMP0_SHIFT  7
#define PMIC_RG_VPROC12_CCOMP1_ADDR   MT6358_VPROC_ANA_CON2
#define PMIC_RG_VPROC12_CCOMP1_MASK   0x3
#define PMIC_RG_VPROC12_CCOMP1_SHIFT  9
#define PMIC_RG_VPROC12_RAMP_SLP_ADDR MT6358_VPROC_ANA_CON2
#define PMIC_RG_VPROC12_RAMP_SLP_MASK 0x7
#define PMIC_RG_VPROC12_RAMP_SLP_SHIFT  11
#define PMIC_RG_VPROC11_RCS_ADDR  MT6358_VPROC_ANA_CON3
#define PMIC_RG_VPROC11_RCS_MASK  0x7
#define PMIC_RG_VPROC11_RCS_SHIFT 0
#define PMIC_RG_VPROC12_RCS_ADDR  MT6358_VPROC_ANA_CON3
#define PMIC_RG_VPROC12_RCS_MASK  0x7
#define PMIC_RG_VPROC12_RCS_SHIFT 3
#define PMIC_RG_VPROC11_RCB_ADDR  MT6358_VPROC_ANA_CON3
#define PMIC_RG_VPROC11_RCB_MASK  0xF
#define PMIC_RG_VPROC11_RCB_SHIFT 6
#define PMIC_RG_VPROC12_RCB_ADDR  MT6358_VPROC_ANA_CON3
#define PMIC_RG_VPROC12_RCB_MASK  0xF
#define PMIC_RG_VPROC12_RCB_SHIFT 10
#define PMIC_RG_VPROC11_TB_WIDTH_ADDR MT6358_VPROC_ANA_CON4
#define PMIC_RG_VPROC11_TB_WIDTH_MASK 0x3
#define PMIC_RG_VPROC11_TB_WIDTH_SHIFT  0
#define PMIC_RG_VPROC12_TB_WIDTH_ADDR MT6358_VPROC_ANA_CON4
#define PMIC_RG_VPROC12_TB_WIDTH_MASK 0x3
#define PMIC_RG_VPROC12_TB_WIDTH_SHIFT  2
#define PMIC_RG_VPROC11_UG_SR_ADDR MT6358_VPROC_ANA_CON4
#define PMIC_RG_VPROC11_UG_SR_MASK 0x3
#define PMIC_RG_VPROC11_UG_SR_SHIFT   4
#define PMIC_RG_VPROC11_LG_SR_ADDR MT6358_VPROC_ANA_CON4
#define PMIC_RG_VPROC11_LG_SR_MASK 0x3
#define PMIC_RG_VPROC11_LG_SR_SHIFT   6
#define PMIC_RG_VPROC12_UG_SR_ADDR MT6358_VPROC_ANA_CON4
#define PMIC_RG_VPROC12_UG_SR_MASK 0x3
#define PMIC_RG_VPROC12_UG_SR_SHIFT   8
#define PMIC_RG_VPROC12_LG_SR_ADDR MT6358_VPROC_ANA_CON4
#define PMIC_RG_VPROC12_LG_SR_MASK 0x3
#define PMIC_RG_VPROC12_LG_SR_SHIFT   10
#define PMIC_RG_VPROC11_PFM_TON_ADDR  MT6358_VPROC_ANA_CON4
#define PMIC_RG_VPROC11_PFM_TON_MASK  0x7
#define PMIC_RG_VPROC11_PFM_TON_SHIFT 12
#define PMIC_RG_VPROC12_PFM_TON_ADDR  MT6358_VPROC_ANA_CON5
#define PMIC_RG_VPROC12_PFM_TON_MASK  0x7
#define PMIC_RG_VPROC12_PFM_TON_SHIFT 0
#define PMIC_RGS_VPROC11_OC_STATUS_ADDR MT6358_VPROC_ANA_CON5
#define PMIC_RGS_VPROC11_OC_STATUS_MASK 0x1
#define PMIC_RGS_VPROC11_OC_STATUS_SHIFT   3
#define PMIC_RGS_VPROC12_OC_STATUS_ADDR MT6358_VPROC_ANA_CON5
#define PMIC_RGS_VPROC12_OC_STATUS_MASK 0x1
#define PMIC_RGS_VPROC12_OC_STATUS_SHIFT   4
#define PMIC_RGS_VPROC11_PREOC_STATUS_ADDR  MT6358_VPROC_ANA_CON5
#define PMIC_RGS_VPROC11_PREOC_STATUS_MASK  0x1
#define PMIC_RGS_VPROC11_PREOC_STATUS_SHIFT 5
#define PMIC_RGS_VPROC11_DIG_MON_ADDR MT6358_VPROC_ANA_CON5
#define PMIC_RGS_VPROC11_DIG_MON_MASK 0xFF
#define PMIC_RGS_VPROC11_DIG_MON_SHIFT  6
#define PMIC_RGS_VPROC11_ENPWM_STATUS_ADDR  MT6358_VPROC_ANA_CON5
#define PMIC_RGS_VPROC11_ENPWM_STATUS_MASK  0x1
#define PMIC_RGS_VPROC11_ENPWM_STATUS_SHIFT 14
#define PMIC_RGS_VPROC12_ENPWM_STATUS_ADDR  MT6358_VPROC_ANA_CON5
#define PMIC_RGS_VPROC12_ENPWM_STATUS_MASK  0x1
#define PMIC_RGS_VPROC12_ENPWM_STATUS_SHIFT 15
#define PMIC_RGS_VPROC12_DIG_MON_ADDR MT6358_VPROC_ANA_CON6
#define PMIC_RGS_VPROC12_DIG_MON_MASK 0xFF
#define PMIC_RGS_VPROC12_DIG_MON_SHIFT  0
#define PMIC_RG_VPROC11_TRAN_BST_ADDR MT6358_VPROC_ANA_CON7
#define PMIC_RG_VPROC11_TRAN_BST_MASK 0x3F
#define PMIC_RG_VPROC11_TRAN_BST_SHIFT  0
#define PMIC_RG_VPROC12_TRAN_BST_ADDR MT6358_VPROC_ANA_CON7
#define PMIC_RG_VPROC12_TRAN_BST_MASK 0x3F
#define PMIC_RG_VPROC12_TRAN_BST_SHIFT  7
#define PMIC_RG_VPROC11_COTRAMP_SLP_ADDR   MT6358_VPROC_ANA_CON7
#define PMIC_RG_VPROC11_COTRAMP_SLP_MASK   0x7
#define PMIC_RG_VPROC11_COTRAMP_SLP_SHIFT   13
#define PMIC_RG_VPROC12_COTRAMP_SLP_ADDR   MT6358_VPROC_ANA_CON8
#define PMIC_RG_VPROC12_COTRAMP_SLP_MASK   0x7
#define PMIC_RG_VPROC12_COTRAMP_SLP_SHIFT   0
#define PMIC_RG_VPROC11_SLEEP_TIME_ADDR MT6358_VPROC_ANA_CON8
#define PMIC_RG_VPROC11_SLEEP_TIME_MASK 0x3
#define PMIC_RG_VPROC11_SLEEP_TIME_SHIFT   3
#define PMIC_RG_VPROC12_SLEEP_TIME_ADDR MT6358_VPROC_ANA_CON8
#define PMIC_RG_VPROC12_SLEEP_TIME_MASK 0x3
#define PMIC_RG_VPROC12_SLEEP_TIME_SHIFT   5
#define PMIC_RG_VPROC11_VREFTB_ADDR   MT6358_VPROC_ANA_CON8
#define PMIC_RG_VPROC11_VREFTB_MASK   0x3
#define PMIC_RG_VPROC11_VREFTB_SHIFT  7
#define PMIC_RG_VPROC12_VREFTB_ADDR   MT6358_VPROC_ANA_CON8
#define PMIC_RG_VPROC12_VREFTB_MASK   0x3
#define PMIC_RG_VPROC12_VREFTB_SHIFT  9
#define PMIC_RG_VPROC11_FUGON_ADDR MT6358_VPROC_ANA_CON8
#define PMIC_RG_VPROC11_FUGON_MASK 0x1
#define PMIC_RG_VPROC11_FUGON_SHIFT   11
#define PMIC_RG_VPROC12_FUGON_ADDR MT6358_VPROC_ANA_CON8
#define PMIC_RG_VPROC12_FUGON_MASK 0x1
#define PMIC_RG_VPROC12_FUGON_SHIFT   12
#define PMIC_RG_VPROC11_FLGON_ADDR MT6358_VPROC_ANA_CON8
#define PMIC_RG_VPROC11_FLGON_MASK 0x1
#define PMIC_RG_VPROC11_FLGON_SHIFT   13
#define PMIC_RG_VPROC12_FLGON_ADDR MT6358_VPROC_ANA_CON8
#define PMIC_RG_VPROC12_FLGON_MASK 0x1
#define PMIC_RG_VPROC12_FLGON_SHIFT   14
#define PMIC_RG_VPROC11_RSV_ADDR  MT6358_VPROC_ANA_CON9
#define PMIC_RG_VPROC11_RSV_MASK  0xFFFF
#define PMIC_RG_VPROC11_RSV_SHIFT 0
#define PMIC_RG_VPROC12_RSV_ADDR  MT6358_VPROC_ANA_CON10
#define PMIC_RG_VPROC12_RSV_MASK  0xFFFF
#define PMIC_RG_VPROC12_RSV_SHIFT 0
#define PMIC_RG_VPROC11VPROC12_DISAUTOK_ADDR  MT6358_VPROC_ANA_CON11
#define PMIC_RG_VPROC11VPROC12_DISAUTOK_MASK  0x1
#define PMIC_RG_VPROC11VPROC12_DISAUTOK_SHIFT 0
#define PMIC_RGS_VPROC11_PFM_FLAG_ADDR  MT6358_VPROC_ANA_CON11
#define PMIC_RGS_VPROC11_PFM_FLAG_MASK  0x1
#define PMIC_RGS_VPROC11_PFM_FLAG_SHIFT 1
#define PMIC_RGS_VPROC12_PFM_FLAG_ADDR  MT6358_VPROC_ANA_CON11
#define PMIC_RGS_VPROC12_PFM_FLAG_MASK  0x1
#define PMIC_RGS_VPROC12_PFM_FLAG_SHIFT 2
#define PMIC_RG_VPROC12_NONAUDIBLE_EN_ADDR  MT6358_VPROC_ANA_CON11
#define PMIC_RG_VPROC12_NONAUDIBLE_EN_MASK  0x1
#define PMIC_RG_VPROC12_NONAUDIBLE_EN_SHIFT 3
#define PMIC_RG_VPROC11_NONAUDIBLE_EN_ADDR  MT6358_VPROC_ANA_CON11
#define PMIC_RG_VPROC11_NONAUDIBLE_EN_MASK  0x1
#define PMIC_RG_VPROC11_NONAUDIBLE_EN_SHIFT 4
#define PMIC_RG_VPROC11_CSP_ADDR  MT6358_VPROC_ANA_CON12
#define PMIC_RG_VPROC11_CSP_MASK  0x7
#define PMIC_RG_VPROC11_CSP_SHIFT 0
#define PMIC_RG_VPROC11_CSN_ADDR  MT6358_VPROC_ANA_CON12
#define PMIC_RG_VPROC11_CSN_MASK  0x7
#define PMIC_RG_VPROC11_CSN_SHIFT 3
#define PMIC_RG_VPROC12_CSP_ADDR  MT6358_VPROC_ANA_CON12
#define PMIC_RG_VPROC12_CSP_MASK  0x7
#define PMIC_RG_VPROC12_CSP_SHIFT 6
#define PMIC_RG_VPROC12_CSN_ADDR  MT6358_VPROC_ANA_CON12
#define PMIC_RG_VPROC12_CSN_MASK  0x7
#define PMIC_RG_VPROC12_CSN_SHIFT 9
#define PMIC_RG_VPROC11_SONIC_PFM_TON_ADDR  MT6358_VPROC_ANA_CON13
#define PMIC_RG_VPROC11_SONIC_PFM_TON_MASK  0x7
#define PMIC_RG_VPROC11_SONIC_PFM_TON_SHIFT 0
#define PMIC_RG_VPROC12_SONIC_PFM_TON_ADDR  MT6358_VPROC_ANA_CON13
#define PMIC_RG_VPROC12_SONIC_PFM_TON_MASK  0x7
#define PMIC_RG_VPROC12_SONIC_PFM_TON_SHIFT 3
#define PMIC_RG_VPROC11_RETENTION_EN_ADDR   MT6358_VPROC_ANA_CON13
#define PMIC_RG_VPROC11_RETENTION_EN_MASK   0x1
#define PMIC_RG_VPROC11_RETENTION_EN_SHIFT  6
#define PMIC_RG_VPROC12_RETENTION_EN_ADDR   MT6358_VPROC_ANA_CON13
#define PMIC_RG_VPROC12_RETENTION_EN_MASK   0x1
#define PMIC_RG_VPROC12_RETENTION_EN_SHIFT  7
#define PMIC_RGS_VPROC11VPROC12_TRIMOK_STATUS_ADDR  MT6358_VPROC_ANA_CON13
#define PMIC_RGS_VPROC11VPROC12_TRIMOK_STATUS_MASK  0x1
#define PMIC_RGS_VPROC11VPROC12_TRIMOK_STATUS_SHIFT 8
#define PMIC_RG_VCORE_FPWM_ADDR MT6358_VCORE_VGPU_ANA_CON0
#define PMIC_RG_VCORE_FPWM_MASK 0x1
#define PMIC_RG_VCORE_FPWM_SHIFT  1
#define PMIC_RG_VGPU_FPWM_ADDR  MT6358_VCORE_VGPU_ANA_CON0
#define PMIC_RG_VGPU_FPWM_MASK  0x1
#define PMIC_RG_VGPU_FPWM_SHIFT 2
#define PMIC_RG_VCORE_NDIS_EN_ADDR MT6358_VCORE_VGPU_ANA_CON0
#define PMIC_RG_VCORE_NDIS_EN_MASK 0x1
#define PMIC_RG_VCORE_NDIS_EN_SHIFT   3
#define PMIC_RG_VGPU_NDIS_EN_ADDR MT6358_VCORE_VGPU_ANA_CON0
#define PMIC_RG_VGPU_NDIS_EN_MASK 0x1
#define PMIC_RG_VGPU_NDIS_EN_SHIFT 4
#define PMIC_RG_VCORE_FCOT_ADDR MT6358_VCORE_VGPU_ANA_CON0
#define PMIC_RG_VCORE_FCOT_MASK 0x1
#define PMIC_RG_VCORE_FCOT_SHIFT  5
#define PMIC_RG_VGPU_FCOT_ADDR  MT6358_VCORE_VGPU_ANA_CON0
#define PMIC_RG_VGPU_FCOT_MASK  0x1
#define PMIC_RG_VGPU_FCOT_SHIFT 6
#define PMIC_RG_VCOREVGPU_TMDL_ADDR   MT6358_VCORE_VGPU_ANA_CON0
#define PMIC_RG_VCOREVGPU_TMDL_MASK   0x1
#define PMIC_RG_VCOREVGPU_TMDL_SHIFT  7
#define PMIC_RG_VCORE_TBDIS_ADDR  MT6358_VCORE_VGPU_ANA_CON0
#define PMIC_RG_VCORE_TBDIS_MASK  0x1
#define PMIC_RG_VCORE_TBDIS_SHIFT 8
#define PMIC_RG_VGPU_TBDIS_ADDR MT6358_VCORE_VGPU_ANA_CON0
#define PMIC_RG_VGPU_TBDIS_MASK 0x1
#define PMIC_RG_VGPU_TBDIS_SHIFT  9
#define PMIC_RG_VCORE_VDIFFOFF_ADDR   MT6358_VCORE_VGPU_ANA_CON0
#define PMIC_RG_VCORE_VDIFFOFF_MASK   0x1
#define PMIC_RG_VCORE_VDIFFOFF_SHIFT  10
#define PMIC_RG_VGPU_VDIFFOFF_ADDR MT6358_VCORE_VGPU_ANA_CON0
#define PMIC_RG_VGPU_VDIFFOFF_MASK 0x1
#define PMIC_RG_VGPU_VDIFFOFF_SHIFT   11
#define PMIC_RG_VCORE_RCOMP0_ADDR MT6358_VCORE_VGPU_ANA_CON1
#define PMIC_RG_VCORE_RCOMP0_MASK 0xF
#define PMIC_RG_VCORE_RCOMP0_SHIFT 0
#define PMIC_RG_VCORE_RCOMP1_ADDR MT6358_VCORE_VGPU_ANA_CON1
#define PMIC_RG_VCORE_RCOMP1_MASK 0x7
#define PMIC_RG_VCORE_RCOMP1_SHIFT 4
#define PMIC_RG_VCORE_CCOMP0_ADDR MT6358_VCORE_VGPU_ANA_CON1
#define PMIC_RG_VCORE_CCOMP0_MASK 0x3
#define PMIC_RG_VCORE_CCOMP0_SHIFT 7
#define PMIC_RG_VCORE_CCOMP1_ADDR MT6358_VCORE_VGPU_ANA_CON1
#define PMIC_RG_VCORE_CCOMP1_MASK 0x3
#define PMIC_RG_VCORE_CCOMP1_SHIFT 9
#define PMIC_RG_VCORE_RAMP_SLP_ADDR   MT6358_VCORE_VGPU_ANA_CON1
#define PMIC_RG_VCORE_RAMP_SLP_MASK   0x7
#define PMIC_RG_VCORE_RAMP_SLP_SHIFT  11
#define PMIC_RG_VGPU_RCOMP0_ADDR  MT6358_VCORE_VGPU_ANA_CON2
#define PMIC_RG_VGPU_RCOMP0_MASK  0xF
#define PMIC_RG_VGPU_RCOMP0_SHIFT 0
#define PMIC_RG_VGPU_RCOMP1_ADDR  MT6358_VCORE_VGPU_ANA_CON2
#define PMIC_RG_VGPU_RCOMP1_MASK  0x7
#define PMIC_RG_VGPU_RCOMP1_SHIFT 4
#define PMIC_RG_VGPU_CCOMP0_ADDR  MT6358_VCORE_VGPU_ANA_CON2
#define PMIC_RG_VGPU_CCOMP0_MASK  0x3
#define PMIC_RG_VGPU_CCOMP0_SHIFT 7
#define PMIC_RG_VGPU_CCOMP1_ADDR  MT6358_VCORE_VGPU_ANA_CON2
#define PMIC_RG_VGPU_CCOMP1_MASK  0x3
#define PMIC_RG_VGPU_CCOMP1_SHIFT 9
#define PMIC_RG_VGPU_RAMP_SLP_ADDR MT6358_VCORE_VGPU_ANA_CON2
#define PMIC_RG_VGPU_RAMP_SLP_MASK 0x7
#define PMIC_RG_VGPU_RAMP_SLP_SHIFT   11
#define PMIC_RG_VCORE_RCS_ADDR  MT6358_VCORE_VGPU_ANA_CON3
#define PMIC_RG_VCORE_RCS_MASK  0x7
#define PMIC_RG_VCORE_RCS_SHIFT 0
#define PMIC_RG_VGPU_RCS_ADDR   MT6358_VCORE_VGPU_ANA_CON3
#define PMIC_RG_VGPU_RCS_MASK   0x7
#define PMIC_RG_VGPU_RCS_SHIFT  3
#define PMIC_RG_VCORE_RCB_ADDR  MT6358_VCORE_VGPU_ANA_CON3
#define PMIC_RG_VCORE_RCB_MASK  0xF
#define PMIC_RG_VCORE_RCB_SHIFT 6
#define PMIC_RG_VGPU_RCB_ADDR   MT6358_VCORE_VGPU_ANA_CON3
#define PMIC_RG_VGPU_RCB_MASK   0xF
#define PMIC_RG_VGPU_RCB_SHIFT  10
#define PMIC_RG_VCORE_TB_WIDTH_ADDR   MT6358_VCORE_VGPU_ANA_CON4
#define PMIC_RG_VCORE_TB_WIDTH_MASK   0x3
#define PMIC_RG_VCORE_TB_WIDTH_SHIFT  0
#define PMIC_RG_VGPU_TB_WIDTH_ADDR MT6358_VCORE_VGPU_ANA_CON4
#define PMIC_RG_VGPU_TB_WIDTH_MASK 0x3
#define PMIC_RG_VGPU_TB_WIDTH_SHIFT   2
#define PMIC_RG_VCORE_UG_SR_ADDR  MT6358_VCORE_VGPU_ANA_CON4
#define PMIC_RG_VCORE_UG_SR_MASK  0x3
#define PMIC_RG_VCORE_UG_SR_SHIFT 4
#define PMIC_RG_VCORE_LG_SR_ADDR  MT6358_VCORE_VGPU_ANA_CON4
#define PMIC_RG_VCORE_LG_SR_MASK  0x3
#define PMIC_RG_VCORE_LG_SR_SHIFT 6
#define PMIC_RG_VGPU_UG_SR_ADDR MT6358_VCORE_VGPU_ANA_CON4
#define PMIC_RG_VGPU_UG_SR_MASK 0x3
#define PMIC_RG_VGPU_UG_SR_SHIFT  8
#define PMIC_RG_VGPU_LG_SR_ADDR MT6358_VCORE_VGPU_ANA_CON4
#define PMIC_RG_VGPU_LG_SR_MASK 0x3
#define PMIC_RG_VGPU_LG_SR_SHIFT  10
#define PMIC_RG_VCORE_PFM_TON_ADDR MT6358_VCORE_VGPU_ANA_CON4
#define PMIC_RG_VCORE_PFM_TON_MASK 0x7
#define PMIC_RG_VCORE_PFM_TON_SHIFT   12
#define PMIC_RG_VGPU_PFM_TON_ADDR MT6358_VCORE_VGPU_ANA_CON5
#define PMIC_RG_VGPU_PFM_TON_MASK 0x7
#define PMIC_RG_VGPU_PFM_TON_SHIFT 0
#define PMIC_RGS_VCORE_OC_STATUS_ADDR MT6358_VCORE_VGPU_ANA_CON5
#define PMIC_RGS_VCORE_OC_STATUS_MASK 0x1
#define PMIC_RGS_VCORE_OC_STATUS_SHIFT  3
#define PMIC_RGS_VGPU_OC_STATUS_ADDR  MT6358_VCORE_VGPU_ANA_CON5
#define PMIC_RGS_VGPU_OC_STATUS_MASK  0x1
#define PMIC_RGS_VGPU_OC_STATUS_SHIFT 4
#define PMIC_RGS_VCORE_PREOC_STATUS_ADDR   MT6358_VCORE_VGPU_ANA_CON5
#define PMIC_RGS_VCORE_PREOC_STATUS_MASK   0x1
#define PMIC_RGS_VCORE_PREOC_STATUS_SHIFT   5
#define PMIC_RGS_VCORE_DIG_MON_ADDR   MT6358_VCORE_VGPU_ANA_CON5
#define PMIC_RGS_VCORE_DIG_MON_MASK   0xFF
#define PMIC_RGS_VCORE_DIG_MON_SHIFT  6
#define PMIC_RGS_VCORE_ENPWM_STATUS_ADDR   MT6358_VCORE_VGPU_ANA_CON5
#define PMIC_RGS_VCORE_ENPWM_STATUS_MASK   0x1
#define PMIC_RGS_VCORE_ENPWM_STATUS_SHIFT   14
#define PMIC_RGS_VGPU_ENPWM_STATUS_ADDR MT6358_VCORE_VGPU_ANA_CON5
#define PMIC_RGS_VGPU_ENPWM_STATUS_MASK 0x1
#define PMIC_RGS_VGPU_ENPWM_STATUS_SHIFT   15
#define PMIC_RGS_VGPU_DIG_MON_ADDR MT6358_VCORE_VGPU_ANA_CON6
#define PMIC_RGS_VGPU_DIG_MON_MASK 0xFF
#define PMIC_RGS_VGPU_DIG_MON_SHIFT   0
#define PMIC_RG_VCORE_TRAN_BST_ADDR   MT6358_VCORE_VGPU_ANA_CON7
#define PMIC_RG_VCORE_TRAN_BST_MASK   0x3F
#define PMIC_RG_VCORE_TRAN_BST_SHIFT  0
#define PMIC_RG_VGPU_TRAN_BST_ADDR MT6358_VCORE_VGPU_ANA_CON7
#define PMIC_RG_VGPU_TRAN_BST_MASK 0x3F
#define PMIC_RG_VGPU_TRAN_BST_SHIFT   7
#define PMIC_RG_VCORE_COTRAMP_SLP_ADDR  MT6358_VCORE_VGPU_ANA_CON7
#define PMIC_RG_VCORE_COTRAMP_SLP_MASK  0x7
#define PMIC_RG_VCORE_COTRAMP_SLP_SHIFT 13
#define PMIC_RG_VGPU_COTRAMP_SLP_ADDR MT6358_VCORE_VGPU_ANA_CON8
#define PMIC_RG_VGPU_COTRAMP_SLP_MASK 0x7
#define PMIC_RG_VGPU_COTRAMP_SLP_SHIFT  0
#define PMIC_RG_VCORE_SLEEP_TIME_ADDR MT6358_VCORE_VGPU_ANA_CON8
#define PMIC_RG_VCORE_SLEEP_TIME_MASK 0x3
#define PMIC_RG_VCORE_SLEEP_TIME_SHIFT  3
#define PMIC_RG_VGPU_SLEEP_TIME_ADDR  MT6358_VCORE_VGPU_ANA_CON8
#define PMIC_RG_VGPU_SLEEP_TIME_MASK  0x3
#define PMIC_RG_VGPU_SLEEP_TIME_SHIFT 5
#define PMIC_RG_VCORE_VREFTB_ADDR MT6358_VCORE_VGPU_ANA_CON8
#define PMIC_RG_VCORE_VREFTB_MASK 0x3
#define PMIC_RG_VCORE_VREFTB_SHIFT 7
#define PMIC_RG_VGPU_VREFTB_ADDR  MT6358_VCORE_VGPU_ANA_CON8
#define PMIC_RG_VGPU_VREFTB_MASK  0x3
#define PMIC_RG_VGPU_VREFTB_SHIFT 9
#define PMIC_RG_VCORE_FUGON_ADDR  MT6358_VCORE_VGPU_ANA_CON8
#define PMIC_RG_VCORE_FUGON_MASK  0x1
#define PMIC_RG_VCORE_FUGON_SHIFT 11
#define PMIC_RG_VGPU_FUGON_ADDR MT6358_VCORE_VGPU_ANA_CON8
#define PMIC_RG_VGPU_FUGON_MASK 0x1
#define PMIC_RG_VGPU_FUGON_SHIFT  12
#define PMIC_RG_VCORE_FLGON_ADDR  MT6358_VCORE_VGPU_ANA_CON8
#define PMIC_RG_VCORE_FLGON_MASK  0x1
#define PMIC_RG_VCORE_FLGON_SHIFT 13
#define PMIC_RG_VGPU_FLGON_ADDR MT6358_VCORE_VGPU_ANA_CON8
#define PMIC_RG_VGPU_FLGON_MASK 0x1
#define PMIC_RG_VGPU_FLGON_SHIFT  14
#define PMIC_RG_VCORE_RSV_ADDR  MT6358_VCORE_VGPU_ANA_CON9
#define PMIC_RG_VCORE_RSV_MASK  0xFFFF
#define PMIC_RG_VCORE_RSV_SHIFT 0
#define PMIC_RG_VGPU_RSV_ADDR   MT6358_VCORE_VGPU_ANA_CON10
#define PMIC_RG_VGPU_RSV_MASK   0xFFFF
#define PMIC_RG_VGPU_RSV_SHIFT  0
#define PMIC_RG_VCOREVGPU_DISAUTOK_ADDR MT6358_VCORE_VGPU_ANA_CON11
#define PMIC_RG_VCOREVGPU_DISAUTOK_MASK 0x1
#define PMIC_RG_VCOREVGPU_DISAUTOK_SHIFT   0
#define PMIC_RGS_VCORE_PFM_FLAG_ADDR  MT6358_VCORE_VGPU_ANA_CON11
#define PMIC_RGS_VCORE_PFM_FLAG_MASK  0x1
#define PMIC_RGS_VCORE_PFM_FLAG_SHIFT 1
#define PMIC_RGS_VGPU_PFM_FLAG_ADDR   MT6358_VCORE_VGPU_ANA_CON11
#define PMIC_RGS_VGPU_PFM_FLAG_MASK   0x1
#define PMIC_RGS_VGPU_PFM_FLAG_SHIFT  2
#define PMIC_RG_VGPU_NONAUDIBLE_EN_ADDR MT6358_VCORE_VGPU_ANA_CON11
#define PMIC_RG_VGPU_NONAUDIBLE_EN_MASK 0x1
#define PMIC_RG_VGPU_NONAUDIBLE_EN_SHIFT   3
#define PMIC_RG_VCORE_NONAUDIBLE_EN_ADDR   MT6358_VCORE_VGPU_ANA_CON11
#define PMIC_RG_VCORE_NONAUDIBLE_EN_MASK   0x1
#define PMIC_RG_VCORE_NONAUDIBLE_EN_SHIFT   4
#define PMIC_RG_VCORE_CSP_ADDR  MT6358_VCORE_VGPU_ANA_CON12
#define PMIC_RG_VCORE_CSP_MASK  0x7
#define PMIC_RG_VCORE_CSP_SHIFT 0
#define PMIC_RG_VCORE_CSN_ADDR  MT6358_VCORE_VGPU_ANA_CON12
#define PMIC_RG_VCORE_CSN_MASK  0x7
#define PMIC_RG_VCORE_CSN_SHIFT 3
#define PMIC_RG_VGPU_CSP_ADDR   MT6358_VCORE_VGPU_ANA_CON12
#define PMIC_RG_VGPU_CSP_MASK   0x7
#define PMIC_RG_VGPU_CSP_SHIFT  6
#define PMIC_RG_VGPU_CSN_ADDR   MT6358_VCORE_VGPU_ANA_CON12
#define PMIC_RG_VGPU_CSN_MASK   0x7
#define PMIC_RG_VGPU_CSN_SHIFT  9
#define PMIC_RG_VCORE_SONIC_PFM_TON_ADDR   MT6358_VCORE_VGPU_ANA_CON12
#define PMIC_RG_VCORE_SONIC_PFM_TON_MASK   0x7
#define PMIC_RG_VCORE_SONIC_PFM_TON_SHIFT   12
#define PMIC_RG_VGPU_SONIC_PFM_TON_ADDR MT6358_VCORE_VGPU_ANA_CON13
#define PMIC_RG_VGPU_SONIC_PFM_TON_MASK 0x7
#define PMIC_RG_VGPU_SONIC_PFM_TON_SHIFT   0
#define PMIC_RG_VCORE_RETENTION_EN_ADDR MT6358_VCORE_VGPU_ANA_CON13
#define PMIC_RG_VCORE_RETENTION_EN_MASK 0x1
#define PMIC_RG_VCORE_RETENTION_EN_SHIFT   3
#define PMIC_RG_VGPU_RETENTION_EN_ADDR  MT6358_VCORE_VGPU_ANA_CON13
#define PMIC_RG_VGPU_RETENTION_EN_MASK  0x1
#define PMIC_RG_VGPU_RETENTION_EN_SHIFT 4
#define PMIC_RGS_VCOREVGPU_TRIMOK_STATUS_ADDR MT6358_VCORE_VGPU_ANA_CON13
#define PMIC_RGS_VCOREVGPU_TRIMOK_STATUS_MASK 0x1
#define PMIC_RGS_VCOREVGPU_TRIMOK_STATUS_SHIFT   5
#define PMIC_BUCK_ANA0_ELR_LEN_ADDR   MT6358_BUCK_ANA0_ELR_NUM
#define PMIC_BUCK_ANA0_ELR_LEN_MASK   0xFF
#define PMIC_BUCK_ANA0_ELR_LEN_SHIFT  0
#define PMIC_RG_VS1_TRIMH_ADDR  MT6358_SMPS_ELR_0
#define PMIC_RG_VS1_TRIMH_MASK  0x1F
#define PMIC_RG_VS1_TRIMH_SHIFT 0
#define PMIC_RG_VS2_TRIMH_ADDR  MT6358_SMPS_ELR_0
#define PMIC_RG_VS2_TRIMH_MASK  0x1F
#define PMIC_RG_VS2_TRIMH_SHIFT 5
#define PMIC_RG_VMODEM_TRIMH_ADDR MT6358_SMPS_ELR_0
#define PMIC_RG_VMODEM_TRIMH_MASK 0x1F
#define PMIC_RG_VMODEM_TRIMH_SHIFT 10
#define PMIC_RG_VMODEM_VSLEEP_TRIM_ADDR MT6358_SMPS_ELR_1
#define PMIC_RG_VMODEM_VSLEEP_TRIM_MASK 0x7
#define PMIC_RG_VMODEM_VSLEEP_TRIM_SHIFT   0
#define PMIC_RG_VGPU_TRIMH_ADDR MT6358_SMPS_ELR_1
#define PMIC_RG_VGPU_TRIMH_MASK 0x1F
#define PMIC_RG_VGPU_TRIMH_SHIFT  3
#define PMIC_RG_VCORE_TRIMH_ADDR  MT6358_SMPS_ELR_1
#define PMIC_RG_VCORE_TRIMH_MASK  0x1F
#define PMIC_RG_VCORE_TRIMH_SHIFT 8
#define PMIC_RG_VPROC11_TRIMH_ADDR MT6358_SMPS_ELR_2
#define PMIC_RG_VPROC11_TRIMH_MASK 0x1F
#define PMIC_RG_VPROC11_TRIMH_SHIFT   0
#define PMIC_RG_VPROC12_TRIMH_ADDR MT6358_SMPS_ELR_2
#define PMIC_RG_VPROC12_TRIMH_MASK 0x1F
#define PMIC_RG_VPROC12_TRIMH_SHIFT   5
#define PMIC_RG_VPA_TRIMH_ADDR  MT6358_SMPS_ELR_2
#define PMIC_RG_VPA_TRIMH_MASK  0x1F
#define PMIC_RG_VPA_TRIMH_SHIFT 10
#define PMIC_RG_VPA_TRIML_ADDR  MT6358_SMPS_ELR_3
#define PMIC_RG_VPA_TRIML_MASK  0x1F
#define PMIC_RG_VPA_TRIML_SHIFT 0
#define PMIC_RG_VPA_TRIM_REF_ADDR MT6358_SMPS_ELR_3
#define PMIC_RG_VPA_TRIM_REF_MASK 0x1F
#define PMIC_RG_VPA_TRIM_REF_SHIFT 5
#define PMIC_RG_VDRAM1_TRIMH_ADDR MT6358_SMPS_ELR_3
#define PMIC_RG_VDRAM1_TRIMH_MASK 0x1F
#define PMIC_RG_VDRAM1_TRIMH_SHIFT 10
#define PMIC_RG_VSRAM_PROC11_TRIMH_ADDR MT6358_SMPS_ELR_4
#define PMIC_RG_VSRAM_PROC11_TRIMH_MASK 0x1F
#define PMIC_RG_VSRAM_PROC11_TRIMH_SHIFT   0
#define PMIC_RG_VSRAM_GPU_TRIMH_ADDR  MT6358_SMPS_ELR_4
#define PMIC_RG_VSRAM_GPU_TRIMH_MASK  0x1F
#define PMIC_RG_VSRAM_GPU_TRIMH_SHIFT 5
#define PMIC_RG_VSRAM_OTHERS_TRIMH_ADDR MT6358_SMPS_ELR_4
#define PMIC_RG_VSRAM_OTHERS_TRIMH_MASK 0x1F
#define PMIC_RG_VSRAM_OTHERS_TRIMH_SHIFT   10
#define PMIC_RG_VOUTDET_EN_ADDR MT6358_SMPS_ELR_4
#define PMIC_RG_VOUTDET_EN_MASK 0x1
#define PMIC_RG_VOUTDET_EN_SHIFT  15
#define PMIC_RG_VSRAM_PROC12_TRIMH_ADDR MT6358_SMPS_ELR_5
#define PMIC_RG_VSRAM_PROC12_TRIMH_MASK 0x1F
#define PMIC_RG_VSRAM_PROC12_TRIMH_SHIFT   0
#define PMIC_RG_VPROC11_ZC_TRIM_ADDR  MT6358_VPROC_ELR_0
#define PMIC_RG_VPROC11_ZC_TRIM_MASK  0x3
#define PMIC_RG_VPROC11_ZC_TRIM_SHIFT 0
#define PMIC_RG_VPROC11_NLIM_TRIM_ADDR  MT6358_VPROC_ELR_0
#define PMIC_RG_VPROC11_NLIM_TRIM_MASK  0xF
#define PMIC_RG_VPROC11_NLIM_TRIM_SHIFT 2
#define PMIC_RG_VPROC11_TON_TRIM_ADDR MT6358_VPROC_ELR_0
#define PMIC_RG_VPROC11_TON_TRIM_MASK 0x3F
#define PMIC_RG_VPROC11_TON_TRIM_SHIFT  6
#define PMIC_RG_VPROC11_RPSI1_TRIM_ADDR MT6358_VPROC_ELR_1
#define PMIC_RG_VPROC11_RPSI1_TRIM_MASK 0x7
#define PMIC_RG_VPROC11_RPSI1_TRIM_SHIFT   0
#define PMIC_RG_VPROC11_PREOC_TRIM_ADDR MT6358_VPROC_ELR_1
#define PMIC_RG_VPROC11_PREOC_TRIM_MASK 0x7
#define PMIC_RG_VPROC11_PREOC_TRIM_SHIFT   3
#define PMIC_RG_VPROC11_CSPSLP_TRIM_ADDR   MT6358_VPROC_ELR_1
#define PMIC_RG_VPROC11_CSPSLP_TRIM_MASK   0xF
#define PMIC_RG_VPROC11_CSPSLP_TRIM_SHIFT   6
#define PMIC_RG_VPROC11_CSNSLP_TRIM_ADDR   MT6358_VPROC_ELR_1
#define PMIC_RG_VPROC11_CSNSLP_TRIM_MASK   0xF
#define PMIC_RG_VPROC11_CSNSLP_TRIM_SHIFT   10
#define PMIC_RG_VPROC12_ZC_TRIM_ADDR  MT6358_VPROC_ELR_1
#define PMIC_RG_VPROC12_ZC_TRIM_MASK  0x3
#define PMIC_RG_VPROC12_ZC_TRIM_SHIFT 14
#define PMIC_RG_VPROC12_NLIM_TRIM_ADDR  MT6358_VPROC_ELR_2
#define PMIC_RG_VPROC12_NLIM_TRIM_MASK  0xF
#define PMIC_RG_VPROC12_NLIM_TRIM_SHIFT 0
#define PMIC_RG_VPROC12_TON_TRIM_ADDR MT6358_VPROC_ELR_2
#define PMIC_RG_VPROC12_TON_TRIM_MASK 0x3F
#define PMIC_RG_VPROC12_TON_TRIM_SHIFT  4
#define PMIC_RG_VPROC12_RPSI1_TRIM_ADDR MT6358_VPROC_ELR_2
#define PMIC_RG_VPROC12_RPSI1_TRIM_MASK 0x7
#define PMIC_RG_VPROC12_RPSI1_TRIM_SHIFT   10
#define PMIC_RG_VPROC12_CSPSLP_TRIM_ADDR   MT6358_VPROC_ELR_3
#define PMIC_RG_VPROC12_CSPSLP_TRIM_MASK   0xF
#define PMIC_RG_VPROC12_CSPSLP_TRIM_SHIFT   0
#define PMIC_RG_VPROC12_CSNSLP_TRIM_ADDR   MT6358_VPROC_ELR_3
#define PMIC_RG_VPROC12_CSNSLP_TRIM_MASK   0xF
#define PMIC_RG_VPROC12_CSNSLP_TRIM_SHIFT   4
#define PMIC_RG_VPROC11VPROC12_DISCONFIG20_ADDR  MT6358_VPROC_ELR_3
#define PMIC_RG_VPROC11VPROC12_DISCONFIG20_MASK  0x1
#define PMIC_RG_VPROC11VPROC12_DISCONFIG20_SHIFT  8
#define PMIC_RG_VPROC11_LDO_AUTO_TRACK_ADDR MT6358_VPROC_ELR_3
#define PMIC_RG_VPROC11_LDO_AUTO_TRACK_MASK 0x1
#define PMIC_RG_VPROC11_LDO_AUTO_TRACK_SHIFT  9
#define PMIC_RG_VPROC12_LDO_AUTO_TRACK_ADDR MT6358_VPROC_ELR_3
#define PMIC_RG_VPROC12_LDO_AUTO_TRACK_MASK 0x1
#define PMIC_RG_VPROC12_LDO_AUTO_TRACK_SHIFT  10
#define PMIC_RG_VCORE_ZC_TRIM_ADDR MT6358_VCORE_VGPU_ELR_0
#define PMIC_RG_VCORE_ZC_TRIM_MASK 0x3
#define PMIC_RG_VCORE_ZC_TRIM_SHIFT   0
#define PMIC_RG_VCORE_NLIM_TRIM_ADDR  MT6358_VCORE_VGPU_ELR_0
#define PMIC_RG_VCORE_NLIM_TRIM_MASK  0xF
#define PMIC_RG_VCORE_NLIM_TRIM_SHIFT 2
#define PMIC_RG_VCORE_TON_TRIM_ADDR   MT6358_VCORE_VGPU_ELR_0
#define PMIC_RG_VCORE_TON_TRIM_MASK   0x3F
#define PMIC_RG_VCORE_TON_TRIM_SHIFT  6
#define PMIC_RG_VCORE_RPSI1_TRIM_ADDR MT6358_VCORE_VGPU_ELR_1
#define PMIC_RG_VCORE_RPSI1_TRIM_MASK 0x7
#define PMIC_RG_VCORE_RPSI1_TRIM_SHIFT  0
#define PMIC_RG_VCORE_PREOC_TRIM_ADDR MT6358_VCORE_VGPU_ELR_1
#define PMIC_RG_VCORE_PREOC_TRIM_MASK 0x7
#define PMIC_RG_VCORE_PREOC_TRIM_SHIFT  3
#define PMIC_RG_VCORE_CSPSLP_TRIM_ADDR  MT6358_VCORE_VGPU_ELR_1
#define PMIC_RG_VCORE_CSPSLP_TRIM_MASK  0xF
#define PMIC_RG_VCORE_CSPSLP_TRIM_SHIFT 6
#define PMIC_RG_VCORE_CSNSLP_TRIM_ADDR  MT6358_VCORE_VGPU_ELR_1
#define PMIC_RG_VCORE_CSNSLP_TRIM_MASK  0xF
#define PMIC_RG_VCORE_CSNSLP_TRIM_SHIFT 10
#define PMIC_RG_VGPU_ZC_TRIM_ADDR MT6358_VCORE_VGPU_ELR_1
#define PMIC_RG_VGPU_ZC_TRIM_MASK 0x3
#define PMIC_RG_VGPU_ZC_TRIM_SHIFT 14
#define PMIC_RG_VGPU_NLIM_TRIM_ADDR   MT6358_VCORE_VGPU_ELR_2
#define PMIC_RG_VGPU_NLIM_TRIM_MASK   0xF
#define PMIC_RG_VGPU_NLIM_TRIM_SHIFT  0
#define PMIC_RG_VGPU_TON_TRIM_ADDR MT6358_VCORE_VGPU_ELR_2
#define PMIC_RG_VGPU_TON_TRIM_MASK 0x3F
#define PMIC_RG_VGPU_TON_TRIM_SHIFT   4
#define PMIC_RG_VGPU_RPSI1_TRIM_ADDR  MT6358_VCORE_VGPU_ELR_2
#define PMIC_RG_VGPU_RPSI1_TRIM_MASK  0x7
#define PMIC_RG_VGPU_RPSI1_TRIM_SHIFT 10
#define PMIC_RG_VGPU_CSPSLP_TRIM_ADDR MT6358_VCORE_VGPU_ELR_3
#define PMIC_RG_VGPU_CSPSLP_TRIM_MASK 0xF
#define PMIC_RG_VGPU_CSPSLP_TRIM_SHIFT  0
#define PMIC_RG_VGPU_CSNSLP_TRIM_ADDR MT6358_VCORE_VGPU_ELR_3
#define PMIC_RG_VGPU_CSNSLP_TRIM_MASK 0xF
#define PMIC_RG_VGPU_CSNSLP_TRIM_SHIFT  4
#define PMIC_RG_VCOREVGPU_DISCONFIG20_ADDR  MT6358_VCORE_VGPU_ELR_3
#define PMIC_RG_VCOREVGPU_DISCONFIG20_MASK  0x1
#define PMIC_RG_VCOREVGPU_DISCONFIG20_SHIFT 8
#define PMIC_RG_VCORE_LDO_AUTO_TRACK_ADDR   MT6358_VCORE_VGPU_ELR_3
#define PMIC_RG_VCORE_LDO_AUTO_TRACK_MASK   0x1
#define PMIC_RG_VCORE_LDO_AUTO_TRACK_SHIFT  9
#define PMIC_RG_VGPU_LDO_AUTO_TRACK_ADDR   MT6358_VCORE_VGPU_ELR_3
#define PMIC_RG_VGPU_LDO_AUTO_TRACK_MASK   0x1
#define PMIC_RG_VGPU_LDO_AUTO_TRACK_SHIFT   10
#define PMIC_BUCK_ANA1_ANA_ID_ADDR MT6358_BUCK_ANA1_DSN_ID
#define PMIC_BUCK_ANA1_ANA_ID_MASK 0xFF
#define PMIC_BUCK_ANA1_ANA_ID_SHIFT   0
#define PMIC_BUCK_ANA1_DIG_ID_ADDR MT6358_BUCK_ANA1_DSN_ID
#define PMIC_BUCK_ANA1_DIG_ID_MASK 0xFF
#define PMIC_BUCK_ANA1_DIG_ID_SHIFT   8
#define PMIC_BUCK_ANA1_ANA_MINOR_REV_ADDR   MT6358_BUCK_ANA1_DSN_REV0
#define PMIC_BUCK_ANA1_ANA_MINOR_REV_MASK   0xF
#define PMIC_BUCK_ANA1_ANA_MINOR_REV_SHIFT  0
#define PMIC_BUCK_ANA1_ANA_MAJOR_REV_ADDR   MT6358_BUCK_ANA1_DSN_REV0
#define PMIC_BUCK_ANA1_ANA_MAJOR_REV_MASK   0xF
#define PMIC_BUCK_ANA1_ANA_MAJOR_REV_SHIFT  4
#define PMIC_BUCK_ANA1_DIG_MINOR_REV_ADDR   MT6358_BUCK_ANA1_DSN_REV0
#define PMIC_BUCK_ANA1_DIG_MINOR_REV_MASK   0xF
#define PMIC_BUCK_ANA1_DIG_MINOR_REV_SHIFT  8
#define PMIC_BUCK_ANA1_DIG_MAJOR_REV_ADDR   MT6358_BUCK_ANA1_DSN_REV0
#define PMIC_BUCK_ANA1_DIG_MAJOR_REV_MASK   0xF
#define PMIC_BUCK_ANA1_DIG_MAJOR_REV_SHIFT  12
#define PMIC_BUCK_ANA1_DSN_CBS_ADDR   MT6358_BUCK_ANA1_DSN_DBI
#define PMIC_BUCK_ANA1_DSN_CBS_MASK   0x3
#define PMIC_BUCK_ANA1_DSN_CBS_SHIFT  0
#define PMIC_BUCK_ANA1_DSN_BIX_ADDR   MT6358_BUCK_ANA1_DSN_DBI
#define PMIC_BUCK_ANA1_DSN_BIX_MASK   0x3
#define PMIC_BUCK_ANA1_DSN_BIX_SHIFT  2
#define PMIC_BUCK_ANA1_DSN_ESP_ADDR   MT6358_BUCK_ANA1_DSN_DBI
#define PMIC_BUCK_ANA1_DSN_ESP_MASK   0xFF
#define PMIC_BUCK_ANA1_DSN_ESP_SHIFT  8
#define PMIC_BUCK_ANA1_DSN_FPI_ADDR   MT6358_BUCK_ANA1_DSN_FPI
#define PMIC_BUCK_ANA1_DSN_FPI_MASK   0xFF
#define PMIC_BUCK_ANA1_DSN_FPI_SHIFT  0
#define PMIC_RG_VMODEM_FCOT_ADDR  MT6358_VMODEM_ANA_CON0
#define PMIC_RG_VMODEM_FCOT_MASK  0x1
#define PMIC_RG_VMODEM_FCOT_SHIFT 1
#define PMIC_RG_VMODEM_RCOMP_ADDR MT6358_VMODEM_ANA_CON0
#define PMIC_RG_VMODEM_RCOMP_MASK 0xF
#define PMIC_RG_VMODEM_RCOMP_SHIFT 2
#define PMIC_RG_VMODEM_TB_DIS_ADDR MT6358_VMODEM_ANA_CON0
#define PMIC_RG_VMODEM_TB_DIS_MASK 0x1
#define PMIC_RG_VMODEM_TB_DIS_SHIFT   6
#define PMIC_RG_VMODEM_DISPG_ADDR MT6358_VMODEM_ANA_CON0
#define PMIC_RG_VMODEM_DISPG_MASK 0x1
#define PMIC_RG_VMODEM_DISPG_SHIFT 7
#define PMIC_RG_VMODEM_FPWM_ADDR  MT6358_VMODEM_ANA_CON0
#define PMIC_RG_VMODEM_FPWM_MASK  0x1
#define PMIC_RG_VMODEM_FPWM_SHIFT 8
#define PMIC_RG_VMODEM_PFM_TON_ADDR   MT6358_VMODEM_ANA_CON0
#define PMIC_RG_VMODEM_PFM_TON_MASK   0x7
#define PMIC_RG_VMODEM_PFM_TON_SHIFT  9
#define PMIC_RG_VMODEM_PWMRAMP_SLP_ADDR MT6358_VMODEM_ANA_CON0
#define PMIC_RG_VMODEM_PWMRAMP_SLP_MASK 0x7
#define PMIC_RG_VMODEM_PWMRAMP_SLP_SHIFT   12
#define PMIC_RG_VMODEM_COTRAMP_SLP_ADDR MT6358_VMODEM_ANA_CON1
#define PMIC_RG_VMODEM_COTRAMP_SLP_MASK 0x7
#define PMIC_RG_VMODEM_COTRAMP_SLP_SHIFT   0
#define PMIC_RG_VMODEM_RCS_ADDR MT6358_VMODEM_ANA_CON1
#define PMIC_RG_VMODEM_RCS_MASK 0x7
#define PMIC_RG_VMODEM_RCS_SHIFT  3
#define PMIC_RG_VMODEM_SLEEP_TIME_ADDR  MT6358_VMODEM_ANA_CON1
#define PMIC_RG_VMODEM_SLEEP_TIME_MASK  0x3
#define PMIC_RG_VMODEM_SLEEP_TIME_SHIFT 6
#define PMIC_RG_VMODEM_NLIM_GATING_ADDR MT6358_VMODEM_ANA_CON1
#define PMIC_RG_VMODEM_NLIM_GATING_MASK 0x1
#define PMIC_RG_VMODEM_NLIM_GATING_SHIFT   8
#define PMIC_RG_VMODEM_VDIFF_OFF_ADDR MT6358_VMODEM_ANA_CON1
#define PMIC_RG_VMODEM_VDIFF_OFF_MASK 0x1
#define PMIC_RG_VMODEM_VDIFF_OFF_SHIFT  9
#define PMIC_RG_VMODEM_VREFUP_ADDR MT6358_VMODEM_ANA_CON1
#define PMIC_RG_VMODEM_VREFUP_MASK 0x3
#define PMIC_RG_VMODEM_VREFUP_SHIFT   10
#define PMIC_RG_VMODEM_TB_WIDTH_ADDR  MT6358_VMODEM_ANA_CON1
#define PMIC_RG_VMODEM_TB_WIDTH_MASK  0x3
#define PMIC_RG_VMODEM_TB_WIDTH_SHIFT 12
#define PMIC_RG_VMODEM_UG_SR_ADDR MT6358_VMODEM_ANA_CON2
#define PMIC_RG_VMODEM_UG_SR_MASK 0x3
#define PMIC_RG_VMODEM_UG_SR_SHIFT 0
#define PMIC_RG_VMODEM_LG_SR_ADDR MT6358_VMODEM_ANA_CON2
#define PMIC_RG_VMODEM_LG_SR_MASK 0x3
#define PMIC_RG_VMODEM_LG_SR_SHIFT 2
#define PMIC_RG_VMODEM_CCOMP_ADDR MT6358_VMODEM_ANA_CON2
#define PMIC_RG_VMODEM_CCOMP_MASK 0x3
#define PMIC_RG_VMODEM_CCOMP_SHIFT 4
#define PMIC_RG_VMODEM_NDIS_EN_ADDR   MT6358_VMODEM_ANA_CON2
#define PMIC_RG_VMODEM_NDIS_EN_MASK   0x1
#define PMIC_RG_VMODEM_NDIS_EN_SHIFT  6
#define PMIC_RG_VMODEM_TMDL_ADDR  MT6358_VMODEM_ANA_CON2
#define PMIC_RG_VMODEM_TMDL_MASK  0x1
#define PMIC_RG_VMODEM_TMDL_SHIFT 7
#define PMIC_RG_VMODEM_RSV_ADDR MT6358_VMODEM_ANA_CON3
#define PMIC_RG_VMODEM_RSV_MASK 0xFFFF
#define PMIC_RG_VMODEM_RSV_SHIFT  0
#define PMIC_RG_VMODEM_FUGON_ADDR MT6358_VMODEM_ANA_CON4
#define PMIC_RG_VMODEM_FUGON_MASK 0x1
#define PMIC_RG_VMODEM_FUGON_SHIFT 0
#define PMIC_RG_VMODEM_FLGON_ADDR MT6358_VMODEM_ANA_CON4
#define PMIC_RG_VMODEM_FLGON_MASK 0x1
#define PMIC_RG_VMODEM_FLGON_SHIFT 1
#define PMIC_RG_VMODEM_VDIFFPFM_OFF_ADDR   MT6358_VMODEM_ANA_CON4
#define PMIC_RG_VMODEM_VDIFFPFM_OFF_MASK   0x1
#define PMIC_RG_VMODEM_VDIFFPFM_OFF_SHIFT   2
#define PMIC_RGS_VMODEM_OC_STATUS_ADDR  MT6358_VMODEM_ANA_CON4
#define PMIC_RGS_VMODEM_OC_STATUS_MASK  0x1
#define PMIC_RGS_VMODEM_OC_STATUS_SHIFT 3
#define PMIC_RGS_VMODEM_ENPWM_STATUS_ADDR   MT6358_VMODEM_ANA_CON4
#define PMIC_RGS_VMODEM_ENPWM_STATUS_MASK   0x1
#define PMIC_RGS_VMODEM_ENPWM_STATUS_SHIFT  4
#define PMIC_RG_VMODEM_DISAUTOK_ADDR  MT6358_VMODEM_ANA_CON4
#define PMIC_RG_VMODEM_DISAUTOK_MASK  0x1
#define PMIC_RG_VMODEM_DISAUTOK_SHIFT 5
#define PMIC_RGS_VMODEM_TRIMOK_STATUS_ADDR  MT6358_VMODEM_ANA_CON4
#define PMIC_RGS_VMODEM_TRIMOK_STATUS_MASK  0x1
#define PMIC_RGS_VMODEM_TRIMOK_STATUS_SHIFT 6
#define PMIC_RGS_VMODEM_DIG_MON_ADDR  MT6358_VMODEM_ANA_CON4
#define PMIC_RGS_VMODEM_DIG_MON_MASK  0xFF
#define PMIC_RGS_VMODEM_DIG_MON_SHIFT 7
#define PMIC_RG_VMODEM_NONAUDIBLE_EN_ADDR   MT6358_VMODEM_ANA_CON4
#define PMIC_RG_VMODEM_NONAUDIBLE_EN_MASK   0x1
#define PMIC_RG_VMODEM_NONAUDIBLE_EN_SHIFT  15
#define PMIC_RGS_VMODEM_PFM_FLAG_ADDR MT6358_VMODEM_ANA_CON5
#define PMIC_RGS_VMODEM_PFM_FLAG_MASK 0x1
#define PMIC_RGS_VMODEM_PFM_FLAG_SHIFT  0
#define PMIC_RG_VMODEM_CSP_ADDR MT6358_VMODEM_ANA_CON6
#define PMIC_RG_VMODEM_CSP_MASK 0x7
#define PMIC_RG_VMODEM_CSP_SHIFT  0
#define PMIC_RG_VMODEM_CSN_ADDR MT6358_VMODEM_ANA_CON6
#define PMIC_RG_VMODEM_CSN_MASK 0x7
#define PMIC_RG_VMODEM_CSN_SHIFT  3
#define PMIC_RG_VMODEM_SONIC_PFM_TON_ADDR   MT6358_VMODEM_ANA_CON6
#define PMIC_RG_VMODEM_SONIC_PFM_TON_MASK   0x7
#define PMIC_RG_VMODEM_SONIC_PFM_TON_SHIFT  6
#define PMIC_RG_VMODEM_RETENTION_EN_ADDR   MT6358_VMODEM_ANA_CON6
#define PMIC_RG_VMODEM_RETENTION_EN_MASK   0x1
#define PMIC_RG_VMODEM_RETENTION_EN_SHIFT   9
#define PMIC_RG_VDRAM1_FCOT_ADDR  MT6358_VDRAM1_ANA_CON0
#define PMIC_RG_VDRAM1_FCOT_MASK  0x1
#define PMIC_RG_VDRAM1_FCOT_SHIFT 1
#define PMIC_RG_VDRAM1_RCOMP_ADDR MT6358_VDRAM1_ANA_CON0
#define PMIC_RG_VDRAM1_RCOMP_MASK 0xF
#define PMIC_RG_VDRAM1_RCOMP_SHIFT 2
#define PMIC_RG_VDRAM1_TB_DIS_ADDR MT6358_VDRAM1_ANA_CON0
#define PMIC_RG_VDRAM1_TB_DIS_MASK 0x1
#define PMIC_RG_VDRAM1_TB_DIS_SHIFT   6
#define PMIC_RG_VDRAM1_DISPG_ADDR MT6358_VDRAM1_ANA_CON0
#define PMIC_RG_VDRAM1_DISPG_MASK 0x1
#define PMIC_RG_VDRAM1_DISPG_SHIFT 7
#define PMIC_RG_VDRAM1_FPWM_ADDR  MT6358_VDRAM1_ANA_CON0
#define PMIC_RG_VDRAM1_FPWM_MASK  0x1
#define PMIC_RG_VDRAM1_FPWM_SHIFT 8
#define PMIC_RG_VDRAM1_PFM_TON_ADDR   MT6358_VDRAM1_ANA_CON0
#define PMIC_RG_VDRAM1_PFM_TON_MASK   0x7
#define PMIC_RG_VDRAM1_PFM_TON_SHIFT  9
#define PMIC_RG_VDRAM1_PWMRAMP_SLP_ADDR MT6358_VDRAM1_ANA_CON0
#define PMIC_RG_VDRAM1_PWMRAMP_SLP_MASK 0x7
#define PMIC_RG_VDRAM1_PWMRAMP_SLP_SHIFT   12
#define PMIC_RG_VDRAM1_COTRAMP_SLP_ADDR MT6358_VDRAM1_ANA_CON1
#define PMIC_RG_VDRAM1_COTRAMP_SLP_MASK 0x7
#define PMIC_RG_VDRAM1_COTRAMP_SLP_SHIFT   0
#define PMIC_RG_VDRAM1_RCS_ADDR MT6358_VDRAM1_ANA_CON1
#define PMIC_RG_VDRAM1_RCS_MASK 0x7
#define PMIC_RG_VDRAM1_RCS_SHIFT  3
#define PMIC_RG_VDRAM1_SLEEP_TIME_ADDR  MT6358_VDRAM1_ANA_CON1
#define PMIC_RG_VDRAM1_SLEEP_TIME_MASK  0x3
#define PMIC_RG_VDRAM1_SLEEP_TIME_SHIFT 6
#define PMIC_RG_VDRAM1_NLIM_GATING_ADDR MT6358_VDRAM1_ANA_CON1
#define PMIC_RG_VDRAM1_NLIM_GATING_MASK 0x1
#define PMIC_RG_VDRAM1_NLIM_GATING_SHIFT   8
#define PMIC_RG_VDRAM1_VDIFF_OFF_ADDR MT6358_VDRAM1_ANA_CON1
#define PMIC_RG_VDRAM1_VDIFF_OFF_MASK 0x1
#define PMIC_RG_VDRAM1_VDIFF_OFF_SHIFT  9
#define PMIC_RG_VDRAM1_VREFUP_ADDR MT6358_VDRAM1_ANA_CON1
#define PMIC_RG_VDRAM1_VREFUP_MASK 0x3
#define PMIC_RG_VDRAM1_VREFUP_SHIFT   10
#define PMIC_RG_VDRAM1_TB_WIDTH_ADDR  MT6358_VDRAM1_ANA_CON1
#define PMIC_RG_VDRAM1_TB_WIDTH_MASK  0x3
#define PMIC_RG_VDRAM1_TB_WIDTH_SHIFT 12
#define PMIC_RG_VDRAM1_UG_SR_ADDR MT6358_VDRAM1_ANA_CON2
#define PMIC_RG_VDRAM1_UG_SR_MASK 0x3
#define PMIC_RG_VDRAM1_UG_SR_SHIFT 0
#define PMIC_RG_VDRAM1_LG_SR_ADDR MT6358_VDRAM1_ANA_CON2
#define PMIC_RG_VDRAM1_LG_SR_MASK 0x3
#define PMIC_RG_VDRAM1_LG_SR_SHIFT 2
#define PMIC_RG_VDRAM1_CCOMP_ADDR MT6358_VDRAM1_ANA_CON2
#define PMIC_RG_VDRAM1_CCOMP_MASK 0x3
#define PMIC_RG_VDRAM1_CCOMP_SHIFT 4
#define PMIC_RG_VDRAM1_NDIS_EN_ADDR   MT6358_VDRAM1_ANA_CON2
#define PMIC_RG_VDRAM1_NDIS_EN_MASK   0x1
#define PMIC_RG_VDRAM1_NDIS_EN_SHIFT  6
#define PMIC_RG_VDRAM1_TMDL_ADDR  MT6358_VDRAM1_ANA_CON2
#define PMIC_RG_VDRAM1_TMDL_MASK  0x1
#define PMIC_RG_VDRAM1_TMDL_SHIFT 7
#define PMIC_RG_VDRAM1_RSV_ADDR MT6358_VDRAM1_ANA_CON3
#define PMIC_RG_VDRAM1_RSV_MASK 0xFFFF
#define PMIC_RG_VDRAM1_RSV_SHIFT  0
#define PMIC_RG_VDRAM1_FUGON_ADDR MT6358_VDRAM1_ANA_CON4
#define PMIC_RG_VDRAM1_FUGON_MASK 0x1
#define PMIC_RG_VDRAM1_FUGON_SHIFT 0
#define PMIC_RG_VDRAM1_FLGON_ADDR MT6358_VDRAM1_ANA_CON4
#define PMIC_RG_VDRAM1_FLGON_MASK 0x1
#define PMIC_RG_VDRAM1_FLGON_SHIFT 1
#define PMIC_RG_VDRAM1_VDIFFPFM_OFF_ADDR   MT6358_VDRAM1_ANA_CON4
#define PMIC_RG_VDRAM1_VDIFFPFM_OFF_MASK   0x1
#define PMIC_RG_VDRAM1_VDIFFPFM_OFF_SHIFT   2
#define PMIC_RGS_VDRAM1_OC_STATUS_ADDR  MT6358_VDRAM1_ANA_CON4
#define PMIC_RGS_VDRAM1_OC_STATUS_MASK  0x1
#define PMIC_RGS_VDRAM1_OC_STATUS_SHIFT 3
#define PMIC_RGS_VDRAM1_ENPWM_STATUS_ADDR   MT6358_VDRAM1_ANA_CON4
#define PMIC_RGS_VDRAM1_ENPWM_STATUS_MASK   0x1
#define PMIC_RGS_VDRAM1_ENPWM_STATUS_SHIFT  4
#define PMIC_RG_VDRAM1_DISAUTOK_ADDR  MT6358_VDRAM1_ANA_CON4
#define PMIC_RG_VDRAM1_DISAUTOK_MASK  0x1
#define PMIC_RG_VDRAM1_DISAUTOK_SHIFT 5
#define PMIC_RGS_VDRAM1_TRIMOK_STATUS_ADDR  MT6358_VDRAM1_ANA_CON4
#define PMIC_RGS_VDRAM1_TRIMOK_STATUS_MASK  0x1
#define PMIC_RGS_VDRAM1_TRIMOK_STATUS_SHIFT 6
#define PMIC_RGS_VDRAM1_DIG_MON_ADDR  MT6358_VDRAM1_ANA_CON4
#define PMIC_RGS_VDRAM1_DIG_MON_MASK  0xFF
#define PMIC_RGS_VDRAM1_DIG_MON_SHIFT 7
#define PMIC_RG_VDRAM1_NONAUDIBLE_EN_ADDR   MT6358_VDRAM1_ANA_CON4
#define PMIC_RG_VDRAM1_NONAUDIBLE_EN_MASK   0x1
#define PMIC_RG_VDRAM1_NONAUDIBLE_EN_SHIFT  15
#define PMIC_RG_VDRAM1_CSP_ADDR MT6358_VDRAM1_ANA_CON5
#define PMIC_RG_VDRAM1_CSP_MASK 0x7
#define PMIC_RG_VDRAM1_CSP_SHIFT  0
#define PMIC_RG_VDRAM1_CSN_ADDR MT6358_VDRAM1_ANA_CON5
#define PMIC_RG_VDRAM1_CSN_MASK 0x7
#define PMIC_RG_VDRAM1_CSN_SHIFT  3
#define PMIC_RGS_VDRAM1_PFM_FLAG_ADDR MT6358_VDRAM1_ANA_CON5
#define PMIC_RGS_VDRAM1_PFM_FLAG_MASK 0x1
#define PMIC_RGS_VDRAM1_PFM_FLAG_SHIFT  6
#define PMIC_RG_VDRAM1_SONIC_PFM_TON_ADDR   MT6358_VDRAM1_ANA_CON5
#define PMIC_RG_VDRAM1_SONIC_PFM_TON_MASK   0x7
#define PMIC_RG_VDRAM1_SONIC_PFM_TON_SHIFT  7
#define PMIC_RG_VDRAM1_RETENTION_EN_ADDR   MT6358_VDRAM1_ANA_CON5
#define PMIC_RG_VDRAM1_RETENTION_EN_MASK   0x1
#define PMIC_RG_VDRAM1_RETENTION_EN_SHIFT   10
#define PMIC_RG_VS1_FCOT_ADDR   MT6358_VS1_ANA_CON0
#define PMIC_RG_VS1_FCOT_MASK   0x1
#define PMIC_RG_VS1_FCOT_SHIFT  1
#define PMIC_RG_VS1_RCOMP_ADDR  MT6358_VS1_ANA_CON0
#define PMIC_RG_VS1_RCOMP_MASK  0xF
#define PMIC_RG_VS1_RCOMP_SHIFT 2
#define PMIC_RG_VS1_TB_DIS_ADDR MT6358_VS1_ANA_CON0
#define PMIC_RG_VS1_TB_DIS_MASK 0x1
#define PMIC_RG_VS1_TB_DIS_SHIFT  6
#define PMIC_RG_VS1_DISPG_ADDR  MT6358_VS1_ANA_CON0
#define PMIC_RG_VS1_DISPG_MASK  0x1
#define PMIC_RG_VS1_DISPG_SHIFT 7
#define PMIC_RG_VS1_FPWM_ADDR   MT6358_VS1_ANA_CON0
#define PMIC_RG_VS1_FPWM_MASK   0x1
#define PMIC_RG_VS1_FPWM_SHIFT  8
#define PMIC_RG_VS1_PFM_TON_ADDR  MT6358_VS1_ANA_CON0
#define PMIC_RG_VS1_PFM_TON_MASK  0x7
#define PMIC_RG_VS1_PFM_TON_SHIFT 9
#define PMIC_RG_VS1_PWMRAMP_SLP_ADDR  MT6358_VS1_ANA_CON0
#define PMIC_RG_VS1_PWMRAMP_SLP_MASK  0x7
#define PMIC_RG_VS1_PWMRAMP_SLP_SHIFT 12
#define PMIC_RG_VS1_COTRAMP_SLP_ADDR  MT6358_VS1_ANA_CON1
#define PMIC_RG_VS1_COTRAMP_SLP_MASK  0x7
#define PMIC_RG_VS1_COTRAMP_SLP_SHIFT 0
#define PMIC_RG_VS1_RCS_ADDR MT6358_VS1_ANA_CON1
#define PMIC_RG_VS1_RCS_MASK 0x7
#define PMIC_RG_VS1_RCS_SHIFT   3
#define PMIC_RG_VS1_SLEEP_TIME_ADDR   MT6358_VS1_ANA_CON1
#define PMIC_RG_VS1_SLEEP_TIME_MASK   0x3
#define PMIC_RG_VS1_SLEEP_TIME_SHIFT  6
#define PMIC_RG_VS1_NLIM_GATING_ADDR  MT6358_VS1_ANA_CON1
#define PMIC_RG_VS1_NLIM_GATING_MASK  0x1
#define PMIC_RG_VS1_NLIM_GATING_SHIFT 8
#define PMIC_RG_VS1_VDIFF_OFF_ADDR MT6358_VS1_ANA_CON1
#define PMIC_RG_VS1_VDIFF_OFF_MASK 0x1
#define PMIC_RG_VS1_VDIFF_OFF_SHIFT   9
#define PMIC_RG_VS1_VREFUP_ADDR MT6358_VS1_ANA_CON1
#define PMIC_RG_VS1_VREFUP_MASK 0x3
#define PMIC_RG_VS1_VREFUP_SHIFT  10
#define PMIC_RG_VS1_TB_WIDTH_ADDR MT6358_VS1_ANA_CON1
#define PMIC_RG_VS1_TB_WIDTH_MASK 0x3
#define PMIC_RG_VS1_TB_WIDTH_SHIFT 12
#define PMIC_RG_VS1_UG_SR_ADDR  MT6358_VS1_ANA_CON2
#define PMIC_RG_VS1_UG_SR_MASK  0x3
#define PMIC_RG_VS1_UG_SR_SHIFT 0
#define PMIC_RG_VS1_LG_SR_ADDR  MT6358_VS1_ANA_CON2
#define PMIC_RG_VS1_LG_SR_MASK  0x3
#define PMIC_RG_VS1_LG_SR_SHIFT 2
#define PMIC_RG_VS1_CCOMP_ADDR  MT6358_VS1_ANA_CON2
#define PMIC_RG_VS1_CCOMP_MASK  0x3
#define PMIC_RG_VS1_CCOMP_SHIFT 4
#define PMIC_RG_VS1_NDIS_EN_ADDR  MT6358_VS1_ANA_CON2
#define PMIC_RG_VS1_NDIS_EN_MASK  0x1
#define PMIC_RG_VS1_NDIS_EN_SHIFT 6
#define PMIC_RG_VS1_TMDL_ADDR   MT6358_VS1_ANA_CON2
#define PMIC_RG_VS1_TMDL_MASK   0x1
#define PMIC_RG_VS1_TMDL_SHIFT  7
#define PMIC_RG_VS1_RSV_ADDR MT6358_VS1_ANA_CON3
#define PMIC_RG_VS1_RSV_MASK 0xFFFF
#define PMIC_RG_VS1_RSV_SHIFT   0
#define PMIC_RG_VS1_FUGON_ADDR  MT6358_VS1_ANA_CON4
#define PMIC_RG_VS1_FUGON_MASK  0x1
#define PMIC_RG_VS1_FUGON_SHIFT 0
#define PMIC_RG_VS1_FLGON_ADDR  MT6358_VS1_ANA_CON4
#define PMIC_RG_VS1_FLGON_MASK  0x1
#define PMIC_RG_VS1_FLGON_SHIFT 1
#define PMIC_RG_VS1_VDIFFPFM_OFF_ADDR MT6358_VS1_ANA_CON4
#define PMIC_RG_VS1_VDIFFPFM_OFF_MASK 0x1
#define PMIC_RG_VS1_VDIFFPFM_OFF_SHIFT  2
#define PMIC_RGS_VS1_OC_STATUS_ADDR   MT6358_VS1_ANA_CON4
#define PMIC_RGS_VS1_OC_STATUS_MASK   0x1
#define PMIC_RGS_VS1_OC_STATUS_SHIFT  3
#define PMIC_RGS_VS1_ENPWM_STATUS_ADDR  MT6358_VS1_ANA_CON4
#define PMIC_RGS_VS1_ENPWM_STATUS_MASK  0x1
#define PMIC_RGS_VS1_ENPWM_STATUS_SHIFT 4
#define PMIC_RG_VS1_DISAUTOK_ADDR MT6358_VS1_ANA_CON4
#define PMIC_RG_VS1_DISAUTOK_MASK 0x1
#define PMIC_RG_VS1_DISAUTOK_SHIFT 5
#define PMIC_RGS_VS1_TRIMOK_STATUS_ADDR MT6358_VS1_ANA_CON4
#define PMIC_RGS_VS1_TRIMOK_STATUS_MASK 0x1
#define PMIC_RGS_VS1_TRIMOK_STATUS_SHIFT   6
#define PMIC_RGS_VS1_DIG_MON_ADDR MT6358_VS1_ANA_CON4
#define PMIC_RGS_VS1_DIG_MON_MASK 0xFF
#define PMIC_RGS_VS1_DIG_MON_SHIFT 7
#define PMIC_RG_VS1_NONAUDIBLE_EN_ADDR  MT6358_VS1_ANA_CON4
#define PMIC_RG_VS1_NONAUDIBLE_EN_MASK  0x1
#define PMIC_RG_VS1_NONAUDIBLE_EN_SHIFT 15
#define PMIC_RG_VS1_CSP_ADDR MT6358_VS1_ANA_CON5
#define PMIC_RG_VS1_CSP_MASK 0x7
#define PMIC_RG_VS1_CSP_SHIFT   0
#define PMIC_RG_VS1_CSN_ADDR MT6358_VS1_ANA_CON5
#define PMIC_RG_VS1_CSN_MASK 0x7
#define PMIC_RG_VS1_CSN_SHIFT   3
#define PMIC_RGS_VS1_PFM_FLAG_ADDR MT6358_VS1_ANA_CON5
#define PMIC_RGS_VS1_PFM_FLAG_MASK 0x1
#define PMIC_RGS_VS1_PFM_FLAG_SHIFT   6
#define PMIC_RG_VS1_SONIC_PFM_TON_ADDR  MT6358_VS1_ANA_CON5
#define PMIC_RG_VS1_SONIC_PFM_TON_MASK  0x7
#define PMIC_RG_VS1_SONIC_PFM_TON_SHIFT 7
#define PMIC_RG_VS1_RETENTION_EN_ADDR MT6358_VS1_ANA_CON5
#define PMIC_RG_VS1_RETENTION_EN_MASK 0x1
#define PMIC_RG_VS1_RETENTION_EN_SHIFT  10
#define PMIC_RG_VS2_FCOT_ADDR   MT6358_VS2_ANA_CON0
#define PMIC_RG_VS2_FCOT_MASK   0x1
#define PMIC_RG_VS2_FCOT_SHIFT  1
#define PMIC_RG_VS2_RCOMP_ADDR  MT6358_VS2_ANA_CON0
#define PMIC_RG_VS2_RCOMP_MASK  0xF
#define PMIC_RG_VS2_RCOMP_SHIFT 2
#define PMIC_RG_VS2_TB_DIS_ADDR MT6358_VS2_ANA_CON0
#define PMIC_RG_VS2_TB_DIS_MASK 0x1
#define PMIC_RG_VS2_TB_DIS_SHIFT  6
#define PMIC_RG_VS2_DISPG_ADDR  MT6358_VS2_ANA_CON0
#define PMIC_RG_VS2_DISPG_MASK  0x1
#define PMIC_RG_VS2_DISPG_SHIFT 7
#define PMIC_RG_VS2_FPWM_ADDR   MT6358_VS2_ANA_CON0
#define PMIC_RG_VS2_FPWM_MASK   0x1
#define PMIC_RG_VS2_FPWM_SHIFT  8
#define PMIC_RG_VS2_PFM_TON_ADDR  MT6358_VS2_ANA_CON0
#define PMIC_RG_VS2_PFM_TON_MASK  0x7
#define PMIC_RG_VS2_PFM_TON_SHIFT 9
#define PMIC_RG_VS2_PWMRAMP_SLP_ADDR  MT6358_VS2_ANA_CON0
#define PMIC_RG_VS2_PWMRAMP_SLP_MASK  0x7
#define PMIC_RG_VS2_PWMRAMP_SLP_SHIFT 12
#define PMIC_RG_VS2_COTRAMP_SLP_ADDR  MT6358_VS2_ANA_CON1
#define PMIC_RG_VS2_COTRAMP_SLP_MASK  0x7
#define PMIC_RG_VS2_COTRAMP_SLP_SHIFT 0
#define PMIC_RG_VS2_RCS_ADDR MT6358_VS2_ANA_CON1
#define PMIC_RG_VS2_RCS_MASK 0x7
#define PMIC_RG_VS2_RCS_SHIFT   3
#define PMIC_RG_VS2_SLEEP_TIME_ADDR   MT6358_VS2_ANA_CON1
#define PMIC_RG_VS2_SLEEP_TIME_MASK   0x3
#define PMIC_RG_VS2_SLEEP_TIME_SHIFT  6
#define PMIC_RG_VS2_NLIM_GATING_ADDR  MT6358_VS2_ANA_CON1
#define PMIC_RG_VS2_NLIM_GATING_MASK  0x1
#define PMIC_RG_VS2_NLIM_GATING_SHIFT 8
#define PMIC_RG_VS2_VDIFF_OFF_ADDR MT6358_VS2_ANA_CON1
#define PMIC_RG_VS2_VDIFF_OFF_MASK 0x1
#define PMIC_RG_VS2_VDIFF_OFF_SHIFT   9
#define PMIC_RG_VS2_VREFUP_ADDR MT6358_VS2_ANA_CON1
#define PMIC_RG_VS2_VREFUP_MASK 0x3
#define PMIC_RG_VS2_VREFUP_SHIFT  10
#define PMIC_RG_VS2_TB_WIDTH_ADDR MT6358_VS2_ANA_CON1
#define PMIC_RG_VS2_TB_WIDTH_MASK 0x3
#define PMIC_RG_VS2_TB_WIDTH_SHIFT 12
#define PMIC_RG_VS2_UG_SR_ADDR  MT6358_VS2_ANA_CON2
#define PMIC_RG_VS2_UG_SR_MASK  0x3
#define PMIC_RG_VS2_UG_SR_SHIFT 0
#define PMIC_RG_VS2_LG_SR_ADDR  MT6358_VS2_ANA_CON2
#define PMIC_RG_VS2_LG_SR_MASK  0x3
#define PMIC_RG_VS2_LG_SR_SHIFT 2
#define PMIC_RG_VS2_CCOMP_ADDR  MT6358_VS2_ANA_CON2
#define PMIC_RG_VS2_CCOMP_MASK  0x3
#define PMIC_RG_VS2_CCOMP_SHIFT 4
#define PMIC_RG_VS2_NDIS_EN_ADDR  MT6358_VS2_ANA_CON2
#define PMIC_RG_VS2_NDIS_EN_MASK  0x1
#define PMIC_RG_VS2_NDIS_EN_SHIFT 6
#define PMIC_RG_VS2_TMDL_ADDR   MT6358_VS2_ANA_CON2
#define PMIC_RG_VS2_TMDL_MASK   0x1
#define PMIC_RG_VS2_TMDL_SHIFT  7
#define PMIC_RG_VS2_RSV_ADDR MT6358_VS2_ANA_CON3
#define PMIC_RG_VS2_RSV_MASK 0xFFFF
#define PMIC_RG_VS2_RSV_SHIFT   0
#define PMIC_RG_VS2_FUGON_ADDR  MT6358_VS2_ANA_CON4
#define PMIC_RG_VS2_FUGON_MASK  0x1
#define PMIC_RG_VS2_FUGON_SHIFT 0
#define PMIC_RG_VS2_FLGON_ADDR  MT6358_VS2_ANA_CON4
#define PMIC_RG_VS2_FLGON_MASK  0x1
#define PMIC_RG_VS2_FLGON_SHIFT 1
#define PMIC_RG_VS2_VDIFFPFM_OFF_ADDR MT6358_VS2_ANA_CON4
#define PMIC_RG_VS2_VDIFFPFM_OFF_MASK 0x1
#define PMIC_RG_VS2_VDIFFPFM_OFF_SHIFT  2
#define PMIC_RGS_VS2_OC_STATUS_ADDR   MT6358_VS2_ANA_CON4
#define PMIC_RGS_VS2_OC_STATUS_MASK   0x1
#define PMIC_RGS_VS2_OC_STATUS_SHIFT  3
#define PMIC_RGS_VS2_ENPWM_STATUS_ADDR  MT6358_VS2_ANA_CON4
#define PMIC_RGS_VS2_ENPWM_STATUS_MASK  0x1
#define PMIC_RGS_VS2_ENPWM_STATUS_SHIFT 4
#define PMIC_RG_VS2_DISAUTOK_ADDR MT6358_VS2_ANA_CON4
#define PMIC_RG_VS2_DISAUTOK_MASK 0x1
#define PMIC_RG_VS2_DISAUTOK_SHIFT 5
#define PMIC_RGS_VS2_TRIMOK_STATUS_ADDR MT6358_VS2_ANA_CON4
#define PMIC_RGS_VS2_TRIMOK_STATUS_MASK 0x1
#define PMIC_RGS_VS2_TRIMOK_STATUS_SHIFT   6
#define PMIC_RGS_VS2_DIG_MON_ADDR MT6358_VS2_ANA_CON4
#define PMIC_RGS_VS2_DIG_MON_MASK 0xFF
#define PMIC_RGS_VS2_DIG_MON_SHIFT 7
#define PMIC_RG_VS2_NONAUDIBLE_EN_ADDR  MT6358_VS2_ANA_CON4
#define PMIC_RG_VS2_NONAUDIBLE_EN_MASK  0x1
#define PMIC_RG_VS2_NONAUDIBLE_EN_SHIFT 15
#define PMIC_RG_VS2_CSP_ADDR MT6358_VS2_ANA_CON5
#define PMIC_RG_VS2_CSP_MASK 0x7
#define PMIC_RG_VS2_CSP_SHIFT   0
#define PMIC_RG_VS2_CSN_ADDR MT6358_VS2_ANA_CON5
#define PMIC_RG_VS2_CSN_MASK 0x7
#define PMIC_RG_VS2_CSN_SHIFT   3
#define PMIC_RGS_VS2_PFM_FLAG_ADDR MT6358_VS2_ANA_CON5
#define PMIC_RGS_VS2_PFM_FLAG_MASK 0x1
#define PMIC_RGS_VS2_PFM_FLAG_SHIFT   6
#define PMIC_RG_VS2_SONIC_PFM_TON_ADDR  MT6358_VS2_ANA_CON5
#define PMIC_RG_VS2_SONIC_PFM_TON_MASK  0x7
#define PMIC_RG_VS2_SONIC_PFM_TON_SHIFT 7
#define PMIC_RG_VS2_RETENTION_EN_ADDR MT6358_VS2_ANA_CON5
#define PMIC_RG_VS2_RETENTION_EN_MASK 0x1
#define PMIC_RG_VS2_RETENTION_EN_SHIFT  10
#define PMIC_RG_VPA_NDIS_EN_ADDR  MT6358_VPA_ANA_CON0
#define PMIC_RG_VPA_NDIS_EN_MASK  0x1
#define PMIC_RG_VPA_NDIS_EN_SHIFT 1
#define PMIC_RG_VPA_MODESET_ADDR  MT6358_VPA_ANA_CON0
#define PMIC_RG_VPA_MODESET_MASK  0x1
#define PMIC_RG_VPA_MODESET_SHIFT 3
#define PMIC_RG_VPA_CC_ADDR  MT6358_VPA_ANA_CON1
#define PMIC_RG_VPA_CC_MASK  0x3
#define PMIC_RG_VPA_CC_SHIFT 0
#define PMIC_RG_VPA_CSR_ADDR MT6358_VPA_ANA_CON1
#define PMIC_RG_VPA_CSR_MASK 0x3
#define PMIC_RG_VPA_CSR_SHIFT   2
#define PMIC_RG_VPA_CSMIR_ADDR  MT6358_VPA_ANA_CON1
#define PMIC_RG_VPA_CSMIR_MASK  0x3
#define PMIC_RG_VPA_CSMIR_SHIFT 4
#define PMIC_RG_VPA_CSL_ADDR MT6358_VPA_ANA_CON1
#define PMIC_RG_VPA_CSL_MASK 0x3
#define PMIC_RG_VPA_CSL_SHIFT   6
#define PMIC_RG_VPA_SLP_ADDR MT6358_VPA_ANA_CON1
#define PMIC_RG_VPA_SLP_MASK 0x3
#define PMIC_RG_VPA_SLP_SHIFT   8
#define PMIC_RG_VPA_AZC_EN_ADDR MT6358_VPA_ANA_CON1
#define PMIC_RG_VPA_AZC_EN_MASK 0x1
#define PMIC_RG_VPA_AZC_EN_SHIFT  10
#define PMIC_RG_VPA_CP_FWUPOFF_ADDR   MT6358_VPA_ANA_CON1
#define PMIC_RG_VPA_CP_FWUPOFF_MASK   0x1
#define PMIC_RG_VPA_CP_FWUPOFF_SHIFT  11
#define PMIC_RG_VPA_AZC_DELAY_ADDR MT6358_VPA_ANA_CON1
#define PMIC_RG_VPA_AZC_DELAY_MASK 0x3
#define PMIC_RG_VPA_AZC_DELAY_SHIFT   12
#define PMIC_RG_VPA_RZSEL_ADDR  MT6358_VPA_ANA_CON1
#define PMIC_RG_VPA_RZSEL_MASK  0x3
#define PMIC_RG_VPA_RZSEL_SHIFT 14
#define PMIC_RG_VPA_HZP_ADDR MT6358_VPA_ANA_CON2
#define PMIC_RG_VPA_HZP_MASK 0x1
#define PMIC_RG_VPA_HZP_SHIFT   0
#define PMIC_RG_VPA_BWEX_GAT_ADDR MT6358_VPA_ANA_CON2
#define PMIC_RG_VPA_BWEX_GAT_MASK 0x1
#define PMIC_RG_VPA_BWEX_GAT_SHIFT 1
#define PMIC_RG_VPA_SLEW_ADDR   MT6358_VPA_ANA_CON2
#define PMIC_RG_VPA_SLEW_MASK   0x3
#define PMIC_RG_VPA_SLEW_SHIFT  2
#define PMIC_RG_VPA_SLEW_NMOS_ADDR MT6358_VPA_ANA_CON2
#define PMIC_RG_VPA_SLEW_NMOS_MASK 0x3
#define PMIC_RG_VPA_SLEW_NMOS_SHIFT   4
#define PMIC_RG_VPA_MIN_ON_ADDR MT6358_VPA_ANA_CON2
#define PMIC_RG_VPA_MIN_ON_MASK 0x3
#define PMIC_RG_VPA_MIN_ON_SHIFT  6
#define PMIC_RG_VPA_VBAT_DEL_ADDR MT6358_VPA_ANA_CON2
#define PMIC_RG_VPA_VBAT_DEL_MASK 0x3
#define PMIC_RG_VPA_VBAT_DEL_SHIFT 8
#define PMIC_RGS_VPA_AZC_VOS_SEL_ADDR MT6358_VPA_ANA_CON3
#define PMIC_RGS_VPA_AZC_VOS_SEL_MASK 0xFF
#define PMIC_RGS_VPA_AZC_VOS_SEL_SHIFT  0
#define PMIC_RG_VPA_MIN_PK_ADDR MT6358_VPA_ANA_CON3
#define PMIC_RG_VPA_MIN_PK_MASK 0x3
#define PMIC_RG_VPA_MIN_PK_SHIFT  8
#define PMIC_RG_VPA_RSV1_ADDR   MT6358_VPA_ANA_CON4
#define PMIC_RG_VPA_RSV1_MASK   0xFF
#define PMIC_RG_VPA_RSV1_SHIFT  0
#define PMIC_RG_VPA_RSV2_ADDR   MT6358_VPA_ANA_CON4
#define PMIC_RG_VPA_RSV2_MASK   0xFF
#define PMIC_RG_VPA_RSV2_SHIFT  8
#define PMIC_RGS_VPA_OC_STATUS_ADDR   MT6358_VPA_ANA_CON5
#define PMIC_RGS_VPA_OC_STATUS_MASK   0x1
#define PMIC_RGS_VPA_OC_STATUS_SHIFT  0
#define PMIC_RGS_VPA_AZC_ZX_ADDR  MT6358_VPA_ANA_CON5
#define PMIC_RGS_VPA_AZC_ZX_MASK  0x1
#define PMIC_RGS_VPA_AZC_ZX_SHIFT 1
#define PMIC_RGS_VPA_DIG_MON_ADDR MT6358_VPA_ANA_CON5
#define PMIC_RGS_VPA_DIG_MON_MASK 0x7
#define PMIC_RGS_VPA_DIG_MON_SHIFT 2
#define PMIC_BUCK_ANA1_ELR_LEN_ADDR   MT6358_BUCK_ANA1_ELR_NUM
#define PMIC_BUCK_ANA1_ELR_LEN_MASK   0xFF
#define PMIC_BUCK_ANA1_ELR_LEN_SHIFT  0
#define PMIC_RG_VMODEM_ZC_TRIM_ADDR   MT6358_VMODEM_ELR_0
#define PMIC_RG_VMODEM_ZC_TRIM_MASK   0x3
#define PMIC_RG_VMODEM_ZC_TRIM_SHIFT  0
#define PMIC_RG_VMODEM_NLIM_TRIM_ADDR MT6358_VMODEM_ELR_0
#define PMIC_RG_VMODEM_NLIM_TRIM_MASK 0xF
#define PMIC_RG_VMODEM_NLIM_TRIM_SHIFT  2
#define PMIC_RG_VMODEM_TON_TRIM_ADDR  MT6358_VMODEM_ELR_0
#define PMIC_RG_VMODEM_TON_TRIM_MASK  0x3F
#define PMIC_RG_VMODEM_TON_TRIM_SHIFT 6
#define PMIC_RG_VMODEM_RPSI_TRIM_ADDR MT6358_VMODEM_ELR_1
#define PMIC_RG_VMODEM_RPSI_TRIM_MASK 0x7
#define PMIC_RG_VMODEM_RPSI_TRIM_SHIFT  0
#define PMIC_RG_VMODEM_CSNSLP_TRIM_ADDR MT6358_VMODEM_ELR_1
#define PMIC_RG_VMODEM_CSNSLP_TRIM_MASK 0xF
#define PMIC_RG_VMODEM_CSNSLP_TRIM_SHIFT   3
#define PMIC_RG_VMODEM_CSPSLP_TRIM_ADDR MT6358_VMODEM_ELR_1
#define PMIC_RG_VMODEM_CSPSLP_TRIM_MASK 0xF
#define PMIC_RG_VMODEM_CSPSLP_TRIM_SHIFT   7
#define PMIC_RG_VDRAM1_ZC_TRIM_ADDR   MT6358_VDRAM1_ELR_0
#define PMIC_RG_VDRAM1_ZC_TRIM_MASK   0x3
#define PMIC_RG_VDRAM1_ZC_TRIM_SHIFT  0
#define PMIC_RG_VDRAM1_NLIM_TRIM_ADDR MT6358_VDRAM1_ELR_0
#define PMIC_RG_VDRAM1_NLIM_TRIM_MASK 0xF
#define PMIC_RG_VDRAM1_NLIM_TRIM_SHIFT  2
#define PMIC_RG_VDRAM1_TON_TRIM_ADDR  MT6358_VDRAM1_ELR_0
#define PMIC_RG_VDRAM1_TON_TRIM_MASK  0x3F
#define PMIC_RG_VDRAM1_TON_TRIM_SHIFT 6
#define PMIC_RG_VDRAM1_RPSI_TRIM_ADDR MT6358_VDRAM1_ELR_1
#define PMIC_RG_VDRAM1_RPSI_TRIM_MASK 0x7
#define PMIC_RG_VDRAM1_RPSI_TRIM_SHIFT  0
#define PMIC_RG_VDRAM1_CSNSLP_TRIM_ADDR MT6358_VDRAM1_ELR_1
#define PMIC_RG_VDRAM1_CSNSLP_TRIM_MASK 0xF
#define PMIC_RG_VDRAM1_CSNSLP_TRIM_SHIFT   3
#define PMIC_RG_VDRAM1_CSPSLP_TRIM_ADDR MT6358_VDRAM1_ELR_1
#define PMIC_RG_VDRAM1_CSPSLP_TRIM_MASK 0xF
#define PMIC_RG_VDRAM1_CSPSLP_TRIM_SHIFT   7
#define PMIC_RG_VS1_ZC_TRIM_ADDR  MT6358_VS1_ELR_0
#define PMIC_RG_VS1_ZC_TRIM_MASK  0x3
#define PMIC_RG_VS1_ZC_TRIM_SHIFT 0
#define PMIC_RG_VS1_NLIM_TRIM_ADDR MT6358_VS1_ELR_0
#define PMIC_RG_VS1_NLIM_TRIM_MASK 0xF
#define PMIC_RG_VS1_NLIM_TRIM_SHIFT   2
#define PMIC_RG_VS1_TON_TRIM_ADDR MT6358_VS1_ELR_0
#define PMIC_RG_VS1_TON_TRIM_MASK 0x3F
#define PMIC_RG_VS1_TON_TRIM_SHIFT 6
#define PMIC_RG_VS1_RPSI_TRIM_ADDR MT6358_VS1_ELR_1
#define PMIC_RG_VS1_RPSI_TRIM_MASK 0x7
#define PMIC_RG_VS1_RPSI_TRIM_SHIFT   0
#define PMIC_RG_VS1_CSNSLP_TRIM_ADDR  MT6358_VS1_ELR_1
#define PMIC_RG_VS1_CSNSLP_TRIM_MASK  0xF
#define PMIC_RG_VS1_CSNSLP_TRIM_SHIFT 3
#define PMIC_RG_VS1_CSPSLP_TRIM_ADDR  MT6358_VS1_ELR_1
#define PMIC_RG_VS1_CSPSLP_TRIM_MASK  0xF
#define PMIC_RG_VS1_CSPSLP_TRIM_SHIFT 7
#define PMIC_RG_VS2_ZC_TRIM_ADDR  MT6358_VS2_ELR_0
#define PMIC_RG_VS2_ZC_TRIM_MASK  0x3
#define PMIC_RG_VS2_ZC_TRIM_SHIFT 0
#define PMIC_RG_VS2_NLIM_TRIM_ADDR MT6358_VS2_ELR_0
#define PMIC_RG_VS2_NLIM_TRIM_MASK 0xF
#define PMIC_RG_VS2_NLIM_TRIM_SHIFT   2
#define PMIC_RG_VS2_TON_TRIM_ADDR MT6358_VS2_ELR_0
#define PMIC_RG_VS2_TON_TRIM_MASK 0x3F
#define PMIC_RG_VS2_TON_TRIM_SHIFT 6
#define PMIC_RG_VS2_RPSI_TRIM_ADDR MT6358_VS2_ELR_1
#define PMIC_RG_VS2_RPSI_TRIM_MASK 0x7
#define PMIC_RG_VS2_RPSI_TRIM_SHIFT   0
#define PMIC_RG_VS2_CSNSLP_TRIM_ADDR  MT6358_VS2_ELR_1
#define PMIC_RG_VS2_CSNSLP_TRIM_MASK  0xF
#define PMIC_RG_VS2_CSNSLP_TRIM_SHIFT 3
#define PMIC_RG_VS2_CSPSLP_TRIM_ADDR  MT6358_VS2_ELR_1
#define PMIC_RG_VS2_CSPSLP_TRIM_MASK  0xF
#define PMIC_RG_VS2_CSPSLP_TRIM_SHIFT 7
#define PMIC_RG_VPA_ZXREF_ADDR  MT6358_VPA_ELR_0
#define PMIC_RG_VPA_ZXREF_MASK  0xFF
#define PMIC_RG_VPA_ZXREF_SHIFT 0
#define PMIC_RG_VPA_NLIM_SEL_ADDR MT6358_VPA_ELR_0
#define PMIC_RG_VPA_NLIM_SEL_MASK 0xF
#define PMIC_RG_VPA_NLIM_SEL_SHIFT 8
#define PMIC_LDO_TOP_ANA_ID_ADDR  MT6358_LDO_TOP_ID
#define PMIC_LDO_TOP_ANA_ID_MASK  0xFF
#define PMIC_LDO_TOP_ANA_ID_SHIFT 0
#define PMIC_LDO_TOP_DIG_ID_ADDR  MT6358_LDO_TOP_ID
#define PMIC_LDO_TOP_DIG_ID_MASK  0xFF
#define PMIC_LDO_TOP_DIG_ID_SHIFT 8
#define PMIC_LDO_TOP_ANA_MINOR_REV_ADDR MT6358_LDO_TOP_REV0
#define PMIC_LDO_TOP_ANA_MINOR_REV_MASK 0xF
#define PMIC_LDO_TOP_ANA_MINOR_REV_SHIFT   0
#define PMIC_LDO_TOP_ANA_MAJOR_REV_ADDR MT6358_LDO_TOP_REV0
#define PMIC_LDO_TOP_ANA_MAJOR_REV_MASK 0xF
#define PMIC_LDO_TOP_ANA_MAJOR_REV_SHIFT   4
#define PMIC_LDO_TOP_DIG_MINOR_REV_ADDR MT6358_LDO_TOP_REV0
#define PMIC_LDO_TOP_DIG_MINOR_REV_MASK 0xF
#define PMIC_LDO_TOP_DIG_MINOR_REV_SHIFT   8
#define PMIC_LDO_TOP_DIG_MAJOR_REV_ADDR MT6358_LDO_TOP_REV0
#define PMIC_LDO_TOP_DIG_MAJOR_REV_MASK 0xF
#define PMIC_LDO_TOP_DIG_MAJOR_REV_SHIFT   12
#define PMIC_LDO_TOP_CBS_ADDR   MT6358_LDO_TOP_DBI
#define PMIC_LDO_TOP_CBS_MASK   0x3
#define PMIC_LDO_TOP_CBS_SHIFT  0
#define PMIC_LDO_TOP_BIX_ADDR   MT6358_LDO_TOP_DBI
#define PMIC_LDO_TOP_BIX_MASK   0x3
#define PMIC_LDO_TOP_BIX_SHIFT  2
#define PMIC_LDO_TOP_ESP_ADDR   MT6358_LDO_TOP_DBI
#define PMIC_LDO_TOP_ESP_MASK   0xFF
#define PMIC_LDO_TOP_ESP_SHIFT  8
#define PMIC_LDO_TOP_FPI_ADDR   MT6358_LDO_TOP_DXI
#define PMIC_LDO_TOP_FPI_MASK   0xFF
#define PMIC_LDO_TOP_FPI_SHIFT  0
#define PMIC_LDO_TOP_CLK_OFFSET_ADDR  MT6358_LDO_TPM0
#define PMIC_LDO_TOP_CLK_OFFSET_MASK  0xFF
#define PMIC_LDO_TOP_CLK_OFFSET_SHIFT 0
#define PMIC_LDO_TOP_RST_OFFSET_ADDR  MT6358_LDO_TPM0
#define PMIC_LDO_TOP_RST_OFFSET_MASK  0xFF
#define PMIC_LDO_TOP_RST_OFFSET_SHIFT 8
#define PMIC_LDO_TOP_INT_OFFSET_ADDR  MT6358_LDO_TPM1
#define PMIC_LDO_TOP_INT_OFFSET_MASK  0xFF
#define PMIC_LDO_TOP_INT_OFFSET_SHIFT 0
#define PMIC_LDO_TOP_INT_LEN_ADDR MT6358_LDO_TPM1
#define PMIC_LDO_TOP_INT_LEN_MASK 0xFF
#define PMIC_LDO_TOP_INT_LEN_SHIFT 8
#define PMIC_RG_LDO_32K_CK_PDN_ADDR   MT6358_LDO_TOP_CKPDN_CON0
#define PMIC_RG_LDO_32K_CK_PDN_MASK   0x1
#define PMIC_RG_LDO_32K_CK_PDN_SHIFT  0
#define PMIC_RG_LDO_INTRP_CK_PDN_ADDR MT6358_LDO_TOP_CKPDN_CON0
#define PMIC_RG_LDO_INTRP_CK_PDN_MASK 0x1
#define PMIC_RG_LDO_INTRP_CK_PDN_SHIFT  1
#define PMIC_RG_LDO_32K_CK_PDN_HWEN_ADDR   MT6358_TOP_TOP_CKHWEN_CON0
#define PMIC_RG_LDO_32K_CK_PDN_HWEN_MASK   0x1
#define PMIC_RG_LDO_32K_CK_PDN_HWEN_SHIFT   0
#define PMIC_RG_LDO_INTRP_CK_PDN_HWEN_ADDR  MT6358_TOP_TOP_CKHWEN_CON0
#define PMIC_RG_LDO_INTRP_CK_PDN_HWEN_MASK  0x1
#define PMIC_RG_LDO_INTRP_CK_PDN_HWEN_SHIFT 1
#define PMIC_RG_LDO_DCM_MODE_ADDR MT6358_LDO_TOP_CLK_DCM_CON0
#define PMIC_RG_LDO_DCM_MODE_MASK 0x1
#define PMIC_RG_LDO_DCM_MODE_SHIFT 0
#define PMIC_RG_LDO_VFE28_CK_SW_MODE_ADDR   MT6358_LDO_TOP_CLK_VFE28_CON0
#define PMIC_RG_LDO_VFE28_CK_SW_MODE_MASK   0x1
#define PMIC_RG_LDO_VFE28_CK_SW_MODE_SHIFT  0
#define PMIC_RG_LDO_VXO22_CK_SW_MODE_ADDR   MT6358_LDO_TOP_CLK_VXO22_CON0
#define PMIC_RG_LDO_VXO22_CK_SW_MODE_MASK   0x1
#define PMIC_RG_LDO_VXO22_CK_SW_MODE_SHIFT  0
#define PMIC_RG_LDO_VRF18_CK_SW_MODE_ADDR   MT6358_LDO_TOP_CLK_VRF18_CON0
#define PMIC_RG_LDO_VRF18_CK_SW_MODE_MASK   0x1
#define PMIC_RG_LDO_VRF18_CK_SW_MODE_SHIFT  0
#define PMIC_RG_LDO_VRF12_CK_SW_MODE_ADDR   MT6358_LDO_TOP_CLK_VRF12_CON0
#define PMIC_RG_LDO_VRF12_CK_SW_MODE_MASK   0x1
#define PMIC_RG_LDO_VRF12_CK_SW_MODE_SHIFT  0
#define PMIC_RG_LDO_VEFUSE_CK_SW_MODE_ADDR  MT6358_LDO_TOP_CLK_VEFUSE_CON0
#define PMIC_RG_LDO_VEFUSE_CK_SW_MODE_MASK  0x1
#define PMIC_RG_LDO_VEFUSE_CK_SW_MODE_SHIFT 0
#define PMIC_RG_LDO_VCN33_CK_SW_MODE_ADDR   MT6358_LDO_TOP_CLK_VCN33_CON0
#define PMIC_RG_LDO_VCN33_CK_SW_MODE_MASK   0x1
#define PMIC_RG_LDO_VCN33_CK_SW_MODE_SHIFT  0
#define PMIC_RG_LDO_VCN28_CK_SW_MODE_ADDR   MT6358_LDO_TOP_CLK_VCN28_CON0
#define PMIC_RG_LDO_VCN28_CK_SW_MODE_MASK   0x1
#define PMIC_RG_LDO_VCN28_CK_SW_MODE_SHIFT  0
#define PMIC_RG_LDO_VCN18_CK_SW_MODE_ADDR   MT6358_LDO_TOP_CLK_VCN18_CON0
#define PMIC_RG_LDO_VCN18_CK_SW_MODE_MASK   0x1
#define PMIC_RG_LDO_VCN18_CK_SW_MODE_SHIFT  0
#define PMIC_RG_LDO_VCAMA1_CK_SW_MODE_ADDR  MT6358_LDO_TOP_CLK_VCAMA1_CON0
#define PMIC_RG_LDO_VCAMA1_CK_SW_MODE_MASK  0x1
#define PMIC_RG_LDO_VCAMA1_CK_SW_MODE_SHIFT 0
#define PMIC_RG_LDO_VCAMA2_CK_SW_MODE_ADDR  MT6358_LDO_TOP_CLK_VCAMA2_CON0
#define PMIC_RG_LDO_VCAMA2_CK_SW_MODE_MASK  0x1
#define PMIC_RG_LDO_VCAMA2_CK_SW_MODE_SHIFT 0
#define PMIC_RG_LDO_VCAMD_CK_SW_MODE_ADDR   MT6358_LDO_TOP_CLK_VCAMD_CON0
#define PMIC_RG_LDO_VCAMD_CK_SW_MODE_MASK   0x1
#define PMIC_RG_LDO_VCAMD_CK_SW_MODE_SHIFT  0
#define PMIC_RG_LDO_VCAMIO_CK_SW_MODE_ADDR  MT6358_LDO_TOP_CLK_VCAMIO_CON0
#define PMIC_RG_LDO_VCAMIO_CK_SW_MODE_MASK  0x1
#define PMIC_RG_LDO_VCAMIO_CK_SW_MODE_SHIFT 0
#define PMIC_RG_LDO_VLDO28_CK_SW_MODE_ADDR  MT6358_LDO_TOP_CLK_VLDO28_CON0
#define PMIC_RG_LDO_VLDO28_CK_SW_MODE_MASK  0x1
#define PMIC_RG_LDO_VLDO28_CK_SW_MODE_SHIFT 0
#define PMIC_RG_LDO_VA12_CK_SW_MODE_ADDR   MT6358_LDO_TOP_CLK_VA12_CON0
#define PMIC_RG_LDO_VA12_CK_SW_MODE_MASK   0x1
#define PMIC_RG_LDO_VA12_CK_SW_MODE_SHIFT   0
#define PMIC_RG_LDO_VAUX18_CK_SW_MODE_ADDR  MT6358_LDO_TOP_CLK_VAUX18_CON0
#define PMIC_RG_LDO_VAUX18_CK_SW_MODE_MASK  0x1
#define PMIC_RG_LDO_VAUX18_CK_SW_MODE_SHIFT 0
#define PMIC_RG_LDO_VAUD28_CK_SW_MODE_ADDR  MT6358_LDO_TOP_CLK_VAUD28_CON0
#define PMIC_RG_LDO_VAUD28_CK_SW_MODE_MASK  0x1
#define PMIC_RG_LDO_VAUD28_CK_SW_MODE_SHIFT 0
#define PMIC_RG_LDO_VIO28_CK_SW_MODE_ADDR   MT6358_LDO_TOP_CLK_VIO28_CON0
#define PMIC_RG_LDO_VIO28_CK_SW_MODE_MASK   0x1
#define PMIC_RG_LDO_VIO28_CK_SW_MODE_SHIFT  0
#define PMIC_RG_LDO_VIO18_CK_SW_MODE_ADDR   MT6358_LDO_TOP_CLK_VIO18_CON0
#define PMIC_RG_LDO_VIO18_CK_SW_MODE_MASK   0x1
#define PMIC_RG_LDO_VIO18_CK_SW_MODE_SHIFT  0
#define PMIC_RG_LDO_VSRAM_PROC11_CK_SW_MODE_ADDR  \
MT6358_LDO_TOP_CLK_VSRAM_PROC11_CON0
#define PMIC_RG_LDO_VSRAM_PROC11_CK_SW_MODE_MASK  0x1
#define PMIC_RG_LDO_VSRAM_PROC11_CK_SW_MODE_SHIFT 0
#define PMIC_RG_LDO_VSRAM_PROC11_OSC_SEL_DIS_ADDR \
MT6358_LDO_TOP_CLK_VSRAM_PROC11_CON0
#define PMIC_RG_LDO_VSRAM_PROC11_OSC_SEL_DIS_MASK 0x1
#define PMIC_RG_LDO_VSRAM_PROC11_OSC_SEL_DIS_SHIFT  2
#define PMIC_RG_LDO_VSRAM_PROC12_CK_SW_MODE_ADDR  \
MT6358_LDO_TOP_CLK_VSRAM_PROC12_CON0
#define PMIC_RG_LDO_VSRAM_PROC12_CK_SW_MODE_MASK  0x1
#define PMIC_RG_LDO_VSRAM_PROC12_CK_SW_MODE_SHIFT 0
#define PMIC_RG_LDO_VSRAM_PROC12_OSC_SEL_DIS_ADDR \
MT6358_LDO_TOP_CLK_VSRAM_PROC12_CON0
#define PMIC_RG_LDO_VSRAM_PROC12_OSC_SEL_DIS_MASK 0x1
#define PMIC_RG_LDO_VSRAM_PROC12_OSC_SEL_DIS_SHIFT  2
#define PMIC_RG_LDO_VSRAM_OTHERS_CK_SW_MODE_ADDR  \
MT6358_LDO_TOP_CLK_VSRAM_OTHERS_CON0
#define PMIC_RG_LDO_VSRAM_OTHERS_CK_SW_MODE_MASK  0x1
#define PMIC_RG_LDO_VSRAM_OTHERS_CK_SW_MODE_SHIFT 0
#define PMIC_RG_LDO_VSRAM_OTHERS_OSC_SEL_DIS_ADDR \
MT6358_LDO_TOP_CLK_VSRAM_OTHERS_CON0
#define PMIC_RG_LDO_VSRAM_OTHERS_OSC_SEL_DIS_MASK 0x1
#define PMIC_RG_LDO_VSRAM_OTHERS_OSC_SEL_DIS_SHIFT  2
#define PMIC_RG_LDO_VSRAM_GPU_CK_SW_MODE_ADDR \
MT6358_LDO_TOP_CLK_VSRAM_GPU_CON0
#define PMIC_RG_LDO_VSRAM_GPU_CK_SW_MODE_MASK 0x1
#define PMIC_RG_LDO_VSRAM_GPU_CK_SW_MODE_SHIFT   0
#define PMIC_RG_LDO_VSRAM_GPU_OSC_SEL_DIS_ADDR   \
MT6358_LDO_TOP_CLK_VSRAM_GPU_CON0
#define PMIC_RG_LDO_VSRAM_GPU_OSC_SEL_DIS_MASK   0x1
#define PMIC_RG_LDO_VSRAM_GPU_OSC_SEL_DIS_SHIFT  2
#define PMIC_RG_LDO_VDRAM2_CK_SW_MODE_ADDR  MT6358_LDO_TOP_CLK_VDRAM2_CON0
#define PMIC_RG_LDO_VDRAM2_CK_SW_MODE_MASK  0x1
#define PMIC_RG_LDO_VDRAM2_CK_SW_MODE_SHIFT 0
#define PMIC_RG_LDO_VMC_CK_SW_MODE_ADDR MT6358_LDO_TOP_CLK_VMC_CON0
#define PMIC_RG_LDO_VMC_CK_SW_MODE_MASK 0x1
#define PMIC_RG_LDO_VMC_CK_SW_MODE_SHIFT   0
#define PMIC_RG_LDO_VMCH_CK_SW_MODE_ADDR   MT6358_LDO_TOP_CLK_VMCH_CON0
#define PMIC_RG_LDO_VMCH_CK_SW_MODE_MASK   0x1
#define PMIC_RG_LDO_VMCH_CK_SW_MODE_SHIFT   0
#define PMIC_RG_LDO_VEMC_CK_SW_MODE_ADDR   MT6358_LDO_TOP_CLK_VEMC_CON0
#define PMIC_RG_LDO_VEMC_CK_SW_MODE_MASK   0x1
#define PMIC_RG_LDO_VEMC_CK_SW_MODE_SHIFT   0
#define PMIC_RG_LDO_VSIM1_CK_SW_MODE_ADDR   MT6358_LDO_TOP_CLK_VSIM1_CON0
#define PMIC_RG_LDO_VSIM1_CK_SW_MODE_MASK   0x1
#define PMIC_RG_LDO_VSIM1_CK_SW_MODE_SHIFT  0
#define PMIC_RG_LDO_VSIM2_CK_SW_MODE_ADDR   MT6358_LDO_TOP_CLK_VSIM2_CON0
#define PMIC_RG_LDO_VSIM2_CK_SW_MODE_MASK   0x1
#define PMIC_RG_LDO_VSIM2_CK_SW_MODE_SHIFT  0
#define PMIC_RG_LDO_VIBR_CK_SW_MODE_ADDR   MT6358_LDO_TOP_CLK_VIBR_CON0
#define PMIC_RG_LDO_VIBR_CK_SW_MODE_MASK   0x1
#define PMIC_RG_LDO_VIBR_CK_SW_MODE_SHIFT   0
#define PMIC_RG_LDO_VUSB_CK_SW_MODE_ADDR   MT6358_LDO_TOP_CLK_VUSB_CON0
#define PMIC_RG_LDO_VUSB_CK_SW_MODE_MASK   0x1
#define PMIC_RG_LDO_VUSB_CK_SW_MODE_SHIFT   0
#define PMIC_RG_LDO_VBIF28_CK_SW_MODE_ADDR  MT6358_LDO_TOP_CLK_VBIF28_CON0
#define PMIC_RG_LDO_VBIF28_CK_SW_MODE_MASK  0x1
#define PMIC_RG_LDO_VBIF28_CK_SW_MODE_SHIFT 0
#define PMIC_RG_INT_EN_VFE28_OC_ADDR  MT6358_LDO_TOP_INT_CON0
#define PMIC_RG_INT_EN_VFE28_OC_MASK  0x1
#define PMIC_RG_INT_EN_VFE28_OC_SHIFT 0
#define PMIC_RG_INT_EN_VXO22_OC_ADDR  MT6358_LDO_TOP_INT_CON0
#define PMIC_RG_INT_EN_VXO22_OC_MASK  0x1
#define PMIC_RG_INT_EN_VXO22_OC_SHIFT 1
#define PMIC_RG_INT_EN_VRF18_OC_ADDR  MT6358_LDO_TOP_INT_CON0
#define PMIC_RG_INT_EN_VRF18_OC_MASK  0x1
#define PMIC_RG_INT_EN_VRF18_OC_SHIFT 2
#define PMIC_RG_INT_EN_VRF12_OC_ADDR  MT6358_LDO_TOP_INT_CON0
#define PMIC_RG_INT_EN_VRF12_OC_MASK  0x1
#define PMIC_RG_INT_EN_VRF12_OC_SHIFT 3
#define PMIC_RG_INT_EN_VEFUSE_OC_ADDR MT6358_LDO_TOP_INT_CON0
#define PMIC_RG_INT_EN_VEFUSE_OC_MASK 0x1
#define PMIC_RG_INT_EN_VEFUSE_OC_SHIFT  4
#define PMIC_RG_INT_EN_VCN33_OC_ADDR  MT6358_LDO_TOP_INT_CON0
#define PMIC_RG_INT_EN_VCN33_OC_MASK  0x1
#define PMIC_RG_INT_EN_VCN33_OC_SHIFT 5
#define PMIC_RG_INT_EN_VCN28_OC_ADDR  MT6358_LDO_TOP_INT_CON0
#define PMIC_RG_INT_EN_VCN28_OC_MASK  0x1
#define PMIC_RG_INT_EN_VCN28_OC_SHIFT 6
#define PMIC_RG_INT_EN_VCN18_OC_ADDR  MT6358_LDO_TOP_INT_CON0
#define PMIC_RG_INT_EN_VCN18_OC_MASK  0x1
#define PMIC_RG_INT_EN_VCN18_OC_SHIFT 7
#define PMIC_RG_INT_EN_VCAMA1_OC_ADDR MT6358_LDO_TOP_INT_CON0
#define PMIC_RG_INT_EN_VCAMA1_OC_MASK 0x1
#define PMIC_RG_INT_EN_VCAMA1_OC_SHIFT  8
#define PMIC_RG_INT_EN_VCAMA2_OC_ADDR MT6358_LDO_TOP_INT_CON0
#define PMIC_RG_INT_EN_VCAMA2_OC_MASK 0x1
#define PMIC_RG_INT_EN_VCAMA2_OC_SHIFT  9
#define PMIC_RG_INT_EN_VCAMD_OC_ADDR  MT6358_LDO_TOP_INT_CON0
#define PMIC_RG_INT_EN_VCAMD_OC_MASK  0x1
#define PMIC_RG_INT_EN_VCAMD_OC_SHIFT 10
#define PMIC_RG_INT_EN_VCAMIO_OC_ADDR MT6358_LDO_TOP_INT_CON0
#define PMIC_RG_INT_EN_VCAMIO_OC_MASK 0x1
#define PMIC_RG_INT_EN_VCAMIO_OC_SHIFT  11
#define PMIC_RG_INT_EN_VLDO28_OC_ADDR MT6358_LDO_TOP_INT_CON0
#define PMIC_RG_INT_EN_VLDO28_OC_MASK 0x1
#define PMIC_RG_INT_EN_VLDO28_OC_SHIFT  12
#define PMIC_RG_INT_EN_VA12_OC_ADDR   MT6358_LDO_TOP_INT_CON0
#define PMIC_RG_INT_EN_VA12_OC_MASK   0x1
#define PMIC_RG_INT_EN_VA12_OC_SHIFT  13
#define PMIC_RG_INT_EN_VAUX18_OC_ADDR MT6358_LDO_TOP_INT_CON0
#define PMIC_RG_INT_EN_VAUX18_OC_MASK 0x1
#define PMIC_RG_INT_EN_VAUX18_OC_SHIFT  14
#define PMIC_RG_INT_EN_VAUD28_OC_ADDR MT6358_LDO_TOP_INT_CON0
#define PMIC_RG_INT_EN_VAUD28_OC_MASK 0x1
#define PMIC_RG_INT_EN_VAUD28_OC_SHIFT  15
#define PMIC_LDO_INT_CON0_SET_ADDR MT6358_LDO_TOP_INT_CON0_SET
#define PMIC_LDO_INT_CON0_SET_MASK 0xFFFF
#define PMIC_LDO_INT_CON0_SET_SHIFT   0
#define PMIC_LDO_INT_CON0_CLR_ADDR MT6358_LDO_TOP_INT_CON0_CLR
#define PMIC_LDO_INT_CON0_CLR_MASK 0xFFFF
#define PMIC_LDO_INT_CON0_CLR_SHIFT   0
#define PMIC_RG_INT_EN_VIO28_OC_ADDR  MT6358_LDO_TOP_INT_CON1
#define PMIC_RG_INT_EN_VIO28_OC_MASK  0x1
#define PMIC_RG_INT_EN_VIO28_OC_SHIFT 0
#define PMIC_RG_INT_EN_VIO18_OC_ADDR  MT6358_LDO_TOP_INT_CON1
#define PMIC_RG_INT_EN_VIO18_OC_MASK  0x1
#define PMIC_RG_INT_EN_VIO18_OC_SHIFT 1
#define PMIC_RG_INT_EN_VSRAM_PROC11_OC_ADDR MT6358_LDO_TOP_INT_CON1
#define PMIC_RG_INT_EN_VSRAM_PROC11_OC_MASK 0x1
#define PMIC_RG_INT_EN_VSRAM_PROC11_OC_SHIFT  2
#define PMIC_RG_INT_EN_VSRAM_PROC12_OC_ADDR MT6358_LDO_TOP_INT_CON1
#define PMIC_RG_INT_EN_VSRAM_PROC12_OC_MASK 0x1
#define PMIC_RG_INT_EN_VSRAM_PROC12_OC_SHIFT  3
#define PMIC_RG_INT_EN_VSRAM_OTHERS_OC_ADDR MT6358_LDO_TOP_INT_CON1
#define PMIC_RG_INT_EN_VSRAM_OTHERS_OC_MASK 0x1
#define PMIC_RG_INT_EN_VSRAM_OTHERS_OC_SHIFT  4
#define PMIC_RG_INT_EN_VSRAM_GPU_OC_ADDR   MT6358_LDO_TOP_INT_CON1
#define PMIC_RG_INT_EN_VSRAM_GPU_OC_MASK   0x1
#define PMIC_RG_INT_EN_VSRAM_GPU_OC_SHIFT   5
#define PMIC_RG_INT_EN_VDRAM2_OC_ADDR MT6358_LDO_TOP_INT_CON1
#define PMIC_RG_INT_EN_VDRAM2_OC_MASK 0x1
#define PMIC_RG_INT_EN_VDRAM2_OC_SHIFT  6
#define PMIC_RG_INT_EN_VMC_OC_ADDR MT6358_LDO_TOP_INT_CON1
#define PMIC_RG_INT_EN_VMC_OC_MASK 0x1
#define PMIC_RG_INT_EN_VMC_OC_SHIFT   7
#define PMIC_RG_INT_EN_VMCH_OC_ADDR   MT6358_LDO_TOP_INT_CON1
#define PMIC_RG_INT_EN_VMCH_OC_MASK   0x1
#define PMIC_RG_INT_EN_VMCH_OC_SHIFT  8
#define PMIC_RG_INT_EN_VEMC_OC_ADDR   MT6358_LDO_TOP_INT_CON1
#define PMIC_RG_INT_EN_VEMC_OC_MASK   0x1
#define PMIC_RG_INT_EN_VEMC_OC_SHIFT  9
#define PMIC_RG_INT_EN_VSIM1_OC_ADDR  MT6358_LDO_TOP_INT_CON1
#define PMIC_RG_INT_EN_VSIM1_OC_MASK  0x1
#define PMIC_RG_INT_EN_VSIM1_OC_SHIFT 10
#define PMIC_RG_INT_EN_VSIM2_OC_ADDR  MT6358_LDO_TOP_INT_CON1
#define PMIC_RG_INT_EN_VSIM2_OC_MASK  0x1
#define PMIC_RG_INT_EN_VSIM2_OC_SHIFT 11
#define PMIC_RG_INT_EN_VIBR_OC_ADDR   MT6358_LDO_TOP_INT_CON1
#define PMIC_RG_INT_EN_VIBR_OC_MASK   0x1
#define PMIC_RG_INT_EN_VIBR_OC_SHIFT  12
#define PMIC_RG_INT_EN_VUSB_OC_ADDR   MT6358_LDO_TOP_INT_CON1
#define PMIC_RG_INT_EN_VUSB_OC_MASK   0x1
#define PMIC_RG_INT_EN_VUSB_OC_SHIFT  13
#define PMIC_RG_INT_EN_VBIF28_OC_ADDR MT6358_LDO_TOP_INT_CON1
#define PMIC_RG_INT_EN_VBIF28_OC_MASK 0x1
#define PMIC_RG_INT_EN_VBIF28_OC_SHIFT  14
#define PMIC_LDO_INT_CON1_SET_ADDR MT6358_LDO_TOP_INT_CON1_SET
#define PMIC_LDO_INT_CON1_SET_MASK 0xFFFF
#define PMIC_LDO_INT_CON1_SET_SHIFT   0
#define PMIC_LDO_INT_CON1_CLR_ADDR MT6358_LDO_TOP_INT_CON1_CLR
#define PMIC_LDO_INT_CON1_CLR_MASK 0xFFFF
#define PMIC_LDO_INT_CON1_CLR_SHIFT   0
#define PMIC_RG_INT_MASK_VFE28_OC_ADDR  MT6358_LDO_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_VFE28_OC_MASK  0x1
#define PMIC_RG_INT_MASK_VFE28_OC_SHIFT 0
#define PMIC_RG_INT_MASK_VXO22_OC_ADDR  MT6358_LDO_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_VXO22_OC_MASK  0x1
#define PMIC_RG_INT_MASK_VXO22_OC_SHIFT 1
#define PMIC_RG_INT_MASK_VRF18_OC_ADDR  MT6358_LDO_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_VRF18_OC_MASK  0x1
#define PMIC_RG_INT_MASK_VRF18_OC_SHIFT 2
#define PMIC_RG_INT_MASK_VRF12_OC_ADDR  MT6358_LDO_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_VRF12_OC_MASK  0x1
#define PMIC_RG_INT_MASK_VRF12_OC_SHIFT 3
#define PMIC_RG_INT_MASK_VEFUSE_OC_ADDR MT6358_LDO_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_VEFUSE_OC_MASK 0x1
#define PMIC_RG_INT_MASK_VEFUSE_OC_SHIFT   4
#define PMIC_RG_INT_MASK_VCN33_OC_ADDR  MT6358_LDO_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_VCN33_OC_MASK  0x1
#define PMIC_RG_INT_MASK_VCN33_OC_SHIFT 5
#define PMIC_RG_INT_MASK_VCN28_OC_ADDR  MT6358_LDO_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_VCN28_OC_MASK  0x1
#define PMIC_RG_INT_MASK_VCN28_OC_SHIFT 6
#define PMIC_RG_INT_MASK_VCN18_OC_ADDR  MT6358_LDO_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_VCN18_OC_MASK  0x1
#define PMIC_RG_INT_MASK_VCN18_OC_SHIFT 7
#define PMIC_RG_INT_MASK_VCAMA1_OC_ADDR MT6358_LDO_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_VCAMA1_OC_MASK 0x1
#define PMIC_RG_INT_MASK_VCAMA1_OC_SHIFT   8
#define PMIC_RG_INT_MASK_VCAMA2_OC_ADDR MT6358_LDO_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_VCAMA2_OC_MASK 0x1
#define PMIC_RG_INT_MASK_VCAMA2_OC_SHIFT   9
#define PMIC_RG_INT_MASK_VCAMD_OC_ADDR  MT6358_LDO_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_VCAMD_OC_MASK  0x1
#define PMIC_RG_INT_MASK_VCAMD_OC_SHIFT 10
#define PMIC_RG_INT_MASK_VCAMIO_OC_ADDR MT6358_LDO_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_VCAMIO_OC_MASK 0x1
#define PMIC_RG_INT_MASK_VCAMIO_OC_SHIFT   11
#define PMIC_RG_INT_MASK_VLDO28_OC_ADDR MT6358_LDO_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_VLDO28_OC_MASK 0x1
#define PMIC_RG_INT_MASK_VLDO28_OC_SHIFT   12
#define PMIC_RG_INT_MASK_VA12_OC_ADDR MT6358_LDO_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_VA12_OC_MASK 0x1
#define PMIC_RG_INT_MASK_VA12_OC_SHIFT  13
#define PMIC_RG_INT_MASK_VAUX18_OC_ADDR MT6358_LDO_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_VAUX18_OC_MASK 0x1
#define PMIC_RG_INT_MASK_VAUX18_OC_SHIFT   14
#define PMIC_RG_INT_MASK_VAUD28_OC_ADDR MT6358_LDO_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_VAUD28_OC_MASK 0x1
#define PMIC_RG_INT_MASK_VAUD28_OC_SHIFT   15
#define PMIC_LDO_INT_MASK_CON0_SET_ADDR MT6358_LDO_TOP_INT_MASK_CON0_SET
#define PMIC_LDO_INT_MASK_CON0_SET_MASK 0xFFFF
#define PMIC_LDO_INT_MASK_CON0_SET_SHIFT   0
#define PMIC_LDO_INT_MASK_CON0_CLR_ADDR MT6358_LDO_TOP_INT_MASK_CON0_CLR
#define PMIC_LDO_INT_MASK_CON0_CLR_MASK 0xFFFF
#define PMIC_LDO_INT_MASK_CON0_CLR_SHIFT   0
#define PMIC_RG_INT_MASK_VIO28_OC_ADDR  MT6358_LDO_TOP_INT_MASK_CON1
#define PMIC_RG_INT_MASK_VIO28_OC_MASK  0x1
#define PMIC_RG_INT_MASK_VIO28_OC_SHIFT 0
#define PMIC_RG_INT_MASK_VIO18_OC_ADDR  MT6358_LDO_TOP_INT_MASK_CON1
#define PMIC_RG_INT_MASK_VIO18_OC_MASK  0x1
#define PMIC_RG_INT_MASK_VIO18_OC_SHIFT 1
#define PMIC_RG_INT_MASK_VSRAM_PROC11_OC_ADDR MT6358_LDO_TOP_INT_MASK_CON1
#define PMIC_RG_INT_MASK_VSRAM_PROC11_OC_MASK 0x1
#define PMIC_RG_INT_MASK_VSRAM_PROC11_OC_SHIFT   2
#define PMIC_RG_INT_MASK_VSRAM_PROC12_OC_ADDR MT6358_LDO_TOP_INT_MASK_CON1
#define PMIC_RG_INT_MASK_VSRAM_PROC12_OC_MASK 0x1
#define PMIC_RG_INT_MASK_VSRAM_PROC12_OC_SHIFT   3
#define PMIC_RG_INT_MASK_VSRAM_OTHERS_OC_ADDR MT6358_LDO_TOP_INT_MASK_CON1
#define PMIC_RG_INT_MASK_VSRAM_OTHERS_OC_MASK 0x1
#define PMIC_RG_INT_MASK_VSRAM_OTHERS_OC_SHIFT   4
#define PMIC_RG_INT_MASK_VSRAM_GPU_OC_ADDR  MT6358_LDO_TOP_INT_MASK_CON1
#define PMIC_RG_INT_MASK_VSRAM_GPU_OC_MASK  0x1
#define PMIC_RG_INT_MASK_VSRAM_GPU_OC_SHIFT 5
#define PMIC_RG_INT_MASK_VDRAM2_OC_ADDR MT6358_LDO_TOP_INT_MASK_CON1
#define PMIC_RG_INT_MASK_VDRAM2_OC_MASK 0x1
#define PMIC_RG_INT_MASK_VDRAM2_OC_SHIFT   6
#define PMIC_RG_INT_MASK_VMC_OC_ADDR  MT6358_LDO_TOP_INT_MASK_CON1
#define PMIC_RG_INT_MASK_VMC_OC_MASK  0x1
#define PMIC_RG_INT_MASK_VMC_OC_SHIFT 7
#define PMIC_RG_INT_MASK_VMCH_OC_ADDR MT6358_LDO_TOP_INT_MASK_CON1
#define PMIC_RG_INT_MASK_VMCH_OC_MASK 0x1
#define PMIC_RG_INT_MASK_VMCH_OC_SHIFT  8
#define PMIC_RG_INT_MASK_VEMC_OC_ADDR MT6358_LDO_TOP_INT_MASK_CON1
#define PMIC_RG_INT_MASK_VEMC_OC_MASK 0x1
#define PMIC_RG_INT_MASK_VEMC_OC_SHIFT  9
#define PMIC_RG_INT_MASK_VSIM1_OC_ADDR  MT6358_LDO_TOP_INT_MASK_CON1
#define PMIC_RG_INT_MASK_VSIM1_OC_MASK  0x1
#define PMIC_RG_INT_MASK_VSIM1_OC_SHIFT 10
#define PMIC_RG_INT_MASK_VSIM2_OC_ADDR  MT6358_LDO_TOP_INT_MASK_CON1
#define PMIC_RG_INT_MASK_VSIM2_OC_MASK  0x1
#define PMIC_RG_INT_MASK_VSIM2_OC_SHIFT 11
#define PMIC_RG_INT_MASK_VIBR_OC_ADDR MT6358_LDO_TOP_INT_MASK_CON1
#define PMIC_RG_INT_MASK_VIBR_OC_MASK 0x1
#define PMIC_RG_INT_MASK_VIBR_OC_SHIFT  12
#define PMIC_RG_INT_MASK_VUSB_OC_ADDR MT6358_LDO_TOP_INT_MASK_CON1
#define PMIC_RG_INT_MASK_VUSB_OC_MASK 0x1
#define PMIC_RG_INT_MASK_VUSB_OC_SHIFT  13
#define PMIC_RG_INT_MASK_VBIF28_OC_ADDR MT6358_LDO_TOP_INT_MASK_CON1
#define PMIC_RG_INT_MASK_VBIF28_OC_MASK 0x1
#define PMIC_RG_INT_MASK_VBIF28_OC_SHIFT   14
#define PMIC_LDO_INT_MASK_CON1_SET_ADDR MT6358_LDO_TOP_INT_MASK_CON1_SET
#define PMIC_LDO_INT_MASK_CON1_SET_MASK 0xFFFF
#define PMIC_LDO_INT_MASK_CON1_SET_SHIFT   0
#define PMIC_LDO_INT_MASK_CON1_CLR_ADDR MT6358_LDO_TOP_INT_MASK_CON1_CLR
#define PMIC_LDO_INT_MASK_CON1_CLR_MASK 0xFFFF
#define PMIC_LDO_INT_MASK_CON1_CLR_SHIFT   0
#define PMIC_RG_INT_STATUS_VFE28_OC_ADDR   MT6358_LDO_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_VFE28_OC_MASK   0x1
#define PMIC_RG_INT_STATUS_VFE28_OC_SHIFT   0
#define PMIC_RG_INT_STATUS_VXO22_OC_ADDR   MT6358_LDO_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_VXO22_OC_MASK   0x1
#define PMIC_RG_INT_STATUS_VXO22_OC_SHIFT   1
#define PMIC_RG_INT_STATUS_VRF18_OC_ADDR   MT6358_LDO_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_VRF18_OC_MASK   0x1
#define PMIC_RG_INT_STATUS_VRF18_OC_SHIFT   2
#define PMIC_RG_INT_STATUS_VRF12_OC_ADDR   MT6358_LDO_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_VRF12_OC_MASK   0x1
#define PMIC_RG_INT_STATUS_VRF12_OC_SHIFT   3
#define PMIC_RG_INT_STATUS_VEFUSE_OC_ADDR   MT6358_LDO_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_VEFUSE_OC_MASK   0x1
#define PMIC_RG_INT_STATUS_VEFUSE_OC_SHIFT  4
#define PMIC_RG_INT_STATUS_VCN33_OC_ADDR   MT6358_LDO_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_VCN33_OC_MASK   0x1
#define PMIC_RG_INT_STATUS_VCN33_OC_SHIFT   5
#define PMIC_RG_INT_STATUS_VCN28_OC_ADDR   MT6358_LDO_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_VCN28_OC_MASK   0x1
#define PMIC_RG_INT_STATUS_VCN28_OC_SHIFT   6
#define PMIC_RG_INT_STATUS_VCN18_OC_ADDR   MT6358_LDO_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_VCN18_OC_MASK   0x1
#define PMIC_RG_INT_STATUS_VCN18_OC_SHIFT   7
#define PMIC_RG_INT_STATUS_VCAMA1_OC_ADDR   MT6358_LDO_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_VCAMA1_OC_MASK   0x1
#define PMIC_RG_INT_STATUS_VCAMA1_OC_SHIFT  8
#define PMIC_RG_INT_STATUS_VCAMA2_OC_ADDR   MT6358_LDO_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_VCAMA2_OC_MASK   0x1
#define PMIC_RG_INT_STATUS_VCAMA2_OC_SHIFT  9
#define PMIC_RG_INT_STATUS_VCAMD_OC_ADDR   MT6358_LDO_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_VCAMD_OC_MASK   0x1
#define PMIC_RG_INT_STATUS_VCAMD_OC_SHIFT   10
#define PMIC_RG_INT_STATUS_VCAMIO_OC_ADDR   MT6358_LDO_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_VCAMIO_OC_MASK   0x1
#define PMIC_RG_INT_STATUS_VCAMIO_OC_SHIFT  11
#define PMIC_RG_INT_STATUS_VLDO28_OC_ADDR   MT6358_LDO_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_VLDO28_OC_MASK   0x1
#define PMIC_RG_INT_STATUS_VLDO28_OC_SHIFT  12
#define PMIC_RG_INT_STATUS_VA12_OC_ADDR MT6358_LDO_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_VA12_OC_MASK 0x1
#define PMIC_RG_INT_STATUS_VA12_OC_SHIFT   13
#define PMIC_RG_INT_STATUS_VAUX18_OC_ADDR   MT6358_LDO_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_VAUX18_OC_MASK   0x1
#define PMIC_RG_INT_STATUS_VAUX18_OC_SHIFT  14
#define PMIC_RG_INT_STATUS_VAUD28_OC_ADDR   MT6358_LDO_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_VAUD28_OC_MASK   0x1
#define PMIC_RG_INT_STATUS_VAUD28_OC_SHIFT  15
#define PMIC_RG_INT_STATUS_VIO28_OC_ADDR   MT6358_LDO_TOP_INT_STATUS1
#define PMIC_RG_INT_STATUS_VIO28_OC_MASK   0x1
#define PMIC_RG_INT_STATUS_VIO28_OC_SHIFT   0
#define PMIC_RG_INT_STATUS_VIO18_OC_ADDR   MT6358_LDO_TOP_INT_STATUS1
#define PMIC_RG_INT_STATUS_VIO18_OC_MASK   0x1
#define PMIC_RG_INT_STATUS_VIO18_OC_SHIFT   1
#define PMIC_RG_INT_STATUS_VSRAM_PROC11_OC_ADDR  MT6358_LDO_TOP_INT_STATUS1
#define PMIC_RG_INT_STATUS_VSRAM_PROC11_OC_MASK  0x1
#define PMIC_RG_INT_STATUS_VSRAM_PROC11_OC_SHIFT  2
#define PMIC_RG_INT_STATUS_VSRAM_PROC12_OC_ADDR  MT6358_LDO_TOP_INT_STATUS1
#define PMIC_RG_INT_STATUS_VSRAM_PROC12_OC_MASK  0x1
#define PMIC_RG_INT_STATUS_VSRAM_PROC12_OC_SHIFT  3
#define PMIC_RG_INT_STATUS_VSRAM_OTHERS_OC_ADDR  MT6358_LDO_TOP_INT_STATUS1
#define PMIC_RG_INT_STATUS_VSRAM_OTHERS_OC_MASK  0x1
#define PMIC_RG_INT_STATUS_VSRAM_OTHERS_OC_SHIFT  4
#define PMIC_RG_INT_STATUS_VSRAM_GPU_OC_ADDR  MT6358_LDO_TOP_INT_STATUS1
#define PMIC_RG_INT_STATUS_VSRAM_GPU_OC_MASK  0x1
#define PMIC_RG_INT_STATUS_VSRAM_GPU_OC_SHIFT 5
#define PMIC_RG_INT_STATUS_VDRAM2_OC_ADDR   MT6358_LDO_TOP_INT_STATUS1
#define PMIC_RG_INT_STATUS_VDRAM2_OC_MASK   0x1
#define PMIC_RG_INT_STATUS_VDRAM2_OC_SHIFT  6
#define PMIC_RG_INT_STATUS_VMC_OC_ADDR  MT6358_LDO_TOP_INT_STATUS1
#define PMIC_RG_INT_STATUS_VMC_OC_MASK  0x1
#define PMIC_RG_INT_STATUS_VMC_OC_SHIFT 7
#define PMIC_RG_INT_STATUS_VMCH_OC_ADDR MT6358_LDO_TOP_INT_STATUS1
#define PMIC_RG_INT_STATUS_VMCH_OC_MASK 0x1
#define PMIC_RG_INT_STATUS_VMCH_OC_SHIFT   8
#define PMIC_RG_INT_STATUS_VEMC_OC_ADDR MT6358_LDO_TOP_INT_STATUS1
#define PMIC_RG_INT_STATUS_VEMC_OC_MASK 0x1
#define PMIC_RG_INT_STATUS_VEMC_OC_SHIFT   9
#define PMIC_RG_INT_STATUS_VSIM1_OC_ADDR   MT6358_LDO_TOP_INT_STATUS1
#define PMIC_RG_INT_STATUS_VSIM1_OC_MASK   0x1
#define PMIC_RG_INT_STATUS_VSIM1_OC_SHIFT   10
#define PMIC_RG_INT_STATUS_VSIM2_OC_ADDR   MT6358_LDO_TOP_INT_STATUS1
#define PMIC_RG_INT_STATUS_VSIM2_OC_MASK   0x1
#define PMIC_RG_INT_STATUS_VSIM2_OC_SHIFT   11
#define PMIC_RG_INT_STATUS_VIBR_OC_ADDR MT6358_LDO_TOP_INT_STATUS1
#define PMIC_RG_INT_STATUS_VIBR_OC_MASK 0x1
#define PMIC_RG_INT_STATUS_VIBR_OC_SHIFT   12
#define PMIC_RG_INT_STATUS_VUSB_OC_ADDR MT6358_LDO_TOP_INT_STATUS1
#define PMIC_RG_INT_STATUS_VUSB_OC_MASK 0x1
#define PMIC_RG_INT_STATUS_VUSB_OC_SHIFT   13
#define PMIC_RG_INT_STATUS_VBIF28_OC_ADDR   MT6358_LDO_TOP_INT_STATUS1
#define PMIC_RG_INT_STATUS_VBIF28_OC_MASK   0x1
#define PMIC_RG_INT_STATUS_VBIF28_OC_SHIFT  14
#define PMIC_RG_INT_RAW_STATUS_VFE28_OC_ADDR  MT6358_LDO_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_VFE28_OC_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_VFE28_OC_SHIFT 0
#define PMIC_RG_INT_RAW_STATUS_VXO22_OC_ADDR  MT6358_LDO_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_VXO22_OC_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_VXO22_OC_SHIFT 1
#define PMIC_RG_INT_RAW_STATUS_VRF18_OC_ADDR  MT6358_LDO_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_VRF18_OC_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_VRF18_OC_SHIFT 2
#define PMIC_RG_INT_RAW_STATUS_VRF12_OC_ADDR  MT6358_LDO_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_VRF12_OC_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_VRF12_OC_SHIFT 3
#define PMIC_RG_INT_RAW_STATUS_VEFUSE_OC_ADDR MT6358_LDO_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_VEFUSE_OC_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_VEFUSE_OC_SHIFT   4
#define PMIC_RG_INT_RAW_STATUS_VCN33_OC_ADDR  MT6358_LDO_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_VCN33_OC_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_VCN33_OC_SHIFT 5
#define PMIC_RG_INT_RAW_STATUS_VCN28_OC_ADDR  MT6358_LDO_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_VCN28_OC_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_VCN28_OC_SHIFT 6
#define PMIC_RG_INT_RAW_STATUS_VCN18_OC_ADDR  MT6358_LDO_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_VCN18_OC_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_VCN18_OC_SHIFT 7
#define PMIC_RG_INT_RAW_STATUS_VCAMA1_OC_ADDR MT6358_LDO_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_VCAMA1_OC_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_VCAMA1_OC_SHIFT   8
#define PMIC_RG_INT_RAW_STATUS_VCAMA2_OC_ADDR MT6358_LDO_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_VCAMA2_OC_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_VCAMA2_OC_SHIFT   9
#define PMIC_RG_INT_RAW_STATUS_VCAMD_OC_ADDR  MT6358_LDO_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_VCAMD_OC_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_VCAMD_OC_SHIFT 10
#define PMIC_RG_INT_RAW_STATUS_VCAMIO_OC_ADDR MT6358_LDO_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_VCAMIO_OC_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_VCAMIO_OC_SHIFT   11
#define PMIC_RG_INT_RAW_STATUS_VLDO28_OC_ADDR MT6358_LDO_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_VLDO28_OC_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_VLDO28_OC_SHIFT   12
#define PMIC_RG_INT_RAW_STATUS_VA12_OC_ADDR MT6358_LDO_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_VA12_OC_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_VA12_OC_SHIFT  13
#define PMIC_RG_INT_RAW_STATUS_VAUX18_OC_ADDR MT6358_LDO_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_VAUX18_OC_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_VAUX18_OC_SHIFT   14
#define PMIC_RG_INT_RAW_STATUS_VAUD28_OC_ADDR MT6358_LDO_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_VAUD28_OC_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_VAUD28_OC_SHIFT   15
#define PMIC_RG_INT_RAW_STATUS_VIO28_OC_ADDR  MT6358_LDO_TOP_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_VIO28_OC_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_VIO28_OC_SHIFT 0
#define PMIC_RG_INT_RAW_STATUS_VIO18_OC_ADDR  MT6358_LDO_TOP_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_VIO18_OC_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_VIO18_OC_SHIFT 1
#define PMIC_RG_INT_RAW_STATUS_VSRAM_PROC11_OC_ADDR \
MT6358_LDO_TOP_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_VSRAM_PROC11_OC_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_VSRAM_PROC11_OC_SHIFT   2
#define PMIC_RG_INT_RAW_STATUS_VSRAM_PROC12_OC_ADDR \
MT6358_LDO_TOP_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_VSRAM_PROC12_OC_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_VSRAM_PROC12_OC_SHIFT   3
#define PMIC_RG_INT_RAW_STATUS_VSRAM_OTHERS_OC_ADDR \
MT6358_LDO_TOP_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_VSRAM_OTHERS_OC_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_VSRAM_OTHERS_OC_SHIFT   4
#define PMIC_RG_INT_RAW_STATUS_VSRAM_GPU_OC_ADDR  \
MT6358_LDO_TOP_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_VSRAM_GPU_OC_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_VSRAM_GPU_OC_SHIFT 5
#define PMIC_RG_INT_RAW_STATUS_VDRAM2_OC_ADDR MT6358_LDO_TOP_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_VDRAM2_OC_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_VDRAM2_OC_SHIFT   6
#define PMIC_RG_INT_RAW_STATUS_VMC_OC_ADDR  MT6358_LDO_TOP_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_VMC_OC_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_VMC_OC_SHIFT 7
#define PMIC_RG_INT_RAW_STATUS_VMCH_OC_ADDR MT6358_LDO_TOP_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_VMCH_OC_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_VMCH_OC_SHIFT  8
#define PMIC_RG_INT_RAW_STATUS_VEMC_OC_ADDR MT6358_LDO_TOP_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_VEMC_OC_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_VEMC_OC_SHIFT  9
#define PMIC_RG_INT_RAW_STATUS_VSIM1_OC_ADDR  MT6358_LDO_TOP_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_VSIM1_OC_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_VSIM1_OC_SHIFT 10
#define PMIC_RG_INT_RAW_STATUS_VSIM2_OC_ADDR  MT6358_LDO_TOP_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_VSIM2_OC_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_VSIM2_OC_SHIFT 11
#define PMIC_RG_INT_RAW_STATUS_VIBR_OC_ADDR MT6358_LDO_TOP_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_VIBR_OC_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_VIBR_OC_SHIFT  12
#define PMIC_RG_INT_RAW_STATUS_VUSB_OC_ADDR MT6358_LDO_TOP_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_VUSB_OC_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_VUSB_OC_SHIFT  13
#define PMIC_RG_INT_RAW_STATUS_VBIF28_OC_ADDR MT6358_LDO_TOP_INT_RAW_STATUS1
#define PMIC_RG_INT_RAW_STATUS_VBIF28_OC_MASK 0x1
#define PMIC_RG_INT_RAW_STATUS_VBIF28_OC_SHIFT   14
#define PMIC_RG_LDO_MON_FLAG_SEL_ADDR MT6358_LDO_TEST_CON0
#define PMIC_RG_LDO_MON_FLAG_SEL_MASK 0xFF
#define PMIC_RG_LDO_MON_FLAG_SEL_SHIFT  0
#define PMIC_RG_LDO_INT_FLAG_EN_ADDR  MT6358_LDO_TEST_CON0
#define PMIC_RG_LDO_INT_FLAG_EN_MASK  0x1
#define PMIC_RG_LDO_INT_FLAG_EN_SHIFT 9
#define PMIC_RG_LDO_MON_GRP_SEL_ADDR  MT6358_LDO_TEST_CON0
#define PMIC_RG_LDO_MON_GRP_SEL_MASK  0x1
#define PMIC_RG_LDO_MON_GRP_SEL_SHIFT 10
#define PMIC_RG_LDO_WDT_MODE_ADDR MT6358_LDO_TOP_WDT_CON0
#define PMIC_RG_LDO_WDT_MODE_MASK 0x1
#define PMIC_RG_LDO_WDT_MODE_SHIFT 0
#define PMIC_RG_LDO_TOP_RSV0_ADDR MT6358_LDO_TOP_RSV_CON0
#define PMIC_RG_LDO_TOP_RSV0_MASK 0xF
#define PMIC_RG_LDO_TOP_RSV0_SHIFT 0
#define PMIC_RG_LDO_TOP_RSV1_ADDR MT6358_LDO_TOP_RSV_CON1
#define PMIC_RG_LDO_TOP_RSV1_MASK 0xF
#define PMIC_RG_LDO_TOP_RSV1_SHIFT 0
#define PMIC_LDO_DEGTD_SEL_ADDR MT6358_LDO_OCFB0
#define PMIC_LDO_DEGTD_SEL_MASK 0x3
#define PMIC_LDO_DEGTD_SEL_SHIFT  14
#define PMIC_RG_LDO_LP_PROT_DISABLE_ADDR   MT6358_LDO_LP_PROTECTION
#define PMIC_RG_LDO_LP_PROT_DISABLE_MASK   0x1
#define PMIC_RG_LDO_LP_PROT_DISABLE_SHIFT   0
#define PMIC_RG_LDO_DUMMY_LOAD_GATED_DIS_ADDR MT6358_LDO_DUMMY_LOAD_GATED
#define PMIC_RG_LDO_DUMMY_LOAD_GATED_DIS_MASK 0x1
#define PMIC_RG_LDO_DUMMY_LOAD_GATED_DIS_SHIFT   0
#define PMIC_LDO_GON0_ANA_ID_ADDR MT6358_LDO_GON0_DSN_ID
#define PMIC_LDO_GON0_ANA_ID_MASK 0xFF
#define PMIC_LDO_GON0_ANA_ID_SHIFT 0
#define PMIC_LDO_GON0_DIG_ID_ADDR MT6358_LDO_GON0_DSN_ID
#define PMIC_LDO_GON0_DIG_ID_MASK 0xFF
#define PMIC_LDO_GON0_DIG_ID_SHIFT 8
#define PMIC_LDO_GON0_ANA_MINOR_REV_ADDR   MT6358_LDO_GON0_DSN_REV0
#define PMIC_LDO_GON0_ANA_MINOR_REV_MASK   0xF
#define PMIC_LDO_GON0_ANA_MINOR_REV_SHIFT   0
#define PMIC_LDO_GON0_ANA_MAJOR_REV_ADDR   MT6358_LDO_GON0_DSN_REV0
#define PMIC_LDO_GON0_ANA_MAJOR_REV_MASK   0xF
#define PMIC_LDO_GON0_ANA_MAJOR_REV_SHIFT   4
#define PMIC_LDO_GON0_DIG_MINOR_REV_ADDR   MT6358_LDO_GON0_DSN_REV0
#define PMIC_LDO_GON0_DIG_MINOR_REV_MASK   0xF
#define PMIC_LDO_GON0_DIG_MINOR_REV_SHIFT   8
#define PMIC_LDO_GON0_DIG_MAJOR_REV_ADDR   MT6358_LDO_GON0_DSN_REV0
#define PMIC_LDO_GON0_DIG_MAJOR_REV_MASK   0xF
#define PMIC_LDO_GON0_DIG_MAJOR_REV_SHIFT   12
#define PMIC_LDO_GON0_DSN_CBS_ADDR MT6358_LDO_GON0_DSN_DBI
#define PMIC_LDO_GON0_DSN_CBS_MASK 0x3
#define PMIC_LDO_GON0_DSN_CBS_SHIFT   0
#define PMIC_LDO_GON0_DSN_BIX_ADDR MT6358_LDO_GON0_DSN_DBI
#define PMIC_LDO_GON0_DSN_BIX_MASK 0x3
#define PMIC_LDO_GON0_DSN_BIX_SHIFT   2
#define PMIC_LDO_GON0_DSN_ESP_ADDR MT6358_LDO_GON0_DSN_DBI
#define PMIC_LDO_GON0_DSN_ESP_MASK 0xFF
#define PMIC_LDO_GON0_DSN_ESP_SHIFT   8
#define PMIC_LDO_GON0_DSN_FPI_ADDR MT6358_LDO_GON0_DSN_DXI
#define PMIC_LDO_GON0_DSN_FPI_MASK 0xFF
#define PMIC_LDO_GON0_DSN_FPI_SHIFT   0
#define PMIC_RG_LDO_VXO22_EN_ADDR MT6358_LDO_VXO22_CON0
#define PMIC_RG_LDO_VXO22_EN_MASK 0x1
#define PMIC_RG_LDO_VXO22_EN_SHIFT 0
#define PMIC_RG_LDO_VXO22_LP_ADDR MT6358_LDO_VXO22_CON0
#define PMIC_RG_LDO_VXO22_LP_MASK 0x1
#define PMIC_RG_LDO_VXO22_LP_SHIFT 1
#define PMIC_RG_LDO_VXO22_SW_OP_EN_ADDR MT6358_LDO_VXO22_OP_EN
#define PMIC_RG_LDO_VXO22_SW_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VXO22_SW_OP_EN_SHIFT   0
#define PMIC_RG_LDO_VXO22_HW0_OP_EN_ADDR   MT6358_LDO_VXO22_OP_EN
#define PMIC_RG_LDO_VXO22_HW0_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VXO22_HW0_OP_EN_SHIFT   1
#define PMIC_RG_LDO_VXO22_HW1_OP_EN_ADDR   MT6358_LDO_VXO22_OP_EN
#define PMIC_RG_LDO_VXO22_HW1_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VXO22_HW1_OP_EN_SHIFT   2
#define PMIC_RG_LDO_VXO22_HW2_OP_EN_ADDR   MT6358_LDO_VXO22_OP_EN
#define PMIC_RG_LDO_VXO22_HW2_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VXO22_HW2_OP_EN_SHIFT   3
#define PMIC_RG_LDO_VXO22_OP_EN_SET_ADDR   MT6358_LDO_VXO22_OP_EN_SET
#define PMIC_RG_LDO_VXO22_OP_EN_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VXO22_OP_EN_SET_SHIFT   0
#define PMIC_RG_LDO_VXO22_OP_EN_CLR_ADDR   MT6358_LDO_VXO22_OP_EN_CLR
#define PMIC_RG_LDO_VXO22_OP_EN_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VXO22_OP_EN_CLR_SHIFT   0
#define PMIC_RG_LDO_VXO22_HW0_OP_CFG_ADDR   MT6358_LDO_VXO22_OP_CFG
#define PMIC_RG_LDO_VXO22_HW0_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VXO22_HW0_OP_CFG_SHIFT  1
#define PMIC_RG_LDO_VXO22_HW1_OP_CFG_ADDR   MT6358_LDO_VXO22_OP_CFG
#define PMIC_RG_LDO_VXO22_HW1_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VXO22_HW1_OP_CFG_SHIFT  2
#define PMIC_RG_LDO_VXO22_HW2_OP_CFG_ADDR   MT6358_LDO_VXO22_OP_CFG
#define PMIC_RG_LDO_VXO22_HW2_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VXO22_HW2_OP_CFG_SHIFT  3
#define PMIC_RG_LDO_VXO22_OP_CFG_SET_ADDR   MT6358_LDO_VXO22_OP_CFG_SET
#define PMIC_RG_LDO_VXO22_OP_CFG_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VXO22_OP_CFG_SET_SHIFT  0
#define PMIC_RG_LDO_VXO22_OP_CFG_CLR_ADDR   MT6358_LDO_VXO22_OP_CFG_CLR
#define PMIC_RG_LDO_VXO22_OP_CFG_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VXO22_OP_CFG_CLR_SHIFT  0
#define PMIC_DA_VXO22_MODE_ADDR MT6358_LDO_VXO22_CON1
#define PMIC_DA_VXO22_MODE_MASK 0x1
#define PMIC_DA_VXO22_MODE_SHIFT  8
#define PMIC_RG_LDO_VXO22_STBTD_ADDR  MT6358_LDO_VXO22_CON1
#define PMIC_RG_LDO_VXO22_STBTD_MASK  0x3
#define PMIC_RG_LDO_VXO22_STBTD_SHIFT 9
#define PMIC_DA_VXO22_STB_ADDR  MT6358_LDO_VXO22_CON1
#define PMIC_DA_VXO22_STB_MASK  0x1
#define PMIC_DA_VXO22_STB_SHIFT 14
#define PMIC_DA_VXO22_EN_ADDR   MT6358_LDO_VXO22_CON1
#define PMIC_DA_VXO22_EN_MASK   0x1
#define PMIC_DA_VXO22_EN_SHIFT  15
#define PMIC_RG_LDO_VXO22_OCFB_EN_ADDR  MT6358_LDO_VXO22_CON2
#define PMIC_RG_LDO_VXO22_OCFB_EN_MASK  0x1
#define PMIC_RG_LDO_VXO22_OCFB_EN_SHIFT 9
#define PMIC_DA_VXO22_OCFB_EN_ADDR MT6358_LDO_VXO22_CON2
#define PMIC_DA_VXO22_OCFB_EN_MASK 0x1
#define PMIC_DA_VXO22_OCFB_EN_SHIFT   10
#define PMIC_RG_LDO_VXO22_DUMMY_LOAD_ADDR   MT6358_LDO_VXO22_CON3
#define PMIC_RG_LDO_VXO22_DUMMY_LOAD_MASK   0x3
#define PMIC_RG_LDO_VXO22_DUMMY_LOAD_SHIFT  5
#define PMIC_DA_VXO22_DUMMY_LOAD_ADDR MT6358_LDO_VXO22_CON3
#define PMIC_DA_VXO22_DUMMY_LOAD_MASK 0x3
#define PMIC_DA_VXO22_DUMMY_LOAD_SHIFT  14
#define PMIC_RG_LDO_VA12_EN_ADDR  MT6358_LDO_VA12_CON0
#define PMIC_RG_LDO_VA12_EN_MASK  0x1
#define PMIC_RG_LDO_VA12_EN_SHIFT 0
#define PMIC_RG_LDO_VA12_LP_ADDR  MT6358_LDO_VA12_CON0
#define PMIC_RG_LDO_VA12_LP_MASK  0x1
#define PMIC_RG_LDO_VA12_LP_SHIFT 1
#define PMIC_RG_LDO_VA12_SW_OP_EN_ADDR  MT6358_LDO_VA12_OP_EN
#define PMIC_RG_LDO_VA12_SW_OP_EN_MASK  0x1
#define PMIC_RG_LDO_VA12_SW_OP_EN_SHIFT 0
#define PMIC_RG_LDO_VA12_HW0_OP_EN_ADDR MT6358_LDO_VA12_OP_EN
#define PMIC_RG_LDO_VA12_HW0_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VA12_HW0_OP_EN_SHIFT   1
#define PMIC_RG_LDO_VA12_HW1_OP_EN_ADDR MT6358_LDO_VA12_OP_EN
#define PMIC_RG_LDO_VA12_HW1_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VA12_HW1_OP_EN_SHIFT   2
#define PMIC_RG_LDO_VA12_HW2_OP_EN_ADDR MT6358_LDO_VA12_OP_EN
#define PMIC_RG_LDO_VA12_HW2_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VA12_HW2_OP_EN_SHIFT   3
#define PMIC_RG_LDO_VA12_OP_EN_SET_ADDR MT6358_LDO_VA12_OP_EN_SET
#define PMIC_RG_LDO_VA12_OP_EN_SET_MASK 0xFFFF
#define PMIC_RG_LDO_VA12_OP_EN_SET_SHIFT   0
#define PMIC_RG_LDO_VA12_OP_EN_CLR_ADDR MT6358_LDO_VA12_OP_EN_CLR
#define PMIC_RG_LDO_VA12_OP_EN_CLR_MASK 0xFFFF
#define PMIC_RG_LDO_VA12_OP_EN_CLR_SHIFT   0
#define PMIC_RG_LDO_VA12_HW0_OP_CFG_ADDR   MT6358_LDO_VA12_OP_CFG
#define PMIC_RG_LDO_VA12_HW0_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VA12_HW0_OP_CFG_SHIFT   1
#define PMIC_RG_LDO_VA12_HW1_OP_CFG_ADDR   MT6358_LDO_VA12_OP_CFG
#define PMIC_RG_LDO_VA12_HW1_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VA12_HW1_OP_CFG_SHIFT   2
#define PMIC_RG_LDO_VA12_HW2_OP_CFG_ADDR   MT6358_LDO_VA12_OP_CFG
#define PMIC_RG_LDO_VA12_HW2_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VA12_HW2_OP_CFG_SHIFT   3
#define PMIC_RG_LDO_VA12_OP_CFG_SET_ADDR   MT6358_LDO_VA12_OP_CFG_SET
#define PMIC_RG_LDO_VA12_OP_CFG_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VA12_OP_CFG_SET_SHIFT   0
#define PMIC_RG_LDO_VA12_OP_CFG_CLR_ADDR   MT6358_LDO_VA12_OP_CFG_CLR
#define PMIC_RG_LDO_VA12_OP_CFG_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VA12_OP_CFG_CLR_SHIFT   0
#define PMIC_DA_VA12_MODE_ADDR  MT6358_LDO_VA12_CON1
#define PMIC_DA_VA12_MODE_MASK  0x1
#define PMIC_DA_VA12_MODE_SHIFT 8
#define PMIC_RG_LDO_VA12_STBTD_ADDR   MT6358_LDO_VA12_CON1
#define PMIC_RG_LDO_VA12_STBTD_MASK   0x3
#define PMIC_RG_LDO_VA12_STBTD_SHIFT  9
#define PMIC_DA_VA12_STB_ADDR   MT6358_LDO_VA12_CON1
#define PMIC_DA_VA12_STB_MASK   0x1
#define PMIC_DA_VA12_STB_SHIFT  14
#define PMIC_DA_VA12_EN_ADDR MT6358_LDO_VA12_CON1
#define PMIC_DA_VA12_EN_MASK 0x1
#define PMIC_DA_VA12_EN_SHIFT   15
#define PMIC_RG_LDO_VA12_AUXADC_PWDB_EN_ADDR  MT6358_LDO_VA12_CON2
#define PMIC_RG_LDO_VA12_AUXADC_PWDB_EN_MASK  0x1
#define PMIC_RG_LDO_VA12_AUXADC_PWDB_EN_SHIFT 2
#define PMIC_RG_LDO_VA12_OCFB_EN_ADDR MT6358_LDO_VA12_CON2
#define PMIC_RG_LDO_VA12_OCFB_EN_MASK 0x1
#define PMIC_RG_LDO_VA12_OCFB_EN_SHIFT  9
#define PMIC_DA_VA12_OCFB_EN_ADDR MT6358_LDO_VA12_CON2
#define PMIC_DA_VA12_OCFB_EN_MASK 0x1
#define PMIC_DA_VA12_OCFB_EN_SHIFT 10
#define PMIC_RG_LDO_VA12_DUMMY_LOAD_ADDR   MT6358_LDO_VA12_CON3
#define PMIC_RG_LDO_VA12_DUMMY_LOAD_MASK   0x3
#define PMIC_RG_LDO_VA12_DUMMY_LOAD_SHIFT   5
#define PMIC_DA_VA12_DUMMY_LOAD_ADDR  MT6358_LDO_VA12_CON3
#define PMIC_DA_VA12_DUMMY_LOAD_MASK  0x3
#define PMIC_DA_VA12_DUMMY_LOAD_SHIFT 14
#define PMIC_RG_LDO_VAUX18_EN_ADDR MT6358_LDO_VAUX18_CON0
#define PMIC_RG_LDO_VAUX18_EN_MASK 0x1
#define PMIC_RG_LDO_VAUX18_EN_SHIFT   0
#define PMIC_RG_LDO_VAUX18_LP_ADDR MT6358_LDO_VAUX18_CON0
#define PMIC_RG_LDO_VAUX18_LP_MASK 0x1
#define PMIC_RG_LDO_VAUX18_LP_SHIFT   1
#define PMIC_RG_LDO_VAUX18_SW_OP_EN_ADDR   MT6358_LDO_VAUX18_OP_EN
#define PMIC_RG_LDO_VAUX18_SW_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VAUX18_SW_OP_EN_SHIFT   0
#define PMIC_RG_LDO_VAUX18_HW0_OP_EN_ADDR   MT6358_LDO_VAUX18_OP_EN
#define PMIC_RG_LDO_VAUX18_HW0_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VAUX18_HW0_OP_EN_SHIFT  1
#define PMIC_RG_LDO_VAUX18_HW1_OP_EN_ADDR   MT6358_LDO_VAUX18_OP_EN
#define PMIC_RG_LDO_VAUX18_HW1_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VAUX18_HW1_OP_EN_SHIFT  2
#define PMIC_RG_LDO_VAUX18_HW2_OP_EN_ADDR   MT6358_LDO_VAUX18_OP_EN
#define PMIC_RG_LDO_VAUX18_HW2_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VAUX18_HW2_OP_EN_SHIFT  3
#define PMIC_RG_LDO_VAUX18_OP_EN_SET_ADDR   MT6358_LDO_VAUX18_OP_EN_SET
#define PMIC_RG_LDO_VAUX18_OP_EN_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VAUX18_OP_EN_SET_SHIFT  0
#define PMIC_RG_LDO_VAUX18_OP_EN_CLR_ADDR   MT6358_LDO_VAUX18_OP_EN_CLR
#define PMIC_RG_LDO_VAUX18_OP_EN_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VAUX18_OP_EN_CLR_SHIFT  0
#define PMIC_RG_LDO_VAUX18_HW0_OP_CFG_ADDR  MT6358_LDO_VAUX18_OP_CFG
#define PMIC_RG_LDO_VAUX18_HW0_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VAUX18_HW0_OP_CFG_SHIFT 1
#define PMIC_RG_LDO_VAUX18_HW1_OP_CFG_ADDR  MT6358_LDO_VAUX18_OP_CFG
#define PMIC_RG_LDO_VAUX18_HW1_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VAUX18_HW1_OP_CFG_SHIFT 2
#define PMIC_RG_LDO_VAUX18_HW2_OP_CFG_ADDR  MT6358_LDO_VAUX18_OP_CFG
#define PMIC_RG_LDO_VAUX18_HW2_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VAUX18_HW2_OP_CFG_SHIFT 3
#define PMIC_RG_LDO_VAUX18_OP_CFG_SET_ADDR  MT6358_LDO_VAUX18_OP_CFG_SET
#define PMIC_RG_LDO_VAUX18_OP_CFG_SET_MASK  0xFFFF
#define PMIC_RG_LDO_VAUX18_OP_CFG_SET_SHIFT 0
#define PMIC_RG_LDO_VAUX18_OP_CFG_CLR_ADDR  MT6358_LDO_VAUX18_OP_CFG_CLR
#define PMIC_RG_LDO_VAUX18_OP_CFG_CLR_MASK  0xFFFF
#define PMIC_RG_LDO_VAUX18_OP_CFG_CLR_SHIFT 0
#define PMIC_DA_VAUX18_MODE_ADDR  MT6358_LDO_VAUX18_CON1
#define PMIC_DA_VAUX18_MODE_MASK  0x1
#define PMIC_DA_VAUX18_MODE_SHIFT 8
#define PMIC_RG_LDO_VAUX18_STBTD_ADDR MT6358_LDO_VAUX18_CON1
#define PMIC_RG_LDO_VAUX18_STBTD_MASK 0x3
#define PMIC_RG_LDO_VAUX18_STBTD_SHIFT  9
#define PMIC_DA_VAUX18_STB_ADDR MT6358_LDO_VAUX18_CON1
#define PMIC_DA_VAUX18_STB_MASK 0x1
#define PMIC_DA_VAUX18_STB_SHIFT  14
#define PMIC_DA_VAUX18_EN_ADDR  MT6358_LDO_VAUX18_CON1
#define PMIC_DA_VAUX18_EN_MASK  0x1
#define PMIC_DA_VAUX18_EN_SHIFT 15
#define PMIC_RG_LDO_VAUX18_AUXADC_PWDB_EN_ADDR   MT6358_LDO_VAUX18_CON2
#define PMIC_RG_LDO_VAUX18_AUXADC_PWDB_EN_MASK   0x1
#define PMIC_RG_LDO_VAUX18_AUXADC_PWDB_EN_SHIFT  2
#define PMIC_RG_LDO_VAUX18_OCFB_EN_ADDR MT6358_LDO_VAUX18_CON2
#define PMIC_RG_LDO_VAUX18_OCFB_EN_MASK 0x1
#define PMIC_RG_LDO_VAUX18_OCFB_EN_SHIFT   9
#define PMIC_DA_VAUX18_OCFB_EN_ADDR   MT6358_LDO_VAUX18_CON2
#define PMIC_DA_VAUX18_OCFB_EN_MASK   0x1
#define PMIC_DA_VAUX18_OCFB_EN_SHIFT  10
#define PMIC_RG_LDO_VAUX18_DUMMY_LOAD_ADDR  MT6358_LDO_VAUX18_CON3
#define PMIC_RG_LDO_VAUX18_DUMMY_LOAD_MASK  0x3
#define PMIC_RG_LDO_VAUX18_DUMMY_LOAD_SHIFT 5
#define PMIC_DA_VAUX18_DUMMY_LOAD_ADDR  MT6358_LDO_VAUX18_CON3
#define PMIC_DA_VAUX18_DUMMY_LOAD_MASK  0x3
#define PMIC_DA_VAUX18_DUMMY_LOAD_SHIFT 14
#define PMIC_RG_LDO_VAUD28_EN_ADDR MT6358_LDO_VAUD28_CON0
#define PMIC_RG_LDO_VAUD28_EN_MASK 0x1
#define PMIC_RG_LDO_VAUD28_EN_SHIFT   0
#define PMIC_RG_LDO_VAUD28_LP_ADDR MT6358_LDO_VAUD28_CON0
#define PMIC_RG_LDO_VAUD28_LP_MASK 0x1
#define PMIC_RG_LDO_VAUD28_LP_SHIFT   1
#define PMIC_RG_LDO_VAUD28_SW_OP_EN_ADDR   MT6358_LDO_VAUD28_OP_EN
#define PMIC_RG_LDO_VAUD28_SW_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VAUD28_SW_OP_EN_SHIFT   0
#define PMIC_RG_LDO_VAUD28_HW0_OP_EN_ADDR   MT6358_LDO_VAUD28_OP_EN
#define PMIC_RG_LDO_VAUD28_HW0_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VAUD28_HW0_OP_EN_SHIFT  1
#define PMIC_RG_LDO_VAUD28_HW1_OP_EN_ADDR   MT6358_LDO_VAUD28_OP_EN
#define PMIC_RG_LDO_VAUD28_HW1_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VAUD28_HW1_OP_EN_SHIFT  2
#define PMIC_RG_LDO_VAUD28_HW2_OP_EN_ADDR   MT6358_LDO_VAUD28_OP_EN
#define PMIC_RG_LDO_VAUD28_HW2_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VAUD28_HW2_OP_EN_SHIFT  3
#define PMIC_RG_LDO_VAUD28_OP_EN_SET_ADDR   MT6358_LDO_VAUD28_OP_EN_SET
#define PMIC_RG_LDO_VAUD28_OP_EN_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VAUD28_OP_EN_SET_SHIFT  0
#define PMIC_RG_LDO_VAUD28_OP_EN_CLR_ADDR   MT6358_LDO_VAUD28_OP_EN_CLR
#define PMIC_RG_LDO_VAUD28_OP_EN_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VAUD28_OP_EN_CLR_SHIFT  0
#define PMIC_RG_LDO_VAUD28_HW0_OP_CFG_ADDR  MT6358_LDO_VAUD28_OP_CFG
#define PMIC_RG_LDO_VAUD28_HW0_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VAUD28_HW0_OP_CFG_SHIFT 1
#define PMIC_RG_LDO_VAUD28_HW1_OP_CFG_ADDR  MT6358_LDO_VAUD28_OP_CFG
#define PMIC_RG_LDO_VAUD28_HW1_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VAUD28_HW1_OP_CFG_SHIFT 2
#define PMIC_RG_LDO_VAUD28_HW2_OP_CFG_ADDR  MT6358_LDO_VAUD28_OP_CFG
#define PMIC_RG_LDO_VAUD28_HW2_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VAUD28_HW2_OP_CFG_SHIFT 3
#define PMIC_RG_LDO_VAUD28_OP_CFG_SET_ADDR  MT6358_LDO_VAUD28_OP_CFG_SET
#define PMIC_RG_LDO_VAUD28_OP_CFG_SET_MASK  0xFFFF
#define PMIC_RG_LDO_VAUD28_OP_CFG_SET_SHIFT 0
#define PMIC_RG_LDO_VAUD28_OP_CFG_CLR_ADDR  MT6358_LDO_VAUD28_OP_CFG_CLR
#define PMIC_RG_LDO_VAUD28_OP_CFG_CLR_MASK  0xFFFF
#define PMIC_RG_LDO_VAUD28_OP_CFG_CLR_SHIFT 0
#define PMIC_DA_VAUD28_MODE_ADDR  MT6358_LDO_VAUD28_CON1
#define PMIC_DA_VAUD28_MODE_MASK  0x1
#define PMIC_DA_VAUD28_MODE_SHIFT 8
#define PMIC_RG_LDO_VAUD28_STBTD_ADDR MT6358_LDO_VAUD28_CON1
#define PMIC_RG_LDO_VAUD28_STBTD_MASK 0x3
#define PMIC_RG_LDO_VAUD28_STBTD_SHIFT  9
#define PMIC_DA_VAUD28_STB_ADDR MT6358_LDO_VAUD28_CON1
#define PMIC_DA_VAUD28_STB_MASK 0x1
#define PMIC_DA_VAUD28_STB_SHIFT  14
#define PMIC_DA_VAUD28_EN_ADDR  MT6358_LDO_VAUD28_CON1
#define PMIC_DA_VAUD28_EN_MASK  0x1
#define PMIC_DA_VAUD28_EN_SHIFT 15
#define PMIC_RG_LDO_VAUD28_AUXADC_PWDB_EN_ADDR   MT6358_LDO_VAUD28_CON2
#define PMIC_RG_LDO_VAUD28_AUXADC_PWDB_EN_MASK   0x1
#define PMIC_RG_LDO_VAUD28_AUXADC_PWDB_EN_SHIFT  2
#define PMIC_RG_LDO_VAUD28_OCFB_EN_ADDR MT6358_LDO_VAUD28_CON2
#define PMIC_RG_LDO_VAUD28_OCFB_EN_MASK 0x1
#define PMIC_RG_LDO_VAUD28_OCFB_EN_SHIFT   9
#define PMIC_DA_VAUD28_OCFB_EN_ADDR   MT6358_LDO_VAUD28_CON2
#define PMIC_DA_VAUD28_OCFB_EN_MASK   0x1
#define PMIC_DA_VAUD28_OCFB_EN_SHIFT  10
#define PMIC_RG_LDO_VAUD28_DUMMY_LOAD_ADDR  MT6358_LDO_VAUD28_CON3
#define PMIC_RG_LDO_VAUD28_DUMMY_LOAD_MASK  0x3
#define PMIC_RG_LDO_VAUD28_DUMMY_LOAD_SHIFT 5
#define PMIC_DA_VAUD28_DUMMY_LOAD_ADDR  MT6358_LDO_VAUD28_CON3
#define PMIC_DA_VAUD28_DUMMY_LOAD_MASK  0x3
#define PMIC_DA_VAUD28_DUMMY_LOAD_SHIFT 14
#define PMIC_RG_LDO_VIO28_EN_ADDR MT6358_LDO_VIO28_CON0
#define PMIC_RG_LDO_VIO28_EN_MASK 0x1
#define PMIC_RG_LDO_VIO28_EN_SHIFT 0
#define PMIC_RG_LDO_VIO28_LP_ADDR MT6358_LDO_VIO28_CON0
#define PMIC_RG_LDO_VIO28_LP_MASK 0x1
#define PMIC_RG_LDO_VIO28_LP_SHIFT 1
#define PMIC_RG_LDO_VIO28_SW_OP_EN_ADDR MT6358_LDO_VIO28_OP_EN
#define PMIC_RG_LDO_VIO28_SW_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VIO28_SW_OP_EN_SHIFT   0
#define PMIC_RG_LDO_VIO28_HW0_OP_EN_ADDR   MT6358_LDO_VIO28_OP_EN
#define PMIC_RG_LDO_VIO28_HW0_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VIO28_HW0_OP_EN_SHIFT   1
#define PMIC_RG_LDO_VIO28_HW1_OP_EN_ADDR   MT6358_LDO_VIO28_OP_EN
#define PMIC_RG_LDO_VIO28_HW1_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VIO28_HW1_OP_EN_SHIFT   2
#define PMIC_RG_LDO_VIO28_HW2_OP_EN_ADDR   MT6358_LDO_VIO28_OP_EN
#define PMIC_RG_LDO_VIO28_HW2_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VIO28_HW2_OP_EN_SHIFT   3
#define PMIC_RG_LDO_VIO28_OP_EN_SET_ADDR   MT6358_LDO_VIO28_OP_EN_SET
#define PMIC_RG_LDO_VIO28_OP_EN_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VIO28_OP_EN_SET_SHIFT   0
#define PMIC_RG_LDO_VIO28_OP_EN_CLR_ADDR   MT6358_LDO_VIO28_OP_EN_CLR
#define PMIC_RG_LDO_VIO28_OP_EN_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VIO28_OP_EN_CLR_SHIFT   0
#define PMIC_RG_LDO_VIO28_HW0_OP_CFG_ADDR   MT6358_LDO_VIO28_OP_CFG
#define PMIC_RG_LDO_VIO28_HW0_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VIO28_HW0_OP_CFG_SHIFT  1
#define PMIC_RG_LDO_VIO28_HW1_OP_CFG_ADDR   MT6358_LDO_VIO28_OP_CFG
#define PMIC_RG_LDO_VIO28_HW1_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VIO28_HW1_OP_CFG_SHIFT  2
#define PMIC_RG_LDO_VIO28_HW2_OP_CFG_ADDR   MT6358_LDO_VIO28_OP_CFG
#define PMIC_RG_LDO_VIO28_HW2_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VIO28_HW2_OP_CFG_SHIFT  3
#define PMIC_RG_LDO_VIO28_OP_CFG_SET_ADDR   MT6358_LDO_VIO28_OP_CFG_SET
#define PMIC_RG_LDO_VIO28_OP_CFG_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VIO28_OP_CFG_SET_SHIFT  0
#define PMIC_RG_LDO_VIO28_OP_CFG_CLR_ADDR   MT6358_LDO_VIO28_OP_CFG_CLR
#define PMIC_RG_LDO_VIO28_OP_CFG_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VIO28_OP_CFG_CLR_SHIFT  0
#define PMIC_DA_VIO28_MODE_ADDR MT6358_LDO_VIO28_CON1
#define PMIC_DA_VIO28_MODE_MASK 0x1
#define PMIC_DA_VIO28_MODE_SHIFT  8
#define PMIC_RG_LDO_VIO28_STBTD_ADDR  MT6358_LDO_VIO28_CON1
#define PMIC_RG_LDO_VIO28_STBTD_MASK  0x3
#define PMIC_RG_LDO_VIO28_STBTD_SHIFT 9
#define PMIC_DA_VIO28_STB_ADDR  MT6358_LDO_VIO28_CON1
#define PMIC_DA_VIO28_STB_MASK  0x1
#define PMIC_DA_VIO28_STB_SHIFT 14
#define PMIC_DA_VIO28_EN_ADDR   MT6358_LDO_VIO28_CON1
#define PMIC_DA_VIO28_EN_MASK   0x1
#define PMIC_DA_VIO28_EN_SHIFT  15
#define PMIC_RG_LDO_VIO28_OCFB_EN_ADDR  MT6358_LDO_VIO28_CON2
#define PMIC_RG_LDO_VIO28_OCFB_EN_MASK  0x1
#define PMIC_RG_LDO_VIO28_OCFB_EN_SHIFT 9
#define PMIC_DA_VIO28_OCFB_EN_ADDR MT6358_LDO_VIO28_CON2
#define PMIC_DA_VIO28_OCFB_EN_MASK 0x1
#define PMIC_DA_VIO28_OCFB_EN_SHIFT   10
#define PMIC_RG_LDO_VIO28_DUMMY_LOAD_ADDR   MT6358_LDO_VIO28_CON3
#define PMIC_RG_LDO_VIO28_DUMMY_LOAD_MASK   0x3
#define PMIC_RG_LDO_VIO28_DUMMY_LOAD_SHIFT  5
#define PMIC_DA_VIO28_DUMMY_LOAD_ADDR MT6358_LDO_VIO28_CON3
#define PMIC_DA_VIO28_DUMMY_LOAD_MASK 0x3
#define PMIC_DA_VIO28_DUMMY_LOAD_SHIFT  14
#define PMIC_RG_LDO_VIO18_EN_ADDR MT6358_LDO_VIO18_CON0
#define PMIC_RG_LDO_VIO18_EN_MASK 0x1
#define PMIC_RG_LDO_VIO18_EN_SHIFT 0
#define PMIC_RG_LDO_VIO18_LP_ADDR MT6358_LDO_VIO18_CON0
#define PMIC_RG_LDO_VIO18_LP_MASK 0x1
#define PMIC_RG_LDO_VIO18_LP_SHIFT 1
#define PMIC_RG_LDO_VIO18_SW_OP_EN_ADDR MT6358_LDO_VIO18_OP_EN
#define PMIC_RG_LDO_VIO18_SW_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VIO18_SW_OP_EN_SHIFT   0
#define PMIC_RG_LDO_VIO18_HW0_OP_EN_ADDR   MT6358_LDO_VIO18_OP_EN
#define PMIC_RG_LDO_VIO18_HW0_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VIO18_HW0_OP_EN_SHIFT   1
#define PMIC_RG_LDO_VIO18_HW1_OP_EN_ADDR   MT6358_LDO_VIO18_OP_EN
#define PMIC_RG_LDO_VIO18_HW1_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VIO18_HW1_OP_EN_SHIFT   2
#define PMIC_RG_LDO_VIO18_HW2_OP_EN_ADDR   MT6358_LDO_VIO18_OP_EN
#define PMIC_RG_LDO_VIO18_HW2_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VIO18_HW2_OP_EN_SHIFT   3
#define PMIC_RG_LDO_VIO18_OP_EN_SET_ADDR   MT6358_LDO_VIO18_OP_EN_SET
#define PMIC_RG_LDO_VIO18_OP_EN_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VIO18_OP_EN_SET_SHIFT   0
#define PMIC_RG_LDO_VIO18_OP_EN_CLR_ADDR   MT6358_LDO_VIO18_OP_EN_CLR
#define PMIC_RG_LDO_VIO18_OP_EN_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VIO18_OP_EN_CLR_SHIFT   0
#define PMIC_RG_LDO_VIO18_HW0_OP_CFG_ADDR   MT6358_LDO_VIO18_OP_CFG
#define PMIC_RG_LDO_VIO18_HW0_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VIO18_HW0_OP_CFG_SHIFT  1
#define PMIC_RG_LDO_VIO18_HW1_OP_CFG_ADDR   MT6358_LDO_VIO18_OP_CFG
#define PMIC_RG_LDO_VIO18_HW1_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VIO18_HW1_OP_CFG_SHIFT  2
#define PMIC_RG_LDO_VIO18_HW2_OP_CFG_ADDR   MT6358_LDO_VIO18_OP_CFG
#define PMIC_RG_LDO_VIO18_HW2_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VIO18_HW2_OP_CFG_SHIFT  3
#define PMIC_RG_LDO_VIO18_OP_CFG_SET_ADDR   MT6358_LDO_VIO18_OP_CFG_SET
#define PMIC_RG_LDO_VIO18_OP_CFG_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VIO18_OP_CFG_SET_SHIFT  0
#define PMIC_RG_LDO_VIO18_OP_CFG_CLR_ADDR   MT6358_LDO_VIO18_OP_CFG_CLR
#define PMIC_RG_LDO_VIO18_OP_CFG_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VIO18_OP_CFG_CLR_SHIFT  0
#define PMIC_DA_VIO18_MODE_ADDR MT6358_LDO_VIO18_CON1
#define PMIC_DA_VIO18_MODE_MASK 0x1
#define PMIC_DA_VIO18_MODE_SHIFT  8
#define PMIC_RG_LDO_VIO18_STBTD_ADDR  MT6358_LDO_VIO18_CON1
#define PMIC_RG_LDO_VIO18_STBTD_MASK  0x3
#define PMIC_RG_LDO_VIO18_STBTD_SHIFT 9
#define PMIC_DA_VIO18_STB_ADDR  MT6358_LDO_VIO18_CON1
#define PMIC_DA_VIO18_STB_MASK  0x1
#define PMIC_DA_VIO18_STB_SHIFT 14
#define PMIC_DA_VIO18_EN_ADDR   MT6358_LDO_VIO18_CON1
#define PMIC_DA_VIO18_EN_MASK   0x1
#define PMIC_DA_VIO18_EN_SHIFT  15
#define PMIC_RG_LDO_VIO18_OCFB_EN_ADDR  MT6358_LDO_VIO18_CON2
#define PMIC_RG_LDO_VIO18_OCFB_EN_MASK  0x1
#define PMIC_RG_LDO_VIO18_OCFB_EN_SHIFT 9
#define PMIC_DA_VIO18_OCFB_EN_ADDR MT6358_LDO_VIO18_CON2
#define PMIC_DA_VIO18_OCFB_EN_MASK 0x1
#define PMIC_DA_VIO18_OCFB_EN_SHIFT   10
#define PMIC_RG_LDO_VIO18_DUMMY_LOAD_ADDR   MT6358_LDO_VIO18_CON3
#define PMIC_RG_LDO_VIO18_DUMMY_LOAD_MASK   0x3
#define PMIC_RG_LDO_VIO18_DUMMY_LOAD_SHIFT  5
#define PMIC_DA_VIO18_DUMMY_LOAD_ADDR MT6358_LDO_VIO18_CON3
#define PMIC_DA_VIO18_DUMMY_LOAD_MASK 0x3
#define PMIC_DA_VIO18_DUMMY_LOAD_SHIFT  14
#define PMIC_LDO_GON1_ANA_ID_ADDR MT6358_LDO_GON1_DSN_ID
#define PMIC_LDO_GON1_ANA_ID_MASK 0xFF
#define PMIC_LDO_GON1_ANA_ID_SHIFT 0
#define PMIC_LDO_GON1_DIG_ID_ADDR MT6358_LDO_GON1_DSN_ID
#define PMIC_LDO_GON1_DIG_ID_MASK 0xFF
#define PMIC_LDO_GON1_DIG_ID_SHIFT 8
#define PMIC_LDO_GON1_ANA_MINOR_REV_ADDR   MT6358_LDO_GON1_DSN_REV0
#define PMIC_LDO_GON1_ANA_MINOR_REV_MASK   0xF
#define PMIC_LDO_GON1_ANA_MINOR_REV_SHIFT   0
#define PMIC_LDO_GON1_ANA_MAJOR_REV_ADDR   MT6358_LDO_GON1_DSN_REV0
#define PMIC_LDO_GON1_ANA_MAJOR_REV_MASK   0xF
#define PMIC_LDO_GON1_ANA_MAJOR_REV_SHIFT   4
#define PMIC_LDO_GON1_DIG_MINOR_REV_ADDR   MT6358_LDO_GON1_DSN_REV0
#define PMIC_LDO_GON1_DIG_MINOR_REV_MASK   0xF
#define PMIC_LDO_GON1_DIG_MINOR_REV_SHIFT   8
#define PMIC_LDO_GON1_DIG_MAJOR_REV_ADDR   MT6358_LDO_GON1_DSN_REV0
#define PMIC_LDO_GON1_DIG_MAJOR_REV_MASK   0xF
#define PMIC_LDO_GON1_DIG_MAJOR_REV_SHIFT   12
#define PMIC_LDO_GON1_DSN_CBS_ADDR MT6358_LDO_GON1_DSN_DBI
#define PMIC_LDO_GON1_DSN_CBS_MASK 0x3
#define PMIC_LDO_GON1_DSN_CBS_SHIFT   0
#define PMIC_LDO_GON1_DSN_BIX_ADDR MT6358_LDO_GON1_DSN_DBI
#define PMIC_LDO_GON1_DSN_BIX_MASK 0x3
#define PMIC_LDO_GON1_DSN_BIX_SHIFT   2
#define PMIC_LDO_GON1_DSN_ESP_ADDR MT6358_LDO_GON1_DSN_DBI
#define PMIC_LDO_GON1_DSN_ESP_MASK 0xFF
#define PMIC_LDO_GON1_DSN_ESP_SHIFT   8
#define PMIC_LDO_GON1_DSN_FPI_ADDR MT6358_LDO_GON1_DSN_DXI
#define PMIC_LDO_GON1_DSN_FPI_MASK 0xFF
#define PMIC_LDO_GON1_DSN_FPI_SHIFT   0
#define PMIC_RG_LDO_VDRAM2_EN_ADDR MT6358_LDO_VDRAM2_CON0
#define PMIC_RG_LDO_VDRAM2_EN_MASK 0x1
#define PMIC_RG_LDO_VDRAM2_EN_SHIFT   0
#define PMIC_RG_LDO_VDRAM2_LP_ADDR MT6358_LDO_VDRAM2_CON0
#define PMIC_RG_LDO_VDRAM2_LP_MASK 0x1
#define PMIC_RG_LDO_VDRAM2_LP_SHIFT   1
#define PMIC_RG_LDO_VDRAM2_SW_OP_EN_ADDR   MT6358_LDO_VDRAM2_OP_EN
#define PMIC_RG_LDO_VDRAM2_SW_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VDRAM2_SW_OP_EN_SHIFT   0
#define PMIC_RG_LDO_VDRAM2_HW0_OP_EN_ADDR   MT6358_LDO_VDRAM2_OP_EN
#define PMIC_RG_LDO_VDRAM2_HW0_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VDRAM2_HW0_OP_EN_SHIFT  1
#define PMIC_RG_LDO_VDRAM2_HW1_OP_EN_ADDR   MT6358_LDO_VDRAM2_OP_EN
#define PMIC_RG_LDO_VDRAM2_HW1_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VDRAM2_HW1_OP_EN_SHIFT  2
#define PMIC_RG_LDO_VDRAM2_HW2_OP_EN_ADDR   MT6358_LDO_VDRAM2_OP_EN
#define PMIC_RG_LDO_VDRAM2_HW2_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VDRAM2_HW2_OP_EN_SHIFT  3
#define PMIC_RG_LDO_VDRAM2_OP_EN_SET_ADDR   MT6358_LDO_VDRAM2_OP_EN_SET
#define PMIC_RG_LDO_VDRAM2_OP_EN_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VDRAM2_OP_EN_SET_SHIFT  0
#define PMIC_RG_LDO_VDRAM2_OP_EN_CLR_ADDR   MT6358_LDO_VDRAM2_OP_EN_CLR
#define PMIC_RG_LDO_VDRAM2_OP_EN_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VDRAM2_OP_EN_CLR_SHIFT  0
#define PMIC_RG_LDO_VDRAM2_HW0_OP_CFG_ADDR  MT6358_LDO_VDRAM2_OP_CFG
#define PMIC_RG_LDO_VDRAM2_HW0_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VDRAM2_HW0_OP_CFG_SHIFT 1
#define PMIC_RG_LDO_VDRAM2_HW1_OP_CFG_ADDR  MT6358_LDO_VDRAM2_OP_CFG
#define PMIC_RG_LDO_VDRAM2_HW1_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VDRAM2_HW1_OP_CFG_SHIFT 2
#define PMIC_RG_LDO_VDRAM2_HW2_OP_CFG_ADDR  MT6358_LDO_VDRAM2_OP_CFG
#define PMIC_RG_LDO_VDRAM2_HW2_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VDRAM2_HW2_OP_CFG_SHIFT 3
#define PMIC_RG_LDO_VDRAM2_OP_CFG_SET_ADDR  MT6358_LDO_VDRAM2_OP_CFG_SET
#define PMIC_RG_LDO_VDRAM2_OP_CFG_SET_MASK  0xFFFF
#define PMIC_RG_LDO_VDRAM2_OP_CFG_SET_SHIFT 0
#define PMIC_RG_LDO_VDRAM2_OP_CFG_CLR_ADDR  MT6358_LDO_VDRAM2_OP_CFG_CLR
#define PMIC_RG_LDO_VDRAM2_OP_CFG_CLR_MASK  0xFFFF
#define PMIC_RG_LDO_VDRAM2_OP_CFG_CLR_SHIFT 0
#define PMIC_DA_VDRAM2_MODE_ADDR  MT6358_LDO_VDRAM2_CON1
#define PMIC_DA_VDRAM2_MODE_MASK  0x1
#define PMIC_DA_VDRAM2_MODE_SHIFT 8
#define PMIC_RG_LDO_VDRAM2_STBTD_ADDR MT6358_LDO_VDRAM2_CON1
#define PMIC_RG_LDO_VDRAM2_STBTD_MASK 0x3
#define PMIC_RG_LDO_VDRAM2_STBTD_SHIFT  9
#define PMIC_DA_VDRAM2_STB_ADDR MT6358_LDO_VDRAM2_CON1
#define PMIC_DA_VDRAM2_STB_MASK 0x1
#define PMIC_DA_VDRAM2_STB_SHIFT  14
#define PMIC_DA_VDRAM2_EN_ADDR  MT6358_LDO_VDRAM2_CON1
#define PMIC_DA_VDRAM2_EN_MASK  0x1
#define PMIC_DA_VDRAM2_EN_SHIFT 15
#define PMIC_RG_LDO_VDRAM2_OCFB_EN_ADDR MT6358_LDO_VDRAM2_CON2
#define PMIC_RG_LDO_VDRAM2_OCFB_EN_MASK 0x1
#define PMIC_RG_LDO_VDRAM2_OCFB_EN_SHIFT   9
#define PMIC_DA_VDRAM2_OCFB_EN_ADDR   MT6358_LDO_VDRAM2_CON2
#define PMIC_DA_VDRAM2_OCFB_EN_MASK   0x1
#define PMIC_DA_VDRAM2_OCFB_EN_SHIFT  10
#define PMIC_RG_LDO_VDRAM2_DUMMY_LOAD_ADDR  MT6358_LDO_VDRAM2_CON3
#define PMIC_RG_LDO_VDRAM2_DUMMY_LOAD_MASK  0x3
#define PMIC_RG_LDO_VDRAM2_DUMMY_LOAD_SHIFT 5
#define PMIC_DA_VDRAM2_DUMMY_LOAD_ADDR  MT6358_LDO_VDRAM2_CON3
#define PMIC_DA_VDRAM2_DUMMY_LOAD_MASK  0x3
#define PMIC_DA_VDRAM2_DUMMY_LOAD_SHIFT 14
#define PMIC_RG_LDO_VEMC_EN_ADDR  MT6358_LDO_VEMC_CON0
#define PMIC_RG_LDO_VEMC_EN_MASK  0x1
#define PMIC_RG_LDO_VEMC_EN_SHIFT 0
#define PMIC_RG_LDO_VEMC_LP_ADDR  MT6358_LDO_VEMC_CON0
#define PMIC_RG_LDO_VEMC_LP_MASK  0x1
#define PMIC_RG_LDO_VEMC_LP_SHIFT 1
#define PMIC_RG_LDO_VEMC_SW_OP_EN_ADDR  MT6358_LDO_VEMC_OP_EN
#define PMIC_RG_LDO_VEMC_SW_OP_EN_MASK  0x1
#define PMIC_RG_LDO_VEMC_SW_OP_EN_SHIFT 0
#define PMIC_RG_LDO_VEMC_HW0_OP_EN_ADDR MT6358_LDO_VEMC_OP_EN
#define PMIC_RG_LDO_VEMC_HW0_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VEMC_HW0_OP_EN_SHIFT   1
#define PMIC_RG_LDO_VEMC_HW1_OP_EN_ADDR MT6358_LDO_VEMC_OP_EN
#define PMIC_RG_LDO_VEMC_HW1_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VEMC_HW1_OP_EN_SHIFT   2
#define PMIC_RG_LDO_VEMC_HW2_OP_EN_ADDR MT6358_LDO_VEMC_OP_EN
#define PMIC_RG_LDO_VEMC_HW2_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VEMC_HW2_OP_EN_SHIFT   3
#define PMIC_RG_LDO_VEMC_OP_EN_SET_ADDR MT6358_LDO_VEMC_OP_EN_SET
#define PMIC_RG_LDO_VEMC_OP_EN_SET_MASK 0xFFFF
#define PMIC_RG_LDO_VEMC_OP_EN_SET_SHIFT   0
#define PMIC_RG_LDO_VEMC_OP_EN_CLR_ADDR MT6358_LDO_VEMC_OP_EN_CLR
#define PMIC_RG_LDO_VEMC_OP_EN_CLR_MASK 0xFFFF
#define PMIC_RG_LDO_VEMC_OP_EN_CLR_SHIFT   0
#define PMIC_RG_LDO_VEMC_HW0_OP_CFG_ADDR   MT6358_LDO_VEMC_OP_CFG
#define PMIC_RG_LDO_VEMC_HW0_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VEMC_HW0_OP_CFG_SHIFT   1
#define PMIC_RG_LDO_VEMC_HW1_OP_CFG_ADDR   MT6358_LDO_VEMC_OP_CFG
#define PMIC_RG_LDO_VEMC_HW1_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VEMC_HW1_OP_CFG_SHIFT   2
#define PMIC_RG_LDO_VEMC_HW2_OP_CFG_ADDR   MT6358_LDO_VEMC_OP_CFG
#define PMIC_RG_LDO_VEMC_HW2_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VEMC_HW2_OP_CFG_SHIFT   3
#define PMIC_RG_LDO_VEMC_OP_CFG_SET_ADDR   MT6358_LDO_VEMC_OP_CFG_SET
#define PMIC_RG_LDO_VEMC_OP_CFG_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VEMC_OP_CFG_SET_SHIFT   0
#define PMIC_RG_LDO_VEMC_OP_CFG_CLR_ADDR   MT6358_LDO_VEMC_OP_CFG_CLR
#define PMIC_RG_LDO_VEMC_OP_CFG_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VEMC_OP_CFG_CLR_SHIFT   0
#define PMIC_DA_VEMC_MODE_ADDR  MT6358_LDO_VEMC_CON1
#define PMIC_DA_VEMC_MODE_MASK  0x1
#define PMIC_DA_VEMC_MODE_SHIFT 8
#define PMIC_RG_LDO_VEMC_STBTD_ADDR   MT6358_LDO_VEMC_CON1
#define PMIC_RG_LDO_VEMC_STBTD_MASK   0x3
#define PMIC_RG_LDO_VEMC_STBTD_SHIFT  9
#define PMIC_DA_VEMC_STB_ADDR   MT6358_LDO_VEMC_CON1
#define PMIC_DA_VEMC_STB_MASK   0x1
#define PMIC_DA_VEMC_STB_SHIFT  14
#define PMIC_DA_VEMC_EN_ADDR MT6358_LDO_VEMC_CON1
#define PMIC_DA_VEMC_EN_MASK 0x1
#define PMIC_DA_VEMC_EN_SHIFT   15
#define PMIC_RG_LDO_VEMC_OCFB_EN_ADDR MT6358_LDO_VEMC_CON2
#define PMIC_RG_LDO_VEMC_OCFB_EN_MASK 0x1
#define PMIC_RG_LDO_VEMC_OCFB_EN_SHIFT  9
#define PMIC_DA_VEMC_OCFB_EN_ADDR MT6358_LDO_VEMC_CON2
#define PMIC_DA_VEMC_OCFB_EN_MASK 0x1
#define PMIC_DA_VEMC_OCFB_EN_SHIFT 10
#define PMIC_RG_LDO_VEMC_DUMMY_LOAD_ADDR   MT6358_LDO_VEMC_CON3
#define PMIC_RG_LDO_VEMC_DUMMY_LOAD_MASK   0x3
#define PMIC_RG_LDO_VEMC_DUMMY_LOAD_SHIFT   5
#define PMIC_DA_VEMC_DUMMY_LOAD_ADDR  MT6358_LDO_VEMC_CON3
#define PMIC_DA_VEMC_DUMMY_LOAD_MASK  0x3
#define PMIC_DA_VEMC_DUMMY_LOAD_SHIFT 14
#define PMIC_RG_LDO_VUSB_EN_0_ADDR MT6358_LDO_VUSB_CON0_0
#define PMIC_RG_LDO_VUSB_EN_0_MASK 0x1
#define PMIC_RG_LDO_VUSB_EN_0_SHIFT   0
#define PMIC_RG_LDO_VUSB_LP_ADDR  MT6358_LDO_VUSB_CON0_0
#define PMIC_RG_LDO_VUSB_LP_MASK  0x1
#define PMIC_RG_LDO_VUSB_LP_SHIFT 1
#define PMIC_RG_LDO_VUSB_SW_OP_EN_ADDR  MT6358_LDO_VUSB_OP_EN
#define PMIC_RG_LDO_VUSB_SW_OP_EN_MASK  0x1
#define PMIC_RG_LDO_VUSB_SW_OP_EN_SHIFT 0
#define PMIC_RG_LDO_VUSB_HW0_OP_EN_ADDR MT6358_LDO_VUSB_OP_EN
#define PMIC_RG_LDO_VUSB_HW0_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VUSB_HW0_OP_EN_SHIFT   1
#define PMIC_RG_LDO_VUSB_HW1_OP_EN_ADDR MT6358_LDO_VUSB_OP_EN
#define PMIC_RG_LDO_VUSB_HW1_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VUSB_HW1_OP_EN_SHIFT   2
#define PMIC_RG_LDO_VUSB_HW2_OP_EN_ADDR MT6358_LDO_VUSB_OP_EN
#define PMIC_RG_LDO_VUSB_HW2_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VUSB_HW2_OP_EN_SHIFT   3
#define PMIC_RG_LDO_VUSB_OP_EN_SET_ADDR MT6358_LDO_VUSB_OP_EN_SET
#define PMIC_RG_LDO_VUSB_OP_EN_SET_MASK 0xFFFF
#define PMIC_RG_LDO_VUSB_OP_EN_SET_SHIFT   0
#define PMIC_RG_LDO_VUSB_OP_EN_CLR_ADDR MT6358_LDO_VUSB_OP_EN_CLR
#define PMIC_RG_LDO_VUSB_OP_EN_CLR_MASK 0xFFFF
#define PMIC_RG_LDO_VUSB_OP_EN_CLR_SHIFT   0
#define PMIC_RG_LDO_VUSB_HW0_OP_CFG_ADDR   MT6358_LDO_VUSB_OP_CFG
#define PMIC_RG_LDO_VUSB_HW0_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VUSB_HW0_OP_CFG_SHIFT   1
#define PMIC_RG_LDO_VUSB_HW1_OP_CFG_ADDR   MT6358_LDO_VUSB_OP_CFG
#define PMIC_RG_LDO_VUSB_HW1_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VUSB_HW1_OP_CFG_SHIFT   2
#define PMIC_RG_LDO_VUSB_HW2_OP_CFG_ADDR   MT6358_LDO_VUSB_OP_CFG
#define PMIC_RG_LDO_VUSB_HW2_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VUSB_HW2_OP_CFG_SHIFT   3
#define PMIC_RG_LDO_VUSB_OP_CFG_SET_ADDR   MT6358_LDO_VUSB_OP_CFG_SET
#define PMIC_RG_LDO_VUSB_OP_CFG_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VUSB_OP_CFG_SET_SHIFT   0
#define PMIC_RG_LDO_VUSB_OP_CFG_CLR_ADDR   MT6358_LDO_VUSB_OP_CFG_CLR
#define PMIC_RG_LDO_VUSB_OP_CFG_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VUSB_OP_CFG_CLR_SHIFT   0
#define PMIC_RG_LDO_VUSB_EN_1_ADDR MT6358_LDO_VUSB_CON0_1
#define PMIC_RG_LDO_VUSB_EN_1_MASK 0x1
#define PMIC_RG_LDO_VUSB_EN_1_SHIFT   0
#define PMIC_DA_VUSB_MODE_ADDR  MT6358_LDO_VUSB_CON1
#define PMIC_DA_VUSB_MODE_MASK  0x1
#define PMIC_DA_VUSB_MODE_SHIFT 8
#define PMIC_RG_LDO_VUSB_STBTD_ADDR   MT6358_LDO_VUSB_CON1
#define PMIC_RG_LDO_VUSB_STBTD_MASK   0x3
#define PMIC_RG_LDO_VUSB_STBTD_SHIFT  9
#define PMIC_DA_VUSB_STB_ADDR   MT6358_LDO_VUSB_CON1
#define PMIC_DA_VUSB_STB_MASK   0x1
#define PMIC_DA_VUSB_STB_SHIFT  14
#define PMIC_DA_VUSB_EN_ADDR MT6358_LDO_VUSB_CON1
#define PMIC_DA_VUSB_EN_MASK 0x1
#define PMIC_DA_VUSB_EN_SHIFT   15
#define PMIC_RG_LDO_VUSB_OCFB_EN_ADDR MT6358_LDO_VUSB_CON2
#define PMIC_RG_LDO_VUSB_OCFB_EN_MASK 0x1
#define PMIC_RG_LDO_VUSB_OCFB_EN_SHIFT  9
#define PMIC_DA_VUSB_OCFB_EN_ADDR MT6358_LDO_VUSB_CON2
#define PMIC_DA_VUSB_OCFB_EN_MASK 0x1
#define PMIC_DA_VUSB_OCFB_EN_SHIFT 10
#define PMIC_RG_LDO_VUSB_DUMMY_LOAD_ADDR   MT6358_LDO_VUSB_CON3
#define PMIC_RG_LDO_VUSB_DUMMY_LOAD_MASK   0x3
#define PMIC_RG_LDO_VUSB_DUMMY_LOAD_SHIFT   5
#define PMIC_DA_VUSB_DUMMY_LOAD_ADDR  MT6358_LDO_VUSB_CON3
#define PMIC_DA_VUSB_DUMMY_LOAD_MASK  0x3
#define PMIC_DA_VUSB_DUMMY_LOAD_SHIFT 14
#define PMIC_RG_LDO_VSRAM_PROC11_EN_ADDR   MT6358_LDO_VSRAM_PROC11_CON0
#define PMIC_RG_LDO_VSRAM_PROC11_EN_MASK   0x1
#define PMIC_RG_LDO_VSRAM_PROC11_EN_SHIFT   0
#define PMIC_RG_LDO_VSRAM_PROC11_LP_ADDR   MT6358_LDO_VSRAM_PROC11_CON0
#define PMIC_RG_LDO_VSRAM_PROC11_LP_MASK   0x1
#define PMIC_RG_LDO_VSRAM_PROC11_LP_SHIFT   1
#define PMIC_RG_LDO_VSRAM_PROC11_VOSEL_SLEEP_ADDR MT6358_LDO_VSRAM_PROC11_CON2
#define PMIC_RG_LDO_VSRAM_PROC11_VOSEL_SLEEP_MASK 0x7F
#define PMIC_RG_LDO_VSRAM_PROC11_VOSEL_SLEEP_SHIFT  0
#define PMIC_RG_LDO_VSRAM_PROC11_SFCHG_FRATE_ADDR \
MT6358_LDO_VSRAM_PROC11_CFG0
#define PMIC_RG_LDO_VSRAM_PROC11_SFCHG_FRATE_MASK 0x7F
#define PMIC_RG_LDO_VSRAM_PROC11_SFCHG_FRATE_SHIFT  0
#define PMIC_RG_LDO_VSRAM_PROC11_SFCHG_FEN_ADDR  \
MT6358_LDO_VSRAM_PROC11_CFG0
#define PMIC_RG_LDO_VSRAM_PROC11_SFCHG_FEN_MASK  0x1
#define PMIC_RG_LDO_VSRAM_PROC11_SFCHG_FEN_SHIFT  7
#define PMIC_RG_LDO_VSRAM_PROC11_SFCHG_RRATE_ADDR \
MT6358_LDO_VSRAM_PROC11_CFG0
#define PMIC_RG_LDO_VSRAM_PROC11_SFCHG_RRATE_MASK 0x7F
#define PMIC_RG_LDO_VSRAM_PROC11_SFCHG_RRATE_SHIFT  8
#define PMIC_RG_LDO_VSRAM_PROC11_SFCHG_REN_ADDR  \
MT6358_LDO_VSRAM_PROC11_CFG0
#define PMIC_RG_LDO_VSRAM_PROC11_SFCHG_REN_MASK  0x1
#define PMIC_RG_LDO_VSRAM_PROC11_SFCHG_REN_SHIFT  15
#define PMIC_RG_LDO_VSRAM_PROC11_DVS_TRANS_TD_ADDR  \
MT6358_LDO_VSRAM_PROC11_CFG1
#define PMIC_RG_LDO_VSRAM_PROC11_DVS_TRANS_TD_MASK  0x3
#define PMIC_RG_LDO_VSRAM_PROC11_DVS_TRANS_TD_SHIFT 0
#define PMIC_RG_LDO_VSRAM_PROC11_DVS_TRANS_CTRL_ADDR   \
MT6358_LDO_VSRAM_PROC11_CFG1
#define PMIC_RG_LDO_VSRAM_PROC11_DVS_TRANS_CTRL_MASK   0x3
#define PMIC_RG_LDO_VSRAM_PROC11_DVS_TRANS_CTRL_SHIFT  4
#define PMIC_RG_LDO_VSRAM_PROC11_DVS_TRANS_ONCE_ADDR   \
MT6358_LDO_VSRAM_PROC11_CFG1
#define PMIC_RG_LDO_VSRAM_PROC11_DVS_TRANS_ONCE_MASK   0x1
#define PMIC_RG_LDO_VSRAM_PROC11_DVS_TRANS_ONCE_SHIFT  6
#define PMIC_RG_LDO_VSRAM_PROC11_SW_OP_EN_ADDR   MT6358_LDO_VSRAM_PROC11_OP_EN
#define PMIC_RG_LDO_VSRAM_PROC11_SW_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VSRAM_PROC11_SW_OP_EN_SHIFT  0
#define PMIC_RG_LDO_VSRAM_PROC11_HW0_OP_EN_ADDR  MT6358_LDO_VSRAM_PROC11_OP_EN
#define PMIC_RG_LDO_VSRAM_PROC11_HW0_OP_EN_MASK  0x1
#define PMIC_RG_LDO_VSRAM_PROC11_HW0_OP_EN_SHIFT  1
#define PMIC_RG_LDO_VSRAM_PROC11_HW1_OP_EN_ADDR  MT6358_LDO_VSRAM_PROC11_OP_EN
#define PMIC_RG_LDO_VSRAM_PROC11_HW1_OP_EN_MASK  0x1
#define PMIC_RG_LDO_VSRAM_PROC11_HW1_OP_EN_SHIFT  2
#define PMIC_RG_LDO_VSRAM_PROC11_HW2_OP_EN_ADDR  MT6358_LDO_VSRAM_PROC11_OP_EN
#define PMIC_RG_LDO_VSRAM_PROC11_HW2_OP_EN_MASK  0x1
#define PMIC_RG_LDO_VSRAM_PROC11_HW2_OP_EN_SHIFT  3
#define PMIC_RG_LDO_VSRAM_PROC11_OP_EN_SET_ADDR  \
MT6358_LDO_VSRAM_PROC11_OP_EN_SET
#define PMIC_RG_LDO_VSRAM_PROC11_OP_EN_SET_MASK  0xFFFF
#define PMIC_RG_LDO_VSRAM_PROC11_OP_EN_SET_SHIFT  0
#define PMIC_RG_LDO_VSRAM_PROC11_OP_EN_CLR_ADDR  \
MT6358_LDO_VSRAM_PROC11_OP_EN_CLR
#define PMIC_RG_LDO_VSRAM_PROC11_OP_EN_CLR_MASK  0xFFFF
#define PMIC_RG_LDO_VSRAM_PROC11_OP_EN_CLR_SHIFT  0
#define PMIC_RG_LDO_VSRAM_PROC11_HW0_OP_CFG_ADDR  MT6358_LDO_VSRAM_PROC11_OP_CFG
#define PMIC_RG_LDO_VSRAM_PROC11_HW0_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VSRAM_PROC11_HW0_OP_CFG_SHIFT 1
#define PMIC_RG_LDO_VSRAM_PROC11_HW1_OP_CFG_ADDR  MT6358_LDO_VSRAM_PROC11_OP_CFG
#define PMIC_RG_LDO_VSRAM_PROC11_HW1_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VSRAM_PROC11_HW1_OP_CFG_SHIFT 2
#define PMIC_RG_LDO_VSRAM_PROC11_HW2_OP_CFG_ADDR  MT6358_LDO_VSRAM_PROC11_OP_CFG
#define PMIC_RG_LDO_VSRAM_PROC11_HW2_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VSRAM_PROC11_HW2_OP_CFG_SHIFT 3
#define PMIC_RG_LDO_VSRAM_PROC11_OP_CFG_SET_ADDR  \
MT6358_LDO_VSRAM_PROC11_OP_CFG_SET
#define PMIC_RG_LDO_VSRAM_PROC11_OP_CFG_SET_MASK  0xFFFF
#define PMIC_RG_LDO_VSRAM_PROC11_OP_CFG_SET_SHIFT 0
#define PMIC_RG_LDO_VSRAM_PROC11_OP_CFG_CLR_ADDR  \
MT6358_LDO_VSRAM_PROC11_OP_CFG_CLR
#define PMIC_RG_LDO_VSRAM_PROC11_OP_CFG_CLR_MASK  0xFFFF
#define PMIC_RG_LDO_VSRAM_PROC11_OP_CFG_CLR_SHIFT 0
#define PMIC_DA_VSRAM_PROC11_MODE_ADDR  MT6358_LDO_VSRAM_PROC11_CON3
#define PMIC_DA_VSRAM_PROC11_MODE_MASK  0x1
#define PMIC_DA_VSRAM_PROC11_MODE_SHIFT 8
#define PMIC_RG_LDO_VSRAM_PROC11_STBTD_ADDR MT6358_LDO_VSRAM_PROC11_CON3
#define PMIC_RG_LDO_VSRAM_PROC11_STBTD_MASK 0x3
#define PMIC_RG_LDO_VSRAM_PROC11_STBTD_SHIFT  9
#define PMIC_RG_LDO_VSRAM_PROC11_OCFB_EN_ADDR MT6358_LDO_VSRAM_PROC11_CON4
#define PMIC_RG_LDO_VSRAM_PROC11_OCFB_EN_MASK 0x1
#define PMIC_RG_LDO_VSRAM_PROC11_OCFB_EN_SHIFT   9
#define PMIC_DA_VSRAM_PROC11_OCFB_EN_ADDR   MT6358_LDO_VSRAM_PROC11_CON4
#define PMIC_DA_VSRAM_PROC11_OCFB_EN_MASK   0x1
#define PMIC_DA_VSRAM_PROC11_OCFB_EN_SHIFT  10
#define PMIC_RG_LDO_VSRAM_PROC11_DUMMY_LOAD_ADDR  MT6358_LDO_VSRAM_PROC11_CON5
#define PMIC_RG_LDO_VSRAM_PROC11_DUMMY_LOAD_MASK  0x3
#define PMIC_RG_LDO_VSRAM_PROC11_DUMMY_LOAD_SHIFT 5
#define PMIC_DA_VSRAM_PROC11_DUMMY_LOAD_ADDR  MT6358_LDO_VSRAM_PROC11_CON5
#define PMIC_DA_VSRAM_PROC11_DUMMY_LOAD_MASK  0x3
#define PMIC_DA_VSRAM_PROC11_DUMMY_LOAD_SHIFT 14
#define PMIC_DA_VSRAM_PROC11_VOSEL_GRAY_ADDR  MT6358_LDO_VSRAM_PROC11_DBG0
#define PMIC_DA_VSRAM_PROC11_VOSEL_GRAY_MASK  0x7F
#define PMIC_DA_VSRAM_PROC11_VOSEL_GRAY_SHIFT 0
#define PMIC_DA_VSRAM_PROC11_VOSEL_ADDR MT6358_LDO_VSRAM_PROC11_DBG0
#define PMIC_DA_VSRAM_PROC11_VOSEL_MASK 0x7F
#define PMIC_DA_VSRAM_PROC11_VOSEL_SHIFT   8
#define PMIC_DA_VSRAM_PROC11_EN_ADDR  MT6358_LDO_VSRAM_PROC11_DBG1
#define PMIC_DA_VSRAM_PROC11_EN_MASK  0x1
#define PMIC_DA_VSRAM_PROC11_EN_SHIFT 0
#define PMIC_DA_VSRAM_PROC11_STB_ADDR MT6358_LDO_VSRAM_PROC11_DBG1
#define PMIC_DA_VSRAM_PROC11_STB_MASK 0x1
#define PMIC_DA_VSRAM_PROC11_STB_SHIFT  1
#define PMIC_DA_VSRAM_PROC11_VSLEEP_SEL_ADDR  MT6358_LDO_VSRAM_PROC11_DBG1
#define PMIC_DA_VSRAM_PROC11_VSLEEP_SEL_MASK  0x1
#define PMIC_DA_VSRAM_PROC11_VSLEEP_SEL_SHIFT 2
#define PMIC_DA_VSRAM_PROC11_R2R_PDN_ADDR   MT6358_LDO_VSRAM_PROC11_DBG1
#define PMIC_DA_VSRAM_PROC11_R2R_PDN_MASK   0x1
#define PMIC_DA_VSRAM_PROC11_R2R_PDN_SHIFT  3
#define PMIC_DA_VSRAM_PROC11_TRACK_NDIS_EN_ADDR  MT6358_LDO_VSRAM_PROC11_DBG1
#define PMIC_DA_VSRAM_PROC11_TRACK_NDIS_EN_MASK  0x1
#define PMIC_DA_VSRAM_PROC11_TRACK_NDIS_EN_SHIFT  4
#define PMIC_RG_LDO_VSRAM_PROC11_TRACK_SLEEP_CTRL_ADDR \
MT6358_LDO_VSRAM_PROC11_TRACKING_CON0
#define PMIC_RG_LDO_VSRAM_PROC11_TRACK_SLEEP_CTRL_MASK 0x1
#define PMIC_RG_LDO_VSRAM_PROC11_TRACK_SLEEP_CTRL_SHIFT 0
#define PMIC_RG_LDO_VSRAM_PROC11_TRACK_ON_CTRL_ADDR \
MT6358_LDO_VSRAM_PROC11_TRACKING_CON0
#define PMIC_RG_LDO_VSRAM_PROC11_TRACK_ON_CTRL_MASK 0x1
#define PMIC_RG_LDO_VSRAM_PROC11_TRACK_ON_CTRL_SHIFT   1
#define PMIC_RG_LDO_VSRAM_PROC11_TRACK_VPROC11_ON_CTRL_ADDR  \
MT6358_LDO_VSRAM_PROC11_TRACKING_CON0
#define PMIC_RG_LDO_VSRAM_PROC11_TRACK_VPROC11_ON_CTRL_MASK  0x1
#define PMIC_RG_LDO_VSRAM_PROC11_TRACK_VPROC11_ON_CTRL_SHIFT 2
#define PMIC_RG_LDO_VSRAM_PROC11_VOSEL_DELTA_ADDR \
MT6358_LDO_VSRAM_PROC11_TRACKING_CON1
#define PMIC_RG_LDO_VSRAM_PROC11_VOSEL_DELTA_MASK 0x7F
#define PMIC_RG_LDO_VSRAM_PROC11_VOSEL_DELTA_SHIFT  0
#define PMIC_RG_LDO_VSRAM_PROC11_VOSEL_OFFSET_ADDR  \
MT6358_LDO_VSRAM_PROC11_TRACKING_CON1
#define PMIC_RG_LDO_VSRAM_PROC11_VOSEL_OFFSET_MASK  0x7F
#define PMIC_RG_LDO_VSRAM_PROC11_VOSEL_OFFSET_SHIFT 8
#define PMIC_RG_LDO_VSRAM_PROC11_VOSEL_ON_LB_ADDR \
MT6358_LDO_VSRAM_PROC11_TRACKING_CON2
#define PMIC_RG_LDO_VSRAM_PROC11_VOSEL_ON_LB_MASK 0x7F
#define PMIC_RG_LDO_VSRAM_PROC11_VOSEL_ON_LB_SHIFT  0
#define PMIC_RG_LDO_VSRAM_PROC11_VOSEL_ON_HB_ADDR \
MT6358_LDO_VSRAM_PROC11_TRACKING_CON2
#define PMIC_RG_LDO_VSRAM_PROC11_VOSEL_ON_HB_MASK 0x7F
#define PMIC_RG_LDO_VSRAM_PROC11_VOSEL_ON_HB_SHIFT  8
#define PMIC_RG_LDO_VSRAM_PROC11_VOSEL_SLEEP_LB_ADDR   \
MT6358_LDO_VSRAM_PROC11_TRACKING_CON3
#define PMIC_RG_LDO_VSRAM_PROC11_VOSEL_SLEEP_LB_MASK   0x7F
#define PMIC_RG_LDO_VSRAM_PROC11_VOSEL_SLEEP_LB_SHIFT  0
#define PMIC_RG_LDO_VSRAM_PROC12_TRACK_SLEEP_CTRL_ADDR \
MT6358_LDO_VSRAM_PROC12_TRACKING_CON0
#define PMIC_RG_LDO_VSRAM_PROC12_TRACK_SLEEP_CTRL_MASK 0x1
#define PMIC_RG_LDO_VSRAM_PROC12_TRACK_SLEEP_CTRL_SHIFT 0
#define PMIC_RG_LDO_VSRAM_PROC12_TRACK_ON_CTRL_ADDR \
MT6358_LDO_VSRAM_PROC12_TRACKING_CON0
#define PMIC_RG_LDO_VSRAM_PROC12_TRACK_ON_CTRL_MASK 0x1
#define PMIC_RG_LDO_VSRAM_PROC12_TRACK_ON_CTRL_SHIFT   1
#define PMIC_RG_LDO_VSRAM_PROC12_TRACK_VPROC12_ON_CTRL_ADDR  \
MT6358_LDO_VSRAM_PROC12_TRACKING_CON0
#define PMIC_RG_LDO_VSRAM_PROC12_TRACK_VPROC12_ON_CTRL_MASK  0x1
#define PMIC_RG_LDO_VSRAM_PROC12_TRACK_VPROC12_ON_CTRL_SHIFT 2
#define PMIC_RG_LDO_VSRAM_PROC12_VOSEL_DELTA_ADDR \
MT6358_LDO_VSRAM_PROC12_TRACKING_CON1
#define PMIC_RG_LDO_VSRAM_PROC12_VOSEL_DELTA_MASK 0x7F
#define PMIC_RG_LDO_VSRAM_PROC12_VOSEL_DELTA_SHIFT  0
#define PMIC_RG_LDO_VSRAM_PROC12_VOSEL_OFFSET_ADDR  \
MT6358_LDO_VSRAM_PROC12_TRACKING_CON1
#define PMIC_RG_LDO_VSRAM_PROC12_VOSEL_OFFSET_MASK  0x7F
#define PMIC_RG_LDO_VSRAM_PROC12_VOSEL_OFFSET_SHIFT 8
#define PMIC_RG_LDO_VSRAM_PROC12_VOSEL_ON_LB_ADDR \
MT6358_LDO_VSRAM_PROC12_TRACKING_CON2
#define PMIC_RG_LDO_VSRAM_PROC12_VOSEL_ON_LB_MASK 0x7F
#define PMIC_RG_LDO_VSRAM_PROC12_VOSEL_ON_LB_SHIFT  0
#define PMIC_RG_LDO_VSRAM_PROC12_VOSEL_ON_HB_ADDR \
MT6358_LDO_VSRAM_PROC12_TRACKING_CON2
#define PMIC_RG_LDO_VSRAM_PROC12_VOSEL_ON_HB_MASK 0x7F
#define PMIC_RG_LDO_VSRAM_PROC12_VOSEL_ON_HB_SHIFT  8
#define PMIC_RG_LDO_VSRAM_PROC12_VOSEL_SLEEP_LB_ADDR   \
MT6358_LDO_VSRAM_PROC12_TRACKING_CON3
#define PMIC_RG_LDO_VSRAM_PROC12_VOSEL_SLEEP_LB_MASK   0x7F
#define PMIC_RG_LDO_VSRAM_PROC12_VOSEL_SLEEP_LB_SHIFT  0
#define PMIC_RG_LDO_VSRAM_WAKEUP_TIME_ADDR  MT6358_LDO_VSRAM_WAKEUP_CON0
#define PMIC_RG_LDO_VSRAM_WAKEUP_TIME_MASK  0x3
#define PMIC_RG_LDO_VSRAM_WAKEUP_TIME_SHIFT 0
#define PMIC_LDO_GON1_ELR_LEN_ADDR MT6358_LDO_GON1_ELR_NUM
#define PMIC_LDO_GON1_ELR_LEN_MASK 0xFF
#define PMIC_LDO_GON1_ELR_LEN_SHIFT   0
#define PMIC_RG_LDO_VDRAM2_VOSEL_0_ADDR MT6358_LDO_VDRAM2_ELR0
#define PMIC_RG_LDO_VDRAM2_VOSEL_0_MASK 0xF
#define PMIC_RG_LDO_VDRAM2_VOSEL_0_SHIFT   0
#define PMIC_RG_LDO_VDRAM2_VOSEL_1_ADDR MT6358_LDO_VDRAM2_ELR1
#define PMIC_RG_LDO_VDRAM2_VOSEL_1_MASK 0xF
#define PMIC_RG_LDO_VDRAM2_VOSEL_1_SHIFT   0
#define PMIC_RG_LDO_FROM_STRUP_EN_ADDR  MT6358_LDO_STRUP_ELR0
#define PMIC_RG_LDO_FROM_STRUP_EN_MASK  0x1
#define PMIC_RG_LDO_FROM_STRUP_EN_SHIFT 0
#define PMIC_LDO_GON2_ANA_ID_ADDR MT6358_LDO_GON2_DSN_ID
#define PMIC_LDO_GON2_ANA_ID_MASK 0xFF
#define PMIC_LDO_GON2_ANA_ID_SHIFT 0
#define PMIC_LDO_GON2_DIG_ID_ADDR MT6358_LDO_GON2_DSN_ID
#define PMIC_LDO_GON2_DIG_ID_MASK 0xFF
#define PMIC_LDO_GON2_DIG_ID_SHIFT 8
#define PMIC_LDO_GON2_ANA_MINOR_REV_ADDR   MT6358_LDO_GON2_DSN_REV0
#define PMIC_LDO_GON2_ANA_MINOR_REV_MASK   0xF
#define PMIC_LDO_GON2_ANA_MINOR_REV_SHIFT   0
#define PMIC_LDO_GON2_ANA_MAJOR_REV_ADDR   MT6358_LDO_GON2_DSN_REV0
#define PMIC_LDO_GON2_ANA_MAJOR_REV_MASK   0xF
#define PMIC_LDO_GON2_ANA_MAJOR_REV_SHIFT   4
#define PMIC_LDO_GON2_DIG_MINOR_REV_ADDR   MT6358_LDO_GON2_DSN_REV0
#define PMIC_LDO_GON2_DIG_MINOR_REV_MASK   0xF
#define PMIC_LDO_GON2_DIG_MINOR_REV_SHIFT   8
#define PMIC_LDO_GON2_DIG_MAJOR_REV_ADDR   MT6358_LDO_GON2_DSN_REV0
#define PMIC_LDO_GON2_DIG_MAJOR_REV_MASK   0xF
#define PMIC_LDO_GON2_DIG_MAJOR_REV_SHIFT   12
#define PMIC_LDO_GON2_DSN_CBS_ADDR MT6358_LDO_GON2_DSN_DBI
#define PMIC_LDO_GON2_DSN_CBS_MASK 0x3
#define PMIC_LDO_GON2_DSN_CBS_SHIFT   0
#define PMIC_LDO_GON2_DSN_BIX_ADDR MT6358_LDO_GON2_DSN_DBI
#define PMIC_LDO_GON2_DSN_BIX_MASK 0x3
#define PMIC_LDO_GON2_DSN_BIX_SHIFT   2
#define PMIC_LDO_GON2_DSN_ESP_ADDR MT6358_LDO_GON2_DSN_DBI
#define PMIC_LDO_GON2_DSN_ESP_MASK 0xFF
#define PMIC_LDO_GON2_DSN_ESP_SHIFT   8
#define PMIC_LDO_GON2_DSN_FPI_ADDR MT6358_LDO_GON2_DSN_DXI
#define PMIC_LDO_GON2_DSN_FPI_MASK 0xFF
#define PMIC_LDO_GON2_DSN_FPI_SHIFT   0
#define PMIC_RG_LDO_VSRAM_PROC12_EN_ADDR   MT6358_LDO_VSRAM_PROC12_CON0
#define PMIC_RG_LDO_VSRAM_PROC12_EN_MASK   0x1
#define PMIC_RG_LDO_VSRAM_PROC12_EN_SHIFT   0
#define PMIC_RG_LDO_VSRAM_PROC12_LP_ADDR   MT6358_LDO_VSRAM_PROC12_CON0
#define PMIC_RG_LDO_VSRAM_PROC12_LP_MASK   0x1
#define PMIC_RG_LDO_VSRAM_PROC12_LP_SHIFT   1
#define PMIC_RG_LDO_VSRAM_PROC12_VOSEL_SLEEP_ADDR MT6358_LDO_VSRAM_PROC12_CON2
#define PMIC_RG_LDO_VSRAM_PROC12_VOSEL_SLEEP_MASK 0x7F
#define PMIC_RG_LDO_VSRAM_PROC12_VOSEL_SLEEP_SHIFT  0
#define PMIC_RG_LDO_VSRAM_PROC12_SFCHG_FRATE_ADDR MT6358_LDO_VSRAM_PROC12_CFG0
#define PMIC_RG_LDO_VSRAM_PROC12_SFCHG_FRATE_MASK 0x7F
#define PMIC_RG_LDO_VSRAM_PROC12_SFCHG_FRATE_SHIFT  0
#define PMIC_RG_LDO_VSRAM_PROC12_SFCHG_FEN_ADDR  MT6358_LDO_VSRAM_PROC12_CFG0
#define PMIC_RG_LDO_VSRAM_PROC12_SFCHG_FEN_MASK  0x1
#define PMIC_RG_LDO_VSRAM_PROC12_SFCHG_FEN_SHIFT  7
#define PMIC_RG_LDO_VSRAM_PROC12_SFCHG_RRATE_ADDR MT6358_LDO_VSRAM_PROC12_CFG0
#define PMIC_RG_LDO_VSRAM_PROC12_SFCHG_RRATE_MASK 0x7F
#define PMIC_RG_LDO_VSRAM_PROC12_SFCHG_RRATE_SHIFT  8
#define PMIC_RG_LDO_VSRAM_PROC12_SFCHG_REN_ADDR  MT6358_LDO_VSRAM_PROC12_CFG0
#define PMIC_RG_LDO_VSRAM_PROC12_SFCHG_REN_MASK  0x1
#define PMIC_RG_LDO_VSRAM_PROC12_SFCHG_REN_SHIFT  15
#define PMIC_RG_LDO_VSRAM_PROC12_DVS_TRANS_TD_ADDR  \
MT6358_LDO_VSRAM_PROC12_CFG1
#define PMIC_RG_LDO_VSRAM_PROC12_DVS_TRANS_TD_MASK  0x3
#define PMIC_RG_LDO_VSRAM_PROC12_DVS_TRANS_TD_SHIFT 0
#define PMIC_RG_LDO_VSRAM_PROC12_DVS_TRANS_CTRL_ADDR   \
MT6358_LDO_VSRAM_PROC12_CFG1
#define PMIC_RG_LDO_VSRAM_PROC12_DVS_TRANS_CTRL_MASK   0x3
#define PMIC_RG_LDO_VSRAM_PROC12_DVS_TRANS_CTRL_SHIFT  4
#define PMIC_RG_LDO_VSRAM_PROC12_DVS_TRANS_ONCE_ADDR   \
MT6358_LDO_VSRAM_PROC12_CFG1
#define PMIC_RG_LDO_VSRAM_PROC12_DVS_TRANS_ONCE_MASK   0x1
#define PMIC_RG_LDO_VSRAM_PROC12_DVS_TRANS_ONCE_SHIFT  6
#define PMIC_RG_LDO_VSRAM_PROC12_SW_OP_EN_ADDR   MT6358_LDO_VSRAM_PROC12_OP_EN
#define PMIC_RG_LDO_VSRAM_PROC12_SW_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VSRAM_PROC12_SW_OP_EN_SHIFT  0
#define PMIC_RG_LDO_VSRAM_PROC12_HW0_OP_EN_ADDR  MT6358_LDO_VSRAM_PROC12_OP_EN
#define PMIC_RG_LDO_VSRAM_PROC12_HW0_OP_EN_MASK  0x1
#define PMIC_RG_LDO_VSRAM_PROC12_HW0_OP_EN_SHIFT  1
#define PMIC_RG_LDO_VSRAM_PROC12_HW1_OP_EN_ADDR  MT6358_LDO_VSRAM_PROC12_OP_EN
#define PMIC_RG_LDO_VSRAM_PROC12_HW1_OP_EN_MASK  0x1
#define PMIC_RG_LDO_VSRAM_PROC12_HW1_OP_EN_SHIFT  2
#define PMIC_RG_LDO_VSRAM_PROC12_HW2_OP_EN_ADDR  MT6358_LDO_VSRAM_PROC12_OP_EN
#define PMIC_RG_LDO_VSRAM_PROC12_HW2_OP_EN_MASK  0x1
#define PMIC_RG_LDO_VSRAM_PROC12_HW2_OP_EN_SHIFT  3
#define PMIC_RG_LDO_VSRAM_PROC12_OP_EN_SET_ADDR  \
MT6358_LDO_VSRAM_PROC12_OP_EN_SET
#define PMIC_RG_LDO_VSRAM_PROC12_OP_EN_SET_MASK  0xFFFF
#define PMIC_RG_LDO_VSRAM_PROC12_OP_EN_SET_SHIFT  0
#define PMIC_RG_LDO_VSRAM_PROC12_OP_EN_CLR_ADDR  \
MT6358_LDO_VSRAM_PROC12_OP_EN_CLR
#define PMIC_RG_LDO_VSRAM_PROC12_OP_EN_CLR_MASK  0xFFFF
#define PMIC_RG_LDO_VSRAM_PROC12_OP_EN_CLR_SHIFT  0
#define PMIC_RG_LDO_VSRAM_PROC12_HW0_OP_CFG_ADDR  \
MT6358_LDO_VSRAM_PROC12_OP_CFG
#define PMIC_RG_LDO_VSRAM_PROC12_HW0_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VSRAM_PROC12_HW0_OP_CFG_SHIFT 1
#define PMIC_RG_LDO_VSRAM_PROC12_HW1_OP_CFG_ADDR  \
MT6358_LDO_VSRAM_PROC12_OP_CFG
#define PMIC_RG_LDO_VSRAM_PROC12_HW1_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VSRAM_PROC12_HW1_OP_CFG_SHIFT 2
#define PMIC_RG_LDO_VSRAM_PROC12_HW2_OP_CFG_ADDR  \
MT6358_LDO_VSRAM_PROC12_OP_CFG
#define PMIC_RG_LDO_VSRAM_PROC12_HW2_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VSRAM_PROC12_HW2_OP_CFG_SHIFT 3
#define PMIC_RG_LDO_VSRAM_PROC12_OP_CFG_SET_ADDR  \
MT6358_LDO_VSRAM_PROC12_OP_CFG_SET
#define PMIC_RG_LDO_VSRAM_PROC12_OP_CFG_SET_MASK  0xFFFF
#define PMIC_RG_LDO_VSRAM_PROC12_OP_CFG_SET_SHIFT 0
#define PMIC_RG_LDO_VSRAM_PROC12_OP_CFG_CLR_ADDR  \
MT6358_LDO_VSRAM_PROC12_OP_CFG_CLR
#define PMIC_RG_LDO_VSRAM_PROC12_OP_CFG_CLR_MASK  0xFFFF
#define PMIC_RG_LDO_VSRAM_PROC12_OP_CFG_CLR_SHIFT 0
#define PMIC_DA_VSRAM_PROC12_MODE_ADDR  MT6358_LDO_VSRAM_PROC12_CON3
#define PMIC_DA_VSRAM_PROC12_MODE_MASK  0x1
#define PMIC_DA_VSRAM_PROC12_MODE_SHIFT 8
#define PMIC_RG_LDO_VSRAM_PROC12_STBTD_ADDR MT6358_LDO_VSRAM_PROC12_CON3
#define PMIC_RG_LDO_VSRAM_PROC12_STBTD_MASK 0x3
#define PMIC_RG_LDO_VSRAM_PROC12_STBTD_SHIFT  9
#define PMIC_RG_LDO_VSRAM_PROC12_OCFB_EN_ADDR MT6358_LDO_VSRAM_PROC12_CON4
#define PMIC_RG_LDO_VSRAM_PROC12_OCFB_EN_MASK 0x1
#define PMIC_RG_LDO_VSRAM_PROC12_OCFB_EN_SHIFT   9
#define PMIC_DA_VSRAM_PROC12_OCFB_EN_ADDR   MT6358_LDO_VSRAM_PROC12_CON4
#define PMIC_DA_VSRAM_PROC12_OCFB_EN_MASK   0x1
#define PMIC_DA_VSRAM_PROC12_OCFB_EN_SHIFT  10
#define PMIC_RG_LDO_VSRAM_PROC12_DUMMY_LOAD_ADDR  MT6358_LDO_VSRAM_PROC12_CON5
#define PMIC_RG_LDO_VSRAM_PROC12_DUMMY_LOAD_MASK  0x3
#define PMIC_RG_LDO_VSRAM_PROC12_DUMMY_LOAD_SHIFT 5
#define PMIC_DA_VSRAM_PROC12_DUMMY_LOAD_ADDR  MT6358_LDO_VSRAM_PROC12_CON5
#define PMIC_DA_VSRAM_PROC12_DUMMY_LOAD_MASK  0x3
#define PMIC_DA_VSRAM_PROC12_DUMMY_LOAD_SHIFT 14
#define PMIC_DA_VSRAM_PROC12_VOSEL_GRAY_ADDR  MT6358_LDO_VSRAM_PROC12_DBG0
#define PMIC_DA_VSRAM_PROC12_VOSEL_GRAY_MASK  0x7F
#define PMIC_DA_VSRAM_PROC12_VOSEL_GRAY_SHIFT 0
#define PMIC_DA_VSRAM_PROC12_VOSEL_ADDR MT6358_LDO_VSRAM_PROC12_DBG0
#define PMIC_DA_VSRAM_PROC12_VOSEL_MASK 0x7F
#define PMIC_DA_VSRAM_PROC12_VOSEL_SHIFT   8
#define PMIC_DA_VSRAM_PROC12_EN_ADDR  MT6358_LDO_VSRAM_PROC12_DBG1
#define PMIC_DA_VSRAM_PROC12_EN_MASK  0x1
#define PMIC_DA_VSRAM_PROC12_EN_SHIFT 0
#define PMIC_DA_VSRAM_PROC12_STB_ADDR MT6358_LDO_VSRAM_PROC12_DBG1
#define PMIC_DA_VSRAM_PROC12_STB_MASK 0x1
#define PMIC_DA_VSRAM_PROC12_STB_SHIFT  1
#define PMIC_DA_VSRAM_PROC12_VSLEEP_SEL_ADDR  MT6358_LDO_VSRAM_PROC12_DBG1
#define PMIC_DA_VSRAM_PROC12_VSLEEP_SEL_MASK  0x1
#define PMIC_DA_VSRAM_PROC12_VSLEEP_SEL_SHIFT 2
#define PMIC_DA_VSRAM_PROC12_R2R_PDN_ADDR   MT6358_LDO_VSRAM_PROC12_DBG1
#define PMIC_DA_VSRAM_PROC12_R2R_PDN_MASK   0x1
#define PMIC_DA_VSRAM_PROC12_R2R_PDN_SHIFT  3
#define PMIC_DA_VSRAM_PROC12_TRACK_NDIS_EN_ADDR  MT6358_LDO_VSRAM_PROC12_DBG1
#define PMIC_DA_VSRAM_PROC12_TRACK_NDIS_EN_MASK  0x1
#define PMIC_DA_VSRAM_PROC12_TRACK_NDIS_EN_SHIFT  4
#define PMIC_RG_LDO_VSRAM_OTHERS_EN_ADDR   MT6358_LDO_VSRAM_OTHERS_CON0
#define PMIC_RG_LDO_VSRAM_OTHERS_EN_MASK   0x1
#define PMIC_RG_LDO_VSRAM_OTHERS_EN_SHIFT   0
#define PMIC_RG_LDO_VSRAM_OTHERS_LP_ADDR   MT6358_LDO_VSRAM_OTHERS_CON0
#define PMIC_RG_LDO_VSRAM_OTHERS_LP_MASK   0x1
#define PMIC_RG_LDO_VSRAM_OTHERS_LP_SHIFT   1
#define PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_SLEEP_ADDR MT6358_LDO_VSRAM_OTHERS_CON2
#define PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_SLEEP_MASK 0x7F
#define PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_SLEEP_SHIFT  0
#define PMIC_RG_LDO_VSRAM_OTHERS_SFCHG_FRATE_ADDR MT6358_LDO_VSRAM_OTHERS_CFG0
#define PMIC_RG_LDO_VSRAM_OTHERS_SFCHG_FRATE_MASK 0x7F
#define PMIC_RG_LDO_VSRAM_OTHERS_SFCHG_FRATE_SHIFT  0
#define PMIC_RG_LDO_VSRAM_OTHERS_SFCHG_FEN_ADDR  MT6358_LDO_VSRAM_OTHERS_CFG0
#define PMIC_RG_LDO_VSRAM_OTHERS_SFCHG_FEN_MASK  0x1
#define PMIC_RG_LDO_VSRAM_OTHERS_SFCHG_FEN_SHIFT  7
#define PMIC_RG_LDO_VSRAM_OTHERS_SFCHG_RRATE_ADDR MT6358_LDO_VSRAM_OTHERS_CFG0
#define PMIC_RG_LDO_VSRAM_OTHERS_SFCHG_RRATE_MASK 0x7F
#define PMIC_RG_LDO_VSRAM_OTHERS_SFCHG_RRATE_SHIFT  8
#define PMIC_RG_LDO_VSRAM_OTHERS_SFCHG_REN_ADDR  MT6358_LDO_VSRAM_OTHERS_CFG0
#define PMIC_RG_LDO_VSRAM_OTHERS_SFCHG_REN_MASK  0x1
#define PMIC_RG_LDO_VSRAM_OTHERS_SFCHG_REN_SHIFT  15
#define PMIC_RG_LDO_VSRAM_OTHERS_DVS_TRANS_TD_ADDR  MT6358_LDO_VSRAM_OTHERS_CFG1
#define PMIC_RG_LDO_VSRAM_OTHERS_DVS_TRANS_TD_MASK  0x3
#define PMIC_RG_LDO_VSRAM_OTHERS_DVS_TRANS_TD_SHIFT 0
#define PMIC_RG_LDO_VSRAM_OTHERS_DVS_TRANS_CTRL_ADDR   \
MT6358_LDO_VSRAM_OTHERS_CFG1
#define PMIC_RG_LDO_VSRAM_OTHERS_DVS_TRANS_CTRL_MASK   0x3
#define PMIC_RG_LDO_VSRAM_OTHERS_DVS_TRANS_CTRL_SHIFT  4
#define PMIC_RG_LDO_VSRAM_OTHERS_DVS_TRANS_ONCE_ADDR   \
MT6358_LDO_VSRAM_OTHERS_CFG1
#define PMIC_RG_LDO_VSRAM_OTHERS_DVS_TRANS_ONCE_MASK   0x1
#define PMIC_RG_LDO_VSRAM_OTHERS_DVS_TRANS_ONCE_SHIFT  6
#define PMIC_RG_LDO_VSRAM_OTHERS_SW_OP_EN_ADDR   MT6358_LDO_VSRAM_OTHERS_OP_EN
#define PMIC_RG_LDO_VSRAM_OTHERS_SW_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VSRAM_OTHERS_SW_OP_EN_SHIFT  0
#define PMIC_RG_LDO_VSRAM_OTHERS_HW0_OP_EN_ADDR  MT6358_LDO_VSRAM_OTHERS_OP_EN
#define PMIC_RG_LDO_VSRAM_OTHERS_HW0_OP_EN_MASK  0x1
#define PMIC_RG_LDO_VSRAM_OTHERS_HW0_OP_EN_SHIFT  1
#define PMIC_RG_LDO_VSRAM_OTHERS_HW1_OP_EN_ADDR  MT6358_LDO_VSRAM_OTHERS_OP_EN
#define PMIC_RG_LDO_VSRAM_OTHERS_HW1_OP_EN_MASK  0x1
#define PMIC_RG_LDO_VSRAM_OTHERS_HW1_OP_EN_SHIFT  2
#define PMIC_RG_LDO_VSRAM_OTHERS_HW2_OP_EN_ADDR  MT6358_LDO_VSRAM_OTHERS_OP_EN
#define PMIC_RG_LDO_VSRAM_OTHERS_HW2_OP_EN_MASK  0x1
#define PMIC_RG_LDO_VSRAM_OTHERS_HW2_OP_EN_SHIFT  3
#define PMIC_RG_LDO_VSRAM_OTHERS_OP_EN_SET_ADDR  \
MT6358_LDO_VSRAM_OTHERS_OP_EN_SET
#define PMIC_RG_LDO_VSRAM_OTHERS_OP_EN_SET_MASK  0xFFFF
#define PMIC_RG_LDO_VSRAM_OTHERS_OP_EN_SET_SHIFT  0
#define PMIC_RG_LDO_VSRAM_OTHERS_OP_EN_CLR_ADDR  \
MT6358_LDO_VSRAM_OTHERS_OP_EN_CLR
#define PMIC_RG_LDO_VSRAM_OTHERS_OP_EN_CLR_MASK  0xFFFF
#define PMIC_RG_LDO_VSRAM_OTHERS_OP_EN_CLR_SHIFT  0
#define PMIC_RG_LDO_VSRAM_OTHERS_HW0_OP_CFG_ADDR  MT6358_LDO_VSRAM_OTHERS_OP_CFG
#define PMIC_RG_LDO_VSRAM_OTHERS_HW0_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VSRAM_OTHERS_HW0_OP_CFG_SHIFT 1
#define PMIC_RG_LDO_VSRAM_OTHERS_HW1_OP_CFG_ADDR  MT6358_LDO_VSRAM_OTHERS_OP_CFG
#define PMIC_RG_LDO_VSRAM_OTHERS_HW1_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VSRAM_OTHERS_HW1_OP_CFG_SHIFT 2
#define PMIC_RG_LDO_VSRAM_OTHERS_HW2_OP_CFG_ADDR  MT6358_LDO_VSRAM_OTHERS_OP_CFG
#define PMIC_RG_LDO_VSRAM_OTHERS_HW2_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VSRAM_OTHERS_HW2_OP_CFG_SHIFT 3
#define PMIC_RG_LDO_VSRAM_OTHERS_OP_CFG_SET_ADDR  \
MT6358_LDO_VSRAM_OTHERS_OP_CFG_SET
#define PMIC_RG_LDO_VSRAM_OTHERS_OP_CFG_SET_MASK  0xFFFF
#define PMIC_RG_LDO_VSRAM_OTHERS_OP_CFG_SET_SHIFT 0
#define PMIC_RG_LDO_VSRAM_OTHERS_OP_CFG_CLR_ADDR  \
MT6358_LDO_VSRAM_OTHERS_OP_CFG_CLR
#define PMIC_RG_LDO_VSRAM_OTHERS_OP_CFG_CLR_MASK  0xFFFF
#define PMIC_RG_LDO_VSRAM_OTHERS_OP_CFG_CLR_SHIFT 0
#define PMIC_DA_VSRAM_OTHERS_MODE_ADDR  MT6358_LDO_VSRAM_OTHERS_CON3
#define PMIC_DA_VSRAM_OTHERS_MODE_MASK  0x1
#define PMIC_DA_VSRAM_OTHERS_MODE_SHIFT 8
#define PMIC_RG_LDO_VSRAM_OTHERS_STBTD_ADDR MT6358_LDO_VSRAM_OTHERS_CON3
#define PMIC_RG_LDO_VSRAM_OTHERS_STBTD_MASK 0x3
#define PMIC_RG_LDO_VSRAM_OTHERS_STBTD_SHIFT  9
#define PMIC_RG_LDO_VSRAM_OTHERS_OCFB_EN_ADDR MT6358_LDO_VSRAM_OTHERS_CON4
#define PMIC_RG_LDO_VSRAM_OTHERS_OCFB_EN_MASK 0x1
#define PMIC_RG_LDO_VSRAM_OTHERS_OCFB_EN_SHIFT   9
#define PMIC_DA_VSRAM_OTHERS_OCFB_EN_ADDR   MT6358_LDO_VSRAM_OTHERS_CON4
#define PMIC_DA_VSRAM_OTHERS_OCFB_EN_MASK   0x1
#define PMIC_DA_VSRAM_OTHERS_OCFB_EN_SHIFT  10
#define PMIC_RG_LDO_VSRAM_OTHERS_DUMMY_LOAD_ADDR  MT6358_LDO_VSRAM_OTHERS_CON5
#define PMIC_RG_LDO_VSRAM_OTHERS_DUMMY_LOAD_MASK  0x3
#define PMIC_RG_LDO_VSRAM_OTHERS_DUMMY_LOAD_SHIFT 5
#define PMIC_DA_VSRAM_OTHERS_DUMMY_LOAD_ADDR  MT6358_LDO_VSRAM_OTHERS_CON5
#define PMIC_DA_VSRAM_OTHERS_DUMMY_LOAD_MASK  0x3
#define PMIC_DA_VSRAM_OTHERS_DUMMY_LOAD_SHIFT 14
#define PMIC_DA_VSRAM_OTHERS_VOSEL_GRAY_ADDR  MT6358_LDO_VSRAM_OTHERS_DBG0
#define PMIC_DA_VSRAM_OTHERS_VOSEL_GRAY_MASK  0x7F
#define PMIC_DA_VSRAM_OTHERS_VOSEL_GRAY_SHIFT 0
#define PMIC_DA_VSRAM_OTHERS_VOSEL_ADDR MT6358_LDO_VSRAM_OTHERS_DBG0
#define PMIC_DA_VSRAM_OTHERS_VOSEL_MASK 0x7F
#define PMIC_DA_VSRAM_OTHERS_VOSEL_SHIFT   8
#define PMIC_DA_VSRAM_OTHERS_EN_ADDR  MT6358_LDO_VSRAM_OTHERS_DBG1
#define PMIC_DA_VSRAM_OTHERS_EN_MASK  0x1
#define PMIC_DA_VSRAM_OTHERS_EN_SHIFT 0
#define PMIC_DA_VSRAM_OTHERS_STB_ADDR MT6358_LDO_VSRAM_OTHERS_DBG1
#define PMIC_DA_VSRAM_OTHERS_STB_MASK 0x1
#define PMIC_DA_VSRAM_OTHERS_STB_SHIFT  1
#define PMIC_DA_VSRAM_OTHERS_VSLEEP_SEL_ADDR  MT6358_LDO_VSRAM_OTHERS_DBG1
#define PMIC_DA_VSRAM_OTHERS_VSLEEP_SEL_MASK  0x1
#define PMIC_DA_VSRAM_OTHERS_VSLEEP_SEL_SHIFT 2
#define PMIC_DA_VSRAM_OTHERS_R2R_PDN_ADDR   MT6358_LDO_VSRAM_OTHERS_DBG1
#define PMIC_DA_VSRAM_OTHERS_R2R_PDN_MASK   0x1
#define PMIC_DA_VSRAM_OTHERS_R2R_PDN_SHIFT  3
#define PMIC_DA_VSRAM_OTHERS_TRACK_NDIS_EN_ADDR  MT6358_LDO_VSRAM_OTHERS_DBG1
#define PMIC_DA_VSRAM_OTHERS_TRACK_NDIS_EN_MASK  0x1
#define PMIC_DA_VSRAM_OTHERS_TRACK_NDIS_EN_SHIFT  4
#define PMIC_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR   \
MT6358_LDO_VSRAM_OTHERS_SSHUB_CON0
#define PMIC_RG_LDO_VSRAM_OTHERS_SSHUB_EN_MASK   0x1
#define PMIC_RG_LDO_VSRAM_OTHERS_SSHUB_EN_SHIFT  0
#define PMIC_RG_LDO_VSRAM_OTHERS_SSHUB_SLEEP_VOSEL_EN_ADDR   \
MT6358_LDO_VSRAM_OTHERS_SSHUB_CON0
#define PMIC_RG_LDO_VSRAM_OTHERS_SSHUB_SLEEP_VOSEL_EN_MASK   0x1
#define PMIC_RG_LDO_VSRAM_OTHERS_SSHUB_SLEEP_VOSEL_EN_SHIFT  1
#define PMIC_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR \
MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1
#define PMIC_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK 0x7F
#define PMIC_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT  0
#define PMIC_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SLEEP_ADDR \
MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1
#define PMIC_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SLEEP_MASK 0x7F
#define PMIC_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SLEEP_SHIFT  8
#define PMIC_RG_LDO_VSRAM_GPU_EN_ADDR MT6358_LDO_VSRAM_GPU_CON0
#define PMIC_RG_LDO_VSRAM_GPU_EN_MASK 0x1
#define PMIC_RG_LDO_VSRAM_GPU_EN_SHIFT  0
#define PMIC_RG_LDO_VSRAM_GPU_LP_ADDR MT6358_LDO_VSRAM_GPU_CON0
#define PMIC_RG_LDO_VSRAM_GPU_LP_MASK 0x1
#define PMIC_RG_LDO_VSRAM_GPU_LP_SHIFT  1
#define PMIC_RG_LDO_VSRAM_GPU_VOSEL_SLEEP_ADDR   MT6358_LDO_VSRAM_GPU_CON2
#define PMIC_RG_LDO_VSRAM_GPU_VOSEL_SLEEP_MASK   0x7F
#define PMIC_RG_LDO_VSRAM_GPU_VOSEL_SLEEP_SHIFT  0
#define PMIC_RG_LDO_VSRAM_GPU_SFCHG_FRATE_ADDR   MT6358_LDO_VSRAM_GPU_CFG0
#define PMIC_RG_LDO_VSRAM_GPU_SFCHG_FRATE_MASK   0x7F
#define PMIC_RG_LDO_VSRAM_GPU_SFCHG_FRATE_SHIFT  0
#define PMIC_RG_LDO_VSRAM_GPU_SFCHG_FEN_ADDR  MT6358_LDO_VSRAM_GPU_CFG0
#define PMIC_RG_LDO_VSRAM_GPU_SFCHG_FEN_MASK  0x1
#define PMIC_RG_LDO_VSRAM_GPU_SFCHG_FEN_SHIFT 7
#define PMIC_RG_LDO_VSRAM_GPU_SFCHG_RRATE_ADDR   MT6358_LDO_VSRAM_GPU_CFG0
#define PMIC_RG_LDO_VSRAM_GPU_SFCHG_RRATE_MASK   0x7F
#define PMIC_RG_LDO_VSRAM_GPU_SFCHG_RRATE_SHIFT  8
#define PMIC_RG_LDO_VSRAM_GPU_SFCHG_REN_ADDR  MT6358_LDO_VSRAM_GPU_CFG0
#define PMIC_RG_LDO_VSRAM_GPU_SFCHG_REN_MASK  0x1
#define PMIC_RG_LDO_VSRAM_GPU_SFCHG_REN_SHIFT 15
#define PMIC_RG_LDO_VSRAM_GPU_DVS_TRANS_TD_ADDR  MT6358_LDO_VSRAM_GPU_CFG1
#define PMIC_RG_LDO_VSRAM_GPU_DVS_TRANS_TD_MASK  0x3
#define PMIC_RG_LDO_VSRAM_GPU_DVS_TRANS_TD_SHIFT  0
#define PMIC_RG_LDO_VSRAM_GPU_DVS_TRANS_CTRL_ADDR MT6358_LDO_VSRAM_GPU_CFG1
#define PMIC_RG_LDO_VSRAM_GPU_DVS_TRANS_CTRL_MASK 0x3
#define PMIC_RG_LDO_VSRAM_GPU_DVS_TRANS_CTRL_SHIFT  4
#define PMIC_RG_LDO_VSRAM_GPU_DVS_TRANS_ONCE_ADDR MT6358_LDO_VSRAM_GPU_CFG1
#define PMIC_RG_LDO_VSRAM_GPU_DVS_TRANS_ONCE_MASK 0x1
#define PMIC_RG_LDO_VSRAM_GPU_DVS_TRANS_ONCE_SHIFT  6
#define PMIC_RG_LDO_VSRAM_GPU_SW_OP_EN_ADDR MT6358_LDO_VSRAM_GPU_OP_EN
#define PMIC_RG_LDO_VSRAM_GPU_SW_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VSRAM_GPU_SW_OP_EN_SHIFT  0
#define PMIC_RG_LDO_VSRAM_GPU_HW0_OP_EN_ADDR  MT6358_LDO_VSRAM_GPU_OP_EN
#define PMIC_RG_LDO_VSRAM_GPU_HW0_OP_EN_MASK  0x1
#define PMIC_RG_LDO_VSRAM_GPU_HW0_OP_EN_SHIFT 1
#define PMIC_RG_LDO_VSRAM_GPU_HW1_OP_EN_ADDR  MT6358_LDO_VSRAM_GPU_OP_EN
#define PMIC_RG_LDO_VSRAM_GPU_HW1_OP_EN_MASK  0x1
#define PMIC_RG_LDO_VSRAM_GPU_HW1_OP_EN_SHIFT 2
#define PMIC_RG_LDO_VSRAM_GPU_HW2_OP_EN_ADDR  MT6358_LDO_VSRAM_GPU_OP_EN
#define PMIC_RG_LDO_VSRAM_GPU_HW2_OP_EN_MASK  0x1
#define PMIC_RG_LDO_VSRAM_GPU_HW2_OP_EN_SHIFT 3
#define PMIC_RG_LDO_VSRAM_GPU_OP_EN_SET_ADDR  MT6358_LDO_VSRAM_GPU_OP_EN_SET
#define PMIC_RG_LDO_VSRAM_GPU_OP_EN_SET_MASK  0xFFFF
#define PMIC_RG_LDO_VSRAM_GPU_OP_EN_SET_SHIFT 0
#define PMIC_RG_LDO_VSRAM_GPU_OP_EN_CLR_ADDR  MT6358_LDO_VSRAM_GPU_OP_EN_CLR
#define PMIC_RG_LDO_VSRAM_GPU_OP_EN_CLR_MASK  0xFFFF
#define PMIC_RG_LDO_VSRAM_GPU_OP_EN_CLR_SHIFT 0
#define PMIC_RG_LDO_VSRAM_GPU_HW0_OP_CFG_ADDR MT6358_LDO_VSRAM_GPU_OP_CFG
#define PMIC_RG_LDO_VSRAM_GPU_HW0_OP_CFG_MASK 0x1
#define PMIC_RG_LDO_VSRAM_GPU_HW0_OP_CFG_SHIFT   1
#define PMIC_RG_LDO_VSRAM_GPU_HW1_OP_CFG_ADDR MT6358_LDO_VSRAM_GPU_OP_CFG
#define PMIC_RG_LDO_VSRAM_GPU_HW1_OP_CFG_MASK 0x1
#define PMIC_RG_LDO_VSRAM_GPU_HW1_OP_CFG_SHIFT   2
#define PMIC_RG_LDO_VSRAM_GPU_HW2_OP_CFG_ADDR MT6358_LDO_VSRAM_GPU_OP_CFG
#define PMIC_RG_LDO_VSRAM_GPU_HW2_OP_CFG_MASK 0x1
#define PMIC_RG_LDO_VSRAM_GPU_HW2_OP_CFG_SHIFT   3
#define PMIC_RG_LDO_VSRAM_GPU_OP_CFG_SET_ADDR MT6358_LDO_VSRAM_GPU_OP_CFG_SET
#define PMIC_RG_LDO_VSRAM_GPU_OP_CFG_SET_MASK 0xFFFF
#define PMIC_RG_LDO_VSRAM_GPU_OP_CFG_SET_SHIFT   0
#define PMIC_RG_LDO_VSRAM_GPU_OP_CFG_CLR_ADDR MT6358_LDO_VSRAM_GPU_OP_CFG_CLR
#define PMIC_RG_LDO_VSRAM_GPU_OP_CFG_CLR_MASK 0xFFFF
#define PMIC_RG_LDO_VSRAM_GPU_OP_CFG_CLR_SHIFT   0
#define PMIC_DA_VSRAM_GPU_MODE_ADDR   MT6358_LDO_VSRAM_GPU_CON3
#define PMIC_DA_VSRAM_GPU_MODE_MASK   0x1
#define PMIC_DA_VSRAM_GPU_MODE_SHIFT  8
#define PMIC_RG_LDO_VSRAM_GPU_STBTD_ADDR   MT6358_LDO_VSRAM_GPU_CON3
#define PMIC_RG_LDO_VSRAM_GPU_STBTD_MASK   0x3
#define PMIC_RG_LDO_VSRAM_GPU_STBTD_SHIFT   9
#define PMIC_RG_LDO_VSRAM_GPU_OCFB_EN_ADDR  MT6358_LDO_VSRAM_GPU_CON4
#define PMIC_RG_LDO_VSRAM_GPU_OCFB_EN_MASK  0x1
#define PMIC_RG_LDO_VSRAM_GPU_OCFB_EN_SHIFT 9
#define PMIC_DA_VSRAM_GPU_OCFB_EN_ADDR  MT6358_LDO_VSRAM_GPU_CON4
#define PMIC_DA_VSRAM_GPU_OCFB_EN_MASK  0x1
#define PMIC_DA_VSRAM_GPU_OCFB_EN_SHIFT 10
#define PMIC_RG_LDO_VSRAM_GPU_DUMMY_LOAD_ADDR MT6358_LDO_VSRAM_GPU_CON5
#define PMIC_RG_LDO_VSRAM_GPU_DUMMY_LOAD_MASK 0x3
#define PMIC_RG_LDO_VSRAM_GPU_DUMMY_LOAD_SHIFT   5
#define PMIC_DA_VSRAM_GPU_DUMMY_LOAD_ADDR   MT6358_LDO_VSRAM_GPU_CON5
#define PMIC_DA_VSRAM_GPU_DUMMY_LOAD_MASK   0x3
#define PMIC_DA_VSRAM_GPU_DUMMY_LOAD_SHIFT  14
#define PMIC_DA_VSRAM_GPU_VOSEL_GRAY_ADDR   MT6358_LDO_VSRAM_GPU_DBG0
#define PMIC_DA_VSRAM_GPU_VOSEL_GRAY_MASK   0x7F
#define PMIC_DA_VSRAM_GPU_VOSEL_GRAY_SHIFT  0
#define PMIC_DA_VSRAM_GPU_VOSEL_ADDR  MT6358_LDO_VSRAM_GPU_DBG0
#define PMIC_DA_VSRAM_GPU_VOSEL_MASK  0x7F
#define PMIC_DA_VSRAM_GPU_VOSEL_SHIFT 8
#define PMIC_DA_VSRAM_GPU_EN_ADDR MT6358_LDO_VSRAM_GPU_DBG1
#define PMIC_DA_VSRAM_GPU_EN_MASK 0x1
#define PMIC_DA_VSRAM_GPU_EN_SHIFT 0
#define PMIC_DA_VSRAM_GPU_STB_ADDR MT6358_LDO_VSRAM_GPU_DBG1
#define PMIC_DA_VSRAM_GPU_STB_MASK 0x1
#define PMIC_DA_VSRAM_GPU_STB_SHIFT   1
#define PMIC_DA_VSRAM_GPU_VSLEEP_SEL_ADDR   MT6358_LDO_VSRAM_GPU_DBG1
#define PMIC_DA_VSRAM_GPU_VSLEEP_SEL_MASK   0x1
#define PMIC_DA_VSRAM_GPU_VSLEEP_SEL_SHIFT  2
#define PMIC_DA_VSRAM_GPU_R2R_PDN_ADDR  MT6358_LDO_VSRAM_GPU_DBG1
#define PMIC_DA_VSRAM_GPU_R2R_PDN_MASK  0x1
#define PMIC_DA_VSRAM_GPU_R2R_PDN_SHIFT 3
#define PMIC_DA_VSRAM_GPU_TRACK_NDIS_EN_ADDR  MT6358_LDO_VSRAM_GPU_DBG1
#define PMIC_DA_VSRAM_GPU_TRACK_NDIS_EN_MASK  0x1
#define PMIC_DA_VSRAM_GPU_TRACK_NDIS_EN_SHIFT 4
#define PMIC_RG_LDO_VSRAM_PROC11_R2R_PDN_DIS_ADDR MT6358_LDO_VSRAM_R2R_PDN_DIS
#define PMIC_RG_LDO_VSRAM_PROC11_R2R_PDN_DIS_MASK 0x1
#define PMIC_RG_LDO_VSRAM_PROC11_R2R_PDN_DIS_SHIFT  0
#define PMIC_RG_LDO_VSRAM_PROC12_R2R_PDN_DIS_ADDR MT6358_LDO_VSRAM_R2R_PDN_DIS
#define PMIC_RG_LDO_VSRAM_PROC12_R2R_PDN_DIS_MASK 0x1
#define PMIC_RG_LDO_VSRAM_PROC12_R2R_PDN_DIS_SHIFT  2
#define PMIC_RG_LDO_VSRAM_OTHERS_R2R_PDN_DIS_ADDR MT6358_LDO_VSRAM_R2R_PDN_DIS
#define PMIC_RG_LDO_VSRAM_OTHERS_R2R_PDN_DIS_MASK 0x1
#define PMIC_RG_LDO_VSRAM_OTHERS_R2R_PDN_DIS_SHIFT  4
#define PMIC_RG_LDO_VSRAM_GPU_R2R_PDN_DIS_ADDR   MT6358_LDO_VSRAM_R2R_PDN_DIS
#define PMIC_RG_LDO_VSRAM_GPU_R2R_PDN_DIS_MASK   0x1
#define PMIC_RG_LDO_VSRAM_GPU_R2R_PDN_DIS_SHIFT  6
#define PMIC_LDO_VSRAM_PROC11_WDTDBG_VOSEL_ADDR  MT6358_LDO_VSRAM_WDT_DBG0
#define PMIC_LDO_VSRAM_PROC11_WDTDBG_VOSEL_MASK  0x7F
#define PMIC_LDO_VSRAM_PROC11_WDTDBG_VOSEL_SHIFT  0
#define PMIC_LDO_VSRAM_PROC12_WDTDBG_VOSEL_ADDR  MT6358_LDO_VSRAM_WDT_DBG0
#define PMIC_LDO_VSRAM_PROC12_WDTDBG_VOSEL_MASK  0x7F
#define PMIC_LDO_VSRAM_PROC12_WDTDBG_VOSEL_SHIFT  8
#define PMIC_LDO_VSRAM_OTHERS_WDTDBG_VOSEL_ADDR  MT6358_LDO_VSRAM_WDT_DBG1
#define PMIC_LDO_VSRAM_OTHERS_WDTDBG_VOSEL_MASK  0x7F
#define PMIC_LDO_VSRAM_OTHERS_WDTDBG_VOSEL_SHIFT  0
#define PMIC_LDO_VSRAM_GPU_WDTDBG_VOSEL_ADDR  MT6358_LDO_VSRAM_WDT_DBG1
#define PMIC_LDO_VSRAM_GPU_WDTDBG_VOSEL_MASK  0x7F
#define PMIC_LDO_VSRAM_GPU_WDTDBG_VOSEL_SHIFT 8
#define PMIC_LDO_GON2_ELR_LEN_ADDR MT6358_LDO_GON2_ELR_NUM
#define PMIC_LDO_GON2_ELR_LEN_MASK 0xFF
#define PMIC_LDO_GON2_ELR_LEN_SHIFT   0
#define PMIC_RG_LDO_VSRAM_PROC11_VOSEL_ADDR MT6358_LDO_VSRAM_CON0
#define PMIC_RG_LDO_VSRAM_PROC11_VOSEL_MASK 0x7F
#define PMIC_RG_LDO_VSRAM_PROC11_VOSEL_SHIFT  0
#define PMIC_RG_LDO_VSRAM_PROC12_VOSEL_ADDR MT6358_LDO_VSRAM_CON1
#define PMIC_RG_LDO_VSRAM_PROC12_VOSEL_MASK 0x7F
#define PMIC_RG_LDO_VSRAM_PROC12_VOSEL_SHIFT  0
#define PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR MT6358_LDO_VSRAM_CON2
#define PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_MASK 0x7F
#define PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT  0
#define PMIC_RG_LDO_VSRAM_GPU_VOSEL_ADDR   MT6358_LDO_VSRAM_CON3
#define PMIC_RG_LDO_VSRAM_GPU_VOSEL_MASK   0x7F
#define PMIC_RG_LDO_VSRAM_GPU_VOSEL_SHIFT   0
#define PMIC_RG_LDO_VSRAM_PROC11_VOSEL_LIMIT_SEL_ADDR  MT6358_LDO_VSRAM_CON4
#define PMIC_RG_LDO_VSRAM_PROC11_VOSEL_LIMIT_SEL_MASK  0x3
#define PMIC_RG_LDO_VSRAM_PROC11_VOSEL_LIMIT_SEL_SHIFT 0
#define PMIC_RG_LDO_VSRAM_PROC12_VOSEL_LIMIT_SEL_ADDR  MT6358_LDO_VSRAM_CON4
#define PMIC_RG_LDO_VSRAM_PROC12_VOSEL_LIMIT_SEL_MASK  0x3
#define PMIC_RG_LDO_VSRAM_PROC12_VOSEL_LIMIT_SEL_SHIFT 2
#define PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_LIMIT_SEL_ADDR  MT6358_LDO_VSRAM_CON4
#define PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_LIMIT_SEL_MASK  0x3
#define PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_LIMIT_SEL_SHIFT 4
#define PMIC_RG_LDO_VSRAM_GPU_VOSEL_LIMIT_SEL_ADDR  MT6358_LDO_VSRAM_CON4
#define PMIC_RG_LDO_VSRAM_GPU_VOSEL_LIMIT_SEL_MASK  0x3
#define PMIC_RG_LDO_VSRAM_GPU_VOSEL_LIMIT_SEL_SHIFT 6
#define PMIC_LDO_GOFF0_ANA_ID_ADDR MT6358_LDO_GOFF0_DSN_ID
#define PMIC_LDO_GOFF0_ANA_ID_MASK 0xFF
#define PMIC_LDO_GOFF0_ANA_ID_SHIFT   0
#define PMIC_LDO_GOFF0_DIG_ID_ADDR MT6358_LDO_GOFF0_DSN_ID
#define PMIC_LDO_GOFF0_DIG_ID_MASK 0xFF
#define PMIC_LDO_GOFF0_DIG_ID_SHIFT   8
#define PMIC_LDO_GOFF0_ANA_MINOR_REV_ADDR   MT6358_LDO_GOFF0_DSN_REV0
#define PMIC_LDO_GOFF0_ANA_MINOR_REV_MASK   0xF
#define PMIC_LDO_GOFF0_ANA_MINOR_REV_SHIFT  0
#define PMIC_LDO_GOFF0_ANA_MAJOR_REV_ADDR   MT6358_LDO_GOFF0_DSN_REV0
#define PMIC_LDO_GOFF0_ANA_MAJOR_REV_MASK   0xF
#define PMIC_LDO_GOFF0_ANA_MAJOR_REV_SHIFT  4
#define PMIC_LDO_GOFF0_DIG_MINOR_REV_ADDR   MT6358_LDO_GOFF0_DSN_REV0
#define PMIC_LDO_GOFF0_DIG_MINOR_REV_MASK   0xF
#define PMIC_LDO_GOFF0_DIG_MINOR_REV_SHIFT  8
#define PMIC_LDO_GOFF0_DIG_MAJOR_REV_ADDR   MT6358_LDO_GOFF0_DSN_REV0
#define PMIC_LDO_GOFF0_DIG_MAJOR_REV_MASK   0xF
#define PMIC_LDO_GOFF0_DIG_MAJOR_REV_SHIFT  12
#define PMIC_LDO_GOFF0_DSN_CBS_ADDR   MT6358_LDO_GOFF0_DSN_DBI
#define PMIC_LDO_GOFF0_DSN_CBS_MASK   0x3
#define PMIC_LDO_GOFF0_DSN_CBS_SHIFT  0
#define PMIC_LDO_GOFF0_DSN_BIX_ADDR   MT6358_LDO_GOFF0_DSN_DBI
#define PMIC_LDO_GOFF0_DSN_BIX_MASK   0x3
#define PMIC_LDO_GOFF0_DSN_BIX_SHIFT  2
#define PMIC_LDO_GOFF0_DSN_ESP_ADDR   MT6358_LDO_GOFF0_DSN_DBI
#define PMIC_LDO_GOFF0_DSN_ESP_MASK   0xFF
#define PMIC_LDO_GOFF0_DSN_ESP_SHIFT  8
#define PMIC_LDO_GOFF0_DSN_FPI_ADDR   MT6358_LDO_GOFF0_DSN_DXI
#define PMIC_LDO_GOFF0_DSN_FPI_MASK   0xFF
#define PMIC_LDO_GOFF0_DSN_FPI_SHIFT  0
#define PMIC_RG_LDO_VFE28_EN_ADDR MT6358_LDO_VFE28_CON0
#define PMIC_RG_LDO_VFE28_EN_MASK 0x1
#define PMIC_RG_LDO_VFE28_EN_SHIFT 0
#define PMIC_RG_LDO_VFE28_LP_ADDR MT6358_LDO_VFE28_CON0
#define PMIC_RG_LDO_VFE28_LP_MASK 0x1
#define PMIC_RG_LDO_VFE28_LP_SHIFT 1
#define PMIC_RG_LDO_VFE28_SW_OP_EN_ADDR MT6358_LDO_VFE28_OP_EN
#define PMIC_RG_LDO_VFE28_SW_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VFE28_SW_OP_EN_SHIFT   0
#define PMIC_RG_LDO_VFE28_HW0_OP_EN_ADDR   MT6358_LDO_VFE28_OP_EN
#define PMIC_RG_LDO_VFE28_HW0_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VFE28_HW0_OP_EN_SHIFT   1
#define PMIC_RG_LDO_VFE28_HW1_OP_EN_ADDR   MT6358_LDO_VFE28_OP_EN
#define PMIC_RG_LDO_VFE28_HW1_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VFE28_HW1_OP_EN_SHIFT   2
#define PMIC_RG_LDO_VFE28_HW2_OP_EN_ADDR   MT6358_LDO_VFE28_OP_EN
#define PMIC_RG_LDO_VFE28_HW2_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VFE28_HW2_OP_EN_SHIFT   3
#define PMIC_RG_LDO_VFE28_OP_EN_SET_ADDR   MT6358_LDO_VFE28_OP_EN_SET
#define PMIC_RG_LDO_VFE28_OP_EN_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VFE28_OP_EN_SET_SHIFT   0
#define PMIC_RG_LDO_VFE28_OP_EN_CLR_ADDR   MT6358_LDO_VFE28_OP_EN_CLR
#define PMIC_RG_LDO_VFE28_OP_EN_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VFE28_OP_EN_CLR_SHIFT   0
#define PMIC_RG_LDO_VFE28_HW0_OP_CFG_ADDR   MT6358_LDO_VFE28_OP_CFG
#define PMIC_RG_LDO_VFE28_HW0_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VFE28_HW0_OP_CFG_SHIFT  1
#define PMIC_RG_LDO_VFE28_HW1_OP_CFG_ADDR   MT6358_LDO_VFE28_OP_CFG
#define PMIC_RG_LDO_VFE28_HW1_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VFE28_HW1_OP_CFG_SHIFT  2
#define PMIC_RG_LDO_VFE28_HW2_OP_CFG_ADDR   MT6358_LDO_VFE28_OP_CFG
#define PMIC_RG_LDO_VFE28_HW2_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VFE28_HW2_OP_CFG_SHIFT  3
#define PMIC_RG_LDO_VFE28_ON_OP_ADDR  MT6358_LDO_VFE28_OP_CFG
#define PMIC_RG_LDO_VFE28_ON_OP_MASK  0x1
#define PMIC_RG_LDO_VFE28_ON_OP_SHIFT 8
#define PMIC_RG_LDO_VFE28_LP_OP_ADDR  MT6358_LDO_VFE28_OP_CFG
#define PMIC_RG_LDO_VFE28_LP_OP_MASK  0x1
#define PMIC_RG_LDO_VFE28_LP_OP_SHIFT 9
#define PMIC_RG_LDO_VFE28_OP_CFG_SET_ADDR   MT6358_LDO_VFE28_OP_CFG_SET
#define PMIC_RG_LDO_VFE28_OP_CFG_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VFE28_OP_CFG_SET_SHIFT  0
#define PMIC_RG_LDO_VFE28_OP_CFG_CLR_ADDR   MT6358_LDO_VFE28_OP_CFG_CLR
#define PMIC_RG_LDO_VFE28_OP_CFG_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VFE28_OP_CFG_CLR_SHIFT  0
#define PMIC_DA_VFE28_MODE_ADDR MT6358_LDO_VFE28_CON1
#define PMIC_DA_VFE28_MODE_MASK 0x1
#define PMIC_DA_VFE28_MODE_SHIFT  8
#define PMIC_RG_LDO_VFE28_STBTD_ADDR  MT6358_LDO_VFE28_CON1
#define PMIC_RG_LDO_VFE28_STBTD_MASK  0x3
#define PMIC_RG_LDO_VFE28_STBTD_SHIFT 9
#define PMIC_DA_VFE28_STB_ADDR  MT6358_LDO_VFE28_CON1
#define PMIC_DA_VFE28_STB_MASK  0x1
#define PMIC_DA_VFE28_STB_SHIFT 14
#define PMIC_DA_VFE28_EN_ADDR   MT6358_LDO_VFE28_CON1
#define PMIC_DA_VFE28_EN_MASK   0x1
#define PMIC_DA_VFE28_EN_SHIFT  15
#define PMIC_RG_LDO_VFE28_OCFB_EN_ADDR  MT6358_LDO_VFE28_CON2
#define PMIC_RG_LDO_VFE28_OCFB_EN_MASK  0x1
#define PMIC_RG_LDO_VFE28_OCFB_EN_SHIFT 9
#define PMIC_DA_VFE28_OCFB_EN_ADDR MT6358_LDO_VFE28_CON2
#define PMIC_DA_VFE28_OCFB_EN_MASK 0x1
#define PMIC_DA_VFE28_OCFB_EN_SHIFT   10
#define PMIC_RG_LDO_VFE28_DUMMY_LOAD_ADDR   MT6358_LDO_VFE28_CON3
#define PMIC_RG_LDO_VFE28_DUMMY_LOAD_MASK   0x3
#define PMIC_RG_LDO_VFE28_DUMMY_LOAD_SHIFT  5
#define PMIC_DA_VFE28_DUMMY_LOAD_ADDR MT6358_LDO_VFE28_CON3
#define PMIC_DA_VFE28_DUMMY_LOAD_MASK 0x3
#define PMIC_DA_VFE28_DUMMY_LOAD_SHIFT  14
#define PMIC_RG_LDO_VRF18_EN_ADDR MT6358_LDO_VRF18_CON0
#define PMIC_RG_LDO_VRF18_EN_MASK 0x1
#define PMIC_RG_LDO_VRF18_EN_SHIFT 0
#define PMIC_RG_LDO_VRF18_LP_ADDR MT6358_LDO_VRF18_CON0
#define PMIC_RG_LDO_VRF18_LP_MASK 0x1
#define PMIC_RG_LDO_VRF18_LP_SHIFT 1
#define PMIC_RG_LDO_VRF18_SW_OP_EN_ADDR MT6358_LDO_VRF18_OP_EN
#define PMIC_RG_LDO_VRF18_SW_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VRF18_SW_OP_EN_SHIFT   0
#define PMIC_RG_LDO_VRF18_HW0_OP_EN_ADDR   MT6358_LDO_VRF18_OP_EN
#define PMIC_RG_LDO_VRF18_HW0_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VRF18_HW0_OP_EN_SHIFT   1
#define PMIC_RG_LDO_VRF18_HW1_OP_EN_ADDR   MT6358_LDO_VRF18_OP_EN
#define PMIC_RG_LDO_VRF18_HW1_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VRF18_HW1_OP_EN_SHIFT   2
#define PMIC_RG_LDO_VRF18_HW2_OP_EN_ADDR   MT6358_LDO_VRF18_OP_EN
#define PMIC_RG_LDO_VRF18_HW2_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VRF18_HW2_OP_EN_SHIFT   3
#define PMIC_RG_LDO_VRF18_OP_EN_SET_ADDR   MT6358_LDO_VRF18_OP_EN_SET
#define PMIC_RG_LDO_VRF18_OP_EN_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VRF18_OP_EN_SET_SHIFT   0
#define PMIC_RG_LDO_VRF18_OP_EN_CLR_ADDR   MT6358_LDO_VRF18_OP_EN_CLR
#define PMIC_RG_LDO_VRF18_OP_EN_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VRF18_OP_EN_CLR_SHIFT   0
#define PMIC_RG_LDO_VRF18_HW0_OP_CFG_ADDR   MT6358_LDO_VRF18_OP_CFG
#define PMIC_RG_LDO_VRF18_HW0_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VRF18_HW0_OP_CFG_SHIFT  1
#define PMIC_RG_LDO_VRF18_HW1_OP_CFG_ADDR   MT6358_LDO_VRF18_OP_CFG
#define PMIC_RG_LDO_VRF18_HW1_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VRF18_HW1_OP_CFG_SHIFT  2
#define PMIC_RG_LDO_VRF18_HW2_OP_CFG_ADDR   MT6358_LDO_VRF18_OP_CFG
#define PMIC_RG_LDO_VRF18_HW2_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VRF18_HW2_OP_CFG_SHIFT  3
#define PMIC_RG_LDO_VRF18_OP_CFG_SET_ADDR   MT6358_LDO_VRF18_OP_CFG_SET
#define PMIC_RG_LDO_VRF18_OP_CFG_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VRF18_OP_CFG_SET_SHIFT  0
#define PMIC_RG_LDO_VRF18_OP_CFG_CLR_ADDR   MT6358_LDO_VRF18_OP_CFG_CLR
#define PMIC_RG_LDO_VRF18_OP_CFG_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VRF18_OP_CFG_CLR_SHIFT  0
#define PMIC_DA_VRF18_MODE_ADDR MT6358_LDO_VRF18_CON1
#define PMIC_DA_VRF18_MODE_MASK 0x1
#define PMIC_DA_VRF18_MODE_SHIFT  8
#define PMIC_RG_LDO_VRF18_STBTD_ADDR  MT6358_LDO_VRF18_CON1
#define PMIC_RG_LDO_VRF18_STBTD_MASK  0x3
#define PMIC_RG_LDO_VRF18_STBTD_SHIFT 9
#define PMIC_DA_VRF18_STB_ADDR  MT6358_LDO_VRF18_CON1
#define PMIC_DA_VRF18_STB_MASK  0x1
#define PMIC_DA_VRF18_STB_SHIFT 14
#define PMIC_DA_VRF18_EN_ADDR   MT6358_LDO_VRF18_CON1
#define PMIC_DA_VRF18_EN_MASK   0x1
#define PMIC_DA_VRF18_EN_SHIFT  15
#define PMIC_RG_LDO_VRF18_OCFB_EN_ADDR  MT6358_LDO_VRF18_CON2
#define PMIC_RG_LDO_VRF18_OCFB_EN_MASK  0x1
#define PMIC_RG_LDO_VRF18_OCFB_EN_SHIFT 9
#define PMIC_DA_VRF18_OCFB_EN_ADDR MT6358_LDO_VRF18_CON2
#define PMIC_DA_VRF18_OCFB_EN_MASK 0x1
#define PMIC_DA_VRF18_OCFB_EN_SHIFT   10
#define PMIC_RG_LDO_VRF18_DUMMY_LOAD_ADDR   MT6358_LDO_VRF18_CON3
#define PMIC_RG_LDO_VRF18_DUMMY_LOAD_MASK   0x3
#define PMIC_RG_LDO_VRF18_DUMMY_LOAD_SHIFT  5
#define PMIC_DA_VRF18_DUMMY_LOAD_ADDR MT6358_LDO_VRF18_CON3
#define PMIC_DA_VRF18_DUMMY_LOAD_MASK 0x3
#define PMIC_DA_VRF18_DUMMY_LOAD_SHIFT  14
#define PMIC_RG_LDO_VRF12_EN_ADDR MT6358_LDO_VRF12_CON0
#define PMIC_RG_LDO_VRF12_EN_MASK 0x1
#define PMIC_RG_LDO_VRF12_EN_SHIFT 0
#define PMIC_RG_LDO_VRF12_LP_ADDR MT6358_LDO_VRF12_CON0
#define PMIC_RG_LDO_VRF12_LP_MASK 0x1
#define PMIC_RG_LDO_VRF12_LP_SHIFT 1
#define PMIC_RG_LDO_VRF12_SW_OP_EN_ADDR MT6358_LDO_VRF12_OP_EN
#define PMIC_RG_LDO_VRF12_SW_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VRF12_SW_OP_EN_SHIFT   0
#define PMIC_RG_LDO_VRF12_HW0_OP_EN_ADDR   MT6358_LDO_VRF12_OP_EN
#define PMIC_RG_LDO_VRF12_HW0_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VRF12_HW0_OP_EN_SHIFT   1
#define PMIC_RG_LDO_VRF12_HW1_OP_EN_ADDR   MT6358_LDO_VRF12_OP_EN
#define PMIC_RG_LDO_VRF12_HW1_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VRF12_HW1_OP_EN_SHIFT   2
#define PMIC_RG_LDO_VRF12_HW2_OP_EN_ADDR   MT6358_LDO_VRF12_OP_EN
#define PMIC_RG_LDO_VRF12_HW2_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VRF12_HW2_OP_EN_SHIFT   3
#define PMIC_RG_LDO_VRF12_OP_EN_SET_ADDR   MT6358_LDO_VRF12_OP_EN_SET
#define PMIC_RG_LDO_VRF12_OP_EN_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VRF12_OP_EN_SET_SHIFT   0
#define PMIC_RG_LDO_VRF12_OP_EN_CLR_ADDR   MT6358_LDO_VRF12_OP_EN_CLR
#define PMIC_RG_LDO_VRF12_OP_EN_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VRF12_OP_EN_CLR_SHIFT   0
#define PMIC_RG_LDO_VRF12_HW0_OP_CFG_ADDR   MT6358_LDO_VRF12_OP_CFG
#define PMIC_RG_LDO_VRF12_HW0_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VRF12_HW0_OP_CFG_SHIFT  1
#define PMIC_RG_LDO_VRF12_HW1_OP_CFG_ADDR   MT6358_LDO_VRF12_OP_CFG
#define PMIC_RG_LDO_VRF12_HW1_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VRF12_HW1_OP_CFG_SHIFT  2
#define PMIC_RG_LDO_VRF12_HW2_OP_CFG_ADDR   MT6358_LDO_VRF12_OP_CFG
#define PMIC_RG_LDO_VRF12_HW2_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VRF12_HW2_OP_CFG_SHIFT  3
#define PMIC_RG_LDO_VRF12_OP_CFG_SET_ADDR   MT6358_LDO_VRF12_OP_CFG_SET
#define PMIC_RG_LDO_VRF12_OP_CFG_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VRF12_OP_CFG_SET_SHIFT  0
#define PMIC_RG_LDO_VRF12_OP_CFG_CLR_ADDR   MT6358_LDO_VRF12_OP_CFG_CLR
#define PMIC_RG_LDO_VRF12_OP_CFG_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VRF12_OP_CFG_CLR_SHIFT  0
#define PMIC_DA_VRF12_MODE_ADDR MT6358_LDO_VRF12_CON1
#define PMIC_DA_VRF12_MODE_MASK 0x1
#define PMIC_DA_VRF12_MODE_SHIFT  8
#define PMIC_RG_LDO_VRF12_STBTD_ADDR  MT6358_LDO_VRF12_CON1
#define PMIC_RG_LDO_VRF12_STBTD_MASK  0x3
#define PMIC_RG_LDO_VRF12_STBTD_SHIFT 9
#define PMIC_DA_VRF12_STB_ADDR  MT6358_LDO_VRF12_CON1
#define PMIC_DA_VRF12_STB_MASK  0x1
#define PMIC_DA_VRF12_STB_SHIFT 14
#define PMIC_DA_VRF12_EN_ADDR   MT6358_LDO_VRF12_CON1
#define PMIC_DA_VRF12_EN_MASK   0x1
#define PMIC_DA_VRF12_EN_SHIFT  15
#define PMIC_RG_LDO_VRF12_OCFB_EN_ADDR  MT6358_LDO_VRF12_CON2
#define PMIC_RG_LDO_VRF12_OCFB_EN_MASK  0x1
#define PMIC_RG_LDO_VRF12_OCFB_EN_SHIFT 9
#define PMIC_DA_VRF12_OCFB_EN_ADDR MT6358_LDO_VRF12_CON2
#define PMIC_DA_VRF12_OCFB_EN_MASK 0x1
#define PMIC_DA_VRF12_OCFB_EN_SHIFT   10
#define PMIC_RG_LDO_VRF12_DUMMY_LOAD_ADDR   MT6358_LDO_VRF12_CON3
#define PMIC_RG_LDO_VRF12_DUMMY_LOAD_MASK   0x3
#define PMIC_RG_LDO_VRF12_DUMMY_LOAD_SHIFT  5
#define PMIC_DA_VRF12_DUMMY_LOAD_ADDR MT6358_LDO_VRF12_CON3
#define PMIC_DA_VRF12_DUMMY_LOAD_MASK 0x3
#define PMIC_DA_VRF12_DUMMY_LOAD_SHIFT  14
#define PMIC_RG_LDO_VEFUSE_EN_ADDR MT6358_LDO_VEFUSE_CON0
#define PMIC_RG_LDO_VEFUSE_EN_MASK 0x1
#define PMIC_RG_LDO_VEFUSE_EN_SHIFT   0
#define PMIC_RG_LDO_VEFUSE_LP_ADDR MT6358_LDO_VEFUSE_CON0
#define PMIC_RG_LDO_VEFUSE_LP_MASK 0x1
#define PMIC_RG_LDO_VEFUSE_LP_SHIFT   1
#define PMIC_RG_LDO_VEFUSE_SW_OP_EN_ADDR   MT6358_LDO_VEFUSE_OP_EN
#define PMIC_RG_LDO_VEFUSE_SW_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VEFUSE_SW_OP_EN_SHIFT   0
#define PMIC_RG_LDO_VEFUSE_HW0_OP_EN_ADDR   MT6358_LDO_VEFUSE_OP_EN
#define PMIC_RG_LDO_VEFUSE_HW0_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VEFUSE_HW0_OP_EN_SHIFT  1
#define PMIC_RG_LDO_VEFUSE_HW1_OP_EN_ADDR   MT6358_LDO_VEFUSE_OP_EN
#define PMIC_RG_LDO_VEFUSE_HW1_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VEFUSE_HW1_OP_EN_SHIFT  2
#define PMIC_RG_LDO_VEFUSE_HW2_OP_EN_ADDR   MT6358_LDO_VEFUSE_OP_EN
#define PMIC_RG_LDO_VEFUSE_HW2_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VEFUSE_HW2_OP_EN_SHIFT  3
#define PMIC_RG_LDO_VEFUSE_OP_EN_SET_ADDR   MT6358_LDO_VEFUSE_OP_EN_SET
#define PMIC_RG_LDO_VEFUSE_OP_EN_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VEFUSE_OP_EN_SET_SHIFT  0
#define PMIC_RG_LDO_VEFUSE_OP_EN_CLR_ADDR   MT6358_LDO_VEFUSE_OP_EN_CLR
#define PMIC_RG_LDO_VEFUSE_OP_EN_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VEFUSE_OP_EN_CLR_SHIFT  0
#define PMIC_RG_LDO_VEFUSE_HW0_OP_CFG_ADDR  MT6358_LDO_VEFUSE_OP_CFG
#define PMIC_RG_LDO_VEFUSE_HW0_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VEFUSE_HW0_OP_CFG_SHIFT 1
#define PMIC_RG_LDO_VEFUSE_HW1_OP_CFG_ADDR  MT6358_LDO_VEFUSE_OP_CFG
#define PMIC_RG_LDO_VEFUSE_HW1_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VEFUSE_HW1_OP_CFG_SHIFT 2
#define PMIC_RG_LDO_VEFUSE_HW2_OP_CFG_ADDR  MT6358_LDO_VEFUSE_OP_CFG
#define PMIC_RG_LDO_VEFUSE_HW2_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VEFUSE_HW2_OP_CFG_SHIFT 3
#define PMIC_RG_LDO_VEFUSE_OP_CFG_SET_ADDR  MT6358_LDO_VEFUSE_OP_CFG_SET
#define PMIC_RG_LDO_VEFUSE_OP_CFG_SET_MASK  0xFFFF
#define PMIC_RG_LDO_VEFUSE_OP_CFG_SET_SHIFT 0
#define PMIC_RG_LDO_VEFUSE_OP_CFG_CLR_ADDR  MT6358_LDO_VEFUSE_OP_CFG_CLR
#define PMIC_RG_LDO_VEFUSE_OP_CFG_CLR_MASK  0xFFFF
#define PMIC_RG_LDO_VEFUSE_OP_CFG_CLR_SHIFT 0
#define PMIC_DA_VEFUSE_MODE_ADDR  MT6358_LDO_VEFUSE_CON1
#define PMIC_DA_VEFUSE_MODE_MASK  0x1
#define PMIC_DA_VEFUSE_MODE_SHIFT 8
#define PMIC_RG_LDO_VEFUSE_STBTD_ADDR MT6358_LDO_VEFUSE_CON1
#define PMIC_RG_LDO_VEFUSE_STBTD_MASK 0x3
#define PMIC_RG_LDO_VEFUSE_STBTD_SHIFT  9
#define PMIC_DA_VEFUSE_STB_ADDR MT6358_LDO_VEFUSE_CON1
#define PMIC_DA_VEFUSE_STB_MASK 0x1
#define PMIC_DA_VEFUSE_STB_SHIFT  14
#define PMIC_DA_VEFUSE_EN_ADDR  MT6358_LDO_VEFUSE_CON1
#define PMIC_DA_VEFUSE_EN_MASK  0x1
#define PMIC_DA_VEFUSE_EN_SHIFT 15
#define PMIC_RG_LDO_VEFUSE_OCFB_EN_ADDR MT6358_LDO_VEFUSE_CON2
#define PMIC_RG_LDO_VEFUSE_OCFB_EN_MASK 0x1
#define PMIC_RG_LDO_VEFUSE_OCFB_EN_SHIFT   9
#define PMIC_DA_VEFUSE_OCFB_EN_ADDR   MT6358_LDO_VEFUSE_CON2
#define PMIC_DA_VEFUSE_OCFB_EN_MASK   0x1
#define PMIC_DA_VEFUSE_OCFB_EN_SHIFT  10
#define PMIC_RG_LDO_VEFUSE_DUMMY_LOAD_ADDR  MT6358_LDO_VEFUSE_CON3
#define PMIC_RG_LDO_VEFUSE_DUMMY_LOAD_MASK  0x3
#define PMIC_RG_LDO_VEFUSE_DUMMY_LOAD_SHIFT 5
#define PMIC_DA_VEFUSE_DUMMY_LOAD_ADDR  MT6358_LDO_VEFUSE_CON3
#define PMIC_DA_VEFUSE_DUMMY_LOAD_MASK  0x3
#define PMIC_DA_VEFUSE_DUMMY_LOAD_SHIFT 14
#define PMIC_RG_LDO_VCN18_EN_ADDR MT6358_LDO_VCN18_CON0
#define PMIC_RG_LDO_VCN18_EN_MASK 0x1
#define PMIC_RG_LDO_VCN18_EN_SHIFT 0
#define PMIC_RG_LDO_VCN18_LP_ADDR MT6358_LDO_VCN18_CON0
#define PMIC_RG_LDO_VCN18_LP_MASK 0x1
#define PMIC_RG_LDO_VCN18_LP_SHIFT 1
#define PMIC_RG_LDO_VCN18_SW_OP_EN_ADDR MT6358_LDO_VCN18_OP_EN
#define PMIC_RG_LDO_VCN18_SW_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VCN18_SW_OP_EN_SHIFT   0
#define PMIC_RG_LDO_VCN18_HW0_OP_EN_ADDR   MT6358_LDO_VCN18_OP_EN
#define PMIC_RG_LDO_VCN18_HW0_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VCN18_HW0_OP_EN_SHIFT   1
#define PMIC_RG_LDO_VCN18_HW1_OP_EN_ADDR   MT6358_LDO_VCN18_OP_EN
#define PMIC_RG_LDO_VCN18_HW1_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VCN18_HW1_OP_EN_SHIFT   2
#define PMIC_RG_LDO_VCN18_HW2_OP_EN_ADDR   MT6358_LDO_VCN18_OP_EN
#define PMIC_RG_LDO_VCN18_HW2_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VCN18_HW2_OP_EN_SHIFT   3
#define PMIC_RG_LDO_VCN18_OP_EN_SET_ADDR   MT6358_LDO_VCN18_OP_EN_SET
#define PMIC_RG_LDO_VCN18_OP_EN_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VCN18_OP_EN_SET_SHIFT   0
#define PMIC_RG_LDO_VCN18_OP_EN_CLR_ADDR   MT6358_LDO_VCN18_OP_EN_CLR
#define PMIC_RG_LDO_VCN18_OP_EN_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VCN18_OP_EN_CLR_SHIFT   0
#define PMIC_RG_LDO_VCN18_HW0_OP_CFG_ADDR   MT6358_LDO_VCN18_OP_CFG
#define PMIC_RG_LDO_VCN18_HW0_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VCN18_HW0_OP_CFG_SHIFT  1
#define PMIC_RG_LDO_VCN18_HW1_OP_CFG_ADDR   MT6358_LDO_VCN18_OP_CFG
#define PMIC_RG_LDO_VCN18_HW1_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VCN18_HW1_OP_CFG_SHIFT  2
#define PMIC_RG_LDO_VCN18_HW2_OP_CFG_ADDR   MT6358_LDO_VCN18_OP_CFG
#define PMIC_RG_LDO_VCN18_HW2_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VCN18_HW2_OP_CFG_SHIFT  3
#define PMIC_RG_LDO_VCN18_OP_CFG_SET_ADDR   MT6358_LDO_VCN18_OP_CFG_SET
#define PMIC_RG_LDO_VCN18_OP_CFG_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VCN18_OP_CFG_SET_SHIFT  0
#define PMIC_RG_LDO_VCN18_OP_CFG_CLR_ADDR   MT6358_LDO_VCN18_OP_CFG_CLR
#define PMIC_RG_LDO_VCN18_OP_CFG_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VCN18_OP_CFG_CLR_SHIFT  0
#define PMIC_DA_VCN18_MODE_ADDR MT6358_LDO_VCN18_CON1
#define PMIC_DA_VCN18_MODE_MASK 0x1
#define PMIC_DA_VCN18_MODE_SHIFT  8
#define PMIC_RG_LDO_VCN18_STBTD_ADDR  MT6358_LDO_VCN18_CON1
#define PMIC_RG_LDO_VCN18_STBTD_MASK  0x3
#define PMIC_RG_LDO_VCN18_STBTD_SHIFT 9
#define PMIC_DA_VCN18_STB_ADDR  MT6358_LDO_VCN18_CON1
#define PMIC_DA_VCN18_STB_MASK  0x1
#define PMIC_DA_VCN18_STB_SHIFT 14
#define PMIC_DA_VCN18_EN_ADDR   MT6358_LDO_VCN18_CON1
#define PMIC_DA_VCN18_EN_MASK   0x1
#define PMIC_DA_VCN18_EN_SHIFT  15
#define PMIC_RG_LDO_VCN18_OCFB_EN_ADDR  MT6358_LDO_VCN18_CON2
#define PMIC_RG_LDO_VCN18_OCFB_EN_MASK  0x1
#define PMIC_RG_LDO_VCN18_OCFB_EN_SHIFT 9
#define PMIC_DA_VCN18_OCFB_EN_ADDR MT6358_LDO_VCN18_CON2
#define PMIC_DA_VCN18_OCFB_EN_MASK 0x1
#define PMIC_DA_VCN18_OCFB_EN_SHIFT   10
#define PMIC_RG_LDO_VCN18_DUMMY_LOAD_ADDR   MT6358_LDO_VCN18_CON3
#define PMIC_RG_LDO_VCN18_DUMMY_LOAD_MASK   0x3
#define PMIC_RG_LDO_VCN18_DUMMY_LOAD_SHIFT  5
#define PMIC_DA_VCN18_DUMMY_LOAD_ADDR MT6358_LDO_VCN18_CON3
#define PMIC_DA_VCN18_DUMMY_LOAD_MASK 0x3
#define PMIC_DA_VCN18_DUMMY_LOAD_SHIFT  14
#define PMIC_RG_LDO_VCAMA1_EN_ADDR MT6358_LDO_VCAMA1_CON0
#define PMIC_RG_LDO_VCAMA1_EN_MASK 0x1
#define PMIC_RG_LDO_VCAMA1_EN_SHIFT   0
#define PMIC_RG_LDO_VCAMA1_LP_ADDR MT6358_LDO_VCAMA1_CON0
#define PMIC_RG_LDO_VCAMA1_LP_MASK 0x1
#define PMIC_RG_LDO_VCAMA1_LP_SHIFT   1
#define PMIC_RG_LDO_VCAMA1_SW_OP_EN_ADDR   MT6358_LDO_VCAMA1_OP_EN
#define PMIC_RG_LDO_VCAMA1_SW_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VCAMA1_SW_OP_EN_SHIFT   0
#define PMIC_RG_LDO_VCAMA1_HW0_OP_EN_ADDR   MT6358_LDO_VCAMA1_OP_EN
#define PMIC_RG_LDO_VCAMA1_HW0_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VCAMA1_HW0_OP_EN_SHIFT  1
#define PMIC_RG_LDO_VCAMA1_HW1_OP_EN_ADDR   MT6358_LDO_VCAMA1_OP_EN
#define PMIC_RG_LDO_VCAMA1_HW1_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VCAMA1_HW1_OP_EN_SHIFT  2
#define PMIC_RG_LDO_VCAMA1_HW2_OP_EN_ADDR   MT6358_LDO_VCAMA1_OP_EN
#define PMIC_RG_LDO_VCAMA1_HW2_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VCAMA1_HW2_OP_EN_SHIFT  3
#define PMIC_RG_LDO_VCAMA1_OP_EN_SET_ADDR   MT6358_LDO_VCAMA1_OP_EN_SET
#define PMIC_RG_LDO_VCAMA1_OP_EN_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VCAMA1_OP_EN_SET_SHIFT  0
#define PMIC_RG_LDO_VCAMA1_OP_EN_CLR_ADDR   MT6358_LDO_VCAMA1_OP_EN_CLR
#define PMIC_RG_LDO_VCAMA1_OP_EN_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VCAMA1_OP_EN_CLR_SHIFT  0
#define PMIC_RG_LDO_VCAMA1_HW0_OP_CFG_ADDR  MT6358_LDO_VCAMA1_OP_CFG
#define PMIC_RG_LDO_VCAMA1_HW0_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VCAMA1_HW0_OP_CFG_SHIFT 1
#define PMIC_RG_LDO_VCAMA1_HW1_OP_CFG_ADDR  MT6358_LDO_VCAMA1_OP_CFG
#define PMIC_RG_LDO_VCAMA1_HW1_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VCAMA1_HW1_OP_CFG_SHIFT 2
#define PMIC_RG_LDO_VCAMA1_HW2_OP_CFG_ADDR  MT6358_LDO_VCAMA1_OP_CFG
#define PMIC_RG_LDO_VCAMA1_HW2_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VCAMA1_HW2_OP_CFG_SHIFT 3
#define PMIC_RG_LDO_VCAMA1_OP_CFG_SET_ADDR  MT6358_LDO_VCAMA1_OP_CFG_SET
#define PMIC_RG_LDO_VCAMA1_OP_CFG_SET_MASK  0xFFFF
#define PMIC_RG_LDO_VCAMA1_OP_CFG_SET_SHIFT 0
#define PMIC_RG_LDO_VCAMA1_OP_CFG_CLR_ADDR  MT6358_LDO_VCAMA1_OP_CFG_CLR
#define PMIC_RG_LDO_VCAMA1_OP_CFG_CLR_MASK  0xFFFF
#define PMIC_RG_LDO_VCAMA1_OP_CFG_CLR_SHIFT 0
#define PMIC_DA_VCAMA1_MODE_ADDR  MT6358_LDO_VCAMA1_CON1
#define PMIC_DA_VCAMA1_MODE_MASK  0x1
#define PMIC_DA_VCAMA1_MODE_SHIFT 8
#define PMIC_RG_LDO_VCAMA1_STBTD_ADDR MT6358_LDO_VCAMA1_CON1
#define PMIC_RG_LDO_VCAMA1_STBTD_MASK 0x3
#define PMIC_RG_LDO_VCAMA1_STBTD_SHIFT  9
#define PMIC_DA_VCAMA1_STB_ADDR MT6358_LDO_VCAMA1_CON1
#define PMIC_DA_VCAMA1_STB_MASK 0x1
#define PMIC_DA_VCAMA1_STB_SHIFT  14
#define PMIC_DA_VCAMA1_EN_ADDR  MT6358_LDO_VCAMA1_CON1
#define PMIC_DA_VCAMA1_EN_MASK  0x1
#define PMIC_DA_VCAMA1_EN_SHIFT 15
#define PMIC_RG_LDO_VCAMA1_OCFB_EN_ADDR MT6358_LDO_VCAMA1_CON2
#define PMIC_RG_LDO_VCAMA1_OCFB_EN_MASK 0x1
#define PMIC_RG_LDO_VCAMA1_OCFB_EN_SHIFT   9
#define PMIC_DA_VCAMA1_OCFB_EN_ADDR   MT6358_LDO_VCAMA1_CON2
#define PMIC_DA_VCAMA1_OCFB_EN_MASK   0x1
#define PMIC_DA_VCAMA1_OCFB_EN_SHIFT  10
#define PMIC_RG_LDO_VCAMA1_DUMMY_LOAD_ADDR  MT6358_LDO_VCAMA1_CON3
#define PMIC_RG_LDO_VCAMA1_DUMMY_LOAD_MASK  0x3
#define PMIC_RG_LDO_VCAMA1_DUMMY_LOAD_SHIFT 5
#define PMIC_DA_VCAMA1_DUMMY_LOAD_ADDR  MT6358_LDO_VCAMA1_CON3
#define PMIC_DA_VCAMA1_DUMMY_LOAD_MASK  0x3
#define PMIC_DA_VCAMA1_DUMMY_LOAD_SHIFT 14
#define PMIC_LDO_GOFF1_ANA_ID_ADDR MT6358_LDO_GOFF1_DSN_ID
#define PMIC_LDO_GOFF1_ANA_ID_MASK 0xFF
#define PMIC_LDO_GOFF1_ANA_ID_SHIFT   0
#define PMIC_LDO_GOFF1_DIG_ID_ADDR MT6358_LDO_GOFF1_DSN_ID
#define PMIC_LDO_GOFF1_DIG_ID_MASK 0xFF
#define PMIC_LDO_GOFF1_DIG_ID_SHIFT   8
#define PMIC_LDO_GOFF1_ANA_MINOR_REV_ADDR   MT6358_LDO_GOFF1_DSN_REV0
#define PMIC_LDO_GOFF1_ANA_MINOR_REV_MASK   0xF
#define PMIC_LDO_GOFF1_ANA_MINOR_REV_SHIFT  0
#define PMIC_LDO_GOFF1_ANA_MAJOR_REV_ADDR   MT6358_LDO_GOFF1_DSN_REV0
#define PMIC_LDO_GOFF1_ANA_MAJOR_REV_MASK   0xF
#define PMIC_LDO_GOFF1_ANA_MAJOR_REV_SHIFT  4
#define PMIC_LDO_GOFF1_DIG_MINOR_REV_ADDR   MT6358_LDO_GOFF1_DSN_REV0
#define PMIC_LDO_GOFF1_DIG_MINOR_REV_MASK   0xF
#define PMIC_LDO_GOFF1_DIG_MINOR_REV_SHIFT  8
#define PMIC_LDO_GOFF1_DIG_MAJOR_REV_ADDR   MT6358_LDO_GOFF1_DSN_REV0
#define PMIC_LDO_GOFF1_DIG_MAJOR_REV_MASK   0xF
#define PMIC_LDO_GOFF1_DIG_MAJOR_REV_SHIFT  12
#define PMIC_LDO_GOFF1_DSN_CBS_ADDR   MT6358_LDO_GOFF1_DSN_DBI
#define PMIC_LDO_GOFF1_DSN_CBS_MASK   0x3
#define PMIC_LDO_GOFF1_DSN_CBS_SHIFT  0
#define PMIC_LDO_GOFF1_DSN_BIX_ADDR   MT6358_LDO_GOFF1_DSN_DBI
#define PMIC_LDO_GOFF1_DSN_BIX_MASK   0x3
#define PMIC_LDO_GOFF1_DSN_BIX_SHIFT  2
#define PMIC_LDO_GOFF1_DSN_ESP_ADDR   MT6358_LDO_GOFF1_DSN_DBI
#define PMIC_LDO_GOFF1_DSN_ESP_MASK   0xFF
#define PMIC_LDO_GOFF1_DSN_ESP_SHIFT  8
#define PMIC_LDO_GOFF1_DSN_FPI_ADDR   MT6358_LDO_GOFF1_DSN_DXI
#define PMIC_LDO_GOFF1_DSN_FPI_MASK   0xFF
#define PMIC_LDO_GOFF1_DSN_FPI_SHIFT  0
#define PMIC_RG_LDO_VCAMA2_EN_ADDR MT6358_LDO_VCAMA2_CON0
#define PMIC_RG_LDO_VCAMA2_EN_MASK 0x1
#define PMIC_RG_LDO_VCAMA2_EN_SHIFT   0
#define PMIC_RG_LDO_VCAMA2_LP_ADDR MT6358_LDO_VCAMA2_CON0
#define PMIC_RG_LDO_VCAMA2_LP_MASK 0x1
#define PMIC_RG_LDO_VCAMA2_LP_SHIFT   1
#define PMIC_RG_LDO_VCAMA2_SW_OP_EN_ADDR   MT6358_LDO_VCAMA2_OP_EN
#define PMIC_RG_LDO_VCAMA2_SW_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VCAMA2_SW_OP_EN_SHIFT   0
#define PMIC_RG_LDO_VCAMA2_HW0_OP_EN_ADDR   MT6358_LDO_VCAMA2_OP_EN
#define PMIC_RG_LDO_VCAMA2_HW0_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VCAMA2_HW0_OP_EN_SHIFT  1
#define PMIC_RG_LDO_VCAMA2_HW1_OP_EN_ADDR   MT6358_LDO_VCAMA2_OP_EN
#define PMIC_RG_LDO_VCAMA2_HW1_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VCAMA2_HW1_OP_EN_SHIFT  2
#define PMIC_RG_LDO_VCAMA2_HW2_OP_EN_ADDR   MT6358_LDO_VCAMA2_OP_EN
#define PMIC_RG_LDO_VCAMA2_HW2_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VCAMA2_HW2_OP_EN_SHIFT  3
#define PMIC_RG_LDO_VCAMA2_OP_EN_SET_ADDR   MT6358_LDO_VCAMA2_OP_EN_SET
#define PMIC_RG_LDO_VCAMA2_OP_EN_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VCAMA2_OP_EN_SET_SHIFT  0
#define PMIC_RG_LDO_VCAMA2_OP_EN_CLR_ADDR   MT6358_LDO_VCAMA2_OP_EN_CLR
#define PMIC_RG_LDO_VCAMA2_OP_EN_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VCAMA2_OP_EN_CLR_SHIFT  0
#define PMIC_RG_LDO_VCAMA2_HW0_OP_CFG_ADDR  MT6358_LDO_VCAMA2_OP_CFG
#define PMIC_RG_LDO_VCAMA2_HW0_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VCAMA2_HW0_OP_CFG_SHIFT 1
#define PMIC_RG_LDO_VCAMA2_HW1_OP_CFG_ADDR  MT6358_LDO_VCAMA2_OP_CFG
#define PMIC_RG_LDO_VCAMA2_HW1_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VCAMA2_HW1_OP_CFG_SHIFT 2
#define PMIC_RG_LDO_VCAMA2_HW2_OP_CFG_ADDR  MT6358_LDO_VCAMA2_OP_CFG
#define PMIC_RG_LDO_VCAMA2_HW2_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VCAMA2_HW2_OP_CFG_SHIFT 3
#define PMIC_RG_LDO_VCAMA2_OP_CFG_SET_ADDR  MT6358_LDO_VCAMA2_OP_CFG_SET
#define PMIC_RG_LDO_VCAMA2_OP_CFG_SET_MASK  0xFFFF
#define PMIC_RG_LDO_VCAMA2_OP_CFG_SET_SHIFT 0
#define PMIC_RG_LDO_VCAMA2_OP_CFG_CLR_ADDR  MT6358_LDO_VCAMA2_OP_CFG_CLR
#define PMIC_RG_LDO_VCAMA2_OP_CFG_CLR_MASK  0xFFFF
#define PMIC_RG_LDO_VCAMA2_OP_CFG_CLR_SHIFT 0
#define PMIC_DA_VCAMA2_MODE_ADDR  MT6358_LDO_VCAMA2_CON1
#define PMIC_DA_VCAMA2_MODE_MASK  0x1
#define PMIC_DA_VCAMA2_MODE_SHIFT 8
#define PMIC_RG_LDO_VCAMA2_STBTD_ADDR MT6358_LDO_VCAMA2_CON1
#define PMIC_RG_LDO_VCAMA2_STBTD_MASK 0x3
#define PMIC_RG_LDO_VCAMA2_STBTD_SHIFT  9
#define PMIC_DA_VCAMA2_STB_ADDR MT6358_LDO_VCAMA2_CON1
#define PMIC_DA_VCAMA2_STB_MASK 0x1
#define PMIC_DA_VCAMA2_STB_SHIFT  14
#define PMIC_DA_VCAMA2_EN_ADDR  MT6358_LDO_VCAMA2_CON1
#define PMIC_DA_VCAMA2_EN_MASK  0x1
#define PMIC_DA_VCAMA2_EN_SHIFT 15
#define PMIC_RG_LDO_VCAMA2_OCFB_EN_ADDR MT6358_LDO_VCAMA2_CON2
#define PMIC_RG_LDO_VCAMA2_OCFB_EN_MASK 0x1
#define PMIC_RG_LDO_VCAMA2_OCFB_EN_SHIFT   9
#define PMIC_DA_VCAMA2_OCFB_EN_ADDR   MT6358_LDO_VCAMA2_CON2
#define PMIC_DA_VCAMA2_OCFB_EN_MASK   0x1
#define PMIC_DA_VCAMA2_OCFB_EN_SHIFT  10
#define PMIC_RG_LDO_VCAMA2_DUMMY_LOAD_ADDR  MT6358_LDO_VCAMA2_CON3
#define PMIC_RG_LDO_VCAMA2_DUMMY_LOAD_MASK  0x3
#define PMIC_RG_LDO_VCAMA2_DUMMY_LOAD_SHIFT 5
#define PMIC_DA_VCAMA2_DUMMY_LOAD_ADDR  MT6358_LDO_VCAMA2_CON3
#define PMIC_DA_VCAMA2_DUMMY_LOAD_MASK  0x3
#define PMIC_DA_VCAMA2_DUMMY_LOAD_SHIFT 14
#define PMIC_RG_LDO_VCAMD_EN_ADDR MT6358_LDO_VCAMD_CON0
#define PMIC_RG_LDO_VCAMD_EN_MASK 0x1
#define PMIC_RG_LDO_VCAMD_EN_SHIFT 0
#define PMIC_RG_LDO_VCAMD_LP_ADDR MT6358_LDO_VCAMD_CON0
#define PMIC_RG_LDO_VCAMD_LP_MASK 0x1
#define PMIC_RG_LDO_VCAMD_LP_SHIFT 1
#define PMIC_RG_LDO_VCAMD_SW_OP_EN_ADDR MT6358_LDO_VCAMD_OP_EN
#define PMIC_RG_LDO_VCAMD_SW_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VCAMD_SW_OP_EN_SHIFT   0
#define PMIC_RG_LDO_VCAMD_HW0_OP_EN_ADDR   MT6358_LDO_VCAMD_OP_EN
#define PMIC_RG_LDO_VCAMD_HW0_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VCAMD_HW0_OP_EN_SHIFT   1
#define PMIC_RG_LDO_VCAMD_HW1_OP_EN_ADDR   MT6358_LDO_VCAMD_OP_EN
#define PMIC_RG_LDO_VCAMD_HW1_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VCAMD_HW1_OP_EN_SHIFT   2
#define PMIC_RG_LDO_VCAMD_HW2_OP_EN_ADDR   MT6358_LDO_VCAMD_OP_EN
#define PMIC_RG_LDO_VCAMD_HW2_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VCAMD_HW2_OP_EN_SHIFT   3
#define PMIC_RG_LDO_VCAMD_OP_EN_SET_ADDR   MT6358_LDO_VCAMD_OP_EN_SET
#define PMIC_RG_LDO_VCAMD_OP_EN_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VCAMD_OP_EN_SET_SHIFT   0
#define PMIC_RG_LDO_VCAMD_OP_EN_CLR_ADDR   MT6358_LDO_VCAMD_OP_EN_CLR
#define PMIC_RG_LDO_VCAMD_OP_EN_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VCAMD_OP_EN_CLR_SHIFT   0
#define PMIC_RG_LDO_VCAMD_HW0_OP_CFG_ADDR   MT6358_LDO_VCAMD_OP_CFG
#define PMIC_RG_LDO_VCAMD_HW0_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VCAMD_HW0_OP_CFG_SHIFT  1
#define PMIC_RG_LDO_VCAMD_HW1_OP_CFG_ADDR   MT6358_LDO_VCAMD_OP_CFG
#define PMIC_RG_LDO_VCAMD_HW1_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VCAMD_HW1_OP_CFG_SHIFT  2
#define PMIC_RG_LDO_VCAMD_HW2_OP_CFG_ADDR   MT6358_LDO_VCAMD_OP_CFG
#define PMIC_RG_LDO_VCAMD_HW2_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VCAMD_HW2_OP_CFG_SHIFT  3
#define PMIC_RG_LDO_VCAMD_OP_CFG_SET_ADDR   MT6358_LDO_VCAMD_OP_CFG_SET
#define PMIC_RG_LDO_VCAMD_OP_CFG_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VCAMD_OP_CFG_SET_SHIFT  0
#define PMIC_RG_LDO_VCAMD_OP_CFG_CLR_ADDR   MT6358_LDO_VCAMD_OP_CFG_CLR
#define PMIC_RG_LDO_VCAMD_OP_CFG_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VCAMD_OP_CFG_CLR_SHIFT  0
#define PMIC_DA_VCAMD_MODE_ADDR MT6358_LDO_VCAMD_CON1
#define PMIC_DA_VCAMD_MODE_MASK 0x1
#define PMIC_DA_VCAMD_MODE_SHIFT  8
#define PMIC_RG_LDO_VCAMD_STBTD_ADDR  MT6358_LDO_VCAMD_CON1
#define PMIC_RG_LDO_VCAMD_STBTD_MASK  0x3
#define PMIC_RG_LDO_VCAMD_STBTD_SHIFT 9
#define PMIC_DA_VCAMD_STB_ADDR  MT6358_LDO_VCAMD_CON1
#define PMIC_DA_VCAMD_STB_MASK  0x1
#define PMIC_DA_VCAMD_STB_SHIFT 14
#define PMIC_DA_VCAMD_EN_ADDR   MT6358_LDO_VCAMD_CON1
#define PMIC_DA_VCAMD_EN_MASK   0x1
#define PMIC_DA_VCAMD_EN_SHIFT  15
#define PMIC_RG_LDO_VCAMD_OCFB_EN_ADDR  MT6358_LDO_VCAMD_CON2
#define PMIC_RG_LDO_VCAMD_OCFB_EN_MASK  0x1
#define PMIC_RG_LDO_VCAMD_OCFB_EN_SHIFT 9
#define PMIC_DA_VCAMD_OCFB_EN_ADDR MT6358_LDO_VCAMD_CON2
#define PMIC_DA_VCAMD_OCFB_EN_MASK 0x1
#define PMIC_DA_VCAMD_OCFB_EN_SHIFT   10
#define PMIC_RG_LDO_VCAMD_DUMMY_LOAD_ADDR   MT6358_LDO_VCAMD_CON3
#define PMIC_RG_LDO_VCAMD_DUMMY_LOAD_MASK   0x3
#define PMIC_RG_LDO_VCAMD_DUMMY_LOAD_SHIFT  5
#define PMIC_DA_VCAMD_DUMMY_LOAD_ADDR MT6358_LDO_VCAMD_CON3
#define PMIC_DA_VCAMD_DUMMY_LOAD_MASK 0x3
#define PMIC_DA_VCAMD_DUMMY_LOAD_SHIFT  14
#define PMIC_RG_LDO_VCAMIO_EN_ADDR MT6358_LDO_VCAMIO_CON0
#define PMIC_RG_LDO_VCAMIO_EN_MASK 0x1
#define PMIC_RG_LDO_VCAMIO_EN_SHIFT   0
#define PMIC_RG_LDO_VCAMIO_LP_ADDR MT6358_LDO_VCAMIO_CON0
#define PMIC_RG_LDO_VCAMIO_LP_MASK 0x1
#define PMIC_RG_LDO_VCAMIO_LP_SHIFT   1
#define PMIC_RG_LDO_VCAMIO_SW_OP_EN_ADDR   MT6358_LDO_VCAMIO_OP_EN
#define PMIC_RG_LDO_VCAMIO_SW_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VCAMIO_SW_OP_EN_SHIFT   0
#define PMIC_RG_LDO_VCAMIO_HW0_OP_EN_ADDR   MT6358_LDO_VCAMIO_OP_EN
#define PMIC_RG_LDO_VCAMIO_HW0_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VCAMIO_HW0_OP_EN_SHIFT  1
#define PMIC_RG_LDO_VCAMIO_HW1_OP_EN_ADDR   MT6358_LDO_VCAMIO_OP_EN
#define PMIC_RG_LDO_VCAMIO_HW1_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VCAMIO_HW1_OP_EN_SHIFT  2
#define PMIC_RG_LDO_VCAMIO_HW2_OP_EN_ADDR   MT6358_LDO_VCAMIO_OP_EN
#define PMIC_RG_LDO_VCAMIO_HW2_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VCAMIO_HW2_OP_EN_SHIFT  3
#define PMIC_RG_LDO_VCAMIO_OP_EN_SET_ADDR   MT6358_LDO_VCAMIO_OP_EN_SET
#define PMIC_RG_LDO_VCAMIO_OP_EN_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VCAMIO_OP_EN_SET_SHIFT  0
#define PMIC_RG_LDO_VCAMIO_OP_EN_CLR_ADDR   MT6358_LDO_VCAMIO_OP_EN_CLR
#define PMIC_RG_LDO_VCAMIO_OP_EN_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VCAMIO_OP_EN_CLR_SHIFT  0
#define PMIC_RG_LDO_VCAMIO_HW0_OP_CFG_ADDR  MT6358_LDO_VCAMIO_OP_CFG
#define PMIC_RG_LDO_VCAMIO_HW0_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VCAMIO_HW0_OP_CFG_SHIFT 1
#define PMIC_RG_LDO_VCAMIO_HW1_OP_CFG_ADDR  MT6358_LDO_VCAMIO_OP_CFG
#define PMIC_RG_LDO_VCAMIO_HW1_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VCAMIO_HW1_OP_CFG_SHIFT 2
#define PMIC_RG_LDO_VCAMIO_HW2_OP_CFG_ADDR  MT6358_LDO_VCAMIO_OP_CFG
#define PMIC_RG_LDO_VCAMIO_HW2_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VCAMIO_HW2_OP_CFG_SHIFT 3
#define PMIC_RG_LDO_VCAMIO_OP_CFG_SET_ADDR  MT6358_LDO_VCAMIO_OP_CFG_SET
#define PMIC_RG_LDO_VCAMIO_OP_CFG_SET_MASK  0xFFFF
#define PMIC_RG_LDO_VCAMIO_OP_CFG_SET_SHIFT 0
#define PMIC_RG_LDO_VCAMIO_OP_CFG_CLR_ADDR  MT6358_LDO_VCAMIO_OP_CFG_CLR
#define PMIC_RG_LDO_VCAMIO_OP_CFG_CLR_MASK  0xFFFF
#define PMIC_RG_LDO_VCAMIO_OP_CFG_CLR_SHIFT 0
#define PMIC_DA_VCAMIO_MODE_ADDR  MT6358_LDO_VCAMIO_CON1
#define PMIC_DA_VCAMIO_MODE_MASK  0x1
#define PMIC_DA_VCAMIO_MODE_SHIFT 8
#define PMIC_RG_LDO_VCAMIO_STBTD_ADDR MT6358_LDO_VCAMIO_CON1
#define PMIC_RG_LDO_VCAMIO_STBTD_MASK 0x3
#define PMIC_RG_LDO_VCAMIO_STBTD_SHIFT  9
#define PMIC_DA_VCAMIO_STB_ADDR MT6358_LDO_VCAMIO_CON1
#define PMIC_DA_VCAMIO_STB_MASK 0x1
#define PMIC_DA_VCAMIO_STB_SHIFT  14
#define PMIC_DA_VCAMIO_EN_ADDR  MT6358_LDO_VCAMIO_CON1
#define PMIC_DA_VCAMIO_EN_MASK  0x1
#define PMIC_DA_VCAMIO_EN_SHIFT 15
#define PMIC_RG_LDO_VCAMIO_OCFB_EN_ADDR MT6358_LDO_VCAMIO_CON2
#define PMIC_RG_LDO_VCAMIO_OCFB_EN_MASK 0x1
#define PMIC_RG_LDO_VCAMIO_OCFB_EN_SHIFT   9
#define PMIC_DA_VCAMIO_OCFB_EN_ADDR   MT6358_LDO_VCAMIO_CON2
#define PMIC_DA_VCAMIO_OCFB_EN_MASK   0x1
#define PMIC_DA_VCAMIO_OCFB_EN_SHIFT  10
#define PMIC_RG_LDO_VCAMIO_DUMMY_LOAD_ADDR  MT6358_LDO_VCAMIO_CON3
#define PMIC_RG_LDO_VCAMIO_DUMMY_LOAD_MASK  0x3
#define PMIC_RG_LDO_VCAMIO_DUMMY_LOAD_SHIFT 5
#define PMIC_DA_VCAMIO_DUMMY_LOAD_ADDR  MT6358_LDO_VCAMIO_CON3
#define PMIC_DA_VCAMIO_DUMMY_LOAD_MASK  0x3
#define PMIC_DA_VCAMIO_DUMMY_LOAD_SHIFT 14
#define PMIC_RG_LDO_VMC_EN_ADDR MT6358_LDO_VMC_CON0
#define PMIC_RG_LDO_VMC_EN_MASK 0x1
#define PMIC_RG_LDO_VMC_EN_SHIFT  0
#define PMIC_RG_LDO_VMC_LP_ADDR MT6358_LDO_VMC_CON0
#define PMIC_RG_LDO_VMC_LP_MASK 0x1
#define PMIC_RG_LDO_VMC_LP_SHIFT  1
#define PMIC_RG_LDO_VMC_SW_OP_EN_ADDR MT6358_LDO_VMC_OP_EN
#define PMIC_RG_LDO_VMC_SW_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VMC_SW_OP_EN_SHIFT  0
#define PMIC_RG_LDO_VMC_HW0_OP_EN_ADDR  MT6358_LDO_VMC_OP_EN
#define PMIC_RG_LDO_VMC_HW0_OP_EN_MASK  0x1
#define PMIC_RG_LDO_VMC_HW0_OP_EN_SHIFT 1
#define PMIC_RG_LDO_VMC_HW1_OP_EN_ADDR  MT6358_LDO_VMC_OP_EN
#define PMIC_RG_LDO_VMC_HW1_OP_EN_MASK  0x1
#define PMIC_RG_LDO_VMC_HW1_OP_EN_SHIFT 2
#define PMIC_RG_LDO_VMC_HW2_OP_EN_ADDR  MT6358_LDO_VMC_OP_EN
#define PMIC_RG_LDO_VMC_HW2_OP_EN_MASK  0x1
#define PMIC_RG_LDO_VMC_HW2_OP_EN_SHIFT 3
#define PMIC_RG_LDO_VMC_OP_EN_SET_ADDR  MT6358_LDO_VMC_OP_EN_SET
#define PMIC_RG_LDO_VMC_OP_EN_SET_MASK  0xFFFF
#define PMIC_RG_LDO_VMC_OP_EN_SET_SHIFT 0
#define PMIC_RG_LDO_VMC_OP_EN_CLR_ADDR  MT6358_LDO_VMC_OP_EN_CLR
#define PMIC_RG_LDO_VMC_OP_EN_CLR_MASK  0xFFFF
#define PMIC_RG_LDO_VMC_OP_EN_CLR_SHIFT 0
#define PMIC_RG_LDO_VMC_HW0_OP_CFG_ADDR MT6358_LDO_VMC_OP_CFG
#define PMIC_RG_LDO_VMC_HW0_OP_CFG_MASK 0x1
#define PMIC_RG_LDO_VMC_HW0_OP_CFG_SHIFT   1
#define PMIC_RG_LDO_VMC_HW1_OP_CFG_ADDR MT6358_LDO_VMC_OP_CFG
#define PMIC_RG_LDO_VMC_HW1_OP_CFG_MASK 0x1
#define PMIC_RG_LDO_VMC_HW1_OP_CFG_SHIFT   2
#define PMIC_RG_LDO_VMC_HW2_OP_CFG_ADDR MT6358_LDO_VMC_OP_CFG
#define PMIC_RG_LDO_VMC_HW2_OP_CFG_MASK 0x1
#define PMIC_RG_LDO_VMC_HW2_OP_CFG_SHIFT   3
#define PMIC_RG_LDO_VMC_OP_CFG_SET_ADDR MT6358_LDO_VMC_OP_CFG_SET
#define PMIC_RG_LDO_VMC_OP_CFG_SET_MASK 0xFFFF
#define PMIC_RG_LDO_VMC_OP_CFG_SET_SHIFT   0
#define PMIC_RG_LDO_VMC_OP_CFG_CLR_ADDR MT6358_LDO_VMC_OP_CFG_CLR
#define PMIC_RG_LDO_VMC_OP_CFG_CLR_MASK 0xFFFF
#define PMIC_RG_LDO_VMC_OP_CFG_CLR_SHIFT   0
#define PMIC_DA_VMC_MODE_ADDR   MT6358_LDO_VMC_CON1
#define PMIC_DA_VMC_MODE_MASK   0x1
#define PMIC_DA_VMC_MODE_SHIFT  8
#define PMIC_RG_LDO_VMC_STBTD_ADDR MT6358_LDO_VMC_CON1
#define PMIC_RG_LDO_VMC_STBTD_MASK 0x3
#define PMIC_RG_LDO_VMC_STBTD_SHIFT   9
#define PMIC_DA_VMC_STB_ADDR MT6358_LDO_VMC_CON1
#define PMIC_DA_VMC_STB_MASK 0x1
#define PMIC_DA_VMC_STB_SHIFT   14
#define PMIC_DA_VMC_EN_ADDR  MT6358_LDO_VMC_CON1
#define PMIC_DA_VMC_EN_MASK  0x1
#define PMIC_DA_VMC_EN_SHIFT 15
#define PMIC_RG_LDO_VMC_OCFB_EN_ADDR  MT6358_LDO_VMC_CON2
#define PMIC_RG_LDO_VMC_OCFB_EN_MASK  0x1
#define PMIC_RG_LDO_VMC_OCFB_EN_SHIFT 9
#define PMIC_DA_VMC_OCFB_EN_ADDR  MT6358_LDO_VMC_CON2
#define PMIC_DA_VMC_OCFB_EN_MASK  0x1
#define PMIC_DA_VMC_OCFB_EN_SHIFT 10
#define PMIC_RG_LDO_VMC_DUMMY_LOAD_ADDR MT6358_LDO_VMC_CON3
#define PMIC_RG_LDO_VMC_DUMMY_LOAD_MASK 0x3
#define PMIC_RG_LDO_VMC_DUMMY_LOAD_SHIFT   5
#define PMIC_DA_VMC_DUMMY_LOAD_ADDR   MT6358_LDO_VMC_CON3
#define PMIC_DA_VMC_DUMMY_LOAD_MASK   0x3
#define PMIC_DA_VMC_DUMMY_LOAD_SHIFT  14
#define PMIC_RG_LDO_VMCH_EN_ADDR  MT6358_LDO_VMCH_CON0
#define PMIC_RG_LDO_VMCH_EN_MASK  0x1
#define PMIC_RG_LDO_VMCH_EN_SHIFT 0
#define PMIC_RG_LDO_VMCH_LP_ADDR  MT6358_LDO_VMCH_CON0
#define PMIC_RG_LDO_VMCH_LP_MASK  0x1
#define PMIC_RG_LDO_VMCH_LP_SHIFT 1
#define PMIC_RG_LDO_VMCH_SW_OP_EN_ADDR  MT6358_LDO_VMCH_OP_EN
#define PMIC_RG_LDO_VMCH_SW_OP_EN_MASK  0x1
#define PMIC_RG_LDO_VMCH_SW_OP_EN_SHIFT 0
#define PMIC_RG_LDO_VMCH_HW0_OP_EN_ADDR MT6358_LDO_VMCH_OP_EN
#define PMIC_RG_LDO_VMCH_HW0_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VMCH_HW0_OP_EN_SHIFT   1
#define PMIC_RG_LDO_VMCH_HW1_OP_EN_ADDR MT6358_LDO_VMCH_OP_EN
#define PMIC_RG_LDO_VMCH_HW1_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VMCH_HW1_OP_EN_SHIFT   2
#define PMIC_RG_LDO_VMCH_HW2_OP_EN_ADDR MT6358_LDO_VMCH_OP_EN
#define PMIC_RG_LDO_VMCH_HW2_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VMCH_HW2_OP_EN_SHIFT   3
#define PMIC_RG_LDO_VMCH_OP_EN_SET_ADDR MT6358_LDO_VMCH_OP_EN_SET
#define PMIC_RG_LDO_VMCH_OP_EN_SET_MASK 0xFFFF
#define PMIC_RG_LDO_VMCH_OP_EN_SET_SHIFT   0
#define PMIC_RG_LDO_VMCH_OP_EN_CLR_ADDR MT6358_LDO_VMCH_OP_EN_CLR
#define PMIC_RG_LDO_VMCH_OP_EN_CLR_MASK 0xFFFF
#define PMIC_RG_LDO_VMCH_OP_EN_CLR_SHIFT   0
#define PMIC_RG_LDO_VMCH_HW0_OP_CFG_ADDR   MT6358_LDO_VMCH_OP_CFG
#define PMIC_RG_LDO_VMCH_HW0_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VMCH_HW0_OP_CFG_SHIFT   1
#define PMIC_RG_LDO_VMCH_HW1_OP_CFG_ADDR   MT6358_LDO_VMCH_OP_CFG
#define PMIC_RG_LDO_VMCH_HW1_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VMCH_HW1_OP_CFG_SHIFT   2
#define PMIC_RG_LDO_VMCH_HW2_OP_CFG_ADDR   MT6358_LDO_VMCH_OP_CFG
#define PMIC_RG_LDO_VMCH_HW2_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VMCH_HW2_OP_CFG_SHIFT   3
#define PMIC_RG_LDO_VMCH_OP_CFG_SET_ADDR   MT6358_LDO_VMCH_OP_CFG_SET
#define PMIC_RG_LDO_VMCH_OP_CFG_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VMCH_OP_CFG_SET_SHIFT   0
#define PMIC_RG_LDO_VMCH_OP_CFG_CLR_ADDR   MT6358_LDO_VMCH_OP_CFG_CLR
#define PMIC_RG_LDO_VMCH_OP_CFG_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VMCH_OP_CFG_CLR_SHIFT   0
#define PMIC_DA_VMCH_MODE_ADDR  MT6358_LDO_VMCH_CON1
#define PMIC_DA_VMCH_MODE_MASK  0x1
#define PMIC_DA_VMCH_MODE_SHIFT 8
#define PMIC_RG_LDO_VMCH_STBTD_ADDR   MT6358_LDO_VMCH_CON1
#define PMIC_RG_LDO_VMCH_STBTD_MASK   0x3
#define PMIC_RG_LDO_VMCH_STBTD_SHIFT  9
#define PMIC_DA_VMCH_STB_ADDR   MT6358_LDO_VMCH_CON1
#define PMIC_DA_VMCH_STB_MASK   0x1
#define PMIC_DA_VMCH_STB_SHIFT  14
#define PMIC_DA_VMCH_EN_ADDR MT6358_LDO_VMCH_CON1
#define PMIC_DA_VMCH_EN_MASK 0x1
#define PMIC_DA_VMCH_EN_SHIFT   15
#define PMIC_RG_LDO_VMCH_OCFB_EN_ADDR MT6358_LDO_VMCH_CON2
#define PMIC_RG_LDO_VMCH_OCFB_EN_MASK 0x1
#define PMIC_RG_LDO_VMCH_OCFB_EN_SHIFT  9
#define PMIC_DA_VMCH_OCFB_EN_ADDR MT6358_LDO_VMCH_CON2
#define PMIC_DA_VMCH_OCFB_EN_MASK 0x1
#define PMIC_DA_VMCH_OCFB_EN_SHIFT 10
#define PMIC_RG_LDO_VMCH_DUMMY_LOAD_ADDR   MT6358_LDO_VMCH_CON3
#define PMIC_RG_LDO_VMCH_DUMMY_LOAD_MASK   0x3
#define PMIC_RG_LDO_VMCH_DUMMY_LOAD_SHIFT   5
#define PMIC_DA_VMCH_DUMMY_LOAD_ADDR  MT6358_LDO_VMCH_CON3
#define PMIC_DA_VMCH_DUMMY_LOAD_MASK  0x3
#define PMIC_DA_VMCH_DUMMY_LOAD_SHIFT 14
#define PMIC_LDO_GOFF2_ANA_ID_ADDR MT6358_LDO_GOFF2_DSN_ID
#define PMIC_LDO_GOFF2_ANA_ID_MASK 0xFF
#define PMIC_LDO_GOFF2_ANA_ID_SHIFT   0
#define PMIC_LDO_GOFF2_DIG_ID_ADDR MT6358_LDO_GOFF2_DSN_ID
#define PMIC_LDO_GOFF2_DIG_ID_MASK 0xFF
#define PMIC_LDO_GOFF2_DIG_ID_SHIFT   8
#define PMIC_LDO_GOFF2_ANA_MINOR_REV_ADDR   MT6358_LDO_GOFF2_DSN_REV0
#define PMIC_LDO_GOFF2_ANA_MINOR_REV_MASK   0xF
#define PMIC_LDO_GOFF2_ANA_MINOR_REV_SHIFT  0
#define PMIC_LDO_GOFF2_ANA_MAJOR_REV_ADDR   MT6358_LDO_GOFF2_DSN_REV0
#define PMIC_LDO_GOFF2_ANA_MAJOR_REV_MASK   0xF
#define PMIC_LDO_GOFF2_ANA_MAJOR_REV_SHIFT  4
#define PMIC_LDO_GOFF2_DIG_MINOR_REV_ADDR   MT6358_LDO_GOFF2_DSN_REV0
#define PMIC_LDO_GOFF2_DIG_MINOR_REV_MASK   0xF
#define PMIC_LDO_GOFF2_DIG_MINOR_REV_SHIFT  8
#define PMIC_LDO_GOFF2_DIG_MAJOR_REV_ADDR   MT6358_LDO_GOFF2_DSN_REV0
#define PMIC_LDO_GOFF2_DIG_MAJOR_REV_MASK   0xF
#define PMIC_LDO_GOFF2_DIG_MAJOR_REV_SHIFT  12
#define PMIC_LDO_GOFF2_DSN_CBS_ADDR   MT6358_LDO_GOFF2_DSN_DBI
#define PMIC_LDO_GOFF2_DSN_CBS_MASK   0x3
#define PMIC_LDO_GOFF2_DSN_CBS_SHIFT  0
#define PMIC_LDO_GOFF2_DSN_BIX_ADDR   MT6358_LDO_GOFF2_DSN_DBI
#define PMIC_LDO_GOFF2_DSN_BIX_MASK   0x3
#define PMIC_LDO_GOFF2_DSN_BIX_SHIFT  2
#define PMIC_LDO_GOFF2_DSN_ESP_ADDR   MT6358_LDO_GOFF2_DSN_DBI
#define PMIC_LDO_GOFF2_DSN_ESP_MASK   0xFF
#define PMIC_LDO_GOFF2_DSN_ESP_SHIFT  8
#define PMIC_LDO_GOFF2_DSN_FPI_ADDR   MT6358_LDO_GOFF2_DSN_DXI
#define PMIC_LDO_GOFF2_DSN_FPI_MASK   0xFF
#define PMIC_LDO_GOFF2_DSN_FPI_SHIFT  0
#define PMIC_RG_LDO_VIBR_EN_ADDR  MT6358_LDO_VIBR_CON0
#define PMIC_RG_LDO_VIBR_EN_MASK  0x1
#define PMIC_RG_LDO_VIBR_EN_SHIFT 0
#define PMIC_RG_LDO_VIBR_LP_ADDR  MT6358_LDO_VIBR_CON0
#define PMIC_RG_LDO_VIBR_LP_MASK  0x1
#define PMIC_RG_LDO_VIBR_LP_SHIFT 1
#define PMIC_RG_LDO_VIBR_SW_OP_EN_ADDR  MT6358_LDO_VIBR_OP_EN
#define PMIC_RG_LDO_VIBR_SW_OP_EN_MASK  0x1
#define PMIC_RG_LDO_VIBR_SW_OP_EN_SHIFT 0
#define PMIC_RG_LDO_VIBR_HW0_OP_EN_ADDR MT6358_LDO_VIBR_OP_EN
#define PMIC_RG_LDO_VIBR_HW0_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VIBR_HW0_OP_EN_SHIFT   1
#define PMIC_RG_LDO_VIBR_HW1_OP_EN_ADDR MT6358_LDO_VIBR_OP_EN
#define PMIC_RG_LDO_VIBR_HW1_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VIBR_HW1_OP_EN_SHIFT   2
#define PMIC_RG_LDO_VIBR_HW2_OP_EN_ADDR MT6358_LDO_VIBR_OP_EN
#define PMIC_RG_LDO_VIBR_HW2_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VIBR_HW2_OP_EN_SHIFT   3
#define PMIC_RG_LDO_VIBR_OP_EN_SET_ADDR MT6358_LDO_VIBR_OP_EN_SET
#define PMIC_RG_LDO_VIBR_OP_EN_SET_MASK 0xFFFF
#define PMIC_RG_LDO_VIBR_OP_EN_SET_SHIFT   0
#define PMIC_RG_LDO_VIBR_OP_EN_CLR_ADDR MT6358_LDO_VIBR_OP_EN_CLR
#define PMIC_RG_LDO_VIBR_OP_EN_CLR_MASK 0xFFFF
#define PMIC_RG_LDO_VIBR_OP_EN_CLR_SHIFT   0
#define PMIC_RG_LDO_VIBR_HW0_OP_CFG_ADDR   MT6358_LDO_VIBR_OP_CFG
#define PMIC_RG_LDO_VIBR_HW0_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VIBR_HW0_OP_CFG_SHIFT   1
#define PMIC_RG_LDO_VIBR_HW1_OP_CFG_ADDR   MT6358_LDO_VIBR_OP_CFG
#define PMIC_RG_LDO_VIBR_HW1_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VIBR_HW1_OP_CFG_SHIFT   2
#define PMIC_RG_LDO_VIBR_HW2_OP_CFG_ADDR   MT6358_LDO_VIBR_OP_CFG
#define PMIC_RG_LDO_VIBR_HW2_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VIBR_HW2_OP_CFG_SHIFT   3
#define PMIC_RG_LDO_VIBR_OP_CFG_SET_ADDR   MT6358_LDO_VIBR_OP_CFG_SET
#define PMIC_RG_LDO_VIBR_OP_CFG_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VIBR_OP_CFG_SET_SHIFT   0
#define PMIC_RG_LDO_VIBR_OP_CFG_CLR_ADDR   MT6358_LDO_VIBR_OP_CFG_CLR
#define PMIC_RG_LDO_VIBR_OP_CFG_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VIBR_OP_CFG_CLR_SHIFT   0
#define PMIC_DA_VIBR_MODE_ADDR  MT6358_LDO_VIBR_CON1
#define PMIC_DA_VIBR_MODE_MASK  0x1
#define PMIC_DA_VIBR_MODE_SHIFT 8
#define PMIC_RG_LDO_VIBR_STBTD_ADDR   MT6358_LDO_VIBR_CON1
#define PMIC_RG_LDO_VIBR_STBTD_MASK   0x3
#define PMIC_RG_LDO_VIBR_STBTD_SHIFT  9
#define PMIC_DA_VIBR_STB_ADDR   MT6358_LDO_VIBR_CON1
#define PMIC_DA_VIBR_STB_MASK   0x1
#define PMIC_DA_VIBR_STB_SHIFT  14
#define PMIC_DA_VIBR_EN_ADDR MT6358_LDO_VIBR_CON1
#define PMIC_DA_VIBR_EN_MASK 0x1
#define PMIC_DA_VIBR_EN_SHIFT   15
#define PMIC_RG_LDO_VIBR_OCFB_EN_ADDR MT6358_LDO_VIBR_CON2
#define PMIC_RG_LDO_VIBR_OCFB_EN_MASK 0x1
#define PMIC_RG_LDO_VIBR_OCFB_EN_SHIFT  9
#define PMIC_DA_VIBR_OCFB_EN_ADDR MT6358_LDO_VIBR_CON2
#define PMIC_DA_VIBR_OCFB_EN_MASK 0x1
#define PMIC_DA_VIBR_OCFB_EN_SHIFT 10
#define PMIC_RG_LDO_VIBR_DUMMY_LOAD_ADDR   MT6358_LDO_VIBR_CON3
#define PMIC_RG_LDO_VIBR_DUMMY_LOAD_MASK   0x3
#define PMIC_RG_LDO_VIBR_DUMMY_LOAD_SHIFT   5
#define PMIC_DA_VIBR_DUMMY_LOAD_ADDR  MT6358_LDO_VIBR_CON3
#define PMIC_DA_VIBR_DUMMY_LOAD_MASK  0x3
#define PMIC_DA_VIBR_DUMMY_LOAD_SHIFT 14
#define PMIC_RG_LDO_VCN33_EN_0_ADDR   MT6358_LDO_VCN33_CON0_0
#define PMIC_RG_LDO_VCN33_EN_0_MASK   0x1
#define PMIC_RG_LDO_VCN33_EN_0_SHIFT  0
#define PMIC_RG_LDO_VCN33_LP_ADDR MT6358_LDO_VCN33_CON0_0
#define PMIC_RG_LDO_VCN33_LP_MASK 0x1
#define PMIC_RG_LDO_VCN33_LP_SHIFT 1
#define PMIC_RG_LDO_VCN33_SW_OP_EN_ADDR MT6358_LDO_VCN33_OP_EN
#define PMIC_RG_LDO_VCN33_SW_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VCN33_SW_OP_EN_SHIFT   0
#define PMIC_RG_LDO_VCN33_HW0_OP_EN_ADDR   MT6358_LDO_VCN33_OP_EN
#define PMIC_RG_LDO_VCN33_HW0_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VCN33_HW0_OP_EN_SHIFT   1
#define PMIC_RG_LDO_VCN33_HW1_OP_EN_ADDR   MT6358_LDO_VCN33_OP_EN
#define PMIC_RG_LDO_VCN33_HW1_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VCN33_HW1_OP_EN_SHIFT   2
#define PMIC_RG_LDO_VCN33_HW2_OP_EN_ADDR   MT6358_LDO_VCN33_OP_EN
#define PMIC_RG_LDO_VCN33_HW2_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VCN33_HW2_OP_EN_SHIFT   3
#define PMIC_RG_LDO_VCN33_OP_EN_SET_ADDR   MT6358_LDO_VCN33_OP_EN_SET
#define PMIC_RG_LDO_VCN33_OP_EN_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VCN33_OP_EN_SET_SHIFT   0
#define PMIC_RG_LDO_VCN33_OP_EN_CLR_ADDR   MT6358_LDO_VCN33_OP_EN_CLR
#define PMIC_RG_LDO_VCN33_OP_EN_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VCN33_OP_EN_CLR_SHIFT   0
#define PMIC_RG_LDO_VCN33_HW0_OP_CFG_ADDR   MT6358_LDO_VCN33_OP_CFG
#define PMIC_RG_LDO_VCN33_HW0_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VCN33_HW0_OP_CFG_SHIFT  1
#define PMIC_RG_LDO_VCN33_HW1_OP_CFG_ADDR   MT6358_LDO_VCN33_OP_CFG
#define PMIC_RG_LDO_VCN33_HW1_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VCN33_HW1_OP_CFG_SHIFT  2
#define PMIC_RG_LDO_VCN33_HW2_OP_CFG_ADDR   MT6358_LDO_VCN33_OP_CFG
#define PMIC_RG_LDO_VCN33_HW2_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VCN33_HW2_OP_CFG_SHIFT  3
#define PMIC_RG_LDO_VCN33_OP_CFG_SET_ADDR   MT6358_LDO_VCN33_OP_CFG_SET
#define PMIC_RG_LDO_VCN33_OP_CFG_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VCN33_OP_CFG_SET_SHIFT  0
#define PMIC_RG_LDO_VCN33_OP_CFG_CLR_ADDR   MT6358_LDO_VCN33_OP_CFG_CLR
#define PMIC_RG_LDO_VCN33_OP_CFG_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VCN33_OP_CFG_CLR_SHIFT  0
#define PMIC_RG_LDO_VCN33_EN_1_ADDR   MT6358_LDO_VCN33_CON0_1
#define PMIC_RG_LDO_VCN33_EN_1_MASK   0x1
#define PMIC_RG_LDO_VCN33_EN_1_SHIFT  0
#define PMIC_DA_VCN33_MODE_ADDR MT6358_LDO_VCN33_CON1
#define PMIC_DA_VCN33_MODE_MASK 0x1
#define PMIC_DA_VCN33_MODE_SHIFT  8
#define PMIC_RG_LDO_VCN33_STBTD_ADDR  MT6358_LDO_VCN33_CON1
#define PMIC_RG_LDO_VCN33_STBTD_MASK  0x3
#define PMIC_RG_LDO_VCN33_STBTD_SHIFT 9
#define PMIC_DA_VCN33_STB_ADDR  MT6358_LDO_VCN33_CON1
#define PMIC_DA_VCN33_STB_MASK  0x1
#define PMIC_DA_VCN33_STB_SHIFT 14
#define PMIC_DA_VCN33_EN_ADDR   MT6358_LDO_VCN33_CON1
#define PMIC_DA_VCN33_EN_MASK   0x1
#define PMIC_DA_VCN33_EN_SHIFT  15
#define PMIC_RG_LDO_VCN33_OCFB_EN_ADDR  MT6358_LDO_VCN33_CON2
#define PMIC_RG_LDO_VCN33_OCFB_EN_MASK  0x1
#define PMIC_RG_LDO_VCN33_OCFB_EN_SHIFT 9
#define PMIC_DA_VCN33_OCFB_EN_ADDR MT6358_LDO_VCN33_CON2
#define PMIC_DA_VCN33_OCFB_EN_MASK 0x1
#define PMIC_DA_VCN33_OCFB_EN_SHIFT   10
#define PMIC_RG_LDO_VCN33_DUMMY_LOAD_ADDR   MT6358_LDO_VCN33_CON3
#define PMIC_RG_LDO_VCN33_DUMMY_LOAD_MASK   0x3
#define PMIC_RG_LDO_VCN33_DUMMY_LOAD_SHIFT  5
#define PMIC_DA_VCN33_DUMMY_LOAD_ADDR MT6358_LDO_VCN33_CON3
#define PMIC_DA_VCN33_DUMMY_LOAD_MASK 0x3
#define PMIC_DA_VCN33_DUMMY_LOAD_SHIFT  14
#define PMIC_RG_LDO_VLDO28_EN_0_ADDR  MT6358_LDO_VLDO28_CON0_0
#define PMIC_RG_LDO_VLDO28_EN_0_MASK  0x1
#define PMIC_RG_LDO_VLDO28_EN_0_SHIFT 0
#define PMIC_RG_LDO_VLDO28_LP_ADDR MT6358_LDO_VLDO28_CON0_0
#define PMIC_RG_LDO_VLDO28_LP_MASK 0x1
#define PMIC_RG_LDO_VLDO28_LP_SHIFT   1
#define PMIC_RG_LDO_VLDO28_SW_OP_EN_ADDR   MT6358_LDO_VLDO28_OP_EN
#define PMIC_RG_LDO_VLDO28_SW_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VLDO28_SW_OP_EN_SHIFT   0
#define PMIC_RG_LDO_VLDO28_HW0_OP_EN_ADDR   MT6358_LDO_VLDO28_OP_EN
#define PMIC_RG_LDO_VLDO28_HW0_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VLDO28_HW0_OP_EN_SHIFT  1
#define PMIC_RG_LDO_VLDO28_HW1_OP_EN_ADDR   MT6358_LDO_VLDO28_OP_EN
#define PMIC_RG_LDO_VLDO28_HW1_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VLDO28_HW1_OP_EN_SHIFT  2
#define PMIC_RG_LDO_VLDO28_HW2_OP_EN_ADDR   MT6358_LDO_VLDO28_OP_EN
#define PMIC_RG_LDO_VLDO28_HW2_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VLDO28_HW2_OP_EN_SHIFT  3
#define PMIC_RG_LDO_VLDO28_OP_EN_SET_ADDR   MT6358_LDO_VLDO28_OP_EN_SET
#define PMIC_RG_LDO_VLDO28_OP_EN_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VLDO28_OP_EN_SET_SHIFT  0
#define PMIC_RG_LDO_VLDO28_OP_EN_CLR_ADDR   MT6358_LDO_VLDO28_OP_EN_CLR
#define PMIC_RG_LDO_VLDO28_OP_EN_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VLDO28_OP_EN_CLR_SHIFT  0
#define PMIC_RG_LDO_VLDO28_HW0_OP_CFG_ADDR  MT6358_LDO_VLDO28_OP_CFG
#define PMIC_RG_LDO_VLDO28_HW0_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VLDO28_HW0_OP_CFG_SHIFT 1
#define PMIC_RG_LDO_VLDO28_HW1_OP_CFG_ADDR  MT6358_LDO_VLDO28_OP_CFG
#define PMIC_RG_LDO_VLDO28_HW1_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VLDO28_HW1_OP_CFG_SHIFT 2
#define PMIC_RG_LDO_VLDO28_HW2_OP_CFG_ADDR  MT6358_LDO_VLDO28_OP_CFG
#define PMIC_RG_LDO_VLDO28_HW2_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VLDO28_HW2_OP_CFG_SHIFT 3
#define PMIC_RG_LDO_VLDO28_OP_CFG_SET_ADDR  MT6358_LDO_VLDO28_OP_CFG_SET
#define PMIC_RG_LDO_VLDO28_OP_CFG_SET_MASK  0xFFFF
#define PMIC_RG_LDO_VLDO28_OP_CFG_SET_SHIFT 0
#define PMIC_RG_LDO_VLDO28_OP_CFG_CLR_ADDR  MT6358_LDO_VLDO28_OP_CFG_CLR
#define PMIC_RG_LDO_VLDO28_OP_CFG_CLR_MASK  0xFFFF
#define PMIC_RG_LDO_VLDO28_OP_CFG_CLR_SHIFT 0
#define PMIC_RG_LDO_VLDO28_EN_1_ADDR  MT6358_LDO_VLDO28_CON0_1
#define PMIC_RG_LDO_VLDO28_EN_1_MASK  0x1
#define PMIC_RG_LDO_VLDO28_EN_1_SHIFT 0
#define PMIC_DA_VLDO28_MODE_ADDR  MT6358_LDO_VLDO28_CON1
#define PMIC_DA_VLDO28_MODE_MASK  0x1
#define PMIC_DA_VLDO28_MODE_SHIFT 8
#define PMIC_RG_LDO_VLDO28_STBTD_ADDR MT6358_LDO_VLDO28_CON1
#define PMIC_RG_LDO_VLDO28_STBTD_MASK 0x3
#define PMIC_RG_LDO_VLDO28_STBTD_SHIFT  9
#define PMIC_DA_VLDO28_STB_ADDR MT6358_LDO_VLDO28_CON1
#define PMIC_DA_VLDO28_STB_MASK 0x1
#define PMIC_DA_VLDO28_STB_SHIFT  14
#define PMIC_DA_VLDO28_EN_ADDR  MT6358_LDO_VLDO28_CON1
#define PMIC_DA_VLDO28_EN_MASK  0x1
#define PMIC_DA_VLDO28_EN_SHIFT 15
#define PMIC_RG_LDO_VLDO28_OCFB_EN_ADDR MT6358_LDO_VLDO28_CON2
#define PMIC_RG_LDO_VLDO28_OCFB_EN_MASK 0x1
#define PMIC_RG_LDO_VLDO28_OCFB_EN_SHIFT   9
#define PMIC_DA_VLDO28_OCFB_EN_ADDR   MT6358_LDO_VLDO28_CON2
#define PMIC_DA_VLDO28_OCFB_EN_MASK   0x1
#define PMIC_DA_VLDO28_OCFB_EN_SHIFT  10
#define PMIC_RG_LDO_VLDO28_DUMMY_LOAD_ADDR  MT6358_LDO_VLDO28_CON3
#define PMIC_RG_LDO_VLDO28_DUMMY_LOAD_MASK  0x3
#define PMIC_RG_LDO_VLDO28_DUMMY_LOAD_SHIFT 5
#define PMIC_DA_VLDO28_DUMMY_LOAD_ADDR  MT6358_LDO_VLDO28_CON3
#define PMIC_DA_VLDO28_DUMMY_LOAD_MASK  0x3
#define PMIC_DA_VLDO28_DUMMY_LOAD_SHIFT 14
#define PMIC_RG_LDO_VSIM1_EN_ADDR MT6358_LDO_VSIM1_CON0
#define PMIC_RG_LDO_VSIM1_EN_MASK 0x1
#define PMIC_RG_LDO_VSIM1_EN_SHIFT 0
#define PMIC_RG_LDO_VSIM1_LP_ADDR MT6358_LDO_VSIM1_CON0
#define PMIC_RG_LDO_VSIM1_LP_MASK 0x1
#define PMIC_RG_LDO_VSIM1_LP_SHIFT 1
#define PMIC_RG_LDO_VSIM1_SW_OP_EN_ADDR MT6358_LDO_VSIM1_OP_EN
#define PMIC_RG_LDO_VSIM1_SW_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VSIM1_SW_OP_EN_SHIFT   0
#define PMIC_RG_LDO_VSIM1_HW0_OP_EN_ADDR   MT6358_LDO_VSIM1_OP_EN
#define PMIC_RG_LDO_VSIM1_HW0_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VSIM1_HW0_OP_EN_SHIFT   1
#define PMIC_RG_LDO_VSIM1_HW1_OP_EN_ADDR   MT6358_LDO_VSIM1_OP_EN
#define PMIC_RG_LDO_VSIM1_HW1_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VSIM1_HW1_OP_EN_SHIFT   2
#define PMIC_RG_LDO_VSIM1_HW2_OP_EN_ADDR   MT6358_LDO_VSIM1_OP_EN
#define PMIC_RG_LDO_VSIM1_HW2_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VSIM1_HW2_OP_EN_SHIFT   3
#define PMIC_RG_LDO_VSIM1_OP_EN_SET_ADDR   MT6358_LDO_VSIM1_OP_EN_SET
#define PMIC_RG_LDO_VSIM1_OP_EN_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VSIM1_OP_EN_SET_SHIFT   0
#define PMIC_RG_LDO_VSIM1_OP_EN_CLR_ADDR   MT6358_LDO_VSIM1_OP_EN_CLR
#define PMIC_RG_LDO_VSIM1_OP_EN_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VSIM1_OP_EN_CLR_SHIFT   0
#define PMIC_RG_LDO_VSIM1_HW0_OP_CFG_ADDR   MT6358_LDO_VSIM1_OP_CFG
#define PMIC_RG_LDO_VSIM1_HW0_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VSIM1_HW0_OP_CFG_SHIFT  1
#define PMIC_RG_LDO_VSIM1_HW1_OP_CFG_ADDR   MT6358_LDO_VSIM1_OP_CFG
#define PMIC_RG_LDO_VSIM1_HW1_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VSIM1_HW1_OP_CFG_SHIFT  2
#define PMIC_RG_LDO_VSIM1_HW2_OP_CFG_ADDR   MT6358_LDO_VSIM1_OP_CFG
#define PMIC_RG_LDO_VSIM1_HW2_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VSIM1_HW2_OP_CFG_SHIFT  3
#define PMIC_RG_LDO_VSIM1_OP_CFG_SET_ADDR   MT6358_LDO_VSIM1_OP_CFG_SET
#define PMIC_RG_LDO_VSIM1_OP_CFG_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VSIM1_OP_CFG_SET_SHIFT  0
#define PMIC_RG_LDO_VSIM1_OP_CFG_CLR_ADDR   MT6358_LDO_VSIM1_OP_CFG_CLR
#define PMIC_RG_LDO_VSIM1_OP_CFG_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VSIM1_OP_CFG_CLR_SHIFT  0
#define PMIC_DA_VSIM1_MODE_ADDR MT6358_LDO_VSIM1_CON1
#define PMIC_DA_VSIM1_MODE_MASK 0x1
#define PMIC_DA_VSIM1_MODE_SHIFT  8
#define PMIC_RG_LDO_VSIM1_STBTD_ADDR  MT6358_LDO_VSIM1_CON1
#define PMIC_RG_LDO_VSIM1_STBTD_MASK  0x3
#define PMIC_RG_LDO_VSIM1_STBTD_SHIFT 9
#define PMIC_DA_VSIM1_STB_ADDR  MT6358_LDO_VSIM1_CON1
#define PMIC_DA_VSIM1_STB_MASK  0x1
#define PMIC_DA_VSIM1_STB_SHIFT 14
#define PMIC_DA_VSIM1_EN_ADDR   MT6358_LDO_VSIM1_CON1
#define PMIC_DA_VSIM1_EN_MASK   0x1
#define PMIC_DA_VSIM1_EN_SHIFT  15
#define PMIC_RG_LDO_VSIM1_OCFB_EN_ADDR  MT6358_LDO_VSIM1_CON2
#define PMIC_RG_LDO_VSIM1_OCFB_EN_MASK  0x1
#define PMIC_RG_LDO_VSIM1_OCFB_EN_SHIFT 9
#define PMIC_DA_VSIM1_OCFB_EN_ADDR MT6358_LDO_VSIM1_CON2
#define PMIC_DA_VSIM1_OCFB_EN_MASK 0x1
#define PMIC_DA_VSIM1_OCFB_EN_SHIFT   10
#define PMIC_RG_LDO_VSIM1_DUMMY_LOAD_ADDR   MT6358_LDO_VSIM1_CON3
#define PMIC_RG_LDO_VSIM1_DUMMY_LOAD_MASK   0x3
#define PMIC_RG_LDO_VSIM1_DUMMY_LOAD_SHIFT  5
#define PMIC_DA_VSIM1_DUMMY_LOAD_ADDR MT6358_LDO_VSIM1_CON3
#define PMIC_DA_VSIM1_DUMMY_LOAD_MASK 0x3
#define PMIC_DA_VSIM1_DUMMY_LOAD_SHIFT  14
#define PMIC_RG_LDO_VSIM2_EN_ADDR MT6358_LDO_VSIM2_CON0
#define PMIC_RG_LDO_VSIM2_EN_MASK 0x1
#define PMIC_RG_LDO_VSIM2_EN_SHIFT 0
#define PMIC_RG_LDO_VSIM2_LP_ADDR MT6358_LDO_VSIM2_CON0
#define PMIC_RG_LDO_VSIM2_LP_MASK 0x1
#define PMIC_RG_LDO_VSIM2_LP_SHIFT 1
#define PMIC_RG_LDO_VSIM2_SW_OP_EN_ADDR MT6358_LDO_VSIM2_OP_EN
#define PMIC_RG_LDO_VSIM2_SW_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VSIM2_SW_OP_EN_SHIFT   0
#define PMIC_RG_LDO_VSIM2_HW0_OP_EN_ADDR   MT6358_LDO_VSIM2_OP_EN
#define PMIC_RG_LDO_VSIM2_HW0_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VSIM2_HW0_OP_EN_SHIFT   1
#define PMIC_RG_LDO_VSIM2_HW1_OP_EN_ADDR   MT6358_LDO_VSIM2_OP_EN
#define PMIC_RG_LDO_VSIM2_HW1_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VSIM2_HW1_OP_EN_SHIFT   2
#define PMIC_RG_LDO_VSIM2_HW2_OP_EN_ADDR   MT6358_LDO_VSIM2_OP_EN
#define PMIC_RG_LDO_VSIM2_HW2_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VSIM2_HW2_OP_EN_SHIFT   3
#define PMIC_RG_LDO_VSIM2_OP_EN_SET_ADDR   MT6358_LDO_VSIM2_OP_EN_SET
#define PMIC_RG_LDO_VSIM2_OP_EN_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VSIM2_OP_EN_SET_SHIFT   0
#define PMIC_RG_LDO_VSIM2_OP_EN_CLR_ADDR   MT6358_LDO_VSIM2_OP_EN_CLR
#define PMIC_RG_LDO_VSIM2_OP_EN_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VSIM2_OP_EN_CLR_SHIFT   0
#define PMIC_RG_LDO_VSIM2_HW0_OP_CFG_ADDR   MT6358_LDO_VSIM2_OP_CFG
#define PMIC_RG_LDO_VSIM2_HW0_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VSIM2_HW0_OP_CFG_SHIFT  1
#define PMIC_RG_LDO_VSIM2_HW1_OP_CFG_ADDR   MT6358_LDO_VSIM2_OP_CFG
#define PMIC_RG_LDO_VSIM2_HW1_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VSIM2_HW1_OP_CFG_SHIFT  2
#define PMIC_RG_LDO_VSIM2_HW2_OP_CFG_ADDR   MT6358_LDO_VSIM2_OP_CFG
#define PMIC_RG_LDO_VSIM2_HW2_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VSIM2_HW2_OP_CFG_SHIFT  3
#define PMIC_RG_LDO_VSIM2_OP_CFG_SET_ADDR   MT6358_LDO_VSIM2_OP_CFG_SET
#define PMIC_RG_LDO_VSIM2_OP_CFG_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VSIM2_OP_CFG_SET_SHIFT  0
#define PMIC_RG_LDO_VSIM2_OP_CFG_CLR_ADDR   MT6358_LDO_VSIM2_OP_CFG_CLR
#define PMIC_RG_LDO_VSIM2_OP_CFG_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VSIM2_OP_CFG_CLR_SHIFT  0
#define PMIC_DA_VSIM2_MODE_ADDR MT6358_LDO_VSIM2_CON1
#define PMIC_DA_VSIM2_MODE_MASK 0x1
#define PMIC_DA_VSIM2_MODE_SHIFT  8
#define PMIC_RG_LDO_VSIM2_STBTD_ADDR  MT6358_LDO_VSIM2_CON1
#define PMIC_RG_LDO_VSIM2_STBTD_MASK  0x3
#define PMIC_RG_LDO_VSIM2_STBTD_SHIFT 9
#define PMIC_DA_VSIM2_STB_ADDR  MT6358_LDO_VSIM2_CON1
#define PMIC_DA_VSIM2_STB_MASK  0x1
#define PMIC_DA_VSIM2_STB_SHIFT 14
#define PMIC_DA_VSIM2_EN_ADDR   MT6358_LDO_VSIM2_CON1
#define PMIC_DA_VSIM2_EN_MASK   0x1
#define PMIC_DA_VSIM2_EN_SHIFT  15
#define PMIC_RG_LDO_VSIM2_OCFB_EN_ADDR  MT6358_LDO_VSIM2_CON2
#define PMIC_RG_LDO_VSIM2_OCFB_EN_MASK  0x1
#define PMIC_RG_LDO_VSIM2_OCFB_EN_SHIFT 9
#define PMIC_DA_VSIM2_OCFB_EN_ADDR MT6358_LDO_VSIM2_CON2
#define PMIC_DA_VSIM2_OCFB_EN_MASK 0x1
#define PMIC_DA_VSIM2_OCFB_EN_SHIFT   10
#define PMIC_RG_LDO_VSIM2_DUMMY_LOAD_ADDR   MT6358_LDO_VSIM2_CON3
#define PMIC_RG_LDO_VSIM2_DUMMY_LOAD_MASK   0x3
#define PMIC_RG_LDO_VSIM2_DUMMY_LOAD_SHIFT  5
#define PMIC_DA_VSIM2_DUMMY_LOAD_ADDR MT6358_LDO_VSIM2_CON3
#define PMIC_DA_VSIM2_DUMMY_LOAD_MASK 0x3
#define PMIC_DA_VSIM2_DUMMY_LOAD_SHIFT  14
#define PMIC_RG_LDO_VMCH_SD_EN_ADDR   MT6358_LDO_VMCH_EINT_SD_CFG
#define PMIC_RG_LDO_VMCH_SD_EN_MASK   0x1
#define PMIC_RG_LDO_VMCH_SD_EN_SHIFT  0
#define PMIC_RG_LDO_VMCH_SD_POL_ADDR  MT6358_LDO_VMCH_EINT_SD_CFG
#define PMIC_RG_LDO_VMCH_SD_POL_MASK  0x1
#define PMIC_RG_LDO_VMCH_SD_POL_SHIFT 2
#define PMIC_RG_LDO_VMCH_SD_DB_SEL_ADDR MT6358_LDO_VMCH_EINT_SD_CFG
#define PMIC_RG_LDO_VMCH_SD_DB_SEL_MASK 0x1
#define PMIC_RG_LDO_VMCH_SD_DB_SEL_SHIFT   4
#define PMIC_RG_LDO_VSIM1_SD_EN_ADDR  MT6358_LDO_VSIM1_EINT_SD_CFG
#define PMIC_RG_LDO_VSIM1_SD_EN_MASK  0x1
#define PMIC_RG_LDO_VSIM1_SD_EN_SHIFT 0
#define PMIC_RG_LDO_VSIM1_SD_POL_ADDR MT6358_LDO_VSIM1_EINT_SD_CFG
#define PMIC_RG_LDO_VSIM1_SD_POL_MASK 0x1
#define PMIC_RG_LDO_VSIM1_SD_POL_SHIFT  2
#define PMIC_RG_LDO_VSIM1_SD_DB_SEL_ADDR   MT6358_LDO_VSIM1_EINT_SD_CFG
#define PMIC_RG_LDO_VSIM1_SD_DB_SEL_MASK   0x1
#define PMIC_RG_LDO_VSIM1_SD_DB_SEL_SHIFT   4
#define PMIC_RG_LDO_VSIM2_SD_EN_ADDR  MT6358_LDO_VSIM2_EINT_SD_CFG
#define PMIC_RG_LDO_VSIM2_SD_EN_MASK  0x1
#define PMIC_RG_LDO_VSIM2_SD_EN_SHIFT 0
#define PMIC_RG_LDO_VSIM2_SD_POL_ADDR MT6358_LDO_VSIM2_EINT_SD_CFG
#define PMIC_RG_LDO_VSIM2_SD_POL_MASK 0x1
#define PMIC_RG_LDO_VSIM2_SD_POL_SHIFT  2
#define PMIC_RG_LDO_VSIM2_SD_DB_SEL_ADDR   MT6358_LDO_VSIM2_EINT_SD_CFG
#define PMIC_RG_LDO_VSIM2_SD_DB_SEL_MASK   0x1
#define PMIC_RG_LDO_VSIM2_SD_DB_SEL_SHIFT   4
#define PMIC_RG_LDO_GOFF2_RSV0_ADDR   MT6358_LDO_GOFF2_RSV_CON0
#define PMIC_RG_LDO_GOFF2_RSV0_MASK   0xF
#define PMIC_RG_LDO_GOFF2_RSV0_SHIFT  0
#define PMIC_RG_LDO_GOFF2_RSV1_ADDR   MT6358_LDO_GOFF2_RSV_CON1
#define PMIC_RG_LDO_GOFF2_RSV1_MASK   0xF
#define PMIC_RG_LDO_GOFF2_RSV1_SHIFT  0
#define PMIC_LDO_GOFF3_ANA_ID_ADDR MT6358_LDO_GOFF3_DSN_ID
#define PMIC_LDO_GOFF3_ANA_ID_MASK 0xFF
#define PMIC_LDO_GOFF3_ANA_ID_SHIFT   0
#define PMIC_LDO_GOFF3_DIG_ID_ADDR MT6358_LDO_GOFF3_DSN_ID
#define PMIC_LDO_GOFF3_DIG_ID_MASK 0xFF
#define PMIC_LDO_GOFF3_DIG_ID_SHIFT   8
#define PMIC_LDO_GOFF3_ANA_MINOR_REV_ADDR   MT6358_LDO_GOFF3_DSN_REV0
#define PMIC_LDO_GOFF3_ANA_MINOR_REV_MASK   0xF
#define PMIC_LDO_GOFF3_ANA_MINOR_REV_SHIFT  0
#define PMIC_LDO_GOFF3_ANA_MAJOR_REV_ADDR   MT6358_LDO_GOFF3_DSN_REV0
#define PMIC_LDO_GOFF3_ANA_MAJOR_REV_MASK   0xF
#define PMIC_LDO_GOFF3_ANA_MAJOR_REV_SHIFT  4
#define PMIC_LDO_GOFF3_DIG_MINOR_REV_ADDR   MT6358_LDO_GOFF3_DSN_REV0
#define PMIC_LDO_GOFF3_DIG_MINOR_REV_MASK   0xF
#define PMIC_LDO_GOFF3_DIG_MINOR_REV_SHIFT  8
#define PMIC_LDO_GOFF3_DIG_MAJOR_REV_ADDR   MT6358_LDO_GOFF3_DSN_REV0
#define PMIC_LDO_GOFF3_DIG_MAJOR_REV_MASK   0xF
#define PMIC_LDO_GOFF3_DIG_MAJOR_REV_SHIFT  12
#define PMIC_LDO_GOFF3_DSN_CBS_ADDR   MT6358_LDO_GOFF3_DSN_DBI
#define PMIC_LDO_GOFF3_DSN_CBS_MASK   0x3
#define PMIC_LDO_GOFF3_DSN_CBS_SHIFT  0
#define PMIC_LDO_GOFF3_DSN_BIX_ADDR   MT6358_LDO_GOFF3_DSN_DBI
#define PMIC_LDO_GOFF3_DSN_BIX_MASK   0x3
#define PMIC_LDO_GOFF3_DSN_BIX_SHIFT  2
#define PMIC_LDO_GOFF3_DSN_ESP_ADDR   MT6358_LDO_GOFF3_DSN_DBI
#define PMIC_LDO_GOFF3_DSN_ESP_MASK   0xFF
#define PMIC_LDO_GOFF3_DSN_ESP_SHIFT  8
#define PMIC_LDO_GOFF3_DSN_FPI_ADDR   MT6358_LDO_GOFF3_DSN_DXI
#define PMIC_LDO_GOFF3_DSN_FPI_MASK   0xFF
#define PMIC_LDO_GOFF3_DSN_FPI_SHIFT  0
#define PMIC_RG_LDO_VCN28_EN_ADDR MT6358_LDO_VCN28_CON0
#define PMIC_RG_LDO_VCN28_EN_MASK 0x1
#define PMIC_RG_LDO_VCN28_EN_SHIFT 0
#define PMIC_RG_LDO_VCN28_LP_ADDR MT6358_LDO_VCN28_CON0
#define PMIC_RG_LDO_VCN28_LP_MASK 0x1
#define PMIC_RG_LDO_VCN28_LP_SHIFT 1
#define PMIC_RG_LDO_VCN28_SW_OP_EN_ADDR MT6358_LDO_VCN28_OP_EN
#define PMIC_RG_LDO_VCN28_SW_OP_EN_MASK 0x1
#define PMIC_RG_LDO_VCN28_SW_OP_EN_SHIFT   0
#define PMIC_RG_LDO_VCN28_HW0_OP_EN_ADDR   MT6358_LDO_VCN28_OP_EN
#define PMIC_RG_LDO_VCN28_HW0_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VCN28_HW0_OP_EN_SHIFT   1
#define PMIC_RG_LDO_VCN28_HW1_OP_EN_ADDR   MT6358_LDO_VCN28_OP_EN
#define PMIC_RG_LDO_VCN28_HW1_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VCN28_HW1_OP_EN_SHIFT   2
#define PMIC_RG_LDO_VCN28_HW2_OP_EN_ADDR   MT6358_LDO_VCN28_OP_EN
#define PMIC_RG_LDO_VCN28_HW2_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VCN28_HW2_OP_EN_SHIFT   3
#define PMIC_RG_LDO_VCN28_HW3_OP_EN_ADDR   MT6358_LDO_VCN28_OP_EN
#define PMIC_RG_LDO_VCN28_HW3_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VCN28_HW3_OP_EN_SHIFT   4
#define PMIC_RG_LDO_VCN28_OP_EN_SET_ADDR   MT6358_LDO_VCN28_OP_EN_SET
#define PMIC_RG_LDO_VCN28_OP_EN_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VCN28_OP_EN_SET_SHIFT   0
#define PMIC_RG_LDO_VCN28_OP_EN_CLR_ADDR   MT6358_LDO_VCN28_OP_EN_CLR
#define PMIC_RG_LDO_VCN28_OP_EN_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VCN28_OP_EN_CLR_SHIFT   0
#define PMIC_RG_LDO_VCN28_HW0_OP_CFG_ADDR   MT6358_LDO_VCN28_OP_CFG
#define PMIC_RG_LDO_VCN28_HW0_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VCN28_HW0_OP_CFG_SHIFT  1
#define PMIC_RG_LDO_VCN28_HW1_OP_CFG_ADDR   MT6358_LDO_VCN28_OP_CFG
#define PMIC_RG_LDO_VCN28_HW1_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VCN28_HW1_OP_CFG_SHIFT  2
#define PMIC_RG_LDO_VCN28_HW2_OP_CFG_ADDR   MT6358_LDO_VCN28_OP_CFG
#define PMIC_RG_LDO_VCN28_HW2_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VCN28_HW2_OP_CFG_SHIFT  3
#define PMIC_RG_LDO_VCN28_HW3_OP_CFG_ADDR   MT6358_LDO_VCN28_OP_CFG
#define PMIC_RG_LDO_VCN28_HW3_OP_CFG_MASK   0x1
#define PMIC_RG_LDO_VCN28_HW3_OP_CFG_SHIFT  4
#define PMIC_RG_LDO_VCN28_OP_CFG_SET_ADDR   MT6358_LDO_VCN28_OP_CFG_SET
#define PMIC_RG_LDO_VCN28_OP_CFG_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VCN28_OP_CFG_SET_SHIFT  0
#define PMIC_RG_LDO_VCN28_OP_CFG_CLR_ADDR   MT6358_LDO_VCN28_OP_CFG_CLR
#define PMIC_RG_LDO_VCN28_OP_CFG_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VCN28_OP_CFG_CLR_SHIFT  0
#define PMIC_DA_VCN28_MODE_ADDR MT6358_LDO_VCN28_CON1
#define PMIC_DA_VCN28_MODE_MASK 0x1
#define PMIC_DA_VCN28_MODE_SHIFT  8
#define PMIC_RG_LDO_VCN28_STBTD_ADDR  MT6358_LDO_VCN28_CON1
#define PMIC_RG_LDO_VCN28_STBTD_MASK  0x3
#define PMIC_RG_LDO_VCN28_STBTD_SHIFT 9
#define PMIC_DA_VCN28_STB_ADDR  MT6358_LDO_VCN28_CON1
#define PMIC_DA_VCN28_STB_MASK  0x1
#define PMIC_DA_VCN28_STB_SHIFT 14
#define PMIC_DA_VCN28_EN_ADDR   MT6358_LDO_VCN28_CON1
#define PMIC_DA_VCN28_EN_MASK   0x1
#define PMIC_DA_VCN28_EN_SHIFT  15
#define PMIC_RG_LDO_VCN28_OCFB_EN_ADDR  MT6358_LDO_VCN28_CON2
#define PMIC_RG_LDO_VCN28_OCFB_EN_MASK  0x1
#define PMIC_RG_LDO_VCN28_OCFB_EN_SHIFT 9
#define PMIC_DA_VCN28_OCFB_EN_ADDR MT6358_LDO_VCN28_CON2
#define PMIC_DA_VCN28_OCFB_EN_MASK 0x1
#define PMIC_DA_VCN28_OCFB_EN_SHIFT   10
#define PMIC_RG_LDO_VCN28_DUMMY_LOAD_ADDR   MT6358_LDO_VCN28_CON3
#define PMIC_RG_LDO_VCN28_DUMMY_LOAD_MASK   0x3
#define PMIC_RG_LDO_VCN28_DUMMY_LOAD_SHIFT  5
#define PMIC_DA_VCN28_DUMMY_LOAD_ADDR MT6358_LDO_VCN28_CON3
#define PMIC_DA_VCN28_DUMMY_LOAD_MASK 0x3
#define PMIC_DA_VCN28_DUMMY_LOAD_SHIFT  14
#define PMIC_RG_VRTC28_EN_ADDR  MT6358_VRTC28_CON0
#define PMIC_RG_VRTC28_EN_MASK  0x1
#define PMIC_RG_VRTC28_EN_SHIFT 1
#define PMIC_DA_VRTC28_EN_ADDR  MT6358_VRTC28_CON0
#define PMIC_DA_VRTC28_EN_MASK  0x1
#define PMIC_DA_VRTC28_EN_SHIFT 15
#define PMIC_RG_LDO_VBIF28_EN_ADDR MT6358_LDO_VBIF28_CON0
#define PMIC_RG_LDO_VBIF28_EN_MASK 0x1
#define PMIC_RG_LDO_VBIF28_EN_SHIFT   0
#define PMIC_RG_LDO_VBIF28_LP_ADDR MT6358_LDO_VBIF28_CON0
#define PMIC_RG_LDO_VBIF28_LP_MASK 0x1
#define PMIC_RG_LDO_VBIF28_LP_SHIFT   1
#define PMIC_RG_LDO_VBIF28_SW_OP_EN_ADDR   MT6358_LDO_VBIF28_OP_EN
#define PMIC_RG_LDO_VBIF28_SW_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VBIF28_SW_OP_EN_SHIFT   0
#define PMIC_RG_LDO_VBIF28_HW0_OP_EN_ADDR   MT6358_LDO_VBIF28_OP_EN
#define PMIC_RG_LDO_VBIF28_HW0_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VBIF28_HW0_OP_EN_SHIFT  1
#define PMIC_RG_LDO_VBIF28_HW1_OP_EN_ADDR   MT6358_LDO_VBIF28_OP_EN
#define PMIC_RG_LDO_VBIF28_HW1_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VBIF28_HW1_OP_EN_SHIFT  2
#define PMIC_RG_LDO_VBIF28_HW2_OP_EN_ADDR   MT6358_LDO_VBIF28_OP_EN
#define PMIC_RG_LDO_VBIF28_HW2_OP_EN_MASK   0x1
#define PMIC_RG_LDO_VBIF28_HW2_OP_EN_SHIFT  3
#define PMIC_RG_LDO_VBIF28_OP_EN_SET_ADDR   MT6358_LDO_VBIF28_OP_EN_SET
#define PMIC_RG_LDO_VBIF28_OP_EN_SET_MASK   0xFFFF
#define PMIC_RG_LDO_VBIF28_OP_EN_SET_SHIFT  0
#define PMIC_RG_LDO_VBIF28_OP_EN_CLR_ADDR   MT6358_LDO_VBIF28_OP_EN_CLR
#define PMIC_RG_LDO_VBIF28_OP_EN_CLR_MASK   0xFFFF
#define PMIC_RG_LDO_VBIF28_OP_EN_CLR_SHIFT  0
#define PMIC_RG_LDO_VBIF28_HW0_OP_CFG_ADDR  MT6358_LDO_VBIF28_OP_CFG
#define PMIC_RG_LDO_VBIF28_HW0_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VBIF28_HW0_OP_CFG_SHIFT 1
#define PMIC_RG_LDO_VBIF28_HW1_OP_CFG_ADDR  MT6358_LDO_VBIF28_OP_CFG
#define PMIC_RG_LDO_VBIF28_HW1_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VBIF28_HW1_OP_CFG_SHIFT 2
#define PMIC_RG_LDO_VBIF28_HW2_OP_CFG_ADDR  MT6358_LDO_VBIF28_OP_CFG
#define PMIC_RG_LDO_VBIF28_HW2_OP_CFG_MASK  0x1
#define PMIC_RG_LDO_VBIF28_HW2_OP_CFG_SHIFT 3
#define PMIC_RG_LDO_VBIF28_OP_CFG_SET_ADDR  MT6358_LDO_VBIF28_OP_CFG_SET
#define PMIC_RG_LDO_VBIF28_OP_CFG_SET_MASK  0xFFFF
#define PMIC_RG_LDO_VBIF28_OP_CFG_SET_SHIFT 0
#define PMIC_RG_LDO_VBIF28_OP_CFG_CLR_ADDR  MT6358_LDO_VBIF28_OP_CFG_CLR
#define PMIC_RG_LDO_VBIF28_OP_CFG_CLR_MASK  0xFFFF
#define PMIC_RG_LDO_VBIF28_OP_CFG_CLR_SHIFT 0
#define PMIC_DA_VBIF28_MODE_ADDR  MT6358_LDO_VBIF28_CON1
#define PMIC_DA_VBIF28_MODE_MASK  0x1
#define PMIC_DA_VBIF28_MODE_SHIFT 8
#define PMIC_RG_LDO_VBIF28_STBTD_ADDR MT6358_LDO_VBIF28_CON1
#define PMIC_RG_LDO_VBIF28_STBTD_MASK 0x3
#define PMIC_RG_LDO_VBIF28_STBTD_SHIFT  9
#define PMIC_DA_VBIF28_STB_ADDR MT6358_LDO_VBIF28_CON1
#define PMIC_DA_VBIF28_STB_MASK 0x1
#define PMIC_DA_VBIF28_STB_SHIFT  14
#define PMIC_DA_VBIF28_EN_ADDR  MT6358_LDO_VBIF28_CON1
#define PMIC_DA_VBIF28_EN_MASK  0x1
#define PMIC_DA_VBIF28_EN_SHIFT 15
#define PMIC_RG_LDO_VBIF28_OCFB_EN_ADDR MT6358_LDO_VBIF28_CON2
#define PMIC_RG_LDO_VBIF28_OCFB_EN_MASK 0x1
#define PMIC_RG_LDO_VBIF28_OCFB_EN_SHIFT   9
#define PMIC_DA_VBIF28_OCFB_EN_ADDR   MT6358_LDO_VBIF28_CON2
#define PMIC_DA_VBIF28_OCFB_EN_MASK   0x1
#define PMIC_DA_VBIF28_OCFB_EN_SHIFT  10
#define PMIC_RG_LDO_VBIF28_DUMMY_LOAD_ADDR  MT6358_LDO_VBIF28_CON3
#define PMIC_RG_LDO_VBIF28_DUMMY_LOAD_MASK  0x3
#define PMIC_RG_LDO_VBIF28_DUMMY_LOAD_SHIFT 5
#define PMIC_DA_VBIF28_DUMMY_LOAD_ADDR  MT6358_LDO_VBIF28_CON3
#define PMIC_DA_VBIF28_DUMMY_LOAD_MASK  0x3
#define PMIC_DA_VBIF28_DUMMY_LOAD_SHIFT 14
#define PMIC_RG_LDO_GOFF3_RSV0_ADDR   MT6358_LDO_GOFF3_RSV_CON0
#define PMIC_RG_LDO_GOFF3_RSV0_MASK   0xF
#define PMIC_RG_LDO_GOFF3_RSV0_SHIFT  0
#define PMIC_RG_LDO_GOFF3_RSV1_ADDR   MT6358_LDO_GOFF3_RSV_CON1
#define PMIC_RG_LDO_GOFF3_RSV1_MASK   0xF
#define PMIC_RG_LDO_GOFF3_RSV1_SHIFT  0
#define PMIC_LDO_ANA0_ANA_ID_ADDR MT6358_LDO_ANA0_DSN_ID
#define PMIC_LDO_ANA0_ANA_ID_MASK 0xFF
#define PMIC_LDO_ANA0_ANA_ID_SHIFT 0
#define PMIC_LDO_ANA0_DIG_ID_ADDR MT6358_LDO_ANA0_DSN_ID
#define PMIC_LDO_ANA0_DIG_ID_MASK 0xFF
#define PMIC_LDO_ANA0_DIG_ID_SHIFT 8
#define PMIC_LDO_ANA0_ANA_MINOR_REV_ADDR   MT6358_LDO_ANA0_DSN_REV0
#define PMIC_LDO_ANA0_ANA_MINOR_REV_MASK   0xF
#define PMIC_LDO_ANA0_ANA_MINOR_REV_SHIFT   0
#define PMIC_LDO_ANA0_ANA_MAJOR_REV_ADDR   MT6358_LDO_ANA0_DSN_REV0
#define PMIC_LDO_ANA0_ANA_MAJOR_REV_MASK   0xF
#define PMIC_LDO_ANA0_ANA_MAJOR_REV_SHIFT   4
#define PMIC_LDO_ANA0_DIG_MINOR_REV_ADDR   MT6358_LDO_ANA0_DSN_REV0
#define PMIC_LDO_ANA0_DIG_MINOR_REV_MASK   0xF
#define PMIC_LDO_ANA0_DIG_MINOR_REV_SHIFT   8
#define PMIC_LDO_ANA0_DIG_MAJOR_REV_ADDR   MT6358_LDO_ANA0_DSN_REV0
#define PMIC_LDO_ANA0_DIG_MAJOR_REV_MASK   0xF
#define PMIC_LDO_ANA0_DIG_MAJOR_REV_SHIFT   12
#define PMIC_LDO_ANA0_DSN_CBS_ADDR MT6358_LDO_ANA0_DSN_DBI
#define PMIC_LDO_ANA0_DSN_CBS_MASK 0x3
#define PMIC_LDO_ANA0_DSN_CBS_SHIFT   0
#define PMIC_LDO_ANA0_DSN_BIX_ADDR MT6358_LDO_ANA0_DSN_DBI
#define PMIC_LDO_ANA0_DSN_BIX_MASK 0x3
#define PMIC_LDO_ANA0_DSN_BIX_SHIFT   2
#define PMIC_LDO_ANA0_DSN_ESP_ADDR MT6358_LDO_ANA0_DSN_DBI
#define PMIC_LDO_ANA0_DSN_ESP_MASK 0xFF
#define PMIC_LDO_ANA0_DSN_ESP_SHIFT   8
#define PMIC_LDO_ANA0_DSN_FPI_ADDR MT6358_LDO_ANA0_DSN_FPI
#define PMIC_LDO_ANA0_DSN_FPI_MASK 0xFF
#define PMIC_LDO_ANA0_DSN_FPI_SHIFT   0
#define PMIC_RG_VCAMA1_VOCAL_ADDR MT6358_VCAMA1_ANA_CON0
#define PMIC_RG_VCAMA1_VOCAL_MASK 0xF
#define PMIC_RG_VCAMA1_VOCAL_SHIFT 0
#define PMIC_RG_VCAMA1_VOSEL_ADDR MT6358_VCAMA1_ANA_CON0
#define PMIC_RG_VCAMA1_VOSEL_MASK 0xF
#define PMIC_RG_VCAMA1_VOSEL_SHIFT 8
#define PMIC_RG_VCAMA1_NDIS_EN_ADDR   MT6358_VCAMA1_ANA_CON1
#define PMIC_RG_VCAMA1_NDIS_EN_MASK   0x1
#define PMIC_RG_VCAMA1_NDIS_EN_SHIFT  0
#define PMIC_RG_VCAMA1_RSV_ADDR MT6358_VCAMA1_ANA_CON1
#define PMIC_RG_VCAMA1_RSV_MASK 0x3
#define PMIC_RG_VCAMA1_RSV_SHIFT  2
#define PMIC_RG_VCAMA2_VOCAL_ADDR MT6358_VCAMA2_ANA_CON0
#define PMIC_RG_VCAMA2_VOCAL_MASK 0xF
#define PMIC_RG_VCAMA2_VOCAL_SHIFT 0
#define PMIC_RG_VCAMA2_VOSEL_ADDR MT6358_VCAMA2_ANA_CON0
#define PMIC_RG_VCAMA2_VOSEL_MASK 0xF
#define PMIC_RG_VCAMA2_VOSEL_SHIFT 8
#define PMIC_RG_VCAMA2_NDIS_EN_ADDR   MT6358_VCAMA2_ANA_CON1
#define PMIC_RG_VCAMA2_NDIS_EN_MASK   0x1
#define PMIC_RG_VCAMA2_NDIS_EN_SHIFT  0
#define PMIC_RG_VCAMA2_RSV_ADDR MT6358_VCAMA2_ANA_CON1
#define PMIC_RG_VCAMA2_RSV_MASK 0x3
#define PMIC_RG_VCAMA2_RSV_SHIFT  2
#define PMIC_RG_VFE28_VOCAL_ADDR  MT6358_VFE28_ANA_CON0
#define PMIC_RG_VFE28_VOCAL_MASK  0xF
#define PMIC_RG_VFE28_VOCAL_SHIFT 0
#define PMIC_RG_VFE28_NDIS_EN_ADDR MT6358_VFE28_ANA_CON1
#define PMIC_RG_VFE28_NDIS_EN_MASK 0x1
#define PMIC_RG_VFE28_NDIS_EN_SHIFT   0
#define PMIC_RG_VFE28_RSV_ADDR  MT6358_VFE28_ANA_CON1
#define PMIC_RG_VFE28_RSV_MASK  0x3
#define PMIC_RG_VFE28_RSV_SHIFT 2
#define PMIC_RG_VCN28_VOCAL_ADDR  MT6358_VCN28_ANA_CON0
#define PMIC_RG_VCN28_VOCAL_MASK  0xF
#define PMIC_RG_VCN28_VOCAL_SHIFT 0
#define PMIC_RG_VCN28_NDIS_EN_ADDR MT6358_VCN28_ANA_CON1
#define PMIC_RG_VCN28_NDIS_EN_MASK 0x1
#define PMIC_RG_VCN28_NDIS_EN_SHIFT   0
#define PMIC_RG_VCN28_RSV_ADDR  MT6358_VCN28_ANA_CON1
#define PMIC_RG_VCN28_RSV_MASK  0x3
#define PMIC_RG_VCN28_RSV_SHIFT 2
#define PMIC_RG_VBIF28_VOCAL_ADDR MT6358_VBIF28_ANA_CON0
#define PMIC_RG_VBIF28_VOCAL_MASK 0xF
#define PMIC_RG_VBIF28_VOCAL_SHIFT 0
#define PMIC_RG_VBIF28_NDIS_EN_ADDR   MT6358_VBIF28_ANA_CON1
#define PMIC_RG_VBIF28_NDIS_EN_MASK   0x1
#define PMIC_RG_VBIF28_NDIS_EN_SHIFT  0
#define PMIC_RG_VBIF28_RSV_ADDR MT6358_VBIF28_ANA_CON1
#define PMIC_RG_VBIF28_RSV_MASK 0x3
#define PMIC_RG_VBIF28_RSV_SHIFT  2
#define PMIC_RG_VAUD28_VOCAL_ADDR MT6358_VAUD28_ANA_CON0
#define PMIC_RG_VAUD28_VOCAL_MASK 0xF
#define PMIC_RG_VAUD28_VOCAL_SHIFT 0
#define PMIC_RG_VAUD28_NDIS_EN_ADDR   MT6358_VAUD28_ANA_CON1
#define PMIC_RG_VAUD28_NDIS_EN_MASK   0x1
#define PMIC_RG_VAUD28_NDIS_EN_SHIFT  0
#define PMIC_RG_VAUD28_RSV_ADDR MT6358_VAUD28_ANA_CON1
#define PMIC_RG_VAUD28_RSV_MASK 0x3
#define PMIC_RG_VAUD28_RSV_SHIFT  2
#define PMIC_RG_VAUX18_VOCAL_ADDR MT6358_VAUX18_ANA_CON0
#define PMIC_RG_VAUX18_VOCAL_MASK 0xF
#define PMIC_RG_VAUX18_VOCAL_SHIFT 0
#define PMIC_RG_VAUX18_NDIS_EN_ADDR   MT6358_VAUX18_ANA_CON1
#define PMIC_RG_VAUX18_NDIS_EN_MASK   0x1
#define PMIC_RG_VAUX18_NDIS_EN_SHIFT  0
#define PMIC_RG_VAUX18_RSV_ADDR MT6358_VAUX18_ANA_CON1
#define PMIC_RG_VAUX18_RSV_MASK 0x3
#define PMIC_RG_VAUX18_RSV_SHIFT  2
#define PMIC_RG_VXO22_VOCAL_ADDR  MT6358_VXO22_ANA_CON0
#define PMIC_RG_VXO22_VOCAL_MASK  0xF
#define PMIC_RG_VXO22_VOCAL_SHIFT 0
#define PMIC_RG_VXO22_VOSEL_ADDR  MT6358_VXO22_ANA_CON0
#define PMIC_RG_VXO22_VOSEL_MASK  0x1
#define PMIC_RG_VXO22_VOSEL_SHIFT 8
#define PMIC_RG_VXO22_NDIS_EN_ADDR MT6358_VXO22_ANA_CON1
#define PMIC_RG_VXO22_NDIS_EN_MASK 0x1
#define PMIC_RG_VXO22_NDIS_EN_SHIFT   0
#define PMIC_RG_VXO22_RSV_ADDR  MT6358_VXO22_ANA_CON1
#define PMIC_RG_VXO22_RSV_MASK  0x3
#define PMIC_RG_VXO22_RSV_SHIFT 2
#define PMIC_RG_VCN33_VOCAL_ADDR  MT6358_VCN33_ANA_CON0
#define PMIC_RG_VCN33_VOCAL_MASK  0xF
#define PMIC_RG_VCN33_VOCAL_SHIFT 0
#define PMIC_RG_VCN33_VOSEL_ADDR  MT6358_VCN33_ANA_CON0
#define PMIC_RG_VCN33_VOSEL_MASK  0x3
#define PMIC_RG_VCN33_VOSEL_SHIFT 8
#define PMIC_RG_VCN33_NDIS_EN_ADDR MT6358_VCN33_ANA_CON1
#define PMIC_RG_VCN33_NDIS_EN_MASK 0x1
#define PMIC_RG_VCN33_NDIS_EN_SHIFT   0
#define PMIC_RG_VCN33_RSV_ADDR  MT6358_VCN33_ANA_CON1
#define PMIC_RG_VCN33_RSV_MASK  0x3
#define PMIC_RG_VCN33_RSV_SHIFT 2
#define PMIC_RG_VSIM1_VOCAL_ADDR  MT6358_VSIM1_ANA_CON0
#define PMIC_RG_VSIM1_VOCAL_MASK  0xF
#define PMIC_RG_VSIM1_VOCAL_SHIFT 0
#define PMIC_RG_VSIM1_VOSEL_ADDR  MT6358_VSIM1_ANA_CON0
#define PMIC_RG_VSIM1_VOSEL_MASK  0xF
#define PMIC_RG_VSIM1_VOSEL_SHIFT 8
#define PMIC_RG_VSIM1_NDIS_EN_ADDR MT6358_VSIM1_ANA_CON1
#define PMIC_RG_VSIM1_NDIS_EN_MASK 0x1
#define PMIC_RG_VSIM1_NDIS_EN_SHIFT   0
#define PMIC_RG_VSIM1_RSV_ADDR  MT6358_VSIM1_ANA_CON1
#define PMIC_RG_VSIM1_RSV_MASK  0x3
#define PMIC_RG_VSIM1_RSV_SHIFT 2
#define PMIC_RG_VSIM2_VOCAL_ADDR  MT6358_VSIM2_ANA_CON0
#define PMIC_RG_VSIM2_VOCAL_MASK  0xF
#define PMIC_RG_VSIM2_VOCAL_SHIFT 0
#define PMIC_RG_VSIM2_VOSEL_ADDR  MT6358_VSIM2_ANA_CON0
#define PMIC_RG_VSIM2_VOSEL_MASK  0xF
#define PMIC_RG_VSIM2_VOSEL_SHIFT 8
#define PMIC_RG_VSIM2_NDIS_EN_ADDR MT6358_VSIM2_ANA_CON1
#define PMIC_RG_VSIM2_NDIS_EN_MASK 0x1
#define PMIC_RG_VSIM2_NDIS_EN_SHIFT   0
#define PMIC_RG_VSIM2_RSV_ADDR  MT6358_VSIM2_ANA_CON1
#define PMIC_RG_VSIM2_RSV_MASK  0x3
#define PMIC_RG_VSIM2_RSV_SHIFT 2
#define PMIC_RG_VUSB_VOCAL_ADDR MT6358_VUSB_ANA_CON0
#define PMIC_RG_VUSB_VOCAL_MASK 0xF
#define PMIC_RG_VUSB_VOCAL_SHIFT  0
#define PMIC_RG_VUSB_VOSEL_ADDR MT6358_VUSB_ANA_CON0
#define PMIC_RG_VUSB_VOSEL_MASK 0x7
#define PMIC_RG_VUSB_VOSEL_SHIFT  8
#define PMIC_RG_VUSB_NDIS_EN_ADDR MT6358_VUSB_ANA_CON1
#define PMIC_RG_VUSB_NDIS_EN_MASK 0x1
#define PMIC_RG_VUSB_NDIS_EN_SHIFT 0
#define PMIC_RG_VUSB_RSV_ADDR   MT6358_VUSB_ANA_CON1
#define PMIC_RG_VUSB_RSV_MASK   0x3
#define PMIC_RG_VUSB_RSV_SHIFT  2
#define PMIC_RG_VEMC_VOCAL_ADDR MT6358_VEMC_ANA_CON0
#define PMIC_RG_VEMC_VOCAL_MASK 0xF
#define PMIC_RG_VEMC_VOCAL_SHIFT  0
#define PMIC_RG_VEMC_VOSEL_ADDR MT6358_VEMC_ANA_CON0
#define PMIC_RG_VEMC_VOSEL_MASK 0x7
#define PMIC_RG_VEMC_VOSEL_SHIFT  8
#define PMIC_RG_VEMC_NDIS_EN_ADDR MT6358_VEMC_ANA_CON1
#define PMIC_RG_VEMC_NDIS_EN_MASK 0x1
#define PMIC_RG_VEMC_NDIS_EN_SHIFT 0
#define PMIC_RG_VEMC_RSV_ADDR   MT6358_VEMC_ANA_CON1
#define PMIC_RG_VEMC_RSV_MASK   0x3
#define PMIC_RG_VEMC_RSV_SHIFT  2
#define PMIC_RG_VLDO28_VOCAL_ADDR MT6358_VLDO28_ANA_CON0
#define PMIC_RG_VLDO28_VOCAL_MASK 0xF
#define PMIC_RG_VLDO28_VOCAL_SHIFT 0
#define PMIC_RG_VLDO28_VOSEL_ADDR MT6358_VLDO28_ANA_CON0
#define PMIC_RG_VLDO28_VOSEL_MASK 0x3
#define PMIC_RG_VLDO28_VOSEL_SHIFT 8
#define PMIC_RG_VLDO28_NDIS_EN_ADDR   MT6358_VLDO28_ANA_CON1
#define PMIC_RG_VLDO28_NDIS_EN_MASK   0x1
#define PMIC_RG_VLDO28_NDIS_EN_SHIFT  0
#define PMIC_RG_VLDO28_RSV_ADDR MT6358_VLDO28_ANA_CON1
#define PMIC_RG_VLDO28_RSV_MASK 0x3
#define PMIC_RG_VLDO28_RSV_SHIFT  2
#define PMIC_RG_VIO28_VOCAL_ADDR  MT6358_VIO28_ANA_CON0
#define PMIC_RG_VIO28_VOCAL_MASK  0xF
#define PMIC_RG_VIO28_VOCAL_SHIFT 0
#define PMIC_RG_VIO28_NDIS_EN_ADDR MT6358_VIO28_ANA_CON1
#define PMIC_RG_VIO28_NDIS_EN_MASK 0x1
#define PMIC_RG_VIO28_NDIS_EN_SHIFT   0
#define PMIC_RG_VIO28_RSV_ADDR  MT6358_VIO28_ANA_CON1
#define PMIC_RG_VIO28_RSV_MASK  0x3
#define PMIC_RG_VIO28_RSV_SHIFT 2
#define PMIC_RG_VIBR_VOCAL_ADDR MT6358_VIBR_ANA_CON0
#define PMIC_RG_VIBR_VOCAL_MASK 0xF
#define PMIC_RG_VIBR_VOCAL_SHIFT  0
#define PMIC_RG_VIBR_VOSEL_ADDR MT6358_VIBR_ANA_CON0
#define PMIC_RG_VIBR_VOSEL_MASK 0xF
#define PMIC_RG_VIBR_VOSEL_SHIFT  8
#define PMIC_RG_VIBR_NDIS_EN_ADDR MT6358_VIBR_ANA_CON1
#define PMIC_RG_VIBR_NDIS_EN_MASK 0x1
#define PMIC_RG_VIBR_NDIS_EN_SHIFT 0
#define PMIC_RG_VIBR_RSV_ADDR   MT6358_VIBR_ANA_CON1
#define PMIC_RG_VIBR_RSV_MASK   0x3
#define PMIC_RG_VIBR_RSV_SHIFT  2
#define PMIC_RG_VMCH_VOCAL_ADDR MT6358_VMCH_ANA_CON0
#define PMIC_RG_VMCH_VOCAL_MASK 0xF
#define PMIC_RG_VMCH_VOCAL_SHIFT  0
#define PMIC_RG_VMCH_VOSEL_ADDR MT6358_VMCH_ANA_CON0
#define PMIC_RG_VMCH_VOSEL_MASK 0x7
#define PMIC_RG_VMCH_VOSEL_SHIFT  8
#define PMIC_RG_VMCH_NDIS_EN_ADDR MT6358_VMCH_ANA_CON1
#define PMIC_RG_VMCH_NDIS_EN_MASK 0x1
#define PMIC_RG_VMCH_NDIS_EN_SHIFT 0
#define PMIC_RG_VMCH_STB_SEL_ADDR MT6358_VMCH_ANA_CON1
#define PMIC_RG_VMCH_STB_SEL_MASK 0x1
#define PMIC_RG_VMCH_STB_SEL_SHIFT 1
#define PMIC_RG_VMCH_RSV_ADDR   MT6358_VMCH_ANA_CON1
#define PMIC_RG_VMCH_RSV_MASK   0x3
#define PMIC_RG_VMCH_RSV_SHIFT  2
#define PMIC_RG_VMC_VOCAL_ADDR  MT6358_VMC_ANA_CON0
#define PMIC_RG_VMC_VOCAL_MASK  0xF
#define PMIC_RG_VMC_VOCAL_SHIFT 0
#define PMIC_RG_VMC_VOSEL_ADDR  MT6358_VMC_ANA_CON0
#define PMIC_RG_VMC_VOSEL_MASK  0xF
#define PMIC_RG_VMC_VOSEL_SHIFT 8
#define PMIC_RG_VMC_NDIS_EN_ADDR  MT6358_VMC_ANA_CON1
#define PMIC_RG_VMC_NDIS_EN_MASK  0x1
#define PMIC_RG_VMC_NDIS_EN_SHIFT 0
#define PMIC_RG_VMC_STB_SEL_ADDR  MT6358_VMC_ANA_CON1
#define PMIC_RG_VMC_STB_SEL_MASK  0x1
#define PMIC_RG_VMC_STB_SEL_SHIFT 1
#define PMIC_RG_VMC_RSV_ADDR MT6358_VMC_ANA_CON1
#define PMIC_RG_VMC_RSV_MASK 0x3
#define PMIC_RG_VMC_RSV_SHIFT   2
#define PMIC_LDO_ANA0_ELR_LEN_ADDR MT6358_LDO_ANA0_ELR_NUM
#define PMIC_LDO_ANA0_ELR_LEN_MASK 0xFF
#define PMIC_LDO_ANA0_ELR_LEN_SHIFT   0
#define PMIC_RG_VCAMA1_VOTRIM_ADDR MT6358_VCAMA1_ELR_0
#define PMIC_RG_VCAMA1_VOTRIM_MASK 0xF
#define PMIC_RG_VCAMA1_VOTRIM_SHIFT   0
#define PMIC_RG_VCAMA2_VOTRIM_ADDR MT6358_VCAMA2_ELR_0
#define PMIC_RG_VCAMA2_VOTRIM_MASK 0xF
#define PMIC_RG_VCAMA2_VOTRIM_SHIFT   0
#define PMIC_RG_VFE28_VOTRIM_ADDR MT6358_VFE28_ELR_0
#define PMIC_RG_VFE28_VOTRIM_MASK 0xF
#define PMIC_RG_VFE28_VOTRIM_SHIFT 0
#define PMIC_RG_VCN28_VOTRIM_ADDR MT6358_VCN28_ELR_0
#define PMIC_RG_VCN28_VOTRIM_MASK 0xF
#define PMIC_RG_VCN28_VOTRIM_SHIFT 0
#define PMIC_RG_VBIF28_VOTRIM_ADDR MT6358_VBIF28_ELR_0
#define PMIC_RG_VBIF28_VOTRIM_MASK 0xF
#define PMIC_RG_VBIF28_VOTRIM_SHIFT   0
#define PMIC_RG_VAUD28_VOTRIM_ADDR MT6358_VAUD28_ELR_0
#define PMIC_RG_VAUD28_VOTRIM_MASK 0xF
#define PMIC_RG_VAUD28_VOTRIM_SHIFT   0
#define PMIC_RG_VAUX18_VOTRIM_ADDR MT6358_VAUX18_ELR_0
#define PMIC_RG_VAUX18_VOTRIM_MASK 0xF
#define PMIC_RG_VAUX18_VOTRIM_SHIFT   0
#define PMIC_RG_VXO22_VOTRIM_ADDR MT6358_VXO22_ELR_0
#define PMIC_RG_VXO22_VOTRIM_MASK 0xF
#define PMIC_RG_VXO22_VOTRIM_SHIFT 0
#define PMIC_RG_VCN33_VOTRIM_ADDR MT6358_VCN33_ELR_0
#define PMIC_RG_VCN33_VOTRIM_MASK 0xF
#define PMIC_RG_VCN33_VOTRIM_SHIFT 0
#define PMIC_RG_VCN33_OC_TRIM_ADDR MT6358_VCN33_ELR_0
#define PMIC_RG_VCN33_OC_TRIM_MASK 0x7
#define PMIC_RG_VCN33_OC_TRIM_SHIFT   4
#define PMIC_RG_VSIM1_VOTRIM_ADDR MT6358_VSIM1_ELR_0
#define PMIC_RG_VSIM1_VOTRIM_MASK 0xF
#define PMIC_RG_VSIM1_VOTRIM_SHIFT 0
#define PMIC_RG_VSIM2_VOTRIM_ADDR MT6358_VSIM2_ELR_0
#define PMIC_RG_VSIM2_VOTRIM_MASK 0xF
#define PMIC_RG_VSIM2_VOTRIM_SHIFT 0
#define PMIC_RG_VUSB_VOTRIM_ADDR  MT6358_VUSB_ELR_0
#define PMIC_RG_VUSB_VOTRIM_MASK  0xF
#define PMIC_RG_VUSB_VOTRIM_SHIFT 0
#define PMIC_RG_VEMC_VOTRIM_ADDR  MT6358_VEMC_ELR_0
#define PMIC_RG_VEMC_VOTRIM_MASK  0xF
#define PMIC_RG_VEMC_VOTRIM_SHIFT 0
#define PMIC_RG_VEMC_OC_TRIM_ADDR MT6358_VEMC_ELR_0
#define PMIC_RG_VEMC_OC_TRIM_MASK 0x7
#define PMIC_RG_VEMC_OC_TRIM_SHIFT 4
#define PMIC_RG_VLDO28_VOTRIM_ADDR MT6358_VLDO28_ELR_0
#define PMIC_RG_VLDO28_VOTRIM_MASK 0xF
#define PMIC_RG_VLDO28_VOTRIM_SHIFT   0
#define PMIC_RG_VIO28_VOTRIM_ADDR MT6358_VIO28_ELR_0
#define PMIC_RG_VIO28_VOTRIM_MASK 0xF
#define PMIC_RG_VIO28_VOTRIM_SHIFT 0
#define PMIC_RG_VIBR_VOTRIM_ADDR  MT6358_VIBR_ELR_0
#define PMIC_RG_VIBR_VOTRIM_MASK  0xF
#define PMIC_RG_VIBR_VOTRIM_SHIFT 0
#define PMIC_RG_VMCH_VOTRIM_ADDR  MT6358_VMCH_ELR_0
#define PMIC_RG_VMCH_VOTRIM_MASK  0xF
#define PMIC_RG_VMCH_VOTRIM_SHIFT 0
#define PMIC_RG_VMCH_OC_TRIM_ADDR MT6358_VMCH_ELR_0
#define PMIC_RG_VMCH_OC_TRIM_MASK 0x7
#define PMIC_RG_VMCH_OC_TRIM_SHIFT 4
#define PMIC_RG_VMC_VOTRIM_ADDR MT6358_VMC_ELR_0
#define PMIC_RG_VMC_VOTRIM_MASK 0xF
#define PMIC_RG_VMC_VOTRIM_SHIFT  0
#define PMIC_LDO_ANA1_ANA_ID_ADDR MT6358_LDO_ANA1_DSN_ID
#define PMIC_LDO_ANA1_ANA_ID_MASK 0xFF
#define PMIC_LDO_ANA1_ANA_ID_SHIFT 0
#define PMIC_LDO_ANA1_DIG_ID_ADDR MT6358_LDO_ANA1_DSN_ID
#define PMIC_LDO_ANA1_DIG_ID_MASK 0xFF
#define PMIC_LDO_ANA1_DIG_ID_SHIFT 8
#define PMIC_LDO_ANA1_ANA_MINOR_REV_ADDR   MT6358_LDO_ANA1_DSN_REV0
#define PMIC_LDO_ANA1_ANA_MINOR_REV_MASK   0xF
#define PMIC_LDO_ANA1_ANA_MINOR_REV_SHIFT   0
#define PMIC_LDO_ANA1_ANA_MAJOR_REV_ADDR   MT6358_LDO_ANA1_DSN_REV0
#define PMIC_LDO_ANA1_ANA_MAJOR_REV_MASK   0xF
#define PMIC_LDO_ANA1_ANA_MAJOR_REV_SHIFT   4
#define PMIC_LDO_ANA1_DIG_MINOR_REV_ADDR   MT6358_LDO_ANA1_DSN_REV0
#define PMIC_LDO_ANA1_DIG_MINOR_REV_MASK   0xF
#define PMIC_LDO_ANA1_DIG_MINOR_REV_SHIFT   8
#define PMIC_LDO_ANA1_DIG_MAJOR_REV_ADDR   MT6358_LDO_ANA1_DSN_REV0
#define PMIC_LDO_ANA1_DIG_MAJOR_REV_MASK   0xF
#define PMIC_LDO_ANA1_DIG_MAJOR_REV_SHIFT   12
#define PMIC_LDO_ANA1_DSN_CBS_ADDR MT6358_LDO_ANA1_DSN_DBI
#define PMIC_LDO_ANA1_DSN_CBS_MASK 0x3
#define PMIC_LDO_ANA1_DSN_CBS_SHIFT   0
#define PMIC_LDO_ANA1_DSN_BIX_ADDR MT6358_LDO_ANA1_DSN_DBI
#define PMIC_LDO_ANA1_DSN_BIX_MASK 0x3
#define PMIC_LDO_ANA1_DSN_BIX_SHIFT   2
#define PMIC_LDO_ANA1_DSN_ESP_ADDR MT6358_LDO_ANA1_DSN_DBI
#define PMIC_LDO_ANA1_DSN_ESP_MASK 0xFF
#define PMIC_LDO_ANA1_DSN_ESP_SHIFT   8
#define PMIC_LDO_ANA1_DSN_FPI_ADDR MT6358_LDO_ANA1_DSN_FPI
#define PMIC_LDO_ANA1_DSN_FPI_MASK 0xFF
#define PMIC_LDO_ANA1_DSN_FPI_SHIFT   0
#define PMIC_RG_VRF18_VOCAL_ADDR  MT6358_VRF18_ANA_CON0
#define PMIC_RG_VRF18_VOCAL_MASK  0xF
#define PMIC_RG_VRF18_VOCAL_SHIFT 0
#define PMIC_RG_VRF18_NDIS_EN_ADDR MT6358_VRF18_ANA_CON1
#define PMIC_RG_VRF18_NDIS_EN_MASK 0x1
#define PMIC_RG_VRF18_NDIS_EN_SHIFT   0
#define PMIC_RG_VRF18_RSV_ADDR  MT6358_VRF18_ANA_CON1
#define PMIC_RG_VRF18_RSV_MASK  0x3
#define PMIC_RG_VRF18_RSV_SHIFT 2
#define PMIC_RG_VCN18_VOCAL_ADDR  MT6358_VCN18_ANA_CON0
#define PMIC_RG_VCN18_VOCAL_MASK  0xF
#define PMIC_RG_VCN18_VOCAL_SHIFT 0
#define PMIC_RG_VCN18_NDIS_EN_ADDR MT6358_VCN18_ANA_CON1
#define PMIC_RG_VCN18_NDIS_EN_MASK 0x1
#define PMIC_RG_VCN18_NDIS_EN_SHIFT   0
#define PMIC_RG_VCN18_RSV_ADDR  MT6358_VCN18_ANA_CON1
#define PMIC_RG_VCN18_RSV_MASK  0x3
#define PMIC_RG_VCN18_RSV_SHIFT 2
#define PMIC_RG_VCAMIO_VOCAL_ADDR MT6358_VCAMIO_ANA_CON0
#define PMIC_RG_VCAMIO_VOCAL_MASK 0xF
#define PMIC_RG_VCAMIO_VOCAL_SHIFT 0
#define PMIC_RG_VCAMIO_NDIS_EN_ADDR   MT6358_VCAMIO_ANA_CON1
#define PMIC_RG_VCAMIO_NDIS_EN_MASK   0x1
#define PMIC_RG_VCAMIO_NDIS_EN_SHIFT  0
#define PMIC_RG_VCAMIO_RSV_ADDR MT6358_VCAMIO_ANA_CON1
#define PMIC_RG_VCAMIO_RSV_MASK 0x3
#define PMIC_RG_VCAMIO_RSV_SHIFT  2
#define PMIC_RG_VIO18_VOCAL_ADDR  MT6358_VIO18_ANA_CON0
#define PMIC_RG_VIO18_VOCAL_MASK  0xF
#define PMIC_RG_VIO18_VOCAL_SHIFT 0
#define PMIC_RG_VIO18_NDIS_EN_ADDR MT6358_VIO18_ANA_CON1
#define PMIC_RG_VIO18_NDIS_EN_MASK 0x1
#define PMIC_RG_VIO18_NDIS_EN_SHIFT   0
#define PMIC_RG_VIO18_RSV_ADDR  MT6358_VIO18_ANA_CON1
#define PMIC_RG_VIO18_RSV_MASK  0x3
#define PMIC_RG_VIO18_RSV_SHIFT 2
#define PMIC_RG_VEFUSE_VOCAL_ADDR MT6358_VEFUSE_ANA_CON0
#define PMIC_RG_VEFUSE_VOCAL_MASK 0xF
#define PMIC_RG_VEFUSE_VOCAL_SHIFT 0
#define PMIC_RG_VEFUSE_VOSEL_ADDR MT6358_VEFUSE_ANA_CON0
#define PMIC_RG_VEFUSE_VOSEL_MASK 0xF
#define PMIC_RG_VEFUSE_VOSEL_SHIFT 8
#define PMIC_RG_VEFUSE_NDIS_EN_ADDR   MT6358_VEFUSE_ANA_CON1
#define PMIC_RG_VEFUSE_NDIS_EN_MASK   0x1
#define PMIC_RG_VEFUSE_NDIS_EN_SHIFT  0
#define PMIC_RG_VEFUSE_RSV_ADDR MT6358_VEFUSE_ANA_CON1
#define PMIC_RG_VEFUSE_RSV_MASK 0x3
#define PMIC_RG_VEFUSE_RSV_SHIFT  2
#define PMIC_RG_VRF12_VOCAL_ADDR  MT6358_VRF12_ANA_CON0
#define PMIC_RG_VRF12_VOCAL_MASK  0xF
#define PMIC_RG_VRF12_VOCAL_SHIFT 0
#define PMIC_RG_VRF12_NDIS_EN_ADDR MT6358_VRF12_ANA_CON1
#define PMIC_RG_VRF12_NDIS_EN_MASK 0x1
#define PMIC_RG_VRF12_NDIS_EN_SHIFT   11
#define PMIC_RG_VRF12_RSV_ADDR  MT6358_VRF12_ANA_CON1
#define PMIC_RG_VRF12_RSV_MASK  0x3
#define PMIC_RG_VRF12_RSV_SHIFT 13
#define PMIC_RG_VSRAM_PROC11_STB_SEL_ADDR   MT6358_VSRAM_PROC11_ANA_CON0
#define PMIC_RG_VSRAM_PROC11_STB_SEL_MASK   0x1
#define PMIC_RG_VSRAM_PROC11_STB_SEL_SHIFT  4
#define PMIC_RG_VSRAM_PROC11_NDIS_EN_ADDR   MT6358_VSRAM_PROC11_ANA_CON0
#define PMIC_RG_VSRAM_PROC11_NDIS_EN_MASK   0x1
#define PMIC_RG_VSRAM_PROC11_NDIS_EN_SHIFT  5
#define PMIC_RG_VSRAM_PROC11_NDIS_PLCUR_ADDR  MT6358_VSRAM_PROC11_ANA_CON0
#define PMIC_RG_VSRAM_PROC11_NDIS_PLCUR_MASK  0x3
#define PMIC_RG_VSRAM_PROC11_NDIS_PLCUR_SHIFT 6
#define PMIC_RG_VSRAM_PROC11_PLCUR_EN_ADDR  MT6358_VSRAM_PROC11_ANA_CON0
#define PMIC_RG_VSRAM_PROC11_PLCUR_EN_MASK  0x1
#define PMIC_RG_VSRAM_PROC11_PLCUR_EN_SHIFT 8
#define PMIC_RG_VSRAM_PROC11_LPOC_EN_ADDR   MT6358_VSRAM_PROC11_ANA_CON0
#define PMIC_RG_VSRAM_PROC11_LPOC_EN_MASK   0x1
#define PMIC_RG_VSRAM_PROC11_LPOC_EN_SHIFT  9
#define PMIC_RG_VSRAM_PROC11_RSV_H_ADDR MT6358_VSRAM_PROC11_ANA_CON1
#define PMIC_RG_VSRAM_PROC11_RSV_H_MASK 0x1F
#define PMIC_RG_VSRAM_PROC11_RSV_H_SHIFT   0
#define PMIC_RG_VSRAM_PROC11_RSV_L_ADDR MT6358_VSRAM_PROC11_ANA_CON1
#define PMIC_RG_VSRAM_PROC11_RSV_L_MASK 0x1F
#define PMIC_RG_VSRAM_PROC11_RSV_L_SHIFT   5
#define PMIC_RG_VSRAM_PROC11_AUTO_TRACK_ADDR  MT6358_VSRAM_PROC11_ANA_CON1
#define PMIC_RG_VSRAM_PROC11_AUTO_TRACK_MASK  0x1
#define PMIC_RG_VSRAM_PROC11_AUTO_TRACK_SHIFT 10
#define PMIC_RG_VSRAM_PROC12_STB_SEL_ADDR   MT6358_VSRAM_PROC12_ANA_CON0
#define PMIC_RG_VSRAM_PROC12_STB_SEL_MASK   0x1
#define PMIC_RG_VSRAM_PROC12_STB_SEL_SHIFT  4
#define PMIC_RG_VSRAM_PROC12_NDIS_EN_ADDR   MT6358_VSRAM_PROC12_ANA_CON0
#define PMIC_RG_VSRAM_PROC12_NDIS_EN_MASK   0x1
#define PMIC_RG_VSRAM_PROC12_NDIS_EN_SHIFT  5
#define PMIC_RG_VSRAM_PROC12_NDIS_PLCUR_ADDR  MT6358_VSRAM_PROC12_ANA_CON0
#define PMIC_RG_VSRAM_PROC12_NDIS_PLCUR_MASK  0x3
#define PMIC_RG_VSRAM_PROC12_NDIS_PLCUR_SHIFT 6
#define PMIC_RG_VSRAM_PROC12_PLCUR_EN_ADDR  MT6358_VSRAM_PROC12_ANA_CON0
#define PMIC_RG_VSRAM_PROC12_PLCUR_EN_MASK  0x1
#define PMIC_RG_VSRAM_PROC12_PLCUR_EN_SHIFT 8
#define PMIC_RG_VSRAM_PROC12_LPOC_EN_ADDR   MT6358_VSRAM_PROC12_ANA_CON0
#define PMIC_RG_VSRAM_PROC12_LPOC_EN_MASK   0x1
#define PMIC_RG_VSRAM_PROC12_LPOC_EN_SHIFT  9
#define PMIC_RG_VSRAM_PROC12_RSV_H_ADDR MT6358_VSRAM_PROC12_ANA_CON0
#define PMIC_RG_VSRAM_PROC12_RSV_H_MASK 0x7
#define PMIC_RG_VSRAM_PROC12_RSV_H_SHIFT   10
#define PMIC_RG_VSRAM_PROC12_RSV_L_ADDR MT6358_VSRAM_PROC12_ANA_CON0
#define PMIC_RG_VSRAM_PROC12_RSV_L_MASK 0x7
#define PMIC_RG_VSRAM_PROC12_RSV_L_SHIFT   13
#define PMIC_RG_VSRAM_OTHERS_STB_SEL_ADDR   MT6358_VSRAM_OTHERS_ANA_CON0
#define PMIC_RG_VSRAM_OTHERS_STB_SEL_MASK   0x1
#define PMIC_RG_VSRAM_OTHERS_STB_SEL_SHIFT  4
#define PMIC_RG_VSRAM_OTHERS_NDIS_EN_ADDR   MT6358_VSRAM_OTHERS_ANA_CON0
#define PMIC_RG_VSRAM_OTHERS_NDIS_EN_MASK   0x1
#define PMIC_RG_VSRAM_OTHERS_NDIS_EN_SHIFT  5
#define PMIC_RG_VSRAM_OTHERS_NDIS_PLCUR_ADDR  MT6358_VSRAM_OTHERS_ANA_CON0
#define PMIC_RG_VSRAM_OTHERS_NDIS_PLCUR_MASK  0x3
#define PMIC_RG_VSRAM_OTHERS_NDIS_PLCUR_SHIFT 6
#define PMIC_RG_VSRAM_OTHERS_PLCUR_EN_ADDR  MT6358_VSRAM_OTHERS_ANA_CON0
#define PMIC_RG_VSRAM_OTHERS_PLCUR_EN_MASK  0x1
#define PMIC_RG_VSRAM_OTHERS_PLCUR_EN_SHIFT 8
#define PMIC_RG_VSRAM_OTHERS_LPOC_EN_ADDR   MT6358_VSRAM_OTHERS_ANA_CON0
#define PMIC_RG_VSRAM_OTHERS_LPOC_EN_MASK   0x1
#define PMIC_RG_VSRAM_OTHERS_LPOC_EN_SHIFT  9
#define PMIC_RG_VSRAM_OTHERS_RSV_H_ADDR MT6358_VSRAM_OTHERS_ANA_CON0
#define PMIC_RG_VSRAM_OTHERS_RSV_H_MASK 0x7
#define PMIC_RG_VSRAM_OTHERS_RSV_H_SHIFT   10
#define PMIC_RG_VSRAM_OTHERS_RSV_L_ADDR MT6358_VSRAM_OTHERS_ANA_CON0
#define PMIC_RG_VSRAM_OTHERS_RSV_L_MASK 0x7
#define PMIC_RG_VSRAM_OTHERS_RSV_L_SHIFT   13
#define PMIC_RG_VSRAM_GPU_STB_SEL_ADDR  MT6358_VSRAM_GPU_ANA_CON0
#define PMIC_RG_VSRAM_GPU_STB_SEL_MASK  0x1
#define PMIC_RG_VSRAM_GPU_STB_SEL_SHIFT 4
#define PMIC_RG_VSRAM_GPU_NDIS_EN_ADDR  MT6358_VSRAM_GPU_ANA_CON0
#define PMIC_RG_VSRAM_GPU_NDIS_EN_MASK  0x1
#define PMIC_RG_VSRAM_GPU_NDIS_EN_SHIFT 5
#define PMIC_RG_VSRAM_GPU_NDIS_PLCUR_ADDR   MT6358_VSRAM_GPU_ANA_CON0
#define PMIC_RG_VSRAM_GPU_NDIS_PLCUR_MASK   0x3
#define PMIC_RG_VSRAM_GPU_NDIS_PLCUR_SHIFT  6
#define PMIC_RG_VSRAM_GPU_PLCUR_EN_ADDR MT6358_VSRAM_GPU_ANA_CON0
#define PMIC_RG_VSRAM_GPU_PLCUR_EN_MASK 0x1
#define PMIC_RG_VSRAM_GPU_PLCUR_EN_SHIFT   8
#define PMIC_RG_VSRAM_GPU_LPOC_EN_ADDR  MT6358_VSRAM_GPU_ANA_CON0
#define PMIC_RG_VSRAM_GPU_LPOC_EN_MASK  0x1
#define PMIC_RG_VSRAM_GPU_LPOC_EN_SHIFT 9
#define PMIC_RG_VSRAM_GPU_RSV_H_ADDR  MT6358_VSRAM_GPU_ANA_CON0
#define PMIC_RG_VSRAM_GPU_RSV_H_MASK  0x7
#define PMIC_RG_VSRAM_GPU_RSV_H_SHIFT 10
#define PMIC_RG_VSRAM_GPU_RSV_L_ADDR  MT6358_VSRAM_GPU_ANA_CON0
#define PMIC_RG_VSRAM_GPU_RSV_L_MASK  0x7
#define PMIC_RG_VSRAM_GPU_RSV_L_SHIFT 13
#define PMIC_RG_VDRAM2_VOCAL_ADDR MT6358_VDRAM2_ANA_CON0
#define PMIC_RG_VDRAM2_VOCAL_MASK 0xF
#define PMIC_RG_VDRAM2_VOCAL_SHIFT 0
#define PMIC_RG_VDRAM2_NDIS_EN_ADDR   MT6358_VDRAM2_ANA_CON1
#define PMIC_RG_VDRAM2_NDIS_EN_MASK   0x1
#define PMIC_RG_VDRAM2_NDIS_EN_SHIFT  0
#define PMIC_RG_VDRAM2_RSV_ADDR MT6358_VDRAM2_ANA_CON1
#define PMIC_RG_VDRAM2_RSV_MASK 0x3
#define PMIC_RG_VDRAM2_RSV_SHIFT  2
#define PMIC_RG_VCAMD_VOCAL_ADDR  MT6358_VCAMD_ANA_CON0
#define PMIC_RG_VCAMD_VOCAL_MASK  0xF
#define PMIC_RG_VCAMD_VOCAL_SHIFT 0
#define PMIC_RG_VCAMD_VOSEL_ADDR  MT6358_VCAMD_ANA_CON0
#define PMIC_RG_VCAMD_VOSEL_MASK  0xF
#define PMIC_RG_VCAMD_VOSEL_SHIFT 8
#define PMIC_RG_VCAMD_NDIS_EN_ADDR MT6358_VCAMD_ANA_CON1
#define PMIC_RG_VCAMD_NDIS_EN_MASK 0x1
#define PMIC_RG_VCAMD_NDIS_EN_SHIFT   0
#define PMIC_RG_VCAMD_RSV_ADDR  MT6358_VCAMD_ANA_CON1
#define PMIC_RG_VCAMD_RSV_MASK  0x3
#define PMIC_RG_VCAMD_RSV_SHIFT 2
#define PMIC_RG_VA12_VOCAL_ADDR MT6358_VA12_ANA_CON0
#define PMIC_RG_VA12_VOCAL_MASK 0xF
#define PMIC_RG_VA12_VOCAL_SHIFT  0
#define PMIC_RG_VA12_NDIS_EN_ADDR MT6358_VA12_ANA_CON1
#define PMIC_RG_VA12_NDIS_EN_MASK 0x1
#define PMIC_RG_VA12_NDIS_EN_SHIFT 0
#define PMIC_RG_VA12_RSV_ADDR   MT6358_VA12_ANA_CON1
#define PMIC_RG_VA12_RSV_MASK   0x3
#define PMIC_RG_VA12_RSV_SHIFT  2
#define PMIC_LDO_ANA1_ELR_LEN_ADDR MT6358_LDO_ANA1_ELR_NUM
#define PMIC_LDO_ANA1_ELR_LEN_MASK 0xFF
#define PMIC_LDO_ANA1_ELR_LEN_SHIFT   0
#define PMIC_RG_VRF18_VOTRIM_ADDR MT6358_VRF18_ELR_0
#define PMIC_RG_VRF18_VOTRIM_MASK 0xF
#define PMIC_RG_VRF18_VOTRIM_SHIFT 0
#define PMIC_RG_VCN18_VOTRIM_ADDR MT6358_VCN18_ELR_0
#define PMIC_RG_VCN18_VOTRIM_MASK 0xF
#define PMIC_RG_VCN18_VOTRIM_SHIFT 0
#define PMIC_RG_VCAMIO_VOTRIM_ADDR MT6358_VCAMIO_ELR_0
#define PMIC_RG_VCAMIO_VOTRIM_MASK 0xF
#define PMIC_RG_VCAMIO_VOTRIM_SHIFT   0
#define PMIC_RG_VIO18_VOTRIM_ADDR MT6358_VIO18_ELR_0
#define PMIC_RG_VIO18_VOTRIM_MASK 0xF
#define PMIC_RG_VIO18_VOTRIM_SHIFT 0
#define PMIC_RG_VEFUSE_VOTRIM_ADDR MT6358_VEFUSE_ELR_0
#define PMIC_RG_VEFUSE_VOTRIM_MASK 0xF
#define PMIC_RG_VEFUSE_VOTRIM_SHIFT   0
#define PMIC_RG_VRF12_VOTRIM_ADDR MT6358_VRF12_ELR_0
#define PMIC_RG_VRF12_VOTRIM_MASK 0xF
#define PMIC_RG_VRF12_VOTRIM_SHIFT 0
#define PMIC_RG_VDRAM2_VOTRIM_ADDR MT6358_VDRAM2_ELR_0
#define PMIC_RG_VDRAM2_VOTRIM_MASK 0xF
#define PMIC_RG_VDRAM2_VOTRIM_SHIFT   0
#define PMIC_RG_VCAMD_VOTRIM_ADDR MT6358_VCAMD_ELR_0
#define PMIC_RG_VCAMD_VOTRIM_MASK 0xF
#define PMIC_RG_VCAMD_VOTRIM_SHIFT 0
#define PMIC_RG_VA12_VOTRIM_ADDR  MT6358_VA12_ELR_0
#define PMIC_RG_VA12_VOTRIM_MASK  0xF
#define PMIC_RG_VA12_VOTRIM_SHIFT 0
#define PMIC_RG_VRTC28_BIAS_SEL_ADDR  MT6358_VRTC28_ELR_0
#define PMIC_RG_VRTC28_BIAS_SEL_MASK  0x1
#define PMIC_RG_VRTC28_BIAS_SEL_SHIFT 0
#define PMIC_DUMMYLOAD_ANA_ID_ADDR MT6358_DUMMYLOAD_DSN_ID
#define PMIC_DUMMYLOAD_ANA_ID_MASK 0xFF
#define PMIC_DUMMYLOAD_ANA_ID_SHIFT   0
#define PMIC_DUMMYLOAD_DIG_ID_ADDR MT6358_DUMMYLOAD_DSN_ID
#define PMIC_DUMMYLOAD_DIG_ID_MASK 0xFF
#define PMIC_DUMMYLOAD_DIG_ID_SHIFT   8
#define PMIC_DUMMYLOAD_ANA_MINOR_REV_ADDR   MT6358_DUMMYLOAD_DSN_REV0
#define PMIC_DUMMYLOAD_ANA_MINOR_REV_MASK   0xF
#define PMIC_DUMMYLOAD_ANA_MINOR_REV_SHIFT  0
#define PMIC_DUMMYLOAD_ANA_MAJOR_REV_ADDR   MT6358_DUMMYLOAD_DSN_REV0
#define PMIC_DUMMYLOAD_ANA_MAJOR_REV_MASK   0xF
#define PMIC_DUMMYLOAD_ANA_MAJOR_REV_SHIFT  4
#define PMIC_DUMMYLOAD_DIG_MINOR_REV_ADDR   MT6358_DUMMYLOAD_DSN_REV0
#define PMIC_DUMMYLOAD_DIG_MINOR_REV_MASK   0xF
#define PMIC_DUMMYLOAD_DIG_MINOR_REV_SHIFT  8
#define PMIC_DUMMYLOAD_DIG_MAJOR_REV_ADDR   MT6358_DUMMYLOAD_DSN_REV0
#define PMIC_DUMMYLOAD_DIG_MAJOR_REV_MASK   0xF
#define PMIC_DUMMYLOAD_DIG_MAJOR_REV_SHIFT  12
#define PMIC_DUMMYLOAD_DSN_CBS_ADDR   MT6358_DUMMYLOAD_DSN_DBI
#define PMIC_DUMMYLOAD_DSN_CBS_MASK   0x3
#define PMIC_DUMMYLOAD_DSN_CBS_SHIFT  0
#define PMIC_DUMMYLOAD_DSN_BIX_ADDR   MT6358_DUMMYLOAD_DSN_DBI
#define PMIC_DUMMYLOAD_DSN_BIX_MASK   0x3
#define PMIC_DUMMYLOAD_DSN_BIX_SHIFT  2
#define PMIC_DUMMYLOAD_DSN_ESP_ADDR   MT6358_DUMMYLOAD_DSN_DBI
#define PMIC_DUMMYLOAD_DSN_ESP_MASK   0xFF
#define PMIC_DUMMYLOAD_DSN_ESP_SHIFT  8
#define PMIC_DUMMYLOAD_DSN_FPI_ADDR   MT6358_DUMMYLOAD_DSN_FPI
#define PMIC_DUMMYLOAD_DSN_FPI_MASK   0xFF
#define PMIC_DUMMYLOAD_DSN_FPI_SHIFT  0
#define PMIC_RG_ISINK_TRIM_EN_ADDR MT6358_DUMMYLOAD_ANA_CON0
#define PMIC_RG_ISINK_TRIM_EN_MASK 0x1
#define PMIC_RG_ISINK_TRIM_EN_SHIFT   0
#define PMIC_RG_ISINK_TRIM_SEL_ADDR   MT6358_DUMMYLOAD_ANA_CON0
#define PMIC_RG_ISINK_TRIM_SEL_MASK   0x7
#define PMIC_RG_ISINK_TRIM_SEL_SHIFT  1
#define PMIC_RG_ISINK_RSV_ADDR  MT6358_DUMMYLOAD_ANA_CON0
#define PMIC_RG_ISINK_RSV_MASK  0xF
#define PMIC_RG_ISINK_RSV_SHIFT 4
#define PMIC_RG_ISINK0_CHOP_EN_ADDR   MT6358_DUMMYLOAD_ANA_CON0
#define PMIC_RG_ISINK0_CHOP_EN_MASK   0x1
#define PMIC_RG_ISINK0_CHOP_EN_SHIFT  8
#define PMIC_RG_ISINK1_CHOP_EN_ADDR   MT6358_DUMMYLOAD_ANA_CON0
#define PMIC_RG_ISINK1_CHOP_EN_MASK   0x1
#define PMIC_RG_ISINK1_CHOP_EN_SHIFT  9
#define PMIC_RG_ISINK0_DOUBLE_ADDR MT6358_DUMMYLOAD_ANA_CON0
#define PMIC_RG_ISINK0_DOUBLE_MASK 0x1
#define PMIC_RG_ISINK0_DOUBLE_SHIFT   12
#define PMIC_RG_ISINK1_DOUBLE_ADDR MT6358_DUMMYLOAD_ANA_CON0
#define PMIC_RG_ISINK1_DOUBLE_MASK 0x1
#define PMIC_RG_ISINK1_DOUBLE_SHIFT   13
#define PMIC_ISINK0_RSV1_ADDR   MT6358_ISINK0_CON1
#define PMIC_ISINK0_RSV1_MASK   0xF
#define PMIC_ISINK0_RSV1_SHIFT  0
#define PMIC_ISINK0_RSV0_ADDR   MT6358_ISINK0_CON1
#define PMIC_ISINK0_RSV0_MASK   0x7
#define PMIC_ISINK0_RSV0_SHIFT  4
#define PMIC_ISINK_CH0_STEP_ADDR  MT6358_ISINK0_CON1
#define PMIC_ISINK_CH0_STEP_MASK  0x7
#define PMIC_ISINK_CH0_STEP_SHIFT 12
#define PMIC_ISINK1_RSV1_ADDR   MT6358_ISINK1_CON1
#define PMIC_ISINK1_RSV1_MASK   0xF
#define PMIC_ISINK1_RSV1_SHIFT  0
#define PMIC_ISINK1_RSV0_ADDR   MT6358_ISINK1_CON1
#define PMIC_ISINK1_RSV0_MASK   0x7
#define PMIC_ISINK1_RSV0_SHIFT  4
#define PMIC_ISINK_CH1_STEP_ADDR  MT6358_ISINK1_CON1
#define PMIC_ISINK_CH1_STEP_MASK  0x7
#define PMIC_ISINK_CH1_STEP_SHIFT 12
#define PMIC_AD_ISINK0_STATUS_ADDR MT6358_ISINK_ANA1_SMPL
#define PMIC_AD_ISINK0_STATUS_MASK 0x1
#define PMIC_AD_ISINK0_STATUS_SHIFT   0
#define PMIC_AD_ISINK1_STATUS_ADDR MT6358_ISINK_ANA1_SMPL
#define PMIC_AD_ISINK1_STATUS_MASK 0x1
#define PMIC_AD_ISINK1_STATUS_SHIFT   1
#define PMIC_ISINK_CH1_EN_ADDR  MT6358_ISINK_EN_CTRL_SMPL
#define PMIC_ISINK_CH1_EN_MASK  0x1
#define PMIC_ISINK_CH1_EN_SHIFT 0
#define PMIC_ISINK_CH0_EN_ADDR  MT6358_ISINK_EN_CTRL_SMPL
#define PMIC_ISINK_CH0_EN_MASK  0x1
#define PMIC_ISINK_CH0_EN_SHIFT 1
#define PMIC_ISINK_CHOP1_EN_ADDR  MT6358_ISINK_EN_CTRL_SMPL
#define PMIC_ISINK_CHOP1_EN_MASK  0x1
#define PMIC_ISINK_CHOP1_EN_SHIFT 4
#define PMIC_ISINK_CHOP0_EN_ADDR  MT6358_ISINK_EN_CTRL_SMPL
#define PMIC_ISINK_CHOP0_EN_MASK  0x1
#define PMIC_ISINK_CHOP0_EN_SHIFT 5
#define PMIC_ISINK_CH1_BIAS_EN_ADDR   MT6358_ISINK_EN_CTRL_SMPL
#define PMIC_ISINK_CH1_BIAS_EN_MASK   0x1
#define PMIC_ISINK_CH1_BIAS_EN_SHIFT  8
#define PMIC_ISINK_CH0_BIAS_EN_ADDR   MT6358_ISINK_EN_CTRL_SMPL
#define PMIC_ISINK_CH0_BIAS_EN_MASK   0x1
#define PMIC_ISINK_CH0_BIAS_EN_SHIFT  9
#define PMIC_DUMMYLOAD_ELR_LEN_ADDR   MT6358_DUMMYLOAD_ELR_NUM
#define PMIC_DUMMYLOAD_ELR_LEN_MASK   0xFF
#define PMIC_DUMMYLOAD_ELR_LEN_SHIFT  0
#define PMIC_RG_ISINK_TRIM_BIAS_ADDR  MT6358_DUMMYLOAD_ELR_0
#define PMIC_RG_ISINK_TRIM_BIAS_MASK  0x7
#define PMIC_RG_ISINK_TRIM_BIAS_SHIFT 0
#define PMIC_AUD_TOP_ANA_ID_ADDR  MT6358_AUD_TOP_ID
#define PMIC_AUD_TOP_ANA_ID_MASK  0xFF
#define PMIC_AUD_TOP_ANA_ID_SHIFT 0
#define PMIC_AUD_TOP_DIG_ID_ADDR  MT6358_AUD_TOP_ID
#define PMIC_AUD_TOP_DIG_ID_MASK  0xFF
#define PMIC_AUD_TOP_DIG_ID_SHIFT 8
#define PMIC_AUD_TOP_ANA_MINOR_REV_ADDR MT6358_AUD_TOP_REV0
#define PMIC_AUD_TOP_ANA_MINOR_REV_MASK 0xF
#define PMIC_AUD_TOP_ANA_MINOR_REV_SHIFT   0
#define PMIC_AUD_TOP_ANA_MAJOR_REV_ADDR MT6358_AUD_TOP_REV0
#define PMIC_AUD_TOP_ANA_MAJOR_REV_MASK 0xF
#define PMIC_AUD_TOP_ANA_MAJOR_REV_SHIFT   4
#define PMIC_AUD_TOP_DIG_MINOR_REV_ADDR MT6358_AUD_TOP_REV0
#define PMIC_AUD_TOP_DIG_MINOR_REV_MASK 0xF
#define PMIC_AUD_TOP_DIG_MINOR_REV_SHIFT   8
#define PMIC_AUD_TOP_DIG_MAJOR_REV_ADDR MT6358_AUD_TOP_REV0
#define PMIC_AUD_TOP_DIG_MAJOR_REV_MASK 0xF
#define PMIC_AUD_TOP_DIG_MAJOR_REV_SHIFT   12
#define PMIC_AUD_TOP_CBS_ADDR   MT6358_AUD_TOP_DBI
#define PMIC_AUD_TOP_CBS_MASK   0x3
#define PMIC_AUD_TOP_CBS_SHIFT  0
#define PMIC_AUD_TOP_BIX_ADDR   MT6358_AUD_TOP_DBI
#define PMIC_AUD_TOP_BIX_MASK   0x3
#define PMIC_AUD_TOP_BIX_SHIFT  2
#define PMIC_AUD_TOP_ESP_ADDR   MT6358_AUD_TOP_DBI
#define PMIC_AUD_TOP_ESP_MASK   0xFF
#define PMIC_AUD_TOP_ESP_SHIFT  8
#define PMIC_AUD_TOP_FPI_ADDR   MT6358_AUD_TOP_DXI
#define PMIC_AUD_TOP_FPI_MASK   0xFF
#define PMIC_AUD_TOP_FPI_SHIFT  0
#define PMIC_AUD_TOP_CLK_OFFSET_ADDR  MT6358_AUD_TOP_CKPDN_TPM0
#define PMIC_AUD_TOP_CLK_OFFSET_MASK  0xFF
#define PMIC_AUD_TOP_CLK_OFFSET_SHIFT 0
#define PMIC_AUD_TOP_RST_OFFSET_ADDR  MT6358_AUD_TOP_CKPDN_TPM0
#define PMIC_AUD_TOP_RST_OFFSET_MASK  0xFF
#define PMIC_AUD_TOP_RST_OFFSET_SHIFT 8
#define PMIC_AUD_TOP_INT_OFFSET_ADDR  MT6358_AUD_TOP_CKPDN_TPM1
#define PMIC_AUD_TOP_INT_OFFSET_MASK  0xFF
#define PMIC_AUD_TOP_INT_OFFSET_SHIFT 0
#define PMIC_AUD_TOP_INT_LEN_ADDR MT6358_AUD_TOP_CKPDN_TPM1
#define PMIC_AUD_TOP_INT_LEN_MASK 0xFF
#define PMIC_AUD_TOP_INT_LEN_SHIFT 8
#define PMIC_RG_ACCDET_CK_PDN_ADDR MT6358_AUD_TOP_CKPDN_CON0
#define PMIC_RG_ACCDET_CK_PDN_MASK 0x1
#define PMIC_RG_ACCDET_CK_PDN_SHIFT   0
#define PMIC_RG_AUD_CK_PDN_ADDR MT6358_AUD_TOP_CKPDN_CON0
#define PMIC_RG_AUD_CK_PDN_MASK 0x1
#define PMIC_RG_AUD_CK_PDN_SHIFT  1
#define PMIC_RG_AUDIF_CK_PDN_ADDR MT6358_AUD_TOP_CKPDN_CON0
#define PMIC_RG_AUDIF_CK_PDN_MASK 0x1
#define PMIC_RG_AUDIF_CK_PDN_SHIFT 2
#define PMIC_RG_ZCD13M_CK_PDN_ADDR MT6358_AUD_TOP_CKPDN_CON0
#define PMIC_RG_ZCD13M_CK_PDN_MASK 0x1
#define PMIC_RG_ZCD13M_CK_PDN_SHIFT   5
#define PMIC_RG_AUDNCP_CK_PDN_ADDR MT6358_AUD_TOP_CKPDN_CON0
#define PMIC_RG_AUDNCP_CK_PDN_MASK 0x1
#define PMIC_RG_AUDNCP_CK_PDN_SHIFT   6
#define PMIC_RG_PAD_AUD_CLK_MISO_CK_PDN_ADDR  MT6358_AUD_TOP_CKPDN_CON0
#define PMIC_RG_PAD_AUD_CLK_MISO_CK_PDN_MASK  0x1
#define PMIC_RG_PAD_AUD_CLK_MISO_CK_PDN_SHIFT 7
#define PMIC_RG_AUD_INTRP_CK_PDN_ADDR MT6358_AUD_TOP_CKPDN_CON0
#define PMIC_RG_AUD_INTRP_CK_PDN_MASK 0x1
#define PMIC_RG_AUD_INTRP_CK_PDN_SHIFT  8
#define PMIC_RG_VOW32K_CK_PDN_ADDR MT6358_AUD_TOP_CKPDN_CON0
#define PMIC_RG_VOW32K_CK_PDN_MASK 0x1
#define PMIC_RG_VOW32K_CK_PDN_SHIFT   12
#define PMIC_RG_VOW13M_CK_PDN_ADDR MT6358_AUD_TOP_CKPDN_CON0
#define PMIC_RG_VOW13M_CK_PDN_MASK 0x1
#define PMIC_RG_VOW13M_CK_PDN_SHIFT   13
#define PMIC_RG_AUD_TOP_CKPDN_CON0_SET_ADDR MT6358_AUD_TOP_CKPDN_CON0_SET
#define PMIC_RG_AUD_TOP_CKPDN_CON0_SET_MASK 0x3FFF
#define PMIC_RG_AUD_TOP_CKPDN_CON0_SET_SHIFT  0
#define PMIC_RG_AUD_TOP_CKPDN_CON0_CLR_ADDR MT6358_AUD_TOP_CKPDN_CON0_CLR
#define PMIC_RG_AUD_TOP_CKPDN_CON0_CLR_MASK 0x3FFF
#define PMIC_RG_AUD_TOP_CKPDN_CON0_CLR_SHIFT  0
#define PMIC_RG_AUD_CK_CKSEL_ADDR MT6358_AUD_TOP_CKSEL_CON0
#define PMIC_RG_AUD_CK_CKSEL_MASK 0x1
#define PMIC_RG_AUD_CK_CKSEL_SHIFT 2
#define PMIC_RG_AUDIF_CK_CKSEL_ADDR   MT6358_AUD_TOP_CKSEL_CON0
#define PMIC_RG_AUDIF_CK_CKSEL_MASK   0x1
#define PMIC_RG_AUDIF_CK_CKSEL_SHIFT  3
#define PMIC_RG_AUD_TOP_CKSEL_CON0_SET_ADDR MT6358_AUD_TOP_CKSEL_CON0_SET
#define PMIC_RG_AUD_TOP_CKSEL_CON0_SET_MASK 0xF
#define PMIC_RG_AUD_TOP_CKSEL_CON0_SET_SHIFT  0
#define PMIC_RG_AUD_TOP_CKSEL_CON0_CLR_ADDR MT6358_AUD_TOP_CKSEL_CON0_CLR
#define PMIC_RG_AUD_TOP_CKSEL_CON0_CLR_MASK 0xF
#define PMIC_RG_AUD_TOP_CKSEL_CON0_CLR_SHIFT  0
#define PMIC_RG_AUD26M_CK_TST_DIS_ADDR  MT6358_AUD_TOP_CKTST_CON0
#define PMIC_RG_AUD26M_CK_TST_DIS_MASK  0x1
#define PMIC_RG_AUD26M_CK_TST_DIS_SHIFT 0
#define PMIC_RG_AUD_CK_TSTSEL_ADDR MT6358_AUD_TOP_CKTST_CON0
#define PMIC_RG_AUD_CK_TSTSEL_MASK 0x1
#define PMIC_RG_AUD_CK_TSTSEL_SHIFT   2
#define PMIC_RG_AUDIF_CK_TSTSEL_ADDR  MT6358_AUD_TOP_CKTST_CON0
#define PMIC_RG_AUDIF_CK_TSTSEL_MASK  0x1
#define PMIC_RG_AUDIF_CK_TSTSEL_SHIFT 3
#define PMIC_RG_AUD26M_CK_TSTSEL_ADDR MT6358_AUD_TOP_CKTST_CON0
#define PMIC_RG_AUD26M_CK_TSTSEL_MASK 0x1
#define PMIC_RG_AUD26M_CK_TSTSEL_SHIFT  4
#define PMIC_RG_VOW13M_CK_TST_DIS_ADDR  MT6358_AUD_TOP_CKTST_CON0
#define PMIC_RG_VOW13M_CK_TST_DIS_MASK  0x1
#define PMIC_RG_VOW13M_CK_TST_DIS_SHIFT 8
#define PMIC_RG_VOW13M_CK_TSTSEL_ADDR MT6358_AUD_TOP_CKTST_CON0
#define PMIC_RG_VOW13M_CK_TSTSEL_MASK 0x1
#define PMIC_RG_VOW13M_CK_TSTSEL_SHIFT  9
#define PMIC_RG_AUD_INTRP_CK_PDN_HWEN_ADDR  MT6358_AUD_TOP_CLK_HWEN_CON0
#define PMIC_RG_AUD_INTRP_CK_PDN_HWEN_MASK  0x1
#define PMIC_RG_AUD_INTRP_CK_PDN_HWEN_SHIFT 0
#define PMIC_RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_ADDR \
MT6358_AUD_TOP_CLK_HWEN_CON0_SET
#define PMIC_RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_MASK 0xFFFF
#define PMIC_RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_SHIFT   0
#define PMIC_RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_ADDR   \
MT6358_AUD_TOP_CLK_HWEN_CON0_CLR
#define PMIC_RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_MASK   0xFFFF
#define PMIC_RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_SHIFT  0
#define PMIC_RG_AUDIO_RST_ADDR  MT6358_AUD_TOP_RST_CON0
#define PMIC_RG_AUDIO_RST_MASK  0x1
#define PMIC_RG_AUDIO_RST_SHIFT 0
#define PMIC_RG_ACCDET_RST_ADDR MT6358_AUD_TOP_RST_CON0
#define PMIC_RG_ACCDET_RST_MASK 0x1
#define PMIC_RG_ACCDET_RST_SHIFT  1
#define PMIC_RG_ZCD_RST_ADDR MT6358_AUD_TOP_RST_CON0
#define PMIC_RG_ZCD_RST_MASK 0x1
#define PMIC_RG_ZCD_RST_SHIFT   2
#define PMIC_RG_AUDNCP_RST_ADDR MT6358_AUD_TOP_RST_CON0
#define PMIC_RG_AUDNCP_RST_MASK 0x1
#define PMIC_RG_AUDNCP_RST_SHIFT  3
#define PMIC_RG_AUD_TOP_RST_CON0_SET_ADDR   MT6358_AUD_TOP_RST_CON0_SET
#define PMIC_RG_AUD_TOP_RST_CON0_SET_MASK   0xF
#define PMIC_RG_AUD_TOP_RST_CON0_SET_SHIFT  0
#define PMIC_RG_AUD_TOP_RST_CON0_CLR_ADDR   MT6358_AUD_TOP_RST_CON0_CLR
#define PMIC_RG_AUD_TOP_RST_CON0_CLR_MASK   0xF
#define PMIC_RG_AUD_TOP_RST_CON0_CLR_SHIFT  0
#define PMIC_BANK_ACCDET_SWRST_ADDR   MT6358_AUD_TOP_RST_BANK_CON0
#define PMIC_BANK_ACCDET_SWRST_MASK   0x1
#define PMIC_BANK_ACCDET_SWRST_SHIFT  0
#define PMIC_BANK_AUDIO_SWRST_ADDR MT6358_AUD_TOP_RST_BANK_CON0
#define PMIC_BANK_AUDIO_SWRST_MASK 0x1
#define PMIC_BANK_AUDIO_SWRST_SHIFT   1
#define PMIC_BANK_AUDZCD_SWRST_ADDR   MT6358_AUD_TOP_RST_BANK_CON0
#define PMIC_BANK_AUDZCD_SWRST_MASK   0x1
#define PMIC_BANK_AUDZCD_SWRST_SHIFT  2
#define PMIC_RG_INT_EN_AUDIO_ADDR MT6358_AUD_TOP_INT_CON0
#define PMIC_RG_INT_EN_AUDIO_MASK 0x1
#define PMIC_RG_INT_EN_AUDIO_SHIFT 0
#define PMIC_RG_INT_EN_ACCDET_ADDR MT6358_AUD_TOP_INT_CON0
#define PMIC_RG_INT_EN_ACCDET_MASK 0x1
#define PMIC_RG_INT_EN_ACCDET_SHIFT   5
#define PMIC_RG_INT_EN_ACCDET_EINT0_ADDR   MT6358_AUD_TOP_INT_CON0
#define PMIC_RG_INT_EN_ACCDET_EINT0_MASK   0x1
#define PMIC_RG_INT_EN_ACCDET_EINT0_SHIFT   6
#define PMIC_RG_INT_EN_ACCDET_EINT1_ADDR   MT6358_AUD_TOP_INT_CON0
#define PMIC_RG_INT_EN_ACCDET_EINT1_MASK   0x1
#define PMIC_RG_INT_EN_ACCDET_EINT1_SHIFT   7
#define PMIC_RG_AUD_INT_CON0_SET_ADDR MT6358_AUD_TOP_INT_CON0_SET
#define PMIC_RG_AUD_INT_CON0_SET_MASK 0xFFFF
#define PMIC_RG_AUD_INT_CON0_SET_SHIFT  0
#define PMIC_RG_AUD_INT_CON0_CLR_ADDR MT6358_AUD_TOP_INT_CON0_CLR
#define PMIC_RG_AUD_INT_CON0_CLR_MASK 0xFFFF
#define PMIC_RG_AUD_INT_CON0_CLR_SHIFT  0
#define PMIC_RG_INT_MASK_AUDIO_ADDR   MT6358_AUD_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_AUDIO_MASK   0x1
#define PMIC_RG_INT_MASK_AUDIO_SHIFT  0
#define PMIC_RG_INT_MASK_ACCDET_ADDR  MT6358_AUD_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_ACCDET_MASK  0x1
#define PMIC_RG_INT_MASK_ACCDET_SHIFT 5
#define PMIC_RG_INT_MASK_ACCDET_EINT0_ADDR  MT6358_AUD_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_ACCDET_EINT0_MASK  0x1
#define PMIC_RG_INT_MASK_ACCDET_EINT0_SHIFT 6
#define PMIC_RG_INT_MASK_ACCDET_EINT1_ADDR  MT6358_AUD_TOP_INT_MASK_CON0
#define PMIC_RG_INT_MASK_ACCDET_EINT1_MASK  0x1
#define PMIC_RG_INT_MASK_ACCDET_EINT1_SHIFT 7
#define PMIC_RG_AUD_INT_MASK_CON0_SET_ADDR  MT6358_AUD_TOP_INT_MASK_CON0_SET
#define PMIC_RG_AUD_INT_MASK_CON0_SET_MASK  0xFF
#define PMIC_RG_AUD_INT_MASK_CON0_SET_SHIFT 0
#define PMIC_RG_AUD_INT_MASK_CON0_CLR_ADDR  MT6358_AUD_TOP_INT_MASK_CON0_CLR
#define PMIC_RG_AUD_INT_MASK_CON0_CLR_MASK  0xFF
#define PMIC_RG_AUD_INT_MASK_CON0_CLR_SHIFT 0
#define PMIC_RG_INT_STATUS_AUDIO_ADDR MT6358_AUD_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_AUDIO_MASK 0x1
#define PMIC_RG_INT_STATUS_AUDIO_SHIFT  0
#define PMIC_RG_INT_STATUS_ACCDET_ADDR  MT6358_AUD_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_ACCDET_MASK  0x1
#define PMIC_RG_INT_STATUS_ACCDET_SHIFT 5
#define PMIC_RG_INT_STATUS_ACCDET_EINT0_ADDR  MT6358_AUD_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_ACCDET_EINT0_MASK  0x1
#define PMIC_RG_INT_STATUS_ACCDET_EINT0_SHIFT 6
#define PMIC_RG_INT_STATUS_ACCDET_EINT1_ADDR  MT6358_AUD_TOP_INT_STATUS0
#define PMIC_RG_INT_STATUS_ACCDET_EINT1_MASK  0x1
#define PMIC_RG_INT_STATUS_ACCDET_EINT1_SHIFT 7
#define PMIC_RG_INT_RAW_STATUS_AUDIO_ADDR   MT6358_AUD_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_AUDIO_MASK   0x1
#define PMIC_RG_INT_RAW_STATUS_AUDIO_SHIFT  0
#define PMIC_RG_INT_RAW_STATUS_ACCDET_ADDR  MT6358_AUD_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_ACCDET_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_ACCDET_SHIFT 5
#define PMIC_RG_INT_RAW_STATUS_ACCDET_EINT0_ADDR  MT6358_AUD_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_ACCDET_EINT0_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_ACCDET_EINT0_SHIFT 6
#define PMIC_RG_INT_RAW_STATUS_ACCDET_EINT1_ADDR  MT6358_AUD_TOP_INT_RAW_STATUS0
#define PMIC_RG_INT_RAW_STATUS_ACCDET_EINT1_MASK  0x1
#define PMIC_RG_INT_RAW_STATUS_ACCDET_EINT1_SHIFT 7
#define PMIC_RG_AUD_TOP_INT_POLARITY_ADDR   MT6358_AUD_TOP_INT_MISC_CON0
#define PMIC_RG_AUD_TOP_INT_POLARITY_MASK   0x1
#define PMIC_RG_AUD_TOP_INT_POLARITY_SHIFT  0
#define PMIC_RG_DIVCKS_CHG_ADDR MT6358_AUDNCP_CLKDIV_CON0
#define PMIC_RG_DIVCKS_CHG_MASK 0x1
#define PMIC_RG_DIVCKS_CHG_SHIFT  0
#define PMIC_RG_DIVCKS_ON_ADDR  MT6358_AUDNCP_CLKDIV_CON1
#define PMIC_RG_DIVCKS_ON_MASK  0x1
#define PMIC_RG_DIVCKS_ON_SHIFT 0
#define PMIC_RG_DIVCKS_PRG_ADDR MT6358_AUDNCP_CLKDIV_CON2
#define PMIC_RG_DIVCKS_PRG_MASK 0x1FF
#define PMIC_RG_DIVCKS_PRG_SHIFT  0
#define PMIC_RG_DIVCKS_PWD_NCP_ADDR   MT6358_AUDNCP_CLKDIV_CON3
#define PMIC_RG_DIVCKS_PWD_NCP_MASK   0x1
#define PMIC_RG_DIVCKS_PWD_NCP_SHIFT  0
#define PMIC_RG_DIVCKS_PWD_NCP_ST_SEL_ADDR  MT6358_AUDNCP_CLKDIV_CON4
#define PMIC_RG_DIVCKS_PWD_NCP_ST_SEL_MASK  0x3
#define PMIC_RG_DIVCKS_PWD_NCP_ST_SEL_SHIFT 0
#define PMIC_RG_AUD_TOP_MON_SEL_ADDR  MT6358_AUD_TOP_MON_CON0
#define PMIC_RG_AUD_TOP_MON_SEL_MASK  0x7
#define PMIC_RG_AUD_TOP_MON_SEL_SHIFT 0
#define PMIC_RG_AUD_CLK_INT_MON_FLAG_SEL_ADDR MT6358_AUD_TOP_MON_CON0
#define PMIC_RG_AUD_CLK_INT_MON_FLAG_SEL_MASK 0xFF
#define PMIC_RG_AUD_CLK_INT_MON_FLAG_SEL_SHIFT   3
#define PMIC_RG_AUD_CLK_INT_MON_FLAG_EN_ADDR  MT6358_AUD_TOP_MON_CON0
#define PMIC_RG_AUD_CLK_INT_MON_FLAG_EN_MASK  0x1
#define PMIC_RG_AUD_CLK_INT_MON_FLAG_EN_SHIFT 11
#define PMIC_AUDIO_DIG_ANA_ID_ADDR MT6358_AUDIO_DIG_DSN_ID
#define PMIC_AUDIO_DIG_ANA_ID_MASK 0xFF
#define PMIC_AUDIO_DIG_ANA_ID_SHIFT   0
#define PMIC_AUDIO_DIG_DIG_ID_ADDR MT6358_AUDIO_DIG_DSN_ID
#define PMIC_AUDIO_DIG_DIG_ID_MASK 0xFF
#define PMIC_AUDIO_DIG_DIG_ID_SHIFT   8
#define PMIC_AUDIO_DIG_ANA_MINOR_REV_ADDR   MT6358_AUDIO_DIG_DSN_REV0
#define PMIC_AUDIO_DIG_ANA_MINOR_REV_MASK   0xF
#define PMIC_AUDIO_DIG_ANA_MINOR_REV_SHIFT  0
#define PMIC_AUDIO_DIG_ANA_MAJOR_REV_ADDR   MT6358_AUDIO_DIG_DSN_REV0
#define PMIC_AUDIO_DIG_ANA_MAJOR_REV_MASK   0xF
#define PMIC_AUDIO_DIG_ANA_MAJOR_REV_SHIFT  4
#define PMIC_AUDIO_DIG_DIG_MINOR_REV_ADDR   MT6358_AUDIO_DIG_DSN_REV0
#define PMIC_AUDIO_DIG_DIG_MINOR_REV_MASK   0xF
#define PMIC_AUDIO_DIG_DIG_MINOR_REV_SHIFT  8
#define PMIC_AUDIO_DIG_DIG_MAJOR_REV_ADDR   MT6358_AUDIO_DIG_DSN_REV0
#define PMIC_AUDIO_DIG_DIG_MAJOR_REV_MASK   0xF
#define PMIC_AUDIO_DIG_DIG_MAJOR_REV_SHIFT  12
#define PMIC_AUDIO_DIG_DSN_CBS_ADDR   MT6358_AUDIO_DIG_DSN_DBI
#define PMIC_AUDIO_DIG_DSN_CBS_MASK   0x3
#define PMIC_AUDIO_DIG_DSN_CBS_SHIFT  0
#define PMIC_AUDIO_DIG_DSN_BIX_ADDR   MT6358_AUDIO_DIG_DSN_DBI
#define PMIC_AUDIO_DIG_DSN_BIX_MASK   0x3
#define PMIC_AUDIO_DIG_DSN_BIX_SHIFT  2
#define PMIC_AUDIO_DIG_ESP_ADDR MT6358_AUDIO_DIG_DSN_DBI
#define PMIC_AUDIO_DIG_ESP_MASK 0xFF
#define PMIC_AUDIO_DIG_ESP_SHIFT  8
#define PMIC_AUDIO_DIG_DSN_FPI_ADDR   MT6358_AUDIO_DIG_DSN_DXI
#define PMIC_AUDIO_DIG_DSN_FPI_MASK   0xFF
#define PMIC_AUDIO_DIG_DSN_FPI_SHIFT  0
#define PMIC_AFE_ON_ADDR  MT6358_AFE_UL_DL_CON0
#define PMIC_AFE_ON_MASK  0x1
#define PMIC_AFE_ON_SHIFT 0
#define PMIC_AFE_DL_LR_SWAP_ADDR  MT6358_AFE_UL_DL_CON0
#define PMIC_AFE_DL_LR_SWAP_MASK  0x1
#define PMIC_AFE_DL_LR_SWAP_SHIFT 14
#define PMIC_AFE_UL_LR_SWAP_ADDR  MT6358_AFE_UL_DL_CON0
#define PMIC_AFE_UL_LR_SWAP_MASK  0x1
#define PMIC_AFE_UL_LR_SWAP_SHIFT 15
#define PMIC_DL_2_SRC_ON_TMP_CTL_PRE_ADDR   MT6358_AFE_DL_SRC2_CON0_L
#define PMIC_DL_2_SRC_ON_TMP_CTL_PRE_MASK   0x1
#define PMIC_DL_2_SRC_ON_TMP_CTL_PRE_SHIFT  0
#define PMIC_C_TWO_DIGITAL_MIC_CTL_ADDR MT6358_AFE_UL_SRC_CON0_H
#define PMIC_C_TWO_DIGITAL_MIC_CTL_MASK 0x1
#define PMIC_C_TWO_DIGITAL_MIC_CTL_SHIFT   7
#define PMIC_C_DIGMIC_PHASE_SEL_CH2_CTL_ADDR  MT6358_AFE_UL_SRC_CON0_H
#define PMIC_C_DIGMIC_PHASE_SEL_CH2_CTL_MASK  0x7
#define PMIC_C_DIGMIC_PHASE_SEL_CH2_CTL_SHIFT 8
#define PMIC_C_DIGMIC_PHASE_SEL_CH1_CTL_ADDR  MT6358_AFE_UL_SRC_CON0_H
#define PMIC_C_DIGMIC_PHASE_SEL_CH1_CTL_MASK  0x7
#define PMIC_C_DIGMIC_PHASE_SEL_CH1_CTL_SHIFT 11
#define PMIC_UL_SRC_ON_TMP_CTL_ADDR   MT6358_AFE_UL_SRC_CON0_L
#define PMIC_UL_SRC_ON_TMP_CTL_MASK   0x1
#define PMIC_UL_SRC_ON_TMP_CTL_SHIFT  0
#define PMIC_UL_SDM_3_LEVEL_CTL_ADDR  MT6358_AFE_UL_SRC_CON0_L
#define PMIC_UL_SDM_3_LEVEL_CTL_MASK  0x1
#define PMIC_UL_SDM_3_LEVEL_CTL_SHIFT 1
#define PMIC_UL_LOOP_BACK_MODE_CTL_ADDR MT6358_AFE_UL_SRC_CON0_L
#define PMIC_UL_LOOP_BACK_MODE_CTL_MASK 0x1
#define PMIC_UL_LOOP_BACK_MODE_CTL_SHIFT   2
#define PMIC_DIGMIC_3P25M_1P625M_SEL_CTL_ADDR MT6358_AFE_UL_SRC_CON0_L
#define PMIC_DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1
#define PMIC_DIGMIC_3P25M_1P625M_SEL_CTL_SHIFT   5
#define PMIC_DMIC_LOW_POWER_MODE_CTL_ADDR   MT6358_AFE_UL_SRC_CON0_L
#define PMIC_DMIC_LOW_POWER_MODE_CTL_MASK   0x3
#define PMIC_DMIC_LOW_POWER_MODE_CTL_SHIFT  14
#define PMIC_DL_SINE_ON_ADDR MT6358_AFE_TOP_CON0
#define PMIC_DL_SINE_ON_MASK 0x1
#define PMIC_DL_SINE_ON_SHIFT   0
#define PMIC_UL_SINE_ON_ADDR MT6358_AFE_TOP_CON0
#define PMIC_UL_SINE_ON_MASK 0x1
#define PMIC_UL_SINE_ON_SHIFT   1
#define PMIC_MTKAIF_SINE_ON_ADDR  MT6358_AFE_TOP_CON0
#define PMIC_MTKAIF_SINE_ON_MASK  0x1
#define PMIC_MTKAIF_SINE_ON_SHIFT 2
#define PMIC_PDN_RESERVED_ADDR  MT6358_AUDIO_TOP_CON0
#define PMIC_PDN_RESERVED_MASK  0x1
#define PMIC_PDN_RESERVED_SHIFT 0
#define PMIC_PDN_AFE_TESTMODEL_CTL_ADDR MT6358_AUDIO_TOP_CON0
#define PMIC_PDN_AFE_TESTMODEL_CTL_MASK 0x1
#define PMIC_PDN_AFE_TESTMODEL_CTL_SHIFT   1
#define PMIC_PWR_CLK_DIS_CTL_ADDR MT6358_AUDIO_TOP_CON0
#define PMIC_PWR_CLK_DIS_CTL_MASK 0x1
#define PMIC_PWR_CLK_DIS_CTL_SHIFT 2
#define PMIC_PDN_I2S_DL_CTL_ADDR  MT6358_AUDIO_TOP_CON0
#define PMIC_PDN_I2S_DL_CTL_MASK  0x1
#define PMIC_PDN_I2S_DL_CTL_SHIFT 3
#define PMIC_PDN_ADC_CTL_ADDR   MT6358_AUDIO_TOP_CON0
#define PMIC_PDN_ADC_CTL_MASK   0x1
#define PMIC_PDN_ADC_CTL_SHIFT  5
#define PMIC_PDN_DAC_CTL_ADDR   MT6358_AUDIO_TOP_CON0
#define PMIC_PDN_DAC_CTL_MASK   0x1
#define PMIC_PDN_DAC_CTL_SHIFT  6
#define PMIC_PDN_AFE_CTL_ADDR   MT6358_AUDIO_TOP_CON0
#define PMIC_PDN_AFE_CTL_MASK   0x1
#define PMIC_PDN_AFE_CTL_SHIFT  7
#define PMIC_AFE_MON_SEL_ADDR   MT6358_AFE_MON_DEBUG0
#define PMIC_AFE_MON_SEL_MASK   0xFF
#define PMIC_AFE_MON_SEL_SHIFT  0
#define PMIC_AUDIO_SYS_TOP_MON_SEL_ADDR MT6358_AFE_MON_DEBUG0
#define PMIC_AUDIO_SYS_TOP_MON_SEL_MASK 0x1F
#define PMIC_AUDIO_SYS_TOP_MON_SEL_SHIFT   8
#define PMIC_AUDIO_SYS_TOP_MON_SWAP_ADDR   MT6358_AFE_MON_DEBUG0
#define PMIC_AUDIO_SYS_TOP_MON_SWAP_MASK   0x3
#define PMIC_AUDIO_SYS_TOP_MON_SWAP_SHIFT   14
#define PMIC_CCI_SCRAMBLER_EN_ADDR MT6358_AFUNC_AUD_CON0
#define PMIC_CCI_SCRAMBLER_EN_MASK 0x1
#define PMIC_CCI_SCRAMBLER_EN_SHIFT   0
#define PMIC_CCI_AUD_SDM_7BIT_SEL_ADDR  MT6358_AFUNC_AUD_CON0
#define PMIC_CCI_AUD_SDM_7BIT_SEL_MASK  0x1
#define PMIC_CCI_AUD_SDM_7BIT_SEL_SHIFT 1
#define PMIC_CCI_AUD_SDM_MUTER_ADDR   MT6358_AFUNC_AUD_CON0
#define PMIC_CCI_AUD_SDM_MUTER_MASK   0x1
#define PMIC_CCI_AUD_SDM_MUTER_SHIFT  2
#define PMIC_CCI_AUD_SDM_MUTEL_ADDR   MT6358_AFUNC_AUD_CON0
#define PMIC_CCI_AUD_SDM_MUTEL_MASK   0x1
#define PMIC_CCI_AUD_SDM_MUTEL_SHIFT  3
#define PMIC_CCI_AUD_SPLIT_TEST_EN_ADDR MT6358_AFUNC_AUD_CON0
#define PMIC_CCI_AUD_SPLIT_TEST_EN_MASK 0x1
#define PMIC_CCI_AUD_SPLIT_TEST_EN_SHIFT   4
#define PMIC_CCI_ZERO_PAD_DISABLE_ADDR  MT6358_AFUNC_AUD_CON0
#define PMIC_CCI_ZERO_PAD_DISABLE_MASK  0x1
#define PMIC_CCI_ZERO_PAD_DISABLE_SHIFT 5
#define PMIC_CCI_AUD_IDAC_TEST_EN_ADDR  MT6358_AFUNC_AUD_CON0
#define PMIC_CCI_AUD_IDAC_TEST_EN_MASK  0x1
#define PMIC_CCI_AUD_IDAC_TEST_EN_SHIFT 6
#define PMIC_CCI_SPLT_SCRMB_ON_ADDR   MT6358_AFUNC_AUD_CON0
#define PMIC_CCI_SPLT_SCRMB_ON_MASK   0x1
#define PMIC_CCI_SPLT_SCRMB_ON_SHIFT  7
#define PMIC_CCI_SPLT_SCRMB_CLK_ON_ADDR MT6358_AFUNC_AUD_CON0
#define PMIC_CCI_SPLT_SCRMB_CLK_ON_MASK 0x1
#define PMIC_CCI_SPLT_SCRMB_CLK_ON_SHIFT   8
#define PMIC_CCI_RAND_EN_ADDR   MT6358_AFUNC_AUD_CON0
#define PMIC_CCI_RAND_EN_MASK   0x1
#define PMIC_CCI_RAND_EN_SHIFT  9
#define PMIC_CCI_LCH_INV_ADDR   MT6358_AFUNC_AUD_CON0
#define PMIC_CCI_LCH_INV_MASK   0x1
#define PMIC_CCI_LCH_INV_SHIFT  10
#define PMIC_CCI_SCRAMBLER_CG_EN_ADDR MT6358_AFUNC_AUD_CON0
#define PMIC_CCI_SCRAMBLER_CG_EN_MASK 0x1
#define PMIC_CCI_SCRAMBLER_CG_EN_SHIFT  11
#define PMIC_CCI_AUDIO_FIFO_WPTR_ADDR MT6358_AFUNC_AUD_CON0
#define PMIC_CCI_AUDIO_FIFO_WPTR_MASK 0x7
#define PMIC_CCI_AUDIO_FIFO_WPTR_SHIFT  12
#define PMIC_CCI_AUD_ANACK_SEL_ADDR   MT6358_AFUNC_AUD_CON0
#define PMIC_CCI_AUD_ANACK_SEL_MASK   0x1
#define PMIC_CCI_AUD_ANACK_SEL_SHIFT  15
#define PMIC_AUD_SDM_TEST_R_ADDR  MT6358_AFUNC_AUD_CON1
#define PMIC_AUD_SDM_TEST_R_MASK  0xFF
#define PMIC_AUD_SDM_TEST_R_SHIFT 0
#define PMIC_AUD_SDM_TEST_L_ADDR  MT6358_AFUNC_AUD_CON1
#define PMIC_AUD_SDM_TEST_L_MASK  0xFF
#define PMIC_AUD_SDM_TEST_L_SHIFT 8
#define PMIC_CCI_ACD_FUNC_RSTB_ADDR   MT6358_AFUNC_AUD_CON2
#define PMIC_CCI_ACD_FUNC_RSTB_MASK   0x1
#define PMIC_CCI_ACD_FUNC_RSTB_SHIFT  0
#define PMIC_CCI_AFIFO_CLK_PWDB_ADDR  MT6358_AFUNC_AUD_CON2
#define PMIC_CCI_AFIFO_CLK_PWDB_MASK  0x1
#define PMIC_CCI_AFIFO_CLK_PWDB_SHIFT 1
#define PMIC_CCI_ACD_MODE_ADDR  MT6358_AFUNC_AUD_CON2
#define PMIC_CCI_ACD_MODE_MASK  0x1
#define PMIC_CCI_ACD_MODE_SHIFT 2
#define PMIC_CCI_AUDIO_FIFO_ENABLE_ADDR MT6358_AFUNC_AUD_CON2
#define PMIC_CCI_AUDIO_FIFO_ENABLE_MASK 0x1
#define PMIC_CCI_AUDIO_FIFO_ENABLE_SHIFT   3
#define PMIC_CCI_AUDIO_FIFO_CLKIN_INV_ADDR  MT6358_AFUNC_AUD_CON2
#define PMIC_CCI_AUDIO_FIFO_CLKIN_INV_MASK  0x1
#define PMIC_CCI_AUDIO_FIFO_CLKIN_INV_SHIFT 4
#define PMIC_CCI_AUD_DAC_ANA_RSTB_SEL_ADDR  MT6358_AFUNC_AUD_CON2
#define PMIC_CCI_AUD_DAC_ANA_RSTB_SEL_MASK  0x1
#define PMIC_CCI_AUD_DAC_ANA_RSTB_SEL_SHIFT 6
#define PMIC_CCI_AUD_DAC_ANA_MUTE_ADDR  MT6358_AFUNC_AUD_CON2
#define PMIC_CCI_AUD_DAC_ANA_MUTE_MASK  0x1
#define PMIC_CCI_AUD_DAC_ANA_MUTE_SHIFT 7
#define PMIC_DIGMIC_TESTCK_SEL_ADDR   MT6358_AFUNC_AUD_CON3
#define PMIC_DIGMIC_TESTCK_SEL_MASK   0x1
#define PMIC_DIGMIC_TESTCK_SEL_SHIFT  0
#define PMIC_DIGMIC_TESTCK_SRC_SEL_ADDR MT6358_AFUNC_AUD_CON3
#define PMIC_DIGMIC_TESTCK_SRC_SEL_MASK 0x7
#define PMIC_DIGMIC_TESTCK_SRC_SEL_SHIFT   4
#define PMIC_SDM_TESTCK_SRC_SEL_ADDR  MT6358_AFUNC_AUD_CON3
#define PMIC_SDM_TESTCK_SRC_SEL_MASK  0x7
#define PMIC_SDM_TESTCK_SRC_SEL_SHIFT 8
#define PMIC_SDM_ANA13M_TESTCK_SRC_SEL_ADDR MT6358_AFUNC_AUD_CON3
#define PMIC_SDM_ANA13M_TESTCK_SRC_SEL_MASK 0x7
#define PMIC_SDM_ANA13M_TESTCK_SRC_SEL_SHIFT  12
#define PMIC_SDM_ANA13M_TESTCK_SEL_ADDR MT6358_AFUNC_AUD_CON3
#define PMIC_SDM_ANA13M_TESTCK_SEL_MASK 0x1
#define PMIC_SDM_ANA13M_TESTCK_SEL_SHIFT   15
#define PMIC_UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_ADDR  MT6358_AFUNC_AUD_CON4
#define PMIC_UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK  0x7
#define PMIC_UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_SHIFT 0
#define PMIC_UL_FIFO_WCLK_6P5M_TESTCK_SEL_ADDR   MT6358_AFUNC_AUD_CON4
#define PMIC_UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK   0x1
#define PMIC_UL_FIFO_WCLK_6P5M_TESTCK_SEL_SHIFT  3
#define PMIC_UL_FIFO_WDATA_TESTSRC_SEL_ADDR MT6358_AFUNC_AUD_CON4
#define PMIC_UL_FIFO_WDATA_TESTSRC_SEL_MASK 0x1
#define PMIC_UL_FIFO_WDATA_TESTSRC_SEL_SHIFT  4
#define PMIC_UL_FIFO_WDATA_TESTEN_ADDR  MT6358_AFUNC_AUD_CON4
#define PMIC_UL_FIFO_WDATA_TESTEN_MASK  0x1
#define PMIC_UL_FIFO_WDATA_TESTEN_SHIFT 5
#define PMIC_UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_ADDR  MT6358_AFUNC_AUD_CON4
#define PMIC_UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK  0x1
#define PMIC_UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_SHIFT 6
#define PMIC_UL_FIFO_WCLK_INV_ADDR MT6358_AFUNC_AUD_CON4
#define PMIC_UL_FIFO_WCLK_INV_MASK 0x1
#define PMIC_UL_FIFO_WCLK_INV_SHIFT   8
#define PMIC_R_AUD_DAC_NEG_LARGE_MONO_ADDR  MT6358_AFUNC_AUD_CON5
#define PMIC_R_AUD_DAC_NEG_LARGE_MONO_MASK  0xFF
#define PMIC_R_AUD_DAC_NEG_LARGE_MONO_SHIFT 0
#define PMIC_R_AUD_DAC_POS_LARGE_MONO_ADDR  MT6358_AFUNC_AUD_CON5
#define PMIC_R_AUD_DAC_POS_LARGE_MONO_MASK  0xFF
#define PMIC_R_AUD_DAC_POS_LARGE_MONO_SHIFT 8
#define PMIC_R_AUD_DAC_SW_RSTB_ADDR   MT6358_AFUNC_AUD_CON6
#define PMIC_R_AUD_DAC_SW_RSTB_MASK   0x1
#define PMIC_R_AUD_DAC_SW_RSTB_SHIFT  0
#define PMIC_R_AUD_DAC_MONO_SEL_ADDR  MT6358_AFUNC_AUD_CON6
#define PMIC_R_AUD_DAC_MONO_SEL_MASK  0x1
#define PMIC_R_AUD_DAC_MONO_SEL_SHIFT 3
#define PMIC_R_AUD_DAC_NEG_TINY_MONO_ADDR   MT6358_AFUNC_AUD_CON6
#define PMIC_R_AUD_DAC_NEG_TINY_MONO_MASK   0x3
#define PMIC_R_AUD_DAC_NEG_TINY_MONO_SHIFT  4
#define PMIC_R_AUD_DAC_POS_TINY_MONO_ADDR   MT6358_AFUNC_AUD_CON6
#define PMIC_R_AUD_DAC_POS_TINY_MONO_MASK   0x3
#define PMIC_R_AUD_DAC_POS_TINY_MONO_SHIFT  6
#define PMIC_R_AUD_DAC_NEG_SMALL_MONO_ADDR  MT6358_AFUNC_AUD_CON6
#define PMIC_R_AUD_DAC_NEG_SMALL_MONO_MASK  0xF
#define PMIC_R_AUD_DAC_NEG_SMALL_MONO_SHIFT 8
#define PMIC_R_AUD_DAC_POS_SMALL_MONO_ADDR  MT6358_AFUNC_AUD_CON6
#define PMIC_R_AUD_DAC_POS_SMALL_MONO_MASK  0xF
#define PMIC_R_AUD_DAC_POS_SMALL_MONO_SHIFT 12
#define PMIC_AUD_SCR_OUT_R_ADDR MT6358_AFUNC_AUD_MON0
#define PMIC_AUD_SCR_OUT_R_MASK 0xFF
#define PMIC_AUD_SCR_OUT_R_SHIFT  0
#define PMIC_AUD_SCR_OUT_L_ADDR MT6358_AFUNC_AUD_MON0
#define PMIC_AUD_SCR_OUT_L_MASK 0xFF
#define PMIC_AUD_SCR_OUT_L_SHIFT  8
#define PMIC_RGS_AUDRCTUNE0READ_ADDR  MT6358_AUDRC_TUNE_MON0
#define PMIC_RGS_AUDRCTUNE0READ_MASK  0x1F
#define PMIC_RGS_AUDRCTUNE0READ_SHIFT 0
#define PMIC_RGS_AUDRCTUNE1READ_ADDR  MT6358_AUDRC_TUNE_MON0
#define PMIC_RGS_AUDRCTUNE1READ_MASK  0x1F
#define PMIC_RGS_AUDRCTUNE1READ_SHIFT 8
#define PMIC_ASYNC_TEST_OUT_BCK_ADDR  MT6358_AUDRC_TUNE_MON0
#define PMIC_ASYNC_TEST_OUT_BCK_MASK  0x1
#define PMIC_ASYNC_TEST_OUT_BCK_SHIFT 15
#define PMIC_RG_MTKAIF_RXIF_FIFO_INTEN_ADDR MT6358_AFE_ADDA_MTKAIF_FIFO_CFG0
#define PMIC_RG_MTKAIF_RXIF_FIFO_INTEN_MASK 0x1
#define PMIC_RG_MTKAIF_RXIF_FIFO_INTEN_SHIFT  0
#define PMIC_AFE_RESERVED_ADDR  MT6358_AFE_ADDA_MTKAIF_FIFO_CFG0
#define PMIC_AFE_RESERVED_MASK  0x7FFF
#define PMIC_AFE_RESERVED_SHIFT 1
#define PMIC_MTKAIF_RXIF_RD_EMPTY_STATUS_ADDR \
MT6358_AFE_ADDA_MTKAIF_FIFO_LOG_MON1
#define PMIC_MTKAIF_RXIF_RD_EMPTY_STATUS_MASK 0x1
#define PMIC_MTKAIF_RXIF_RD_EMPTY_STATUS_SHIFT   0
#define PMIC_MTKAIF_RXIF_WR_FULL_STATUS_ADDR  \
MT6358_AFE_ADDA_MTKAIF_FIFO_LOG_MON1
#define PMIC_MTKAIF_RXIF_WR_FULL_STATUS_MASK  0x1
#define PMIC_MTKAIF_RXIF_WR_FULL_STATUS_SHIFT 1
#define PMIC_MTKAIF_RXIF_FIFO_STATUS_ADDR   MT6358_AFE_ADDA_MTKAIF_MON0
#define PMIC_MTKAIF_RXIF_FIFO_STATUS_MASK   0xFFF
#define PMIC_MTKAIF_RXIF_FIFO_STATUS_SHIFT  0
#define PMIC_MTKAIFTX_V3_SDATA_OUT1_ADDR   MT6358_AFE_ADDA_MTKAIF_MON0
#define PMIC_MTKAIFTX_V3_SDATA_OUT1_MASK   0x1
#define PMIC_MTKAIFTX_V3_SDATA_OUT1_SHIFT   12
#define PMIC_MTKAIFTX_V3_SDATA_OUT2_ADDR   MT6358_AFE_ADDA_MTKAIF_MON0
#define PMIC_MTKAIFTX_V3_SDATA_OUT2_MASK   0x1
#define PMIC_MTKAIFTX_V3_SDATA_OUT2_SHIFT   13
#define PMIC_MTKAIFTX_V3_SYNC_OUT_ADDR  MT6358_AFE_ADDA_MTKAIF_MON0
#define PMIC_MTKAIFTX_V3_SYNC_OUT_MASK  0x1
#define PMIC_MTKAIFTX_V3_SYNC_OUT_SHIFT 14
#define PMIC_MTKAIF_RXIF_INVALID_CYCLE_ADDR MT6358_AFE_ADDA_MTKAIF_MON1
#define PMIC_MTKAIF_RXIF_INVALID_CYCLE_MASK 0xFF
#define PMIC_MTKAIF_RXIF_INVALID_CYCLE_SHIFT  0
#define PMIC_MTKAIF_RXIF_INVALID_FLAG_ADDR  MT6358_AFE_ADDA_MTKAIF_MON1
#define PMIC_MTKAIF_RXIF_INVALID_FLAG_MASK  0x1
#define PMIC_MTKAIF_RXIF_INVALID_FLAG_SHIFT 8
#define PMIC_MTKAIF_RXIF_SEARCH_FAIL_FLAG_ADDR   MT6358_AFE_ADDA_MTKAIF_MON1
#define PMIC_MTKAIF_RXIF_SEARCH_FAIL_FLAG_MASK   0x1
#define PMIC_MTKAIF_RXIF_SEARCH_FAIL_FLAG_SHIFT  11
#define PMIC_MTKAIFRX_V3_SDATA_IN1_ADDR MT6358_AFE_ADDA_MTKAIF_MON1
#define PMIC_MTKAIFRX_V3_SDATA_IN1_MASK 0x1
#define PMIC_MTKAIFRX_V3_SDATA_IN1_SHIFT   12
#define PMIC_MTKAIFRX_V3_SDATA_IN2_ADDR MT6358_AFE_ADDA_MTKAIF_MON1
#define PMIC_MTKAIFRX_V3_SDATA_IN2_MASK 0x1
#define PMIC_MTKAIFRX_V3_SDATA_IN2_SHIFT   13
#define PMIC_MTKAIFRX_V3_SYNC_IN_ADDR MT6358_AFE_ADDA_MTKAIF_MON1
#define PMIC_MTKAIFRX_V3_SYNC_IN_MASK 0x1
#define PMIC_MTKAIFRX_V3_SYNC_IN_SHIFT  14
#define PMIC_MTKAIF_TXIF_IN_CH1_ADDR  MT6358_AFE_ADDA_MTKAIF_MON2
#define PMIC_MTKAIF_TXIF_IN_CH1_MASK  0xFF
#define PMIC_MTKAIF_TXIF_IN_CH1_SHIFT 0
#define PMIC_MTKAIF_TXIF_IN_CH2_ADDR  MT6358_AFE_ADDA_MTKAIF_MON2
#define PMIC_MTKAIF_TXIF_IN_CH2_MASK  0xFF
#define PMIC_MTKAIF_TXIF_IN_CH2_SHIFT 8
#define PMIC_MTKAIF_RXIF_OUT_CH1_ADDR MT6358_AFE_ADDA_MTKAIF_MON3
#define PMIC_MTKAIF_RXIF_OUT_CH1_MASK 0xFF
#define PMIC_MTKAIF_RXIF_OUT_CH1_SHIFT  0
#define PMIC_MTKAIF_RXIF_OUT_CH2_ADDR MT6358_AFE_ADDA_MTKAIF_MON3
#define PMIC_MTKAIF_RXIF_OUT_CH2_MASK 0xFF
#define PMIC_MTKAIF_RXIF_OUT_CH2_SHIFT  8
#define PMIC_RG_MTKAIF_LOOPBACK_TEST1_ADDR  MT6358_AFE_ADDA_MTKAIF_CFG0
#define PMIC_RG_MTKAIF_LOOPBACK_TEST1_MASK  0x1
#define PMIC_RG_MTKAIF_LOOPBACK_TEST1_SHIFT 0
#define PMIC_RG_MTKAIF_LOOPBACK_TEST2_ADDR  MT6358_AFE_ADDA_MTKAIF_CFG0
#define PMIC_RG_MTKAIF_LOOPBACK_TEST2_MASK  0x1
#define PMIC_RG_MTKAIF_LOOPBACK_TEST2_SHIFT 1
#define PMIC_RG_MTKAIF_PMIC_TXIF_8TO5_ADDR  MT6358_AFE_ADDA_MTKAIF_CFG0
#define PMIC_RG_MTKAIF_PMIC_TXIF_8TO5_MASK  0x1
#define PMIC_RG_MTKAIF_PMIC_TXIF_8TO5_SHIFT 2
#define PMIC_RG_MTKAIF_TXIF_PROTOCOL2_ADDR  MT6358_AFE_ADDA_MTKAIF_CFG0
#define PMIC_RG_MTKAIF_TXIF_PROTOCOL2_MASK  0x1
#define PMIC_RG_MTKAIF_TXIF_PROTOCOL2_SHIFT 4
#define PMIC_RG_MTKAIF_BYPASS_SRC_TEST_ADDR MT6358_AFE_ADDA_MTKAIF_CFG0
#define PMIC_RG_MTKAIF_BYPASS_SRC_TEST_MASK 0x1
#define PMIC_RG_MTKAIF_BYPASS_SRC_TEST_SHIFT  5
#define PMIC_RG_MTKAIF_BYPASS_SRC_MODE_ADDR MT6358_AFE_ADDA_MTKAIF_CFG0
#define PMIC_RG_MTKAIF_BYPASS_SRC_MODE_MASK 0x3
#define PMIC_RG_MTKAIF_BYPASS_SRC_MODE_SHIFT  6
#define PMIC_RG_MTKAIF_RXIF_PROTOCOL2_ADDR  MT6358_AFE_ADDA_MTKAIF_CFG0
#define PMIC_RG_MTKAIF_RXIF_PROTOCOL2_MASK  0x1
#define PMIC_RG_MTKAIF_RXIF_PROTOCOL2_SHIFT 8
#define PMIC_RG_MTKAIF_RXIF_CLKINV_ADDR MT6358_AFE_ADDA_MTKAIF_CFG0
#define PMIC_RG_MTKAIF_RXIF_CLKINV_MASK 0x1
#define PMIC_RG_MTKAIF_RXIF_CLKINV_SHIFT   15
#define PMIC_RG_MTKAIF_RXIF_DATA_MODE_ADDR  MT6358_AFE_ADDA_MTKAIF_RX_CFG0
#define PMIC_RG_MTKAIF_RXIF_DATA_MODE_MASK  0x1
#define PMIC_RG_MTKAIF_RXIF_DATA_MODE_SHIFT 0
#define PMIC_RG_MTKAIF_RXIF_DETECT_ON_ADDR  MT6358_AFE_ADDA_MTKAIF_RX_CFG0
#define PMIC_RG_MTKAIF_RXIF_DETECT_ON_MASK  0x1
#define PMIC_RG_MTKAIF_RXIF_DETECT_ON_SHIFT 3
#define PMIC_RG_MTKAIF_RXIF_FIFO_RSP_ADDR   MT6358_AFE_ADDA_MTKAIF_RX_CFG0
#define PMIC_RG_MTKAIF_RXIF_FIFO_RSP_MASK   0x7
#define PMIC_RG_MTKAIF_RXIF_FIFO_RSP_SHIFT  4
#define PMIC_RG_MTKAIF_RXIF_DATA_BIT_ADDR   MT6358_AFE_ADDA_MTKAIF_RX_CFG0
#define PMIC_RG_MTKAIF_RXIF_DATA_BIT_MASK   0x7
#define PMIC_RG_MTKAIF_RXIF_DATA_BIT_SHIFT  8
#define PMIC_RG_MTKAIF_RXIF_VOICE_MODE_ADDR MT6358_AFE_ADDA_MTKAIF_RX_CFG0
#define PMIC_RG_MTKAIF_RXIF_VOICE_MODE_MASK 0xF
#define PMIC_RG_MTKAIF_RXIF_VOICE_MODE_SHIFT  12
#define PMIC_RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_ADDR  \
MT6358_AFE_ADDA_MTKAIF_RX_CFG1
#define PMIC_RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_MASK  0xF
#define PMIC_RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_SHIFT 0
#define PMIC_RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_ADDR MT6358_AFE_ADDA_MTKAIF_RX_CFG1
#define PMIC_RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_MASK 0xF
#define PMIC_RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_SHIFT  4
#define PMIC_RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_ADDR \
MT6358_AFE_ADDA_MTKAIF_RX_CFG1
#define PMIC_RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_MASK 0xF
#define PMIC_RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_SHIFT   8
#define PMIC_RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_ADDR  \
MT6358_AFE_ADDA_MTKAIF_RX_CFG1
#define PMIC_RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_MASK  0xF
#define PMIC_RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_SHIFT 12
#define PMIC_RG_MTKAIF_RXIF_SYNC_CNT_TABLE_ADDR  MT6358_AFE_ADDA_MTKAIF_RX_CFG2
#define PMIC_RG_MTKAIF_RXIF_SYNC_CNT_TABLE_MASK  0xFFF
#define PMIC_RG_MTKAIF_RXIF_SYNC_CNT_TABLE_SHIFT  0
#define PMIC_RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_ADDR  MT6358_AFE_ADDA_MTKAIF_RX_CFG2
#define PMIC_RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_MASK  0x1
#define PMIC_RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_SHIFT 12
#define PMIC_RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_ADDR   \
MT6358_AFE_ADDA_MTKAIF_RX_CFG3
#define PMIC_RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK   0x1
#define PMIC_RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_SHIFT  3
#define PMIC_RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_ADDR \
MT6358_AFE_ADDA_MTKAIF_RX_CFG3
#define PMIC_RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK 0x7
#define PMIC_RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_SHIFT   4
#define PMIC_RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_ADDR MT6358_AFE_ADDA_MTKAIF_RX_CFG3
#define PMIC_RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_MASK 0x1
#define PMIC_RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_SHIFT  7
#define PMIC_RG_MTKAIF_SYNC_WORD1_ADDR  MT6358_AFE_ADDA_MTKAIF_TX_CFG1
#define PMIC_RG_MTKAIF_SYNC_WORD1_MASK  0x7
#define PMIC_RG_MTKAIF_SYNC_WORD1_SHIFT 0
#define PMIC_RG_MTKAIF_SYNC_WORD2_ADDR  MT6358_AFE_ADDA_MTKAIF_TX_CFG1
#define PMIC_RG_MTKAIF_SYNC_WORD2_MASK  0x7
#define PMIC_RG_MTKAIF_SYNC_WORD2_SHIFT 4
#define PMIC_R_AUD_SDM_MUTE_R_ADDR MT6358_AFE_SGEN_CFG0
#define PMIC_R_AUD_SDM_MUTE_R_MASK 0x1
#define PMIC_R_AUD_SDM_MUTE_R_SHIFT   4
#define PMIC_R_AUD_SDM_MUTE_L_ADDR MT6358_AFE_SGEN_CFG0
#define PMIC_R_AUD_SDM_MUTE_L_MASK 0x1
#define PMIC_R_AUD_SDM_MUTE_L_SHIFT   5
#define PMIC_C_MUTE_SW_CTL_ADDR MT6358_AFE_SGEN_CFG0
#define PMIC_C_MUTE_SW_CTL_MASK 0x1
#define PMIC_C_MUTE_SW_CTL_SHIFT  6
#define PMIC_C_DAC_EN_CTL_ADDR  MT6358_AFE_SGEN_CFG0
#define PMIC_C_DAC_EN_CTL_MASK  0x1
#define PMIC_C_DAC_EN_CTL_SHIFT 7
#define PMIC_C_AMP_DIV_CH1_CTL_ADDR   MT6358_AFE_SGEN_CFG0
#define PMIC_C_AMP_DIV_CH1_CTL_MASK   0xF
#define PMIC_C_AMP_DIV_CH1_CTL_SHIFT  12
#define PMIC_C_FREQ_DIV_CH1_CTL_ADDR  MT6358_AFE_SGEN_CFG1
#define PMIC_C_FREQ_DIV_CH1_CTL_MASK  0x1F
#define PMIC_C_FREQ_DIV_CH1_CTL_SHIFT 0
#define PMIC_C_SGEN_RCH_INV_8BIT_ADDR MT6358_AFE_SGEN_CFG1
#define PMIC_C_SGEN_RCH_INV_8BIT_MASK 0x1
#define PMIC_C_SGEN_RCH_INV_8BIT_SHIFT  14
#define PMIC_C_SGEN_RCH_INV_5BIT_ADDR MT6358_AFE_SGEN_CFG1
#define PMIC_C_SGEN_RCH_INV_5BIT_MASK 0x1
#define PMIC_C_SGEN_RCH_INV_5BIT_SHIFT  15
#define PMIC_RG_AMIC_UL_ADC_CLK_SEL_ADDR   MT6358_AFE_ADC_ASYNC_FIFO_CFG
#define PMIC_RG_AMIC_UL_ADC_CLK_SEL_MASK   0x1
#define PMIC_RG_AMIC_UL_ADC_CLK_SEL_SHIFT   1
#define PMIC_RG_UL_ASYNC_FIFO_SOFT_RST_ADDR MT6358_AFE_ADC_ASYNC_FIFO_CFG
#define PMIC_RG_UL_ASYNC_FIFO_SOFT_RST_MASK 0x1
#define PMIC_RG_UL_ASYNC_FIFO_SOFT_RST_SHIFT  4
#define PMIC_RG_UL_ASYNC_FIFO_SOFT_RST_EN_ADDR   MT6358_AFE_ADC_ASYNC_FIFO_CFG
#define PMIC_RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK   0x1
#define PMIC_RG_UL_ASYNC_FIFO_SOFT_RST_EN_SHIFT  5
#define PMIC_DCCLK_GEN_ON_ADDR  MT6358_AFE_DCCLK_CFG0
#define PMIC_DCCLK_GEN_ON_MASK  0x1
#define PMIC_DCCLK_GEN_ON_SHIFT 0
#define PMIC_DCCLK_PDN_ADDR  MT6358_AFE_DCCLK_CFG0
#define PMIC_DCCLK_PDN_MASK  0x1
#define PMIC_DCCLK_PDN_SHIFT 1
#define PMIC_DCCLK_INV_ADDR  MT6358_AFE_DCCLK_CFG0
#define PMIC_DCCLK_INV_MASK  0x1
#define PMIC_DCCLK_INV_SHIFT 4
#define PMIC_DCCLK_DIV_ADDR  MT6358_AFE_DCCLK_CFG0
#define PMIC_DCCLK_DIV_MASK  0x7FF
#define PMIC_DCCLK_DIV_SHIFT 5
#define PMIC_DCCLK_PHASE_SEL_ADDR MT6358_AFE_DCCLK_CFG1
#define PMIC_DCCLK_PHASE_SEL_MASK 0xF
#define PMIC_DCCLK_PHASE_SEL_SHIFT 4
#define PMIC_DCCLK_RESYNC_BYPASS_ADDR MT6358_AFE_DCCLK_CFG1
#define PMIC_DCCLK_RESYNC_BYPASS_MASK 0x1
#define PMIC_DCCLK_RESYNC_BYPASS_SHIFT  8
#define PMIC_RESYNC_SRC_CK_INV_ADDR   MT6358_AFE_DCCLK_CFG1
#define PMIC_RESYNC_SRC_CK_INV_MASK   0x1
#define PMIC_RESYNC_SRC_CK_INV_SHIFT  9
#define PMIC_RESYNC_SRC_SEL_ADDR  MT6358_AFE_DCCLK_CFG1
#define PMIC_RESYNC_SRC_SEL_MASK  0x3
#define PMIC_RESYNC_SRC_SEL_SHIFT 10
#define PMIC_RG_AUD_PAD_TOP_PHASE_MODE_ADDR MT6358_AUDIO_DIG_CFG
#define PMIC_RG_AUD_PAD_TOP_PHASE_MODE_MASK 0x7F
#define PMIC_RG_AUD_PAD_TOP_PHASE_MODE_SHIFT  0
#define PMIC_RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_ADDR  MT6358_AUDIO_DIG_CFG
#define PMIC_RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK  0x1
#define PMIC_RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SHIFT 7
#define PMIC_RG_AUD_PAD_TOP_PHASE_MODE2_ADDR  MT6358_AUDIO_DIG_CFG
#define PMIC_RG_AUD_PAD_TOP_PHASE_MODE2_MASK  0x7F
#define PMIC_RG_AUD_PAD_TOP_PHASE_MODE2_SHIFT 8
#define PMIC_RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_ADDR MT6358_AUDIO_DIG_CFG
#define PMIC_RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK 0x1
#define PMIC_RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SHIFT   15
#define PMIC_RG_AUD_PAD_TOP_TX_FIFO_ON_ADDR MT6358_AFE_AUD_PAD_TOP
#define PMIC_RG_AUD_PAD_TOP_TX_FIFO_ON_MASK 0x1
#define PMIC_RG_AUD_PAD_TOP_TX_FIFO_ON_SHIFT  8
#define PMIC_RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_ADDR  MT6358_AFE_AUD_PAD_TOP
#define PMIC_RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK  0x1
#define PMIC_RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_SHIFT 11
#define PMIC_RG_AUD_PAD_TOP_TX_FIFO_RSP_ADDR  MT6358_AFE_AUD_PAD_TOP
#define PMIC_RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK  0x7
#define PMIC_RG_AUD_PAD_TOP_TX_FIFO_RSP_SHIFT 12
#define PMIC_ADDA_AUD_PAD_TOP_MON_ADDR  MT6358_AFE_AUD_PAD_TOP_MON
#define PMIC_ADDA_AUD_PAD_TOP_MON_MASK  0xFFFF
#define PMIC_ADDA_AUD_PAD_TOP_MON_SHIFT 0
#define PMIC_ADDA_AUD_PAD_TOP_MON1_ADDR MT6358_AFE_AUD_PAD_TOP_MON1
#define PMIC_ADDA_AUD_PAD_TOP_MON1_MASK 0xFFFF
#define PMIC_ADDA_AUD_PAD_TOP_MON1_SHIFT   0
#define PMIC_NLE_LCH_ON_ADDR MT6358_AFE_DL_NLE_CFG
#define PMIC_NLE_LCH_ON_MASK 0x1
#define PMIC_NLE_LCH_ON_SHIFT   0
#define PMIC_NLE_LCH_CH_SEL_ADDR  MT6358_AFE_DL_NLE_CFG
#define PMIC_NLE_LCH_CH_SEL_MASK  0x1
#define PMIC_NLE_LCH_CH_SEL_SHIFT 1
#define PMIC_NLE_LCH_HPGAIN_SEL_ADDR  MT6358_AFE_DL_NLE_CFG
#define PMIC_NLE_LCH_HPGAIN_SEL_MASK  0x1
#define PMIC_NLE_LCH_HPGAIN_SEL_SHIFT 2
#define PMIC_NLE_RCH_ON_ADDR MT6358_AFE_DL_NLE_CFG
#define PMIC_NLE_RCH_ON_MASK 0x1
#define PMIC_NLE_RCH_ON_SHIFT   8
#define PMIC_NLE_RCH_CH_SEL_ADDR  MT6358_AFE_DL_NLE_CFG
#define PMIC_NLE_RCH_CH_SEL_MASK  0x1
#define PMIC_NLE_RCH_CH_SEL_SHIFT 9
#define PMIC_NLE_RCH_HPGAIN_SEL_ADDR  MT6358_AFE_DL_NLE_CFG
#define PMIC_NLE_RCH_HPGAIN_SEL_MASK  0x1
#define PMIC_NLE_RCH_HPGAIN_SEL_SHIFT 10
#define PMIC_NLE_MONITOR_ADDR   MT6358_AFE_DL_NLE_MON
#define PMIC_NLE_MONITOR_MASK   0x3FFF
#define PMIC_NLE_MONITOR_SHIFT  0
#define PMIC_CK_CG_EN_MON_ADDR  MT6358_AFE_CG_EN_MON
#define PMIC_CK_CG_EN_MON_MASK  0x3F
#define PMIC_CK_CG_EN_MON_SHIFT 0
#define PMIC_AUDIO_DIG_2ND_ANA_ID_ADDR  MT6358_AUDIO_DIG_2ND_DSN_ID
#define PMIC_AUDIO_DIG_2ND_ANA_ID_MASK  0xFF
#define PMIC_AUDIO_DIG_2ND_ANA_ID_SHIFT 0
#define PMIC_AUDIO_DIG_2ND_DIG_ID_ADDR  MT6358_AUDIO_DIG_2ND_DSN_ID
#define PMIC_AUDIO_DIG_2ND_DIG_ID_MASK  0xFF
#define PMIC_AUDIO_DIG_2ND_DIG_ID_SHIFT 8
#define PMIC_AUDIO_DIG_2ND_ANA_MINOR_REV_ADDR MT6358_AUDIO_DIG_2ND_DSN_REV0
#define PMIC_AUDIO_DIG_2ND_ANA_MINOR_REV_MASK 0xF
#define PMIC_AUDIO_DIG_2ND_ANA_MINOR_REV_SHIFT   0
#define PMIC_AUDIO_DIG_2ND_ANA_MAJOR_REV_ADDR MT6358_AUDIO_DIG_2ND_DSN_REV0
#define PMIC_AUDIO_DIG_2ND_ANA_MAJOR_REV_MASK 0xF
#define PMIC_AUDIO_DIG_2ND_ANA_MAJOR_REV_SHIFT   4
#define PMIC_AUDIO_DIG_2ND_DIG_MINOR_REV_ADDR MT6358_AUDIO_DIG_2ND_DSN_REV0
#define PMIC_AUDIO_DIG_2ND_DIG_MINOR_REV_MASK 0xF
#define PMIC_AUDIO_DIG_2ND_DIG_MINOR_REV_SHIFT   8
#define PMIC_AUDIO_DIG_2ND_DIG_MAJOR_REV_ADDR MT6358_AUDIO_DIG_2ND_DSN_REV0
#define PMIC_AUDIO_DIG_2ND_DIG_MAJOR_REV_MASK 0xF
#define PMIC_AUDIO_DIG_2ND_DIG_MAJOR_REV_SHIFT   12
#define PMIC_AUDIO_DIG_2ND_DSN_CBS_ADDR MT6358_AUDIO_DIG_2ND_DSN_DBI
#define PMIC_AUDIO_DIG_2ND_DSN_CBS_MASK 0x3
#define PMIC_AUDIO_DIG_2ND_DSN_CBS_SHIFT   0
#define PMIC_AUDIO_DIG_2ND_DSN_BIX_ADDR MT6358_AUDIO_DIG_2ND_DSN_DBI
#define PMIC_AUDIO_DIG_2ND_DSN_BIX_MASK 0x3
#define PMIC_AUDIO_DIG_2ND_DSN_BIX_SHIFT   2
#define PMIC_AUDIO_DIG_2ND_ESP_ADDR   MT6358_AUDIO_DIG_2ND_DSN_DBI
#define PMIC_AUDIO_DIG_2ND_ESP_MASK   0xFF
#define PMIC_AUDIO_DIG_2ND_ESP_SHIFT  8
#define PMIC_AUDIO_DIG_2ND_DSN_FPI_ADDR MT6358_AUDIO_DIG_2ND_DSN_DXI
#define PMIC_AUDIO_DIG_2ND_DSN_FPI_MASK 0xFF
#define PMIC_AUDIO_DIG_2ND_DSN_FPI_SHIFT   0
#define PMIC_RG_UP8X_SYNC_WORD_ADDR   MT6358_AFE_PMIC_NEWIF_CFG3
#define PMIC_RG_UP8X_SYNC_WORD_MASK   0xFFFF
#define PMIC_RG_UP8X_SYNC_WORD_SHIFT  0
#define PMIC_VOW_INTR_FLAG_ADDR MT6358_AFE_VOW_TOP
#define PMIC_VOW_INTR_FLAG_MASK 0x1
#define PMIC_VOW_INTR_FLAG_SHIFT  0
#define PMIC_SAMPLE_BASE_MODE_ADDR MT6358_AFE_VOW_TOP
#define PMIC_SAMPLE_BASE_MODE_MASK 0x1
#define PMIC_SAMPLE_BASE_MODE_SHIFT   1
#define PMIC_S_N_VALUE_RST_ADDR MT6358_AFE_VOW_TOP
#define PMIC_S_N_VALUE_RST_MASK 0x1
#define PMIC_S_N_VALUE_RST_SHIFT  2
#define PMIC_VOW_INTR_CLR_ADDR  MT6358_AFE_VOW_TOP
#define PMIC_VOW_INTR_CLR_MASK  0x1
#define PMIC_VOW_INTR_CLR_SHIFT 3
#define PMIC_VOW_INTR_SOURCE_SEL_ADDR MT6358_AFE_VOW_TOP
#define PMIC_VOW_INTR_SOURCE_SEL_MASK 0x1
#define PMIC_VOW_INTR_SOURCE_SEL_SHIFT  4
#define PMIC_VOW_LOOP_BACK_MODE_ADDR  MT6358_AFE_VOW_TOP
#define PMIC_VOW_LOOP_BACK_MODE_MASK  0x1
#define PMIC_VOW_LOOP_BACK_MODE_SHIFT 5
#define PMIC_VOW_SDM_3_LEVEL_ADDR MT6358_AFE_VOW_TOP
#define PMIC_VOW_SDM_3_LEVEL_MASK 0x1
#define PMIC_VOW_SDM_3_LEVEL_SHIFT 6
#define PMIC_MAIN_DMIC_CK_VOW_SEL_ADDR  MT6358_AFE_VOW_TOP
#define PMIC_MAIN_DMIC_CK_VOW_SEL_MASK  0x1
#define PMIC_MAIN_DMIC_CK_VOW_SEL_SHIFT 7
#define PMIC_VOW_DIGMIC_CK_PHASE_SEL_ADDR   MT6358_AFE_VOW_TOP
#define PMIC_VOW_DIGMIC_CK_PHASE_SEL_MASK   0x7
#define PMIC_VOW_DIGMIC_CK_PHASE_SEL_SHIFT  8
#define PMIC_VOW_ON_ADDR  MT6358_AFE_VOW_TOP
#define PMIC_VOW_ON_MASK  0x1
#define PMIC_VOW_ON_SHIFT 11
#define PMIC_VOW_CK_DIV_RST_ADDR  MT6358_AFE_VOW_TOP
#define PMIC_VOW_CK_DIV_RST_MASK  0x1
#define PMIC_VOW_CK_DIV_RST_SHIFT 12
#define PMIC_VOW_DIGMIC_ON_ADDR MT6358_AFE_VOW_TOP
#define PMIC_VOW_DIGMIC_ON_MASK 0x1
#define PMIC_VOW_DIGMIC_ON_SHIFT  13
#define PMIC_VOW_1P6M_800K_SEL_ADDR   MT6358_AFE_VOW_TOP
#define PMIC_VOW_1P6M_800K_SEL_MASK   0x1
#define PMIC_VOW_1P6M_800K_SEL_SHIFT  14
#define PMIC_PDN_VOW_ADDR MT6358_AFE_VOW_TOP
#define PMIC_PDN_VOW_MASK 0x1
#define PMIC_PDN_VOW_SHIFT  15
#define PMIC_AMPREF_ADDR  MT6358_AFE_VOW_CFG0
#define PMIC_AMPREF_MASK  0xFFFF
#define PMIC_AMPREF_SHIFT 0
#define PMIC_TIMERINI_ADDR  MT6358_AFE_VOW_CFG1
#define PMIC_TIMERINI_MASK  0xFFFF
#define PMIC_TIMERINI_SHIFT  0
#define PMIC_A_INI_ADDR   MT6358_AFE_VOW_CFG2
#define PMIC_A_INI_MASK   0x7
#define PMIC_A_INI_SHIFT  0
#define PMIC_B_INI_ADDR   MT6358_AFE_VOW_CFG2
#define PMIC_B_INI_MASK   0x7
#define PMIC_B_INI_SHIFT  4
#define PMIC_A_DEFAULT_ADDR  MT6358_AFE_VOW_CFG2
#define PMIC_A_DEFAULT_MASK  0x7
#define PMIC_A_DEFAULT_SHIFT 8
#define PMIC_B_DEFAULT_ADDR  MT6358_AFE_VOW_CFG2
#define PMIC_B_DEFAULT_MASK  0x7
#define PMIC_B_DEFAULT_SHIFT 12
#define PMIC_K_ALPHA_FALL_ADDR  MT6358_AFE_VOW_CFG3
#define PMIC_K_ALPHA_FALL_MASK  0xF
#define PMIC_K_ALPHA_FALL_SHIFT 0
#define PMIC_K_ALPHA_RISE_ADDR  MT6358_AFE_VOW_CFG3
#define PMIC_K_ALPHA_RISE_MASK  0xF
#define PMIC_K_ALPHA_RISE_SHIFT 4
#define PMIC_K_BETA_FALL_ADDR   MT6358_AFE_VOW_CFG3
#define PMIC_K_BETA_FALL_MASK   0xF
#define PMIC_K_BETA_FALL_SHIFT  8
#define PMIC_K_BETA_RISE_ADDR   MT6358_AFE_VOW_CFG3
#define PMIC_K_BETA_RISE_MASK   0xF
#define PMIC_K_BETA_RISE_SHIFT  12
#define PMIC_K_GAMMA_ADDR MT6358_AFE_VOW_CFG4
#define PMIC_K_GAMMA_MASK 0xF
#define PMIC_K_GAMMA_SHIFT  0
#define PMIC_VOW_TXIF_SCK_DIV_ADDR MT6358_AFE_VOW_CFG4
#define PMIC_VOW_TXIF_SCK_DIV_MASK 0x1F
#define PMIC_VOW_TXIF_SCK_DIV_SHIFT   4
#define PMIC_VOW_TXIF_MONO_ADDR MT6358_AFE_VOW_CFG4
#define PMIC_VOW_TXIF_MONO_MASK 0x1
#define PMIC_VOW_TXIF_MONO_SHIFT  9
#define PMIC_VOW_ADC_CLK_INV_ADDR MT6358_AFE_VOW_CFG4
#define PMIC_VOW_ADC_CLK_INV_MASK 0x1
#define PMIC_VOW_ADC_CLK_INV_SHIFT 10
#define PMIC_VOW_ADC_TESTCK_SEL_ADDR  MT6358_AFE_VOW_CFG4
#define PMIC_VOW_ADC_TESTCK_SEL_MASK  0x1
#define PMIC_VOW_ADC_TESTCK_SEL_SHIFT 11
#define PMIC_VOW_ADC_TESTCK_SRC_SEL_ADDR   MT6358_AFE_VOW_CFG4
#define PMIC_VOW_ADC_TESTCK_SRC_SEL_MASK   0x7
#define PMIC_VOW_ADC_TESTCK_SRC_SEL_SHIFT   12
#define PMIC_VOW_TXIF_SCK_INV_ADDR MT6358_AFE_VOW_CFG4
#define PMIC_VOW_TXIF_SCK_INV_MASK 0x1
#define PMIC_VOW_TXIF_SCK_INV_SHIFT   15
#define PMIC_N_MIN_ADDR   MT6358_AFE_VOW_CFG5
#define PMIC_N_MIN_MASK   0xFFFF
#define PMIC_N_MIN_SHIFT  0
#define PMIC_RG_BUCK_DVFS_HW_CNT_THR_ADDR   MT6358_AFE_VOW_CFG6
#define PMIC_RG_BUCK_DVFS_HW_CNT_THR_MASK   0x3F
#define PMIC_RG_BUCK_DVFS_HW_CNT_THR_SHIFT  0
#define PMIC_RG_BUCK_DVFS_DONE_HW_MODE_ADDR MT6358_AFE_VOW_CFG6
#define PMIC_RG_BUCK_DVFS_DONE_HW_MODE_MASK 0x1
#define PMIC_RG_BUCK_DVFS_DONE_HW_MODE_SHIFT  6
#define PMIC_RG_BUCK_DVFS_DONE_SW_CTL_ADDR  MT6358_AFE_VOW_CFG6
#define PMIC_RG_BUCK_DVFS_DONE_SW_CTL_MASK  0x1
#define PMIC_RG_BUCK_DVFS_DONE_SW_CTL_SHIFT 7
#define PMIC_RG_FLR_RATIO_ADDR  MT6358_AFE_VOW_CFG6
#define PMIC_RG_FLR_RATIO_MASK  0x7
#define PMIC_RG_FLR_RATIO_SHIFT 8
#define PMIC_RG_FLR_BYPASS_ADDR MT6358_AFE_VOW_CFG6
#define PMIC_RG_FLR_BYPASS_MASK 0x1
#define PMIC_RG_FLR_BYPASS_SHIFT  11
#define PMIC_RG_WINDOW_SIZE_SEL_ADDR  MT6358_AFE_VOW_CFG6
#define PMIC_RG_WINDOW_SIZE_SEL_MASK  0x1
#define PMIC_RG_WINDOW_SIZE_SEL_SHIFT 12
#define PMIC_VOW_DOWNCNT_ADDR   MT6358_AFE_VOW_MON0
#define PMIC_VOW_DOWNCNT_MASK   0xFFFF
#define PMIC_VOW_DOWNCNT_SHIFT  0
#define PMIC_SECOND_CNT_START_ADDR MT6358_AFE_VOW_MON1
#define PMIC_SECOND_CNT_START_MASK 0x1
#define PMIC_SECOND_CNT_START_SHIFT   0
#define PMIC_VOW_A_ADDR   MT6358_AFE_VOW_MON1
#define PMIC_VOW_A_MASK   0x7
#define PMIC_VOW_A_SHIFT  1
#define PMIC_VOW_B_ADDR   MT6358_AFE_VOW_MON1
#define PMIC_VOW_B_MASK   0x7
#define PMIC_VOW_B_SHIFT  4
#define PMIC_SLT_COUNTER_MON_ADDR MT6358_AFE_VOW_MON1
#define PMIC_SLT_COUNTER_MON_MASK 0x7
#define PMIC_SLT_COUNTER_MON_SHIFT 7
#define PMIC_K_TMP_MON_ADDR  MT6358_AFE_VOW_MON1
#define PMIC_K_TMP_MON_MASK  0xF
#define PMIC_K_TMP_MON_SHIFT 10
#define PMIC_VOW_S_L_ADDR MT6358_AFE_VOW_MON2
#define PMIC_VOW_S_L_MASK 0xFFFF
#define PMIC_VOW_S_L_SHIFT  0
#define PMIC_VOW_S_H_ADDR MT6358_AFE_VOW_MON3
#define PMIC_VOW_S_H_MASK 0xFFFF
#define PMIC_VOW_S_H_SHIFT  0
#define PMIC_VOW_N_L_ADDR MT6358_AFE_VOW_MON4
#define PMIC_VOW_N_L_MASK 0xFFFF
#define PMIC_VOW_N_L_SHIFT  0
#define PMIC_VOW_N_H_ADDR MT6358_AFE_VOW_MON5
#define PMIC_VOW_N_H_MASK 0xFFFF
#define PMIC_VOW_N_H_SHIFT  0
#define PMIC_VOW_SN_INI_CFG_VAL_ADDR  MT6358_AFE_VOW_SN_INI_CFG
#define PMIC_VOW_SN_INI_CFG_VAL_MASK  0x7FFF
#define PMIC_VOW_SN_INI_CFG_VAL_SHIFT 0
#define PMIC_VOW_SN_INI_CFG_EN_ADDR   MT6358_AFE_VOW_SN_INI_CFG
#define PMIC_VOW_SN_INI_CFG_EN_MASK   0x1
#define PMIC_VOW_SN_INI_CFG_EN_SHIFT  15
#define PMIC_VOW_TGEN_FREQ_DIV_ADDR   MT6358_AFE_VOW_TGEN_CFG0
#define PMIC_VOW_TGEN_FREQ_DIV_MASK   0x3FFF
#define PMIC_VOW_TGEN_FREQ_DIV_SHIFT  0
#define PMIC_VOW_TGEN_MUTE_SW_ADDR MT6358_AFE_VOW_TGEN_CFG0
#define PMIC_VOW_TGEN_MUTE_SW_MASK 0x1
#define PMIC_VOW_TGEN_MUTE_SW_SHIFT   14
#define PMIC_VOW_TGEN_EN_ADDR   MT6358_AFE_VOW_TGEN_CFG0
#define PMIC_VOW_TGEN_EN_MASK   0x1
#define PMIC_VOW_TGEN_EN_SHIFT  15
#define PMIC_RG_VOW_POSDIV_ADDR MT6358_AFE_VOW_POSDIV_CFG0
#define PMIC_RG_VOW_POSDIV_MASK 0x3
#define PMIC_RG_VOW_POSDIV_SHIFT  0
#define PMIC_VOW_CIC_MODE_SEL_ADDR MT6358_AFE_VOW_POSDIV_CFG0
#define PMIC_VOW_CIC_MODE_SEL_MASK 0x3
#define PMIC_VOW_CIC_MODE_SEL_SHIFT   2
#define PMIC_VOW_INTR_SW_VAL_ADDR MT6358_AFE_VOW_POSDIV_CFG0
#define PMIC_VOW_INTR_SW_VAL_MASK 0x1
#define PMIC_VOW_INTR_SW_VAL_SHIFT 4
#define PMIC_VOW_INTR_SW_MODE_ADDR MT6358_AFE_VOW_POSDIV_CFG0
#define PMIC_VOW_INTR_SW_MODE_MASK 0x1
#define PMIC_VOW_INTR_SW_MODE_SHIFT   5
#define PMIC_VOW_CLK_SEL_ADDR   MT6358_AFE_VOW_POSDIV_CFG0
#define PMIC_VOW_CLK_SEL_MASK   0x1
#define PMIC_VOW_CLK_SEL_SHIFT  6
#define PMIC_RG_A1P6M_EN_SEL_ADDR MT6358_AFE_VOW_POSDIV_CFG0
#define PMIC_RG_A1P6M_EN_SEL_MASK 0x1
#define PMIC_RG_A1P6M_EN_SEL_SHIFT 7
#define PMIC_RG_BUCK_CLK_DIV_ADDR MT6358_AFE_VOW_POSDIV_CFG0
#define PMIC_RG_BUCK_CLK_DIV_MASK 0x1F
#define PMIC_RG_BUCK_CLK_DIV_SHIFT 8
#define PMIC_VOW_32K_MODE_ADDR  MT6358_AFE_VOW_POSDIV_CFG0
#define PMIC_VOW_32K_MODE_MASK  0x1
#define PMIC_VOW_32K_MODE_SHIFT 13
#define PMIC_BUCK_DVFS_DONE_ADDR  MT6358_AFE_VOW_POSDIV_CFG0
#define PMIC_BUCK_DVFS_DONE_MASK  0x1
#define PMIC_BUCK_DVFS_DONE_SHIFT 15
#define PMIC_RG_HPF_ON_ADDR  MT6358_AFE_VOW_HPF_CFG0
#define PMIC_RG_HPF_ON_MASK  0x1
#define PMIC_RG_HPF_ON_SHIFT 0
#define PMIC_RG_SNRDET_HPF_BYPASS_ADDR  MT6358_AFE_VOW_HPF_CFG0
#define PMIC_RG_SNRDET_HPF_BYPASS_MASK  0x1
#define PMIC_RG_SNRDET_HPF_BYPASS_SHIFT 1
#define PMIC_RG_MTKAIF_HPF_BYPASS_ADDR  MT6358_AFE_VOW_HPF_CFG0
#define PMIC_RG_MTKAIF_HPF_BYPASS_MASK  0x1
#define PMIC_RG_MTKAIF_HPF_BYPASS_SHIFT 2
#define PMIC_RG_BASELINE_ALPHA_ORDER_ADDR   MT6358_AFE_VOW_HPF_CFG0
#define PMIC_RG_BASELINE_ALPHA_ORDER_MASK   0xF
#define PMIC_RG_BASELINE_ALPHA_ORDER_SHIFT  4
#define PMIC_VOW_POSDIVCLK_PDN_ADDR   MT6358_AFE_VOW_HPF_CFG0
#define PMIC_VOW_POSDIVCLK_PDN_MASK   0x1
#define PMIC_VOW_POSDIVCLK_PDN_SHIFT  8
#define PMIC_VOW_DMICCLK_PDN_ADDR MT6358_AFE_VOW_HPF_CFG0
#define PMIC_VOW_DMICCLK_PDN_MASK 0x1
#define PMIC_VOW_DMICCLK_PDN_SHIFT 9
#define PMIC_VOW_IRQ_LATCH_SNR_EN_ADDR  MT6358_AFE_VOW_HPF_CFG0
#define PMIC_VOW_IRQ_LATCH_SNR_EN_MASK  0x1
#define PMIC_VOW_IRQ_LATCH_SNR_EN_SHIFT 10
#define PMIC_VOW_HPF_DC_TEST_ADDR MT6358_AFE_VOW_HPF_CFG0
#define PMIC_VOW_HPF_DC_TEST_MASK 0xF
#define PMIC_VOW_HPF_DC_TEST_SHIFT 12
#define PMIC_RG_PERIODIC_CNT_PERIOD_ADDR   MT6358_AFE_VOW_PERIODIC_CFG0
#define PMIC_RG_PERIODIC_CNT_PERIOD_MASK   0x3FFF
#define PMIC_RG_PERIODIC_CNT_PERIOD_SHIFT   0
#define PMIC_RG_PERIODIC_CNT_CLR_ADDR MT6358_AFE_VOW_PERIODIC_CFG0
#define PMIC_RG_PERIODIC_CNT_CLR_MASK 0x1
#define PMIC_RG_PERIODIC_CNT_CLR_SHIFT  14
#define PMIC_RG_PERIODIC_EN_ADDR  MT6358_AFE_VOW_PERIODIC_CFG0
#define PMIC_RG_PERIODIC_EN_MASK  0x1
#define PMIC_RG_PERIODIC_EN_SHIFT 15
#define PMIC_RG_PERIODIC_CNT_SET_VALUE_ADDR MT6358_AFE_VOW_PERIODIC_CFG1
#define PMIC_RG_PERIODIC_CNT_SET_VALUE_MASK 0x3FFF
#define PMIC_RG_PERIODIC_CNT_SET_VALUE_SHIFT  0
#define PMIC_RG_PERIODIC_CNT_PAUSE_ADDR MT6358_AFE_VOW_PERIODIC_CFG1
#define PMIC_RG_PERIODIC_CNT_PAUSE_MASK 0x1
#define PMIC_RG_PERIODIC_CNT_PAUSE_SHIFT   14
#define PMIC_RG_PERIODIC_CNT_SET_ADDR MT6358_AFE_VOW_PERIODIC_CFG1
#define PMIC_RG_PERIODIC_CNT_SET_MASK 0x1
#define PMIC_RG_PERIODIC_CNT_SET_SHIFT  15
#define PMIC_AUDPREAMPLON_PERIODIC_ON_CYCLE_ADDR  MT6358_AFE_VOW_PERIODIC_CFG2
#define PMIC_AUDPREAMPLON_PERIODIC_ON_CYCLE_MASK  0x3FFF
#define PMIC_AUDPREAMPLON_PERIODIC_ON_CYCLE_SHIFT 0
#define PMIC_AUDPREAMPLON_PERIODIC_INVERSE_ADDR  MT6358_AFE_VOW_PERIODIC_CFG2
#define PMIC_AUDPREAMPLON_PERIODIC_INVERSE_MASK  0x1
#define PMIC_AUDPREAMPLON_PERIODIC_INVERSE_SHIFT  14
#define PMIC_AUDPREAMPLON_PERIODIC_MODE_ADDR  MT6358_AFE_VOW_PERIODIC_CFG2
#define PMIC_AUDPREAMPLON_PERIODIC_MODE_MASK  0x1
#define PMIC_AUDPREAMPLON_PERIODIC_MODE_SHIFT 15
#define PMIC_AUDPREAMPLDCPRECHARGE_PERIODIC_ON_CYCLE_ADDR \
MT6358_AFE_VOW_PERIODIC_CFG3
#define PMIC_AUDPREAMPLDCPRECHARGE_PERIODIC_ON_CYCLE_MASK 0x3FFF
#define PMIC_AUDPREAMPLDCPRECHARGE_PERIODIC_ON_CYCLE_SHIFT   0
#define PMIC_AUDPREAMPLDCPRECHARGE_PERIODIC_INVERSE_ADDR  \
MT6358_AFE_VOW_PERIODIC_CFG3
#define PMIC_AUDPREAMPLDCPRECHARGE_PERIODIC_INVERSE_MASK  0x1
#define PMIC_AUDPREAMPLDCPRECHARGE_PERIODIC_INVERSE_SHIFT 14
#define PMIC_AUDPREAMPLDCPRECHARGE_PERIODIC_MODE_ADDR  \
MT6358_AFE_VOW_PERIODIC_CFG3
#define PMIC_AUDPREAMPLDCPRECHARGE_PERIODIC_MODE_MASK  0x1
#define PMIC_AUDPREAMPLDCPRECHARGE_PERIODIC_MODE_SHIFT 15
#define PMIC_AUDADCLPWRUP_PERIODIC_ON_CYCLE_ADDR  MT6358_AFE_VOW_PERIODIC_CFG4
#define PMIC_AUDADCLPWRUP_PERIODIC_ON_CYCLE_MASK  0x3FFF
#define PMIC_AUDADCLPWRUP_PERIODIC_ON_CYCLE_SHIFT 0
#define PMIC_AUDADCLPWRUP_PERIODIC_INVERSE_ADDR  MT6358_AFE_VOW_PERIODIC_CFG4
#define PMIC_AUDADCLPWRUP_PERIODIC_INVERSE_MASK  0x1
#define PMIC_AUDADCLPWRUP_PERIODIC_INVERSE_SHIFT  14
#define PMIC_AUDADCLPWRUP_PERIODIC_MODE_ADDR  MT6358_AFE_VOW_PERIODIC_CFG4
#define PMIC_AUDADCLPWRUP_PERIODIC_MODE_MASK  0x1
#define PMIC_AUDADCLPWRUP_PERIODIC_MODE_SHIFT 15
#define PMIC_AUDGLBVOWLPWEN_PERIODIC_ON_CYCLE_ADDR  \
MT6358_AFE_VOW_PERIODIC_CFG5
#define PMIC_AUDGLBVOWLPWEN_PERIODIC_ON_CYCLE_MASK  0x3FFF
#define PMIC_AUDGLBVOWLPWEN_PERIODIC_ON_CYCLE_SHIFT 0
#define PMIC_AUDGLBVOWLPWEN_PERIODIC_INVERSE_ADDR MT6358_AFE_VOW_PERIODIC_CFG5
#define PMIC_AUDGLBVOWLPWEN_PERIODIC_INVERSE_MASK 0x1
#define PMIC_AUDGLBVOWLPWEN_PERIODIC_INVERSE_SHIFT  14
#define PMIC_AUDGLBVOWLPWEN_PERIODIC_MODE_ADDR   MT6358_AFE_VOW_PERIODIC_CFG5
#define PMIC_AUDGLBVOWLPWEN_PERIODIC_MODE_MASK   0x1
#define PMIC_AUDGLBVOWLPWEN_PERIODIC_MODE_SHIFT  15
#define PMIC_AUDDIGMICEN_PERIODIC_ON_CYCLE_ADDR  MT6358_AFE_VOW_PERIODIC_CFG6
#define PMIC_AUDDIGMICEN_PERIODIC_ON_CYCLE_MASK  0x3FFF
#define PMIC_AUDDIGMICEN_PERIODIC_ON_CYCLE_SHIFT  0
#define PMIC_AUDDIGMICEN_PERIODIC_INVERSE_ADDR   MT6358_AFE_VOW_PERIODIC_CFG6
#define PMIC_AUDDIGMICEN_PERIODIC_INVERSE_MASK   0x1
#define PMIC_AUDDIGMICEN_PERIODIC_INVERSE_SHIFT  14
#define PMIC_AUDDIGMICEN_PERIODIC_MODE_ADDR MT6358_AFE_VOW_PERIODIC_CFG6
#define PMIC_AUDDIGMICEN_PERIODIC_MODE_MASK 0x1
#define PMIC_AUDDIGMICEN_PERIODIC_MODE_SHIFT  15
#define PMIC_AUDPWDBMICBIAS0_PERIODIC_ON_CYCLE_ADDR MT6358_AFE_VOW_PERIODIC_CFG7
#define PMIC_AUDPWDBMICBIAS0_PERIODIC_ON_CYCLE_MASK 0x3FFF
#define PMIC_AUDPWDBMICBIAS0_PERIODIC_ON_CYCLE_SHIFT   0
#define PMIC_AUDPWDBMICBIAS0_PERIODIC_INVERSE_ADDR  MT6358_AFE_VOW_PERIODIC_CFG7
#define PMIC_AUDPWDBMICBIAS0_PERIODIC_INVERSE_MASK  0x1
#define PMIC_AUDPWDBMICBIAS0_PERIODIC_INVERSE_SHIFT 14
#define PMIC_AUDPWDBMICBIAS0_PERIODIC_MODE_ADDR  MT6358_AFE_VOW_PERIODIC_CFG7
#define PMIC_AUDPWDBMICBIAS0_PERIODIC_MODE_MASK  0x1
#define PMIC_AUDPWDBMICBIAS0_PERIODIC_MODE_SHIFT  15
#define PMIC_AUDPWDBMICBIAS1_PERIODIC_ON_CYCLE_ADDR MT6358_AFE_VOW_PERIODIC_CFG8
#define PMIC_AUDPWDBMICBIAS1_PERIODIC_ON_CYCLE_MASK 0x3FFF
#define PMIC_AUDPWDBMICBIAS1_PERIODIC_ON_CYCLE_SHIFT   0
#define PMIC_AUDPWDBMICBIAS1_PERIODIC_INVERSE_ADDR  MT6358_AFE_VOW_PERIODIC_CFG8
#define PMIC_AUDPWDBMICBIAS1_PERIODIC_INVERSE_MASK  0x1
#define PMIC_AUDPWDBMICBIAS1_PERIODIC_INVERSE_SHIFT 14
#define PMIC_AUDPWDBMICBIAS1_PERIODIC_MODE_ADDR  MT6358_AFE_VOW_PERIODIC_CFG8
#define PMIC_AUDPWDBMICBIAS1_PERIODIC_MODE_MASK  0x1
#define PMIC_AUDPWDBMICBIAS1_PERIODIC_MODE_SHIFT  15
#define PMIC_XO_VOW_CK_EN_PERIODIC_ON_CYCLE_ADDR  MT6358_AFE_VOW_PERIODIC_CFG9
#define PMIC_XO_VOW_CK_EN_PERIODIC_ON_CYCLE_MASK  0x3FFF
#define PMIC_XO_VOW_CK_EN_PERIODIC_ON_CYCLE_SHIFT 0
#define PMIC_XO_VOW_CK_EN_PERIODIC_INVERSE_ADDR  MT6358_AFE_VOW_PERIODIC_CFG9
#define PMIC_XO_VOW_CK_EN_PERIODIC_INVERSE_MASK  0x1
#define PMIC_XO_VOW_CK_EN_PERIODIC_INVERSE_SHIFT  14
#define PMIC_XO_VOW_CK_EN_PERIODIC_MODE_ADDR  MT6358_AFE_VOW_PERIODIC_CFG9
#define PMIC_XO_VOW_CK_EN_PERIODIC_MODE_MASK  0x1
#define PMIC_XO_VOW_CK_EN_PERIODIC_MODE_SHIFT 15
#define PMIC_AUDGLB_PWRDN_PERIODIC_ON_CYCLE_ADDR  MT6358_AFE_VOW_PERIODIC_CFG10
#define PMIC_AUDGLB_PWRDN_PERIODIC_ON_CYCLE_MASK  0x3FFF
#define PMIC_AUDGLB_PWRDN_PERIODIC_ON_CYCLE_SHIFT 0
#define PMIC_AUDGLB_PWRDN_PERIODIC_INVERSE_ADDR  MT6358_AFE_VOW_PERIODIC_CFG10
#define PMIC_AUDGLB_PWRDN_PERIODIC_INVERSE_MASK  0x1
#define PMIC_AUDGLB_PWRDN_PERIODIC_INVERSE_SHIFT  14
#define PMIC_AUDGLB_PWRDN_PERIODIC_MODE_ADDR  MT6358_AFE_VOW_PERIODIC_CFG10
#define PMIC_AUDGLB_PWRDN_PERIODIC_MODE_MASK  0x1
#define PMIC_AUDGLB_PWRDN_PERIODIC_MODE_SHIFT 15
#define PMIC_VOW_ON_PERIODIC_ON_CYCLE_ADDR  MT6358_AFE_VOW_PERIODIC_CFG11
#define PMIC_VOW_ON_PERIODIC_ON_CYCLE_MASK  0x3FFF
#define PMIC_VOW_ON_PERIODIC_ON_CYCLE_SHIFT 0
#define PMIC_VOW_ON_PERIODIC_INVERSE_ADDR   MT6358_AFE_VOW_PERIODIC_CFG11
#define PMIC_VOW_ON_PERIODIC_INVERSE_MASK   0x1
#define PMIC_VOW_ON_PERIODIC_INVERSE_SHIFT  14
#define PMIC_VOW_ON_PERIODIC_MODE_ADDR  MT6358_AFE_VOW_PERIODIC_CFG11
#define PMIC_VOW_ON_PERIODIC_MODE_MASK  0x1
#define PMIC_VOW_ON_PERIODIC_MODE_SHIFT 15
#define PMIC_DMIC_ON_PERIODIC_ON_CYCLE_ADDR MT6358_AFE_VOW_PERIODIC_CFG12
#define PMIC_DMIC_ON_PERIODIC_ON_CYCLE_MASK 0x3FFF
#define PMIC_DMIC_ON_PERIODIC_ON_CYCLE_SHIFT  0
#define PMIC_DMIC_ON_PERIODIC_INVERSE_ADDR  MT6358_AFE_VOW_PERIODIC_CFG12
#define PMIC_DMIC_ON_PERIODIC_INVERSE_MASK  0x1
#define PMIC_DMIC_ON_PERIODIC_INVERSE_SHIFT 14
#define PMIC_DMIC_ON_PERIODIC_MODE_ADDR MT6358_AFE_VOW_PERIODIC_CFG12
#define PMIC_DMIC_ON_PERIODIC_MODE_MASK 0x1
#define PMIC_DMIC_ON_PERIODIC_MODE_SHIFT   15
#define PMIC_AUDPREAMPLON_PERIODIC_OFF_CYCLE_ADDR MT6358_AFE_VOW_PERIODIC_CFG13
#define PMIC_AUDPREAMPLON_PERIODIC_OFF_CYCLE_MASK 0x3FFF
#define PMIC_AUDPREAMPLON_PERIODIC_OFF_CYCLE_SHIFT  0
#define PMIC_PDN_VOW_F32K_CK_ADDR MT6358_AFE_VOW_PERIODIC_CFG13
#define PMIC_PDN_VOW_F32K_CK_MASK 0x1
#define PMIC_PDN_VOW_F32K_CK_SHIFT 15
#define PMIC_AUDPREAMPLDCPRECHARGE_PERIODIC_OFF_CYCLE_ADDR   \
MT6358_AFE_VOW_PERIODIC_CFG14
#define PMIC_AUDPREAMPLDCPRECHARGE_PERIODIC_OFF_CYCLE_MASK   0x3FFF
#define PMIC_AUDPREAMPLDCPRECHARGE_PERIODIC_OFF_CYCLE_SHIFT  0
#define PMIC_VOW_SNRDET_PERIODIC_CFG_ADDR   MT6358_AFE_VOW_PERIODIC_CFG14
#define PMIC_VOW_SNRDET_PERIODIC_CFG_MASK   0x1
#define PMIC_VOW_SNRDET_PERIODIC_CFG_SHIFT  15
#define PMIC_AUDADCLPWRUP_PERIODIC_OFF_CYCLE_ADDR MT6358_AFE_VOW_PERIODIC_CFG15
#define PMIC_AUDADCLPWRUP_PERIODIC_OFF_CYCLE_MASK 0x3FFF
#define PMIC_AUDADCLPWRUP_PERIODIC_OFF_CYCLE_SHIFT  0
#define PMIC_AUDGLBVOWLPWEN_PERIODIC_OFF_CYCLE_ADDR \
MT6358_AFE_VOW_PERIODIC_CFG16
#define PMIC_AUDGLBVOWLPWEN_PERIODIC_OFF_CYCLE_MASK 0x3FFF
#define PMIC_AUDGLBVOWLPWEN_PERIODIC_OFF_CYCLE_SHIFT   0
#define PMIC_AUDDIGMICEN_PERIODIC_OFF_CYCLE_ADDR  MT6358_AFE_VOW_PERIODIC_CFG17
#define PMIC_AUDDIGMICEN_PERIODIC_OFF_CYCLE_MASK  0x3FFF
#define PMIC_AUDDIGMICEN_PERIODIC_OFF_CYCLE_SHIFT 0
#define PMIC_AUDPWDBMICBIAS0_PERIODIC_OFF_CYCLE_ADDR   \
MT6358_AFE_VOW_PERIODIC_CFG18
#define PMIC_AUDPWDBMICBIAS0_PERIODIC_OFF_CYCLE_MASK   0x3FFF
#define PMIC_AUDPWDBMICBIAS0_PERIODIC_OFF_CYCLE_SHIFT  0
#define PMIC_AUDPWDBMICBIAS1_PERIODIC_OFF_CYCLE_ADDR   \
MT6358_AFE_VOW_PERIODIC_CFG19
#define PMIC_AUDPWDBMICBIAS1_PERIODIC_OFF_CYCLE_MASK   0x3FFF
#define PMIC_AUDPWDBMICBIAS1_PERIODIC_OFF_CYCLE_SHIFT  0
#define PMIC_XO_VOW_CK_EN_PERIODIC_OFF_CYCLE_ADDR MT6358_AFE_VOW_PERIODIC_CFG20
#define PMIC_XO_VOW_CK_EN_PERIODIC_OFF_CYCLE_MASK 0x3FFF
#define PMIC_XO_VOW_CK_EN_PERIODIC_OFF_CYCLE_SHIFT  0
#define PMIC_CLKSQ_EN_VOW_PERIODIC_MODE_ADDR  MT6358_AFE_VOW_PERIODIC_CFG20
#define PMIC_CLKSQ_EN_VOW_PERIODIC_MODE_MASK  0x1
#define PMIC_CLKSQ_EN_VOW_PERIODIC_MODE_SHIFT 15
#define PMIC_AUDGLB_PWRDN_PERIODIC_OFF_CYCLE_ADDR MT6358_AFE_VOW_PERIODIC_CFG21
#define PMIC_AUDGLB_PWRDN_PERIODIC_OFF_CYCLE_MASK 0x3FFF
#define PMIC_AUDGLB_PWRDN_PERIODIC_OFF_CYCLE_SHIFT  0
#define PMIC_VOW_ON_PERIODIC_OFF_CYCLE_ADDR MT6358_AFE_VOW_PERIODIC_CFG22
#define PMIC_VOW_ON_PERIODIC_OFF_CYCLE_MASK 0x3FFF
#define PMIC_VOW_ON_PERIODIC_OFF_CYCLE_SHIFT  0
#define PMIC_DMIC_ON_PERIODIC_OFF_CYCLE_ADDR  MT6358_AFE_VOW_PERIODIC_CFG23
#define PMIC_DMIC_ON_PERIODIC_OFF_CYCLE_MASK  0x3FFF
#define PMIC_DMIC_ON_PERIODIC_OFF_CYCLE_SHIFT 0
#define PMIC_VOW_PERIODIC_MON_ADDR MT6358_AFE_VOW_PERIODIC_MON0
#define PMIC_VOW_PERIODIC_MON_MASK 0xFFFF
#define PMIC_VOW_PERIODIC_MON_SHIFT   0
#define PMIC_VOW_PERIODIC_COUNT_MON_ADDR   MT6358_AFE_VOW_PERIODIC_MON1
#define PMIC_VOW_PERIODIC_COUNT_MON_MASK   0xFFFF
#define PMIC_VOW_PERIODIC_COUNT_MON_SHIFT   0
#define PMIC_AUDENC_ANA_ID_ADDR MT6358_AUDENC_DSN_ID
#define PMIC_AUDENC_ANA_ID_MASK 0xFF
#define PMIC_AUDENC_ANA_ID_SHIFT  0
#define PMIC_AUDENC_DIG_ID_ADDR MT6358_AUDENC_DSN_ID
#define PMIC_AUDENC_DIG_ID_MASK 0xFF
#define PMIC_AUDENC_DIG_ID_SHIFT  8
#define PMIC_AUDENC_ANA_MINOR_REV_ADDR  MT6358_AUDENC_DSN_REV0
#define PMIC_AUDENC_ANA_MINOR_REV_MASK  0xF
#define PMIC_AUDENC_ANA_MINOR_REV_SHIFT 0
#define PMIC_AUDENC_ANA_MAJOR_REV_ADDR  MT6358_AUDENC_DSN_REV0
#define PMIC_AUDENC_ANA_MAJOR_REV_MASK  0xF
#define PMIC_AUDENC_ANA_MAJOR_REV_SHIFT 4
#define PMIC_AUDENC_DIG_MINOR_REV_ADDR  MT6358_AUDENC_DSN_REV0
#define PMIC_AUDENC_DIG_MINOR_REV_MASK  0xF
#define PMIC_AUDENC_DIG_MINOR_REV_SHIFT 8
#define PMIC_AUDENC_DIG_MAJOR_REV_ADDR  MT6358_AUDENC_DSN_REV0
#define PMIC_AUDENC_DIG_MAJOR_REV_MASK  0xF
#define PMIC_AUDENC_DIG_MAJOR_REV_SHIFT 12
#define PMIC_AUDENC_DSN_CBS_ADDR  MT6358_AUDENC_DSN_DBI
#define PMIC_AUDENC_DSN_CBS_MASK  0x3
#define PMIC_AUDENC_DSN_CBS_SHIFT 0
#define PMIC_AUDENC_DSN_BIX_ADDR  MT6358_AUDENC_DSN_DBI
#define PMIC_AUDENC_DSN_BIX_MASK  0x3
#define PMIC_AUDENC_DSN_BIX_SHIFT 2
#define PMIC_AUDENC_DSN_ESP_ADDR  MT6358_AUDENC_DSN_DBI
#define PMIC_AUDENC_DSN_ESP_MASK  0xFF
#define PMIC_AUDENC_DSN_ESP_SHIFT 8
#define PMIC_AUDENC_DSN_FPI_ADDR  MT6358_AUDENC_DSN_FPI
#define PMIC_AUDENC_DSN_FPI_MASK  0xFF
#define PMIC_AUDENC_DSN_FPI_SHIFT 0
#define PMIC_RG_AUDPREAMPLON_ADDR MT6358_AUDENC_ANA_CON0
#define PMIC_RG_AUDPREAMPLON_MASK 0x1
#define PMIC_RG_AUDPREAMPLON_SHIFT 0
#define PMIC_RG_AUDPREAMPLDCCEN_ADDR  MT6358_AUDENC_ANA_CON0
#define PMIC_RG_AUDPREAMPLDCCEN_MASK  0x1
#define PMIC_RG_AUDPREAMPLDCCEN_SHIFT 1
#define PMIC_RG_AUDPREAMPLDCPRECHARGE_ADDR  MT6358_AUDENC_ANA_CON0
#define PMIC_RG_AUDPREAMPLDCPRECHARGE_MASK  0x1
#define PMIC_RG_AUDPREAMPLDCPRECHARGE_SHIFT 2
#define PMIC_RG_AUDPREAMPLPGATEST_ADDR  MT6358_AUDENC_ANA_CON0
#define PMIC_RG_AUDPREAMPLPGATEST_MASK  0x1
#define PMIC_RG_AUDPREAMPLPGATEST_SHIFT 3
#define PMIC_RG_AUDPREAMPLVSCALE_ADDR MT6358_AUDENC_ANA_CON0
#define PMIC_RG_AUDPREAMPLVSCALE_MASK 0x3
#define PMIC_RG_AUDPREAMPLVSCALE_SHIFT  4
#define PMIC_RG_AUDPREAMPLINPUTSEL_ADDR MT6358_AUDENC_ANA_CON0
#define PMIC_RG_AUDPREAMPLINPUTSEL_MASK 0x3
#define PMIC_RG_AUDPREAMPLINPUTSEL_SHIFT   6
#define PMIC_RG_AUDPREAMPLGAIN_ADDR   MT6358_AUDENC_ANA_CON0
#define PMIC_RG_AUDPREAMPLGAIN_MASK   0x7
#define PMIC_RG_AUDPREAMPLGAIN_SHIFT  8
#define PMIC_RG_AUDADCLPWRUP_ADDR MT6358_AUDENC_ANA_CON0
#define PMIC_RG_AUDADCLPWRUP_MASK 0x1
#define PMIC_RG_AUDADCLPWRUP_SHIFT 12
#define PMIC_RG_AUDADCLINPUTSEL_ADDR  MT6358_AUDENC_ANA_CON0
#define PMIC_RG_AUDADCLINPUTSEL_MASK  0x3
#define PMIC_RG_AUDADCLINPUTSEL_SHIFT 13
#define PMIC_RG_AUDPREAMPRON_ADDR MT6358_AUDENC_ANA_CON1
#define PMIC_RG_AUDPREAMPRON_MASK 0x1
#define PMIC_RG_AUDPREAMPRON_SHIFT 0
#define PMIC_RG_AUDPREAMPRDCCEN_ADDR  MT6358_AUDENC_ANA_CON1
#define PMIC_RG_AUDPREAMPRDCCEN_MASK  0x1
#define PMIC_RG_AUDPREAMPRDCCEN_SHIFT 1
#define PMIC_RG_AUDPREAMPRDCPRECHARGE_ADDR  MT6358_AUDENC_ANA_CON1
#define PMIC_RG_AUDPREAMPRDCPRECHARGE_MASK  0x1
#define PMIC_RG_AUDPREAMPRDCPRECHARGE_SHIFT 2
#define PMIC_RG_AUDPREAMPRPGATEST_ADDR  MT6358_AUDENC_ANA_CON1
#define PMIC_RG_AUDPREAMPRPGATEST_MASK  0x1
#define PMIC_RG_AUDPREAMPRPGATEST_SHIFT 3
#define PMIC_RG_AUDPREAMPRVSCALE_ADDR MT6358_AUDENC_ANA_CON1
#define PMIC_RG_AUDPREAMPRVSCALE_MASK 0x3
#define PMIC_RG_AUDPREAMPRVSCALE_SHIFT  4
#define PMIC_RG_AUDPREAMPRINPUTSEL_ADDR MT6358_AUDENC_ANA_CON1
#define PMIC_RG_AUDPREAMPRINPUTSEL_MASK 0x3
#define PMIC_RG_AUDPREAMPRINPUTSEL_SHIFT   6
#define PMIC_RG_AUDPREAMPRGAIN_ADDR   MT6358_AUDENC_ANA_CON1
#define PMIC_RG_AUDPREAMPRGAIN_MASK   0x7
#define PMIC_RG_AUDPREAMPRGAIN_SHIFT  8
#define PMIC_RG_AUDIO_VOW_EN_ADDR MT6358_AUDENC_ANA_CON1
#define PMIC_RG_AUDIO_VOW_EN_MASK 0x1
#define PMIC_RG_AUDIO_VOW_EN_SHIFT 11
#define PMIC_RG_AUDADCRPWRUP_ADDR MT6358_AUDENC_ANA_CON1
#define PMIC_RG_AUDADCRPWRUP_MASK 0x1
#define PMIC_RG_AUDADCRPWRUP_SHIFT 12
#define PMIC_RG_AUDADCRINPUTSEL_ADDR  MT6358_AUDENC_ANA_CON1
#define PMIC_RG_AUDADCRINPUTSEL_MASK  0x3
#define PMIC_RG_AUDADCRINPUTSEL_SHIFT 13
#define PMIC_RG_CLKSQ_EN_VOW_ADDR MT6358_AUDENC_ANA_CON1
#define PMIC_RG_CLKSQ_EN_VOW_MASK 0x1
#define PMIC_RG_CLKSQ_EN_VOW_SHIFT 15
#define PMIC_RG_AUDULHALFBIAS_ADDR MT6358_AUDENC_ANA_CON2
#define PMIC_RG_AUDULHALFBIAS_MASK 0x1
#define PMIC_RG_AUDULHALFBIAS_SHIFT   0
#define PMIC_RG_AUDGLBVOWLPWEN_ADDR   MT6358_AUDENC_ANA_CON2
#define PMIC_RG_AUDGLBVOWLPWEN_MASK   0x1
#define PMIC_RG_AUDGLBVOWLPWEN_SHIFT  1
#define PMIC_RG_AUDPREAMPLPEN_ADDR MT6358_AUDENC_ANA_CON2
#define PMIC_RG_AUDPREAMPLPEN_MASK 0x1
#define PMIC_RG_AUDPREAMPLPEN_SHIFT   2
#define PMIC_RG_AUDADC1STSTAGELPEN_ADDR MT6358_AUDENC_ANA_CON2
#define PMIC_RG_AUDADC1STSTAGELPEN_MASK 0x1
#define PMIC_RG_AUDADC1STSTAGELPEN_SHIFT   3
#define PMIC_RG_AUDADC2NDSTAGELPEN_ADDR MT6358_AUDENC_ANA_CON2
#define PMIC_RG_AUDADC2NDSTAGELPEN_MASK 0x1
#define PMIC_RG_AUDADC2NDSTAGELPEN_SHIFT   4
#define PMIC_RG_AUDADCFLASHLPEN_ADDR  MT6358_AUDENC_ANA_CON2
#define PMIC_RG_AUDADCFLASHLPEN_MASK  0x1
#define PMIC_RG_AUDADCFLASHLPEN_SHIFT 5
#define PMIC_RG_AUDPREAMPIDDTEST_ADDR MT6358_AUDENC_ANA_CON2
#define PMIC_RG_AUDPREAMPIDDTEST_MASK 0x3
#define PMIC_RG_AUDPREAMPIDDTEST_SHIFT  6
#define PMIC_RG_AUDADC1STSTAGEIDDTEST_ADDR  MT6358_AUDENC_ANA_CON2
#define PMIC_RG_AUDADC1STSTAGEIDDTEST_MASK  0x3
#define PMIC_RG_AUDADC1STSTAGEIDDTEST_SHIFT 8
#define PMIC_RG_AUDADC2NDSTAGEIDDTEST_ADDR  MT6358_AUDENC_ANA_CON2
#define PMIC_RG_AUDADC2NDSTAGEIDDTEST_MASK  0x3
#define PMIC_RG_AUDADC2NDSTAGEIDDTEST_SHIFT 10
#define PMIC_RG_AUDADCREFBUFIDDTEST_ADDR   MT6358_AUDENC_ANA_CON2
#define PMIC_RG_AUDADCREFBUFIDDTEST_MASK   0x3
#define PMIC_RG_AUDADCREFBUFIDDTEST_SHIFT   12
#define PMIC_RG_AUDADCFLASHIDDTEST_ADDR MT6358_AUDENC_ANA_CON2
#define PMIC_RG_AUDADCFLASHIDDTEST_MASK 0x3
#define PMIC_RG_AUDADCFLASHIDDTEST_SHIFT   14
#define PMIC_RG_AUDADCDAC0P25FS_ADDR  MT6358_AUDENC_ANA_CON3
#define PMIC_RG_AUDADCDAC0P25FS_MASK  0x1
#define PMIC_RG_AUDADCDAC0P25FS_SHIFT 0
#define PMIC_RG_AUDADCCLKSEL_ADDR MT6358_AUDENC_ANA_CON3
#define PMIC_RG_AUDADCCLKSEL_MASK 0x1
#define PMIC_RG_AUDADCCLKSEL_SHIFT 1
#define PMIC_RG_AUDADCCLKSOURCE_ADDR  MT6358_AUDENC_ANA_CON3
#define PMIC_RG_AUDADCCLKSOURCE_MASK  0x3
#define PMIC_RG_AUDADCCLKSOURCE_SHIFT 2
#define PMIC_RG_AUDPREAMPAAFEN_ADDR   MT6358_AUDENC_ANA_CON3
#define PMIC_RG_AUDPREAMPAAFEN_MASK   0x1
#define PMIC_RG_AUDPREAMPAAFEN_SHIFT  8
#define PMIC_RG_DCCVCMBUFLPMODSEL_ADDR  MT6358_AUDENC_ANA_CON3
#define PMIC_RG_DCCVCMBUFLPMODSEL_MASK  0x1
#define PMIC_RG_DCCVCMBUFLPMODSEL_SHIFT 9
#define PMIC_RG_DCCVCMBUFLPSWEN_ADDR  MT6358_AUDENC_ANA_CON3
#define PMIC_RG_DCCVCMBUFLPSWEN_MASK  0x1
#define PMIC_RG_DCCVCMBUFLPSWEN_SHIFT 10
#define PMIC_RG_CMSTBENH_ADDR   MT6358_AUDENC_ANA_CON3
#define PMIC_RG_CMSTBENH_MASK   0x1
#define PMIC_RG_CMSTBENH_SHIFT  11
#define PMIC_RG_PGABODYSW_ADDR  MT6358_AUDENC_ANA_CON3
#define PMIC_RG_PGABODYSW_MASK  0x1
#define PMIC_RG_PGABODYSW_SHIFT 12
#define PMIC_RG_AUDADC1STSTAGESDENB_ADDR   MT6358_AUDENC_ANA_CON4
#define PMIC_RG_AUDADC1STSTAGESDENB_MASK   0x1
#define PMIC_RG_AUDADC1STSTAGESDENB_SHIFT   0
#define PMIC_RG_AUDADC2NDSTAGERESET_ADDR   MT6358_AUDENC_ANA_CON4
#define PMIC_RG_AUDADC2NDSTAGERESET_MASK   0x1
#define PMIC_RG_AUDADC2NDSTAGERESET_SHIFT   1
#define PMIC_RG_AUDADC3RDSTAGERESET_ADDR   MT6358_AUDENC_ANA_CON4
#define PMIC_RG_AUDADC3RDSTAGERESET_MASK   0x1
#define PMIC_RG_AUDADC3RDSTAGERESET_SHIFT   2
#define PMIC_RG_AUDADCFSRESET_ADDR MT6358_AUDENC_ANA_CON4
#define PMIC_RG_AUDADCFSRESET_MASK 0x1
#define PMIC_RG_AUDADCFSRESET_SHIFT   3
#define PMIC_RG_AUDADCWIDECM_ADDR MT6358_AUDENC_ANA_CON4
#define PMIC_RG_AUDADCWIDECM_MASK 0x1
#define PMIC_RG_AUDADCWIDECM_SHIFT 4
#define PMIC_RG_AUDADCNOPATEST_ADDR   MT6358_AUDENC_ANA_CON4
#define PMIC_RG_AUDADCNOPATEST_MASK   0x1
#define PMIC_RG_AUDADCNOPATEST_SHIFT  5
#define PMIC_RG_AUDADCBYPASS_ADDR MT6358_AUDENC_ANA_CON4
#define PMIC_RG_AUDADCBYPASS_MASK 0x1
#define PMIC_RG_AUDADCBYPASS_SHIFT 6
#define PMIC_RG_AUDADCFFBYPASS_ADDR   MT6358_AUDENC_ANA_CON4
#define PMIC_RG_AUDADCFFBYPASS_MASK   0x1
#define PMIC_RG_AUDADCFFBYPASS_SHIFT  7
#define PMIC_RG_AUDADCDACFBCURRENT_ADDR MT6358_AUDENC_ANA_CON4
#define PMIC_RG_AUDADCDACFBCURRENT_MASK 0x1
#define PMIC_RG_AUDADCDACFBCURRENT_SHIFT   8
#define PMIC_RG_AUDADCDACIDDTEST_ADDR MT6358_AUDENC_ANA_CON4
#define PMIC_RG_AUDADCDACIDDTEST_MASK 0x3
#define PMIC_RG_AUDADCDACIDDTEST_SHIFT  9
#define PMIC_RG_AUDADCDACNRZ_ADDR MT6358_AUDENC_ANA_CON4
#define PMIC_RG_AUDADCDACNRZ_MASK 0x1
#define PMIC_RG_AUDADCDACNRZ_SHIFT 11
#define PMIC_RG_AUDADCNODEM_ADDR  MT6358_AUDENC_ANA_CON4
#define PMIC_RG_AUDADCNODEM_MASK  0x1
#define PMIC_RG_AUDADCNODEM_SHIFT 12
#define PMIC_RG_AUDADCDACTEST_ADDR MT6358_AUDENC_ANA_CON4
#define PMIC_RG_AUDADCDACTEST_MASK 0x1
#define PMIC_RG_AUDADCDACTEST_SHIFT   13
#define PMIC_RG_AUDRCTUNEL_ADDR MT6358_AUDENC_ANA_CON5
#define PMIC_RG_AUDRCTUNEL_MASK 0x1F
#define PMIC_RG_AUDRCTUNEL_SHIFT  0
#define PMIC_RG_AUDRCTUNELSEL_ADDR MT6358_AUDENC_ANA_CON5
#define PMIC_RG_AUDRCTUNELSEL_MASK 0x1
#define PMIC_RG_AUDRCTUNELSEL_SHIFT   5
#define PMIC_RG_AUDRCTUNER_ADDR MT6358_AUDENC_ANA_CON5
#define PMIC_RG_AUDRCTUNER_MASK 0x1F
#define PMIC_RG_AUDRCTUNER_SHIFT  8
#define PMIC_RG_AUDRCTUNERSEL_ADDR MT6358_AUDENC_ANA_CON5
#define PMIC_RG_AUDRCTUNERSEL_MASK 0x1
#define PMIC_RG_AUDRCTUNERSEL_SHIFT   13
#define PMIC_RG_CLKSQ_EN_ADDR   MT6358_AUDENC_ANA_CON6
#define PMIC_RG_CLKSQ_EN_MASK   0x1
#define PMIC_RG_CLKSQ_EN_SHIFT  0
#define PMIC_RG_CLKSQ_IN_SEL_TEST_ADDR  MT6358_AUDENC_ANA_CON6
#define PMIC_RG_CLKSQ_IN_SEL_TEST_MASK  0x1
#define PMIC_RG_CLKSQ_IN_SEL_TEST_SHIFT 1
#define PMIC_RG_CM_REFGENSEL_ADDR MT6358_AUDENC_ANA_CON6
#define PMIC_RG_CM_REFGENSEL_MASK 0x1
#define PMIC_RG_CM_REFGENSEL_SHIFT 2
#define PMIC_RG_AUDSPARE_ADDR   MT6358_AUDENC_ANA_CON6
#define PMIC_RG_AUDSPARE_MASK   0xF
#define PMIC_RG_AUDSPARE_SHIFT  4
#define PMIC_RG_AUDENCSPARE_ADDR  MT6358_AUDENC_ANA_CON6
#define PMIC_RG_AUDENCSPARE_MASK  0x3F
#define PMIC_RG_AUDENCSPARE_SHIFT 8
#define PMIC_RG_AUDENCSPARE2_ADDR MT6358_AUDENC_ANA_CON7
#define PMIC_RG_AUDENCSPARE2_MASK 0xFF
#define PMIC_RG_AUDENCSPARE2_SHIFT 0
#define PMIC_RG_AUDDIGMICEN_ADDR  MT6358_AUDENC_ANA_CON8
#define PMIC_RG_AUDDIGMICEN_MASK  0x1
#define PMIC_RG_AUDDIGMICEN_SHIFT 0
#define PMIC_RG_AUDDIGMICBIAS_ADDR MT6358_AUDENC_ANA_CON8
#define PMIC_RG_AUDDIGMICBIAS_MASK 0x3
#define PMIC_RG_AUDDIGMICBIAS_SHIFT   1
#define PMIC_RG_DMICHPCLKEN_ADDR  MT6358_AUDENC_ANA_CON8
#define PMIC_RG_DMICHPCLKEN_MASK  0x1
#define PMIC_RG_DMICHPCLKEN_SHIFT 3
#define PMIC_RG_AUDDIGMICPDUTY_ADDR   MT6358_AUDENC_ANA_CON8
#define PMIC_RG_AUDDIGMICPDUTY_MASK   0x3
#define PMIC_RG_AUDDIGMICPDUTY_SHIFT  4
#define PMIC_RG_AUDDIGMICNDUTY_ADDR   MT6358_AUDENC_ANA_CON8
#define PMIC_RG_AUDDIGMICNDUTY_MASK   0x3
#define PMIC_RG_AUDDIGMICNDUTY_SHIFT  6
#define PMIC_RG_DMICMONEN_ADDR  MT6358_AUDENC_ANA_CON8
#define PMIC_RG_DMICMONEN_MASK  0x1
#define PMIC_RG_DMICMONEN_SHIFT 8
#define PMIC_RG_DMICMONSEL_ADDR MT6358_AUDENC_ANA_CON8
#define PMIC_RG_DMICMONSEL_MASK 0x7
#define PMIC_RG_DMICMONSEL_SHIFT  9
#define PMIC_RG_AUDSPAREVMIC_ADDR MT6358_AUDENC_ANA_CON8
#define PMIC_RG_AUDSPAREVMIC_MASK 0xF
#define PMIC_RG_AUDSPAREVMIC_SHIFT 12
#define PMIC_RG_AUDPWDBMICBIAS0_ADDR  MT6358_AUDENC_ANA_CON9
#define PMIC_RG_AUDPWDBMICBIAS0_MASK  0x1
#define PMIC_RG_AUDPWDBMICBIAS0_SHIFT 0
#define PMIC_RG_AUDMICBIAS0BYPASSEN_ADDR   MT6358_AUDENC_ANA_CON9
#define PMIC_RG_AUDMICBIAS0BYPASSEN_MASK   0x1
#define PMIC_RG_AUDMICBIAS0BYPASSEN_SHIFT   1
#define PMIC_RG_AUDMICBIAS0LOWPEN_ADDR  MT6358_AUDENC_ANA_CON9
#define PMIC_RG_AUDMICBIAS0LOWPEN_MASK  0x1
#define PMIC_RG_AUDMICBIAS0LOWPEN_SHIFT 2
#define PMIC_RG_AUDMICBIAS0VREF_ADDR  MT6358_AUDENC_ANA_CON9
#define PMIC_RG_AUDMICBIAS0VREF_MASK  0x7
#define PMIC_RG_AUDMICBIAS0VREF_SHIFT 4
#define PMIC_RG_AUDMICBIAS0DCSW0P1EN_ADDR   MT6358_AUDENC_ANA_CON9
#define PMIC_RG_AUDMICBIAS0DCSW0P1EN_MASK   0x1
#define PMIC_RG_AUDMICBIAS0DCSW0P1EN_SHIFT  8
#define PMIC_RG_AUDMICBIAS0DCSW0P2EN_ADDR   MT6358_AUDENC_ANA_CON9
#define PMIC_RG_AUDMICBIAS0DCSW0P2EN_MASK   0x1
#define PMIC_RG_AUDMICBIAS0DCSW0P2EN_SHIFT  9
#define PMIC_RG_AUDMICBIAS0DCSW0NEN_ADDR   MT6358_AUDENC_ANA_CON9
#define PMIC_RG_AUDMICBIAS0DCSW0NEN_MASK   0x1
#define PMIC_RG_AUDMICBIAS0DCSW0NEN_SHIFT   10
#define PMIC_RG_AUDMICBIAS0DCSW2P1EN_ADDR   MT6358_AUDENC_ANA_CON9
#define PMIC_RG_AUDMICBIAS0DCSW2P1EN_MASK   0x1
#define PMIC_RG_AUDMICBIAS0DCSW2P1EN_SHIFT  12
#define PMIC_RG_AUDMICBIAS0DCSW2P2EN_ADDR   MT6358_AUDENC_ANA_CON9
#define PMIC_RG_AUDMICBIAS0DCSW2P2EN_MASK   0x1
#define PMIC_RG_AUDMICBIAS0DCSW2P2EN_SHIFT  13
#define PMIC_RG_AUDMICBIAS0DCSW2NEN_ADDR   MT6358_AUDENC_ANA_CON9
#define PMIC_RG_AUDMICBIAS0DCSW2NEN_MASK   0x1
#define PMIC_RG_AUDMICBIAS0DCSW2NEN_SHIFT   14
#define PMIC_RG_AUDPWDBMICBIAS1_ADDR  MT6358_AUDENC_ANA_CON10
#define PMIC_RG_AUDPWDBMICBIAS1_MASK  0x1
#define PMIC_RG_AUDPWDBMICBIAS1_SHIFT 0
#define PMIC_RG_AUDMICBIAS1BYPASSEN_ADDR   MT6358_AUDENC_ANA_CON10
#define PMIC_RG_AUDMICBIAS1BYPASSEN_MASK   0x1
#define PMIC_RG_AUDMICBIAS1BYPASSEN_SHIFT   1
#define PMIC_RG_AUDMICBIAS1LOWPEN_ADDR  MT6358_AUDENC_ANA_CON10
#define PMIC_RG_AUDMICBIAS1LOWPEN_MASK  0x1
#define PMIC_RG_AUDMICBIAS1LOWPEN_SHIFT 2
#define PMIC_RG_AUDMICBIAS1VREF_ADDR  MT6358_AUDENC_ANA_CON10
#define PMIC_RG_AUDMICBIAS1VREF_MASK  0x7
#define PMIC_RG_AUDMICBIAS1VREF_SHIFT 4
#define PMIC_RG_AUDMICBIAS1DCSW1PEN_ADDR   MT6358_AUDENC_ANA_CON10
#define PMIC_RG_AUDMICBIAS1DCSW1PEN_MASK   0x1
#define PMIC_RG_AUDMICBIAS1DCSW1PEN_SHIFT   8
#define PMIC_RG_AUDMICBIAS1DCSW1NEN_ADDR   MT6358_AUDENC_ANA_CON10
#define PMIC_RG_AUDMICBIAS1DCSW1NEN_MASK   0x1
#define PMIC_RG_AUDMICBIAS1DCSW1NEN_SHIFT   9
#define PMIC_RG_BANDGAPGEN_ADDR MT6358_AUDENC_ANA_CON10
#define PMIC_RG_BANDGAPGEN_MASK 0x1
#define PMIC_RG_BANDGAPGEN_SHIFT  12
#define PMIC_RG_MTEST_EN_ADDR   MT6358_AUDENC_ANA_CON10
#define PMIC_RG_MTEST_EN_MASK   0x1
#define PMIC_RG_MTEST_EN_SHIFT  13
#define PMIC_RG_MTEST_SEL_ADDR  MT6358_AUDENC_ANA_CON10
#define PMIC_RG_MTEST_SEL_MASK  0x1
#define PMIC_RG_MTEST_SEL_SHIFT 14
#define PMIC_RG_MTEST_CURRENT_ADDR MT6358_AUDENC_ANA_CON10
#define PMIC_RG_MTEST_CURRENT_MASK 0x1
#define PMIC_RG_MTEST_CURRENT_SHIFT   15
#define PMIC_RG_AUDACCDETMICBIAS0PULLLOW_ADDR MT6358_AUDENC_ANA_CON11
#define PMIC_RG_AUDACCDETMICBIAS0PULLLOW_MASK 0x1
#define PMIC_RG_AUDACCDETMICBIAS0PULLLOW_SHIFT   0
#define PMIC_RG_AUDACCDETMICBIAS1PULLLOW_ADDR MT6358_AUDENC_ANA_CON11
#define PMIC_RG_AUDACCDETMICBIAS1PULLLOW_MASK 0x1
#define PMIC_RG_AUDACCDETMICBIAS1PULLLOW_SHIFT   1
#define PMIC_RG_AUDACCDETVIN1PULLLOW_ADDR   MT6358_AUDENC_ANA_CON11
#define PMIC_RG_AUDACCDETVIN1PULLLOW_MASK   0x1
#define PMIC_RG_AUDACCDETVIN1PULLLOW_SHIFT  2
#define PMIC_RG_AUDACCDETVTHACAL_ADDR MT6358_AUDENC_ANA_CON11
#define PMIC_RG_AUDACCDETVTHACAL_MASK 0x1
#define PMIC_RG_AUDACCDETVTHACAL_SHIFT  4
#define PMIC_RG_AUDACCDETVTHBCAL_ADDR MT6358_AUDENC_ANA_CON11
#define PMIC_RG_AUDACCDETVTHBCAL_MASK 0x1
#define PMIC_RG_AUDACCDETVTHBCAL_SHIFT  5
#define PMIC_RG_AUDACCDETTVDET_ADDR   MT6358_AUDENC_ANA_CON11
#define PMIC_RG_AUDACCDETTVDET_MASK   0x1
#define PMIC_RG_AUDACCDETTVDET_SHIFT  6
#define PMIC_RG_ACCDETSEL_ADDR  MT6358_AUDENC_ANA_CON11
#define PMIC_RG_ACCDETSEL_MASK  0x1
#define PMIC_RG_ACCDETSEL_SHIFT 7
#define PMIC_RG_SWBUFMODSEL_ADDR  MT6358_AUDENC_ANA_CON11
#define PMIC_RG_SWBUFMODSEL_MASK  0x1
#define PMIC_RG_SWBUFMODSEL_SHIFT 8
#define PMIC_RG_SWBUFSWEN_ADDR  MT6358_AUDENC_ANA_CON11
#define PMIC_RG_SWBUFSWEN_MASK  0x1
#define PMIC_RG_SWBUFSWEN_SHIFT 9
#define PMIC_RG_EINTCOMPVTH_ADDR  MT6358_AUDENC_ANA_CON11
#define PMIC_RG_EINTCOMPVTH_MASK  0x1
#define PMIC_RG_EINTCOMPVTH_SHIFT 10
#define PMIC_RG_EINTCONFIGACCDET_ADDR MT6358_AUDENC_ANA_CON11
#define PMIC_RG_EINTCONFIGACCDET_MASK 0x1
#define PMIC_RG_EINTCONFIGACCDET_SHIFT  11
#define PMIC_RG_EINTHIRENB_ADDR MT6358_AUDENC_ANA_CON11
#define PMIC_RG_EINTHIRENB_MASK 0x1
#define PMIC_RG_EINTHIRENB_SHIFT  12
#define PMIC_RG_ACCDET2AUXRESBYPASS_ADDR   MT6358_AUDENC_ANA_CON11
#define PMIC_RG_ACCDET2AUXRESBYPASS_MASK   0x1
#define PMIC_RG_ACCDET2AUXRESBYPASS_SHIFT   13
#define PMIC_RG_ACCDET2AUXBUFFERBYPASS_ADDR MT6358_AUDENC_ANA_CON11
#define PMIC_RG_ACCDET2AUXBUFFERBYPASS_MASK 0x1
#define PMIC_RG_ACCDET2AUXBUFFERBYPASS_SHIFT  14
#define PMIC_RG_ACCDET2AUXSWEN_ADDR   MT6358_AUDENC_ANA_CON11
#define PMIC_RG_ACCDET2AUXSWEN_MASK   0x1
#define PMIC_RG_ACCDET2AUXSWEN_SHIFT  15
#define PMIC_RGS_AUDRCTUNELREAD_ADDR  MT6358_AUDENC_ANA_CON12
#define PMIC_RGS_AUDRCTUNELREAD_MASK  0x1F
#define PMIC_RGS_AUDRCTUNELREAD_SHIFT 0
#define PMIC_RGS_AUDRCTUNERREAD_ADDR  MT6358_AUDENC_ANA_CON12
#define PMIC_RGS_AUDRCTUNERREAD_MASK  0x1F
#define PMIC_RGS_AUDRCTUNERREAD_SHIFT 8
#define PMIC_AUDDEC_ANA_ID_ADDR MT6358_AUDDEC_DSN_ID
#define PMIC_AUDDEC_ANA_ID_MASK 0xFF
#define PMIC_AUDDEC_ANA_ID_SHIFT  0
#define PMIC_AUDDEC_DIG_ID_ADDR MT6358_AUDDEC_DSN_ID
#define PMIC_AUDDEC_DIG_ID_MASK 0xFF
#define PMIC_AUDDEC_DIG_ID_SHIFT  8
#define PMIC_AUDDEC_ANA_MINOR_REV_ADDR  MT6358_AUDDEC_DSN_REV0
#define PMIC_AUDDEC_ANA_MINOR_REV_MASK  0xF
#define PMIC_AUDDEC_ANA_MINOR_REV_SHIFT 0
#define PMIC_AUDDEC_ANA_MAJOR_REV_ADDR  MT6358_AUDDEC_DSN_REV0
#define PMIC_AUDDEC_ANA_MAJOR_REV_MASK  0xF
#define PMIC_AUDDEC_ANA_MAJOR_REV_SHIFT 4
#define PMIC_AUDDEC_DIG_MINOR_REV_ADDR  MT6358_AUDDEC_DSN_REV0
#define PMIC_AUDDEC_DIG_MINOR_REV_MASK  0xF
#define PMIC_AUDDEC_DIG_MINOR_REV_SHIFT 8
#define PMIC_AUDDEC_DIG_MAJOR_REV_ADDR  MT6358_AUDDEC_DSN_REV0
#define PMIC_AUDDEC_DIG_MAJOR_REV_MASK  0xF
#define PMIC_AUDDEC_DIG_MAJOR_REV_SHIFT 12
#define PMIC_AUDDEC_DSN_CBS_ADDR  MT6358_AUDDEC_DSN_DBI
#define PMIC_AUDDEC_DSN_CBS_MASK  0x3
#define PMIC_AUDDEC_DSN_CBS_SHIFT 0
#define PMIC_AUDDEC_DSN_BIX_ADDR  MT6358_AUDDEC_DSN_DBI
#define PMIC_AUDDEC_DSN_BIX_MASK  0x3
#define PMIC_AUDDEC_DSN_BIX_SHIFT 2
#define PMIC_AUDDEC_DSN_ESP_ADDR  MT6358_AUDDEC_DSN_DBI
#define PMIC_AUDDEC_DSN_ESP_MASK  0xFF
#define PMIC_AUDDEC_DSN_ESP_SHIFT 8
#define PMIC_AUDDEC_DSN_FPI_ADDR  MT6358_AUDDEC_DSN_FPI
#define PMIC_AUDDEC_DSN_FPI_MASK  0xFF
#define PMIC_AUDDEC_DSN_FPI_SHIFT 0
#define PMIC_RG_AUDDACLPWRUP_VAUDP15_ADDR   MT6358_AUDDEC_ANA_CON0
#define PMIC_RG_AUDDACLPWRUP_VAUDP15_MASK   0x1
#define PMIC_RG_AUDDACLPWRUP_VAUDP15_SHIFT  0
#define PMIC_RG_AUDDACRPWRUP_VAUDP15_ADDR   MT6358_AUDDEC_ANA_CON0
#define PMIC_RG_AUDDACRPWRUP_VAUDP15_MASK   0x1
#define PMIC_RG_AUDDACRPWRUP_VAUDP15_SHIFT  1
#define PMIC_RG_AUD_DAC_PWR_UP_VA28_ADDR   MT6358_AUDDEC_ANA_CON0
#define PMIC_RG_AUD_DAC_PWR_UP_VA28_MASK   0x1
#define PMIC_RG_AUD_DAC_PWR_UP_VA28_SHIFT   2
#define PMIC_RG_AUD_DAC_PWL_UP_VA28_ADDR   MT6358_AUDDEC_ANA_CON0
#define PMIC_RG_AUD_DAC_PWL_UP_VA28_MASK   0x1
#define PMIC_RG_AUD_DAC_PWL_UP_VA28_SHIFT   3
#define PMIC_RG_AUDHPLPWRUP_VAUDP15_ADDR   MT6358_AUDDEC_ANA_CON0
#define PMIC_RG_AUDHPLPWRUP_VAUDP15_MASK   0x1
#define PMIC_RG_AUDHPLPWRUP_VAUDP15_SHIFT   4
#define PMIC_RG_AUDHPRPWRUP_VAUDP15_ADDR   MT6358_AUDDEC_ANA_CON0
#define PMIC_RG_AUDHPRPWRUP_VAUDP15_MASK   0x1
#define PMIC_RG_AUDHPRPWRUP_VAUDP15_SHIFT   5
#define PMIC_RG_AUDHPLPWRUP_IBIAS_VAUDP15_ADDR   MT6358_AUDDEC_ANA_CON0
#define PMIC_RG_AUDHPLPWRUP_IBIAS_VAUDP15_MASK   0x1
#define PMIC_RG_AUDHPLPWRUP_IBIAS_VAUDP15_SHIFT  6
#define PMIC_RG_AUDHPRPWRUP_IBIAS_VAUDP15_ADDR   MT6358_AUDDEC_ANA_CON0
#define PMIC_RG_AUDHPRPWRUP_IBIAS_VAUDP15_MASK   0x1
#define PMIC_RG_AUDHPRPWRUP_IBIAS_VAUDP15_SHIFT  7
#define PMIC_RG_AUDHPLMUXINPUTSEL_VAUDP15_ADDR   MT6358_AUDDEC_ANA_CON0
#define PMIC_RG_AUDHPLMUXINPUTSEL_VAUDP15_MASK   0x3
#define PMIC_RG_AUDHPLMUXINPUTSEL_VAUDP15_SHIFT  8
#define PMIC_RG_AUDHPRMUXINPUTSEL_VAUDP15_ADDR   MT6358_AUDDEC_ANA_CON0
#define PMIC_RG_AUDHPRMUXINPUTSEL_VAUDP15_MASK   0x3
#define PMIC_RG_AUDHPRMUXINPUTSEL_VAUDP15_SHIFT  10
#define PMIC_RG_AUDHPLSCDISABLE_VAUDP15_ADDR  MT6358_AUDDEC_ANA_CON0
#define PMIC_RG_AUDHPLSCDISABLE_VAUDP15_MASK  0x1
#define PMIC_RG_AUDHPLSCDISABLE_VAUDP15_SHIFT 12
#define PMIC_RG_AUDHPRSCDISABLE_VAUDP15_ADDR  MT6358_AUDDEC_ANA_CON0
#define PMIC_RG_AUDHPRSCDISABLE_VAUDP15_MASK  0x1
#define PMIC_RG_AUDHPRSCDISABLE_VAUDP15_SHIFT 13
#define PMIC_RG_AUDHPLBSCCURRENT_VAUDP15_ADDR MT6358_AUDDEC_ANA_CON0
#define PMIC_RG_AUDHPLBSCCURRENT_VAUDP15_MASK 0x1
#define PMIC_RG_AUDHPLBSCCURRENT_VAUDP15_SHIFT   14
#define PMIC_RG_AUDHPRBSCCURRENT_VAUDP15_ADDR MT6358_AUDDEC_ANA_CON0
#define PMIC_RG_AUDHPRBSCCURRENT_VAUDP15_MASK 0x1
#define PMIC_RG_AUDHPRBSCCURRENT_VAUDP15_SHIFT   15
#define PMIC_RG_AUDHPLOUTPWRUP_VAUDP15_ADDR MT6358_AUDDEC_ANA_CON1
#define PMIC_RG_AUDHPLOUTPWRUP_VAUDP15_MASK 0x1
#define PMIC_RG_AUDHPLOUTPWRUP_VAUDP15_SHIFT  0
#define PMIC_RG_AUDHPROUTPWRUP_VAUDP15_ADDR MT6358_AUDDEC_ANA_CON1
#define PMIC_RG_AUDHPROUTPWRUP_VAUDP15_MASK 0x1
#define PMIC_RG_AUDHPROUTPWRUP_VAUDP15_SHIFT  1
#define PMIC_RG_AUDHPLOUTAUXPWRUP_VAUDP15_ADDR   MT6358_AUDDEC_ANA_CON1
#define PMIC_RG_AUDHPLOUTAUXPWRUP_VAUDP15_MASK   0x1
#define PMIC_RG_AUDHPLOUTAUXPWRUP_VAUDP15_SHIFT  2
#define PMIC_RG_AUDHPROUTAUXPWRUP_VAUDP15_ADDR   MT6358_AUDDEC_ANA_CON1
#define PMIC_RG_AUDHPROUTAUXPWRUP_VAUDP15_MASK   0x1
#define PMIC_RG_AUDHPROUTAUXPWRUP_VAUDP15_SHIFT  3
#define PMIC_RG_HPLAUXFBRSW_EN_VAUDP15_ADDR MT6358_AUDDEC_ANA_CON1
#define PMIC_RG_HPLAUXFBRSW_EN_VAUDP15_MASK 0x1
#define PMIC_RG_HPLAUXFBRSW_EN_VAUDP15_SHIFT  4
#define PMIC_RG_HPRAUXFBRSW_EN_VAUDP15_ADDR MT6358_AUDDEC_ANA_CON1
#define PMIC_RG_HPRAUXFBRSW_EN_VAUDP15_MASK 0x1
#define PMIC_RG_HPRAUXFBRSW_EN_VAUDP15_SHIFT  5
#define PMIC_RG_HPLSHORT2HPLAUX_EN_VAUDP15_ADDR  MT6358_AUDDEC_ANA_CON1
#define PMIC_RG_HPLSHORT2HPLAUX_EN_VAUDP15_MASK  0x1
#define PMIC_RG_HPLSHORT2HPLAUX_EN_VAUDP15_SHIFT  6
#define PMIC_RG_HPRSHORT2HPRAUX_EN_VAUDP15_ADDR  MT6358_AUDDEC_ANA_CON1
#define PMIC_RG_HPRSHORT2HPRAUX_EN_VAUDP15_MASK  0x1
#define PMIC_RG_HPRSHORT2HPRAUX_EN_VAUDP15_SHIFT  7
#define PMIC_RG_HPLOUTSTGCTRL_VAUDP15_ADDR  MT6358_AUDDEC_ANA_CON1
#define PMIC_RG_HPLOUTSTGCTRL_VAUDP15_MASK  0x7
#define PMIC_RG_HPLOUTSTGCTRL_VAUDP15_SHIFT 8
#define PMIC_RG_HPROUTSTGCTRL_VAUDP15_ADDR  MT6358_AUDDEC_ANA_CON1
#define PMIC_RG_HPROUTSTGCTRL_VAUDP15_MASK  0x7
#define PMIC_RG_HPROUTSTGCTRL_VAUDP15_SHIFT 11
#define PMIC_RG_HPLOUTPUTSTBENH_VAUDP15_ADDR  MT6358_AUDDEC_ANA_CON2
#define PMIC_RG_HPLOUTPUTSTBENH_VAUDP15_MASK  0x7
#define PMIC_RG_HPLOUTPUTSTBENH_VAUDP15_SHIFT 0
#define PMIC_RG_HPROUTPUTSTBENH_VAUDP15_ADDR  MT6358_AUDDEC_ANA_CON2
#define PMIC_RG_HPROUTPUTSTBENH_VAUDP15_MASK  0x7
#define PMIC_RG_HPROUTPUTSTBENH_VAUDP15_SHIFT 4
#define PMIC_RG_AUDHPSTARTUP_VAUDP15_ADDR   MT6358_AUDDEC_ANA_CON2
#define PMIC_RG_AUDHPSTARTUP_VAUDP15_MASK   0x1
#define PMIC_RG_AUDHPSTARTUP_VAUDP15_SHIFT  13
#define PMIC_RG_AUDREFN_DERES_EN_VAUDP15_ADDR MT6358_AUDDEC_ANA_CON2
#define PMIC_RG_AUDREFN_DERES_EN_VAUDP15_MASK 0x1
#define PMIC_RG_AUDREFN_DERES_EN_VAUDP15_SHIFT   14
#define PMIC_RG_HPPSHORT2VCM_VAUDP15_ADDR   MT6358_AUDDEC_ANA_CON2
#define PMIC_RG_HPPSHORT2VCM_VAUDP15_MASK   0x1
#define PMIC_RG_HPPSHORT2VCM_VAUDP15_SHIFT  15
#define PMIC_RG_HPINPUTSTBENH_VAUDP15_ADDR  MT6358_AUDDEC_ANA_CON3
#define PMIC_RG_HPINPUTSTBENH_VAUDP15_MASK  0x1
#define PMIC_RG_HPINPUTSTBENH_VAUDP15_SHIFT 13
#define PMIC_RG_HPINPUTRESET0_VAUDP15_ADDR  MT6358_AUDDEC_ANA_CON3
#define PMIC_RG_HPINPUTRESET0_VAUDP15_MASK  0x1
#define PMIC_RG_HPINPUTRESET0_VAUDP15_SHIFT 14
#define PMIC_RG_HPOUTPUTRESET0_VAUDP15_ADDR MT6358_AUDDEC_ANA_CON3
#define PMIC_RG_HPOUTPUTRESET0_VAUDP15_MASK 0x1
#define PMIC_RG_HPOUTPUTRESET0_VAUDP15_SHIFT  15
#define PMIC_RG_ABIDEC_RSVD0_VAUDP28_ADDR   MT6358_AUDDEC_ANA_CON4
#define PMIC_RG_ABIDEC_RSVD0_VAUDP28_MASK   0xFF
#define PMIC_RG_ABIDEC_RSVD0_VAUDP28_SHIFT  0
#define PMIC_RG_AUDHPDECMGAINADJ_VAUDP15_ADDR MT6358_AUDDEC_ANA_CON5
#define PMIC_RG_AUDHPDECMGAINADJ_VAUDP15_MASK 0x7
#define PMIC_RG_AUDHPDECMGAINADJ_VAUDP15_SHIFT   0
#define PMIC_RG_AUDHPDEDMGAINADJ_VAUDP15_ADDR MT6358_AUDDEC_ANA_CON5
#define PMIC_RG_AUDHPDEDMGAINADJ_VAUDP15_MASK 0x7
#define PMIC_RG_AUDHPDEDMGAINADJ_VAUDP15_SHIFT   4
#define PMIC_RG_AUDHSPWRUP_VAUDP15_ADDR MT6358_AUDDEC_ANA_CON6
#define PMIC_RG_AUDHSPWRUP_VAUDP15_MASK 0x1
#define PMIC_RG_AUDHSPWRUP_VAUDP15_SHIFT   0
#define PMIC_RG_AUDHSPWRUP_IBIAS_VAUDP15_ADDR MT6358_AUDDEC_ANA_CON6
#define PMIC_RG_AUDHSPWRUP_IBIAS_VAUDP15_MASK 0x1
#define PMIC_RG_AUDHSPWRUP_IBIAS_VAUDP15_SHIFT   1
#define PMIC_RG_AUDHSMUXINPUTSEL_VAUDP15_ADDR MT6358_AUDDEC_ANA_CON6
#define PMIC_RG_AUDHSMUXINPUTSEL_VAUDP15_MASK 0x3
#define PMIC_RG_AUDHSMUXINPUTSEL_VAUDP15_SHIFT   2
#define PMIC_RG_AUDHSSCDISABLE_VAUDP15_ADDR MT6358_AUDDEC_ANA_CON6
#define PMIC_RG_AUDHSSCDISABLE_VAUDP15_MASK 0x1
#define PMIC_RG_AUDHSSCDISABLE_VAUDP15_SHIFT  4
#define PMIC_RG_AUDHSBSCCURRENT_VAUDP15_ADDR  MT6358_AUDDEC_ANA_CON6
#define PMIC_RG_AUDHSBSCCURRENT_VAUDP15_MASK  0x1
#define PMIC_RG_AUDHSBSCCURRENT_VAUDP15_SHIFT 5
#define PMIC_RG_AUDHSSTARTUP_VAUDP15_ADDR   MT6358_AUDDEC_ANA_CON6
#define PMIC_RG_AUDHSSTARTUP_VAUDP15_MASK   0x1
#define PMIC_RG_AUDHSSTARTUP_VAUDP15_SHIFT  6
#define PMIC_RG_HSOUTPUTSTBENH_VAUDP15_ADDR MT6358_AUDDEC_ANA_CON6
#define PMIC_RG_HSOUTPUTSTBENH_VAUDP15_MASK 0x1
#define PMIC_RG_HSOUTPUTSTBENH_VAUDP15_SHIFT  7
#define PMIC_RG_HSINPUTSTBENH_VAUDP15_ADDR  MT6358_AUDDEC_ANA_CON6
#define PMIC_RG_HSINPUTSTBENH_VAUDP15_MASK  0x1
#define PMIC_RG_HSINPUTSTBENH_VAUDP15_SHIFT 8
#define PMIC_RG_HSINPUTRESET0_VAUDP15_ADDR  MT6358_AUDDEC_ANA_CON6
#define PMIC_RG_HSINPUTRESET0_VAUDP15_MASK  0x1
#define PMIC_RG_HSINPUTRESET0_VAUDP15_SHIFT 9
#define PMIC_RG_HSOUTPUTRESET0_VAUDP15_ADDR MT6358_AUDDEC_ANA_CON6
#define PMIC_RG_HSOUTPUTRESET0_VAUDP15_MASK 0x1
#define PMIC_RG_HSOUTPUTRESET0_VAUDP15_SHIFT  10
#define PMIC_RG_HSOUT_SHORTVCM_VAUDP15_ADDR MT6358_AUDDEC_ANA_CON6
#define PMIC_RG_HSOUT_SHORTVCM_VAUDP15_MASK 0x1
#define PMIC_RG_HSOUT_SHORTVCM_VAUDP15_SHIFT  11
#define PMIC_RG_AUDLOLPWRUP_VAUDP15_ADDR   MT6358_AUDDEC_ANA_CON7
#define PMIC_RG_AUDLOLPWRUP_VAUDP15_MASK   0x1
#define PMIC_RG_AUDLOLPWRUP_VAUDP15_SHIFT   0
#define PMIC_RG_AUDLOLPWRUP_IBIAS_VAUDP15_ADDR   MT6358_AUDDEC_ANA_CON7
#define PMIC_RG_AUDLOLPWRUP_IBIAS_VAUDP15_MASK   0x1
#define PMIC_RG_AUDLOLPWRUP_IBIAS_VAUDP15_SHIFT  1
#define PMIC_RG_AUDLOLMUXINPUTSEL_VAUDP15_ADDR   MT6358_AUDDEC_ANA_CON7
#define PMIC_RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK   0x3
#define PMIC_RG_AUDLOLMUXINPUTSEL_VAUDP15_SHIFT  2
#define PMIC_RG_AUDLOLSCDISABLE_VAUDP15_ADDR  MT6358_AUDDEC_ANA_CON7
#define PMIC_RG_AUDLOLSCDISABLE_VAUDP15_MASK  0x1
#define PMIC_RG_AUDLOLSCDISABLE_VAUDP15_SHIFT 4
#define PMIC_RG_AUDLOLBSCCURRENT_VAUDP15_ADDR MT6358_AUDDEC_ANA_CON7
#define PMIC_RG_AUDLOLBSCCURRENT_VAUDP15_MASK 0x1
#define PMIC_RG_AUDLOLBSCCURRENT_VAUDP15_SHIFT   5
#define PMIC_RG_AUDLOSTARTUP_VAUDP15_ADDR   MT6358_AUDDEC_ANA_CON7
#define PMIC_RG_AUDLOSTARTUP_VAUDP15_MASK   0x1
#define PMIC_RG_AUDLOSTARTUP_VAUDP15_SHIFT  6
#define PMIC_RG_LOINPUTSTBENH_VAUDP15_ADDR  MT6358_AUDDEC_ANA_CON7
#define PMIC_RG_LOINPUTSTBENH_VAUDP15_MASK  0x1
#define PMIC_RG_LOINPUTSTBENH_VAUDP15_SHIFT 7
#define PMIC_RG_LOOUTPUTSTBENH_VAUDP15_ADDR MT6358_AUDDEC_ANA_CON7
#define PMIC_RG_LOOUTPUTSTBENH_VAUDP15_MASK 0x1
#define PMIC_RG_LOOUTPUTSTBENH_VAUDP15_SHIFT  8
#define PMIC_RG_LOINPUTRESET0_VAUDP15_ADDR  MT6358_AUDDEC_ANA_CON7
#define PMIC_RG_LOINPUTRESET0_VAUDP15_MASK  0x1
#define PMIC_RG_LOINPUTRESET0_VAUDP15_SHIFT 9
#define PMIC_RG_LOOUTPUTRESET0_VAUDP15_ADDR MT6358_AUDDEC_ANA_CON7
#define PMIC_RG_LOOUTPUTRESET0_VAUDP15_MASK 0x1
#define PMIC_RG_LOOUTPUTRESET0_VAUDP15_SHIFT  10
#define PMIC_RG_LOOUT_SHORTVCM_VAUDP15_ADDR MT6358_AUDDEC_ANA_CON7
#define PMIC_RG_LOOUT_SHORTVCM_VAUDP15_MASK 0x1
#define PMIC_RG_LOOUT_SHORTVCM_VAUDP15_SHIFT  11
#define PMIC_RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_ADDR MT6358_AUDDEC_ANA_CON8
#define PMIC_RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_MASK 0xF
#define PMIC_RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_SHIFT   0
#define PMIC_RG_AUDTRIMBUF_GAINSEL_VAUDP15_ADDR  MT6358_AUDDEC_ANA_CON8
#define PMIC_RG_AUDTRIMBUF_GAINSEL_VAUDP15_MASK  0x3
#define PMIC_RG_AUDTRIMBUF_GAINSEL_VAUDP15_SHIFT  4
#define PMIC_RG_AUDTRIMBUF_EN_VAUDP15_ADDR  MT6358_AUDDEC_ANA_CON8
#define PMIC_RG_AUDTRIMBUF_EN_VAUDP15_MASK  0x1
#define PMIC_RG_AUDTRIMBUF_EN_VAUDP15_SHIFT 6
#define PMIC_RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_ADDR   MT6358_AUDDEC_ANA_CON8
#define PMIC_RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_MASK   0x3
#define PMIC_RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_SHIFT  8
#define PMIC_RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_ADDR  MT6358_AUDDEC_ANA_CON8
#define PMIC_RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_MASK  0x3
#define PMIC_RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_SHIFT 10
#define PMIC_RG_AUDHPSPKDET_EN_VAUDP15_ADDR MT6358_AUDDEC_ANA_CON8
#define PMIC_RG_AUDHPSPKDET_EN_VAUDP15_MASK 0x1
#define PMIC_RG_AUDHPSPKDET_EN_VAUDP15_SHIFT  12
#define PMIC_RG_ABIDEC_RSVD0_VA28_ADDR  MT6358_AUDDEC_ANA_CON9
#define PMIC_RG_ABIDEC_RSVD0_VA28_MASK  0xFF
#define PMIC_RG_ABIDEC_RSVD0_VA28_SHIFT 0
#define PMIC_RG_ABIDEC_RSVD0_VAUDP15_ADDR   MT6358_AUDDEC_ANA_CON9
#define PMIC_RG_ABIDEC_RSVD0_VAUDP15_MASK   0xFF
#define PMIC_RG_ABIDEC_RSVD0_VAUDP15_SHIFT  8
#define PMIC_RG_ABIDEC_RSVD1_VAUDP15_ADDR   MT6358_AUDDEC_ANA_CON10
#define PMIC_RG_ABIDEC_RSVD1_VAUDP15_MASK   0xFF
#define PMIC_RG_ABIDEC_RSVD1_VAUDP15_SHIFT  0
#define PMIC_RG_ABIDEC_RSVD2_VAUDP15_ADDR   MT6358_AUDDEC_ANA_CON10
#define PMIC_RG_ABIDEC_RSVD2_VAUDP15_MASK   0xFF
#define PMIC_RG_ABIDEC_RSVD2_VAUDP15_SHIFT  8
#define PMIC_RG_AUDZCDMUXSEL_VAUDP15_ADDR   MT6358_AUDDEC_ANA_CON11
#define PMIC_RG_AUDZCDMUXSEL_VAUDP15_MASK   0x7
#define PMIC_RG_AUDZCDMUXSEL_VAUDP15_SHIFT  0
#define PMIC_RG_AUDZCDCLKSEL_VAUDP15_ADDR   MT6358_AUDDEC_ANA_CON11
#define PMIC_RG_AUDZCDCLKSEL_VAUDP15_MASK   0x1
#define PMIC_RG_AUDZCDCLKSEL_VAUDP15_SHIFT  3
#define PMIC_RG_AUDBIASADJ_0_VAUDP15_ADDR   MT6358_AUDDEC_ANA_CON11
#define PMIC_RG_AUDBIASADJ_0_VAUDP15_MASK   0x1FF
#define PMIC_RG_AUDBIASADJ_0_VAUDP15_SHIFT  7
#define PMIC_RG_AUDBIASADJ_1_VAUDP15_ADDR   MT6358_AUDDEC_ANA_CON12
#define PMIC_RG_AUDBIASADJ_1_VAUDP15_MASK   0xFF
#define PMIC_RG_AUDBIASADJ_1_VAUDP15_SHIFT  0
#define PMIC_RG_AUDIBIASPWRDN_VAUDP15_ADDR  MT6358_AUDDEC_ANA_CON12
#define PMIC_RG_AUDIBIASPWRDN_VAUDP15_MASK  0x1
#define PMIC_RG_AUDIBIASPWRDN_VAUDP15_SHIFT 8
#define PMIC_RG_RSTB_DECODER_VA28_ADDR  MT6358_AUDDEC_ANA_CON13
#define PMIC_RG_RSTB_DECODER_VA28_MASK  0x1
#define PMIC_RG_RSTB_DECODER_VA28_SHIFT 0
#define PMIC_RG_SEL_DECODER_96K_VA28_ADDR   MT6358_AUDDEC_ANA_CON13
#define PMIC_RG_SEL_DECODER_96K_VA28_MASK   0x1
#define PMIC_RG_SEL_DECODER_96K_VA28_SHIFT  1
#define PMIC_RG_SEL_DELAY_VCORE_ADDR  MT6358_AUDDEC_ANA_CON13
#define PMIC_RG_SEL_DELAY_VCORE_MASK  0x1
#define PMIC_RG_SEL_DELAY_VCORE_SHIFT 2
#define PMIC_RG_AUDGLB_PWRDN_VA28_ADDR  MT6358_AUDDEC_ANA_CON13
#define PMIC_RG_AUDGLB_PWRDN_VA28_MASK  0x1
#define PMIC_RG_AUDGLB_PWRDN_VA28_SHIFT 4
#define PMIC_RG_RSTB_ENCODER_VA28_ADDR  MT6358_AUDDEC_ANA_CON13
#define PMIC_RG_RSTB_ENCODER_VA28_MASK  0x1
#define PMIC_RG_RSTB_ENCODER_VA28_SHIFT 5
#define PMIC_RG_SEL_ENCODER_96K_VA28_ADDR   MT6358_AUDDEC_ANA_CON13
#define PMIC_RG_SEL_ENCODER_96K_VA28_MASK   0x1
#define PMIC_RG_SEL_ENCODER_96K_VA28_SHIFT  6
#define PMIC_RG_HCLDO_EN_VA18_ADDR MT6358_AUDDEC_ANA_CON14
#define PMIC_RG_HCLDO_EN_VA18_MASK 0x1
#define PMIC_RG_HCLDO_EN_VA18_SHIFT   0
#define PMIC_RG_HCLDO_PDDIS_EN_VA18_ADDR   MT6358_AUDDEC_ANA_CON14
#define PMIC_RG_HCLDO_PDDIS_EN_VA18_MASK   0x1
#define PMIC_RG_HCLDO_PDDIS_EN_VA18_SHIFT   1
#define PMIC_RG_HCLDO_REMOTE_SENSE_VA18_ADDR  MT6358_AUDDEC_ANA_CON14
#define PMIC_RG_HCLDO_REMOTE_SENSE_VA18_MASK  0x1
#define PMIC_RG_HCLDO_REMOTE_SENSE_VA18_SHIFT 2
#define PMIC_RG_LCLDO_EN_VA18_ADDR MT6358_AUDDEC_ANA_CON14
#define PMIC_RG_LCLDO_EN_VA18_MASK 0x1
#define PMIC_RG_LCLDO_EN_VA18_SHIFT   4
#define PMIC_RG_LCLDO_PDDIS_EN_VA18_ADDR   MT6358_AUDDEC_ANA_CON14
#define PMIC_RG_LCLDO_PDDIS_EN_VA18_MASK   0x1
#define PMIC_RG_LCLDO_PDDIS_EN_VA18_SHIFT   5
#define PMIC_RG_LCLDO_REMOTE_SENSE_VA18_ADDR  MT6358_AUDDEC_ANA_CON14
#define PMIC_RG_LCLDO_REMOTE_SENSE_VA18_MASK  0x1
#define PMIC_RG_LCLDO_REMOTE_SENSE_VA18_SHIFT 6
#define PMIC_RG_LCLDO_ENC_EN_VA28_ADDR  MT6358_AUDDEC_ANA_CON14
#define PMIC_RG_LCLDO_ENC_EN_VA28_MASK  0x1
#define PMIC_RG_LCLDO_ENC_EN_VA28_SHIFT 8
#define PMIC_RG_LCLDO_ENC_PDDIS_EN_VA28_ADDR  MT6358_AUDDEC_ANA_CON14
#define PMIC_RG_LCLDO_ENC_PDDIS_EN_VA28_MASK  0x1
#define PMIC_RG_LCLDO_ENC_PDDIS_EN_VA28_SHIFT 9
#define PMIC_RG_LCLDO_ENC_REMOTE_SENSE_VA28_ADDR  MT6358_AUDDEC_ANA_CON14
#define PMIC_RG_LCLDO_ENC_REMOTE_SENSE_VA28_MASK  0x1
#define PMIC_RG_LCLDO_ENC_REMOTE_SENSE_VA28_SHIFT 10
#define PMIC_RG_VA33REFGEN_EN_VA18_ADDR MT6358_AUDDEC_ANA_CON14
#define PMIC_RG_VA33REFGEN_EN_VA18_MASK 0x1
#define PMIC_RG_VA33REFGEN_EN_VA18_SHIFT   12
#define PMIC_RG_VA28REFGEN_EN_VA28_ADDR MT6358_AUDDEC_ANA_CON14
#define PMIC_RG_VA28REFGEN_EN_VA28_MASK 0x1
#define PMIC_RG_VA28REFGEN_EN_VA28_SHIFT   13
#define PMIC_RG_HCLDO_VOSEL_VA18_ADDR MT6358_AUDDEC_ANA_CON14
#define PMIC_RG_HCLDO_VOSEL_VA18_MASK 0x1
#define PMIC_RG_HCLDO_VOSEL_VA18_SHIFT  14
#define PMIC_RG_LCLDO_VOSEL_VA18_ADDR MT6358_AUDDEC_ANA_CON14
#define PMIC_RG_LCLDO_VOSEL_VA18_MASK 0x1
#define PMIC_RG_LCLDO_VOSEL_VA18_SHIFT  15
#define PMIC_RG_NVREG_EN_VAUDP15_ADDR MT6358_AUDDEC_ANA_CON15
#define PMIC_RG_NVREG_EN_VAUDP15_MASK 0x1
#define PMIC_RG_NVREG_EN_VAUDP15_SHIFT  0
#define PMIC_RG_NVREG_PULL0V_VAUDP15_ADDR   MT6358_AUDDEC_ANA_CON15
#define PMIC_RG_NVREG_PULL0V_VAUDP15_MASK   0x1
#define PMIC_RG_NVREG_PULL0V_VAUDP15_SHIFT  1
#define PMIC_RG_AUDPMU_RSD0_VAUDP15_ADDR   MT6358_AUDDEC_ANA_CON15
#define PMIC_RG_AUDPMU_RSD0_VAUDP15_MASK   0xF
#define PMIC_RG_AUDPMU_RSD0_VAUDP15_SHIFT   4
#define PMIC_RG_AUDPMU_RSD0_VA18_ADDR MT6358_AUDDEC_ANA_CON15
#define PMIC_RG_AUDPMU_RSD0_VA18_MASK 0xF
#define PMIC_RG_AUDPMU_RSD0_VA18_SHIFT  8
#define PMIC_RG_AUDPMU_RSD0_VA28_ADDR MT6358_AUDDEC_ANA_CON15
#define PMIC_RG_AUDPMU_RSD0_VA28_MASK 0xF
#define PMIC_RG_AUDPMU_RSD0_VA28_SHIFT  12
#define PMIC_AUDDEC_ELR_LEN_ADDR  MT6358_AUDDEC_ELR_NUM
#define PMIC_AUDDEC_ELR_LEN_MASK  0xFF
#define PMIC_AUDDEC_ELR_LEN_SHIFT 0
#define PMIC_RG_AUDHPLTRIM_VAUDP15_ADDR MT6358_AUDDEC_ELR_0
#define PMIC_RG_AUDHPLTRIM_VAUDP15_MASK 0xF
#define PMIC_RG_AUDHPLTRIM_VAUDP15_SHIFT   0
#define PMIC_RG_AUDHPRTRIM_VAUDP15_ADDR MT6358_AUDDEC_ELR_0
#define PMIC_RG_AUDHPRTRIM_VAUDP15_MASK 0xF
#define PMIC_RG_AUDHPRTRIM_VAUDP15_SHIFT   4
#define PMIC_RG_AUDHPLFINETRIM_VAUDP15_ADDR MT6358_AUDDEC_ELR_0
#define PMIC_RG_AUDHPLFINETRIM_VAUDP15_MASK 0x3
#define PMIC_RG_AUDHPLFINETRIM_VAUDP15_SHIFT  8
#define PMIC_RG_AUDHPRFINETRIM_VAUDP15_ADDR MT6358_AUDDEC_ELR_0
#define PMIC_RG_AUDHPRFINETRIM_VAUDP15_MASK 0x3
#define PMIC_RG_AUDHPRFINETRIM_VAUDP15_SHIFT  10
#define PMIC_RG_AUDHPTRIM_EN_VAUDP15_ADDR   MT6358_AUDDEC_ELR_0
#define PMIC_RG_AUDHPTRIM_EN_VAUDP15_MASK   0x1
#define PMIC_RG_AUDHPTRIM_EN_VAUDP15_SHIFT  12
#define PMIC_AUDZCD_ANA_ID_ADDR MT6358_AUDZCD_DSN_ID
#define PMIC_AUDZCD_ANA_ID_MASK 0xFF
#define PMIC_AUDZCD_ANA_ID_SHIFT  0
#define PMIC_AUDZCD_DIG_ID_ADDR MT6358_AUDZCD_DSN_ID
#define PMIC_AUDZCD_DIG_ID_MASK 0xFF
#define PMIC_AUDZCD_DIG_ID_SHIFT  8
#define PMIC_AUDZCD_ANA_MINOR_REV_ADDR  MT6358_AUDZCD_DSN_REV0
#define PMIC_AUDZCD_ANA_MINOR_REV_MASK  0xF
#define PMIC_AUDZCD_ANA_MINOR_REV_SHIFT 0
#define PMIC_AUDZCD_ANA_MAJOR_REV_ADDR  MT6358_AUDZCD_DSN_REV0
#define PMIC_AUDZCD_ANA_MAJOR_REV_MASK  0xF
#define PMIC_AUDZCD_ANA_MAJOR_REV_SHIFT 4
#define PMIC_AUDZCD_DIG_MINOR_REV_ADDR  MT6358_AUDZCD_DSN_REV0
#define PMIC_AUDZCD_DIG_MINOR_REV_MASK  0xF
#define PMIC_AUDZCD_DIG_MINOR_REV_SHIFT 8
#define PMIC_AUDZCD_DIG_MAJOR_REV_ADDR  MT6358_AUDZCD_DSN_REV0
#define PMIC_AUDZCD_DIG_MAJOR_REV_MASK  0xF
#define PMIC_AUDZCD_DIG_MAJOR_REV_SHIFT 12
#define PMIC_AUDZCD_DSN_CBS_ADDR  MT6358_AUDZCD_DSN_DBI
#define PMIC_AUDZCD_DSN_CBS_MASK  0x3
#define PMIC_AUDZCD_DSN_CBS_SHIFT 0
#define PMIC_AUDZCD_DSN_BIX_ADDR  MT6358_AUDZCD_DSN_DBI
#define PMIC_AUDZCD_DSN_BIX_MASK  0x3
#define PMIC_AUDZCD_DSN_BIX_SHIFT 2
#define PMIC_AUDZCD_DSN_ESP_ADDR  MT6358_AUDZCD_DSN_DBI
#define PMIC_AUDZCD_DSN_ESP_MASK  0xFF
#define PMIC_AUDZCD_DSN_ESP_SHIFT 8
#define PMIC_AUDZCD_DSN_FPI_ADDR  MT6358_AUDZCD_DSN_FPI
#define PMIC_AUDZCD_DSN_FPI_MASK  0xFF
#define PMIC_AUDZCD_DSN_FPI_SHIFT 0
#define PMIC_RG_AUDZCDENABLE_ADDR MT6358_ZCD_CON0
#define PMIC_RG_AUDZCDENABLE_MASK 0x1
#define PMIC_RG_AUDZCDENABLE_SHIFT 0
#define PMIC_RG_AUDZCDGAINSTEPTIME_ADDR MT6358_ZCD_CON0
#define PMIC_RG_AUDZCDGAINSTEPTIME_MASK 0x7
#define PMIC_RG_AUDZCDGAINSTEPTIME_SHIFT   1
#define PMIC_RG_AUDZCDGAINSTEPSIZE_ADDR MT6358_ZCD_CON0
#define PMIC_RG_AUDZCDGAINSTEPSIZE_MASK 0x3
#define PMIC_RG_AUDZCDGAINSTEPSIZE_SHIFT   4
#define PMIC_RG_AUDZCDTIMEOUTMODESEL_ADDR   MT6358_ZCD_CON0
#define PMIC_RG_AUDZCDTIMEOUTMODESEL_MASK   0x1
#define PMIC_RG_AUDZCDTIMEOUTMODESEL_SHIFT  6
#define PMIC_RG_AUDLOLGAIN_ADDR MT6358_ZCD_CON1
#define PMIC_RG_AUDLOLGAIN_MASK 0x1F
#define PMIC_RG_AUDLOLGAIN_SHIFT  0
#define PMIC_RG_AUDLORGAIN_ADDR MT6358_ZCD_CON1
#define PMIC_RG_AUDLORGAIN_MASK 0x1F
#define PMIC_RG_AUDLORGAIN_SHIFT  7
#define PMIC_RG_AUDHPLGAIN_ADDR MT6358_ZCD_CON2
#define PMIC_RG_AUDHPLGAIN_MASK 0x1F
#define PMIC_RG_AUDHPLGAIN_SHIFT  0
#define PMIC_RG_AUDHPRGAIN_ADDR MT6358_ZCD_CON2
#define PMIC_RG_AUDHPRGAIN_MASK 0x1F
#define PMIC_RG_AUDHPRGAIN_SHIFT  7
#define PMIC_RG_AUDHSGAIN_ADDR  MT6358_ZCD_CON3
#define PMIC_RG_AUDHSGAIN_MASK  0x1F
#define PMIC_RG_AUDHSGAIN_SHIFT 0
#define PMIC_RG_AUDIVLGAIN_ADDR MT6358_ZCD_CON4
#define PMIC_RG_AUDIVLGAIN_MASK 0x7
#define PMIC_RG_AUDIVLGAIN_SHIFT  0
#define PMIC_RG_AUDIVRGAIN_ADDR MT6358_ZCD_CON4
#define PMIC_RG_AUDIVRGAIN_MASK 0x7
#define PMIC_RG_AUDIVRGAIN_SHIFT  8
#define PMIC_RG_AUDINTGAIN1_ADDR  MT6358_ZCD_CON5
#define PMIC_RG_AUDINTGAIN1_MASK  0x3F
#define PMIC_RG_AUDINTGAIN1_SHIFT 0
#define PMIC_RG_AUDINTGAIN2_ADDR  MT6358_ZCD_CON5
#define PMIC_RG_AUDINTGAIN2_MASK  0x3F
#define PMIC_RG_AUDINTGAIN2_SHIFT 8
#define PMIC_ACCDET_ANA_ID_ADDR MT6358_ACCDET_DSN_DIG_ID
#define PMIC_ACCDET_ANA_ID_MASK 0xFF
#define PMIC_ACCDET_ANA_ID_SHIFT  0
#define PMIC_ACCDET_DIG_ID_ADDR MT6358_ACCDET_DSN_DIG_ID
#define PMIC_ACCDET_DIG_ID_MASK 0xFF
#define PMIC_ACCDET_DIG_ID_SHIFT  8
#define PMIC_ACCDET_ANA_MINOR_REV_ADDR  MT6358_ACCDET_DSN_DIG_REV0
#define PMIC_ACCDET_ANA_MINOR_REV_MASK  0xF
#define PMIC_ACCDET_ANA_MINOR_REV_SHIFT 0
#define PMIC_ACCDET_ANA_MAJOR_REV_ADDR  MT6358_ACCDET_DSN_DIG_REV0
#define PMIC_ACCDET_ANA_MAJOR_REV_MASK  0xF
#define PMIC_ACCDET_ANA_MAJOR_REV_SHIFT 4
#define PMIC_ACCDET_DIG_MINOR_REV_ADDR  MT6358_ACCDET_DSN_DIG_REV0
#define PMIC_ACCDET_DIG_MINOR_REV_MASK  0xF
#define PMIC_ACCDET_DIG_MINOR_REV_SHIFT 8
#define PMIC_ACCDET_DIG_MAJOR_REV_ADDR  MT6358_ACCDET_DSN_DIG_REV0
#define PMIC_ACCDET_DIG_MAJOR_REV_MASK  0xF
#define PMIC_ACCDET_DIG_MAJOR_REV_SHIFT 12
#define PMIC_ACCDET_DSN_CBS_ADDR  MT6358_ACCDET_DSN_DBI
#define PMIC_ACCDET_DSN_CBS_MASK  0x3
#define PMIC_ACCDET_DSN_CBS_SHIFT 0
#define PMIC_ACCDET_DSN_BIX_ADDR  MT6358_ACCDET_DSN_DBI
#define PMIC_ACCDET_DSN_BIX_MASK  0x3
#define PMIC_ACCDET_DSN_BIX_SHIFT 2
#define PMIC_ACCDET_ESP_ADDR MT6358_ACCDET_DSN_DBI
#define PMIC_ACCDET_ESP_MASK 0xFF
#define PMIC_ACCDET_ESP_SHIFT   8
#define PMIC_ACCDET_DSN_FPI_ADDR  MT6358_ACCDET_DSN_FPI
#define PMIC_ACCDET_DSN_FPI_MASK  0xFF
#define PMIC_ACCDET_DSN_FPI_SHIFT 0
#define PMIC_AUDACCDETAUXADCSWCTRL_ADDR MT6358_ACCDET_CON0
#define PMIC_AUDACCDETAUXADCSWCTRL_MASK 0x1
#define PMIC_AUDACCDETAUXADCSWCTRL_SHIFT   10
#define PMIC_AUDACCDETAUXADCSWCTRL_SEL_ADDR MT6358_ACCDET_CON0
#define PMIC_AUDACCDETAUXADCSWCTRL_SEL_MASK 0x1
#define PMIC_AUDACCDETAUXADCSWCTRL_SEL_SHIFT  11
#define PMIC_RG_AUDACCDETRSV_ADDR MT6358_ACCDET_CON0
#define PMIC_RG_AUDACCDETRSV_MASK 0x3
#define PMIC_RG_AUDACCDETRSV_SHIFT 13
#define PMIC_ACCDET_EN_ADDR  MT6358_ACCDET_CON1
#define PMIC_ACCDET_EN_MASK  0x1
#define PMIC_ACCDET_EN_SHIFT 0
#define PMIC_ACCDET_SEQ_INIT_ADDR MT6358_ACCDET_CON1
#define PMIC_ACCDET_SEQ_INIT_MASK 0x1
#define PMIC_ACCDET_SEQ_INIT_SHIFT 1
#define PMIC_ACCDET_EINT0_EN_ADDR MT6358_ACCDET_CON1
#define PMIC_ACCDET_EINT0_EN_MASK 0x1
#define PMIC_ACCDET_EINT0_EN_SHIFT 2
#define PMIC_ACCDET_EINT0_SEQ_INIT_ADDR MT6358_ACCDET_CON1
#define PMIC_ACCDET_EINT0_SEQ_INIT_MASK 0x1
#define PMIC_ACCDET_EINT0_SEQ_INIT_SHIFT   3
#define PMIC_ACCDET_EINT1_EN_ADDR MT6358_ACCDET_CON1
#define PMIC_ACCDET_EINT1_EN_MASK 0x1
#define PMIC_ACCDET_EINT1_EN_SHIFT 4
#define PMIC_ACCDET_EINT1_SEQ_INIT_ADDR MT6358_ACCDET_CON1
#define PMIC_ACCDET_EINT1_SEQ_INIT_MASK 0x1
#define PMIC_ACCDET_EINT1_SEQ_INIT_SHIFT   5
#define PMIC_ACCDET_ANASWCTRL_SEL_ADDR  MT6358_ACCDET_CON1
#define PMIC_ACCDET_ANASWCTRL_SEL_MASK  0x1
#define PMIC_ACCDET_ANASWCTRL_SEL_SHIFT 6
#define PMIC_ACCDET_CMP_PWM_EN_ADDR   MT6358_ACCDET_CON2
#define PMIC_ACCDET_CMP_PWM_EN_MASK   0x1
#define PMIC_ACCDET_CMP_PWM_EN_SHIFT  0
#define PMIC_ACCDET_VTH_PWM_EN_ADDR   MT6358_ACCDET_CON2
#define PMIC_ACCDET_VTH_PWM_EN_MASK   0x1
#define PMIC_ACCDET_VTH_PWM_EN_SHIFT  1
#define PMIC_ACCDET_MBIAS_PWM_EN_ADDR MT6358_ACCDET_CON2
#define PMIC_ACCDET_MBIAS_PWM_EN_MASK 0x1
#define PMIC_ACCDET_MBIAS_PWM_EN_SHIFT  2
#define PMIC_ACCDET_EINT0_PWM_EN_ADDR MT6358_ACCDET_CON2
#define PMIC_ACCDET_EINT0_PWM_EN_MASK 0x1
#define PMIC_ACCDET_EINT0_PWM_EN_SHIFT  3
#define PMIC_ACCDET_EINT1_PWM_EN_ADDR MT6358_ACCDET_CON2
#define PMIC_ACCDET_EINT1_PWM_EN_MASK 0x1
#define PMIC_ACCDET_EINT1_PWM_EN_SHIFT  4
#define PMIC_ACCDET_CMP_PWM_IDLE_ADDR MT6358_ACCDET_CON2
#define PMIC_ACCDET_CMP_PWM_IDLE_MASK 0x1
#define PMIC_ACCDET_CMP_PWM_IDLE_SHIFT  8
#define PMIC_ACCDET_VTH_PWM_IDLE_ADDR MT6358_ACCDET_CON2
#define PMIC_ACCDET_VTH_PWM_IDLE_MASK 0x1
#define PMIC_ACCDET_VTH_PWM_IDLE_SHIFT  9
#define PMIC_ACCDET_MBIAS_PWM_IDLE_ADDR MT6358_ACCDET_CON2
#define PMIC_ACCDET_MBIAS_PWM_IDLE_MASK 0x1
#define PMIC_ACCDET_MBIAS_PWM_IDLE_SHIFT   10
#define PMIC_ACCDET_EINT0_PWM_IDLE_ADDR MT6358_ACCDET_CON2
#define PMIC_ACCDET_EINT0_PWM_IDLE_MASK 0x1
#define PMIC_ACCDET_EINT0_PWM_IDLE_SHIFT   11
#define PMIC_ACCDET_EINT1_PWM_IDLE_ADDR MT6358_ACCDET_CON2
#define PMIC_ACCDET_EINT1_PWM_IDLE_MASK 0x1
#define PMIC_ACCDET_EINT1_PWM_IDLE_SHIFT   12
#define PMIC_ACCDET_PWM_WIDTH_ADDR MT6358_ACCDET_CON3
#define PMIC_ACCDET_PWM_WIDTH_MASK 0xFFFF
#define PMIC_ACCDET_PWM_WIDTH_SHIFT   0
#define PMIC_ACCDET_PWM_THRESH_ADDR   MT6358_ACCDET_CON4
#define PMIC_ACCDET_PWM_THRESH_MASK   0xFFFF
#define PMIC_ACCDET_PWM_THRESH_SHIFT  0
#define PMIC_ACCDET_RISE_DELAY_ADDR   MT6358_ACCDET_CON5
#define PMIC_ACCDET_RISE_DELAY_MASK   0x7FFF
#define PMIC_ACCDET_RISE_DELAY_SHIFT  0
#define PMIC_ACCDET_FALL_DELAY_ADDR   MT6358_ACCDET_CON5
#define PMIC_ACCDET_FALL_DELAY_MASK   0x1
#define PMIC_ACCDET_FALL_DELAY_SHIFT  15
#define PMIC_ACCDET_DEBOUNCE0_ADDR MT6358_ACCDET_CON6
#define PMIC_ACCDET_DEBOUNCE0_MASK 0xFFFF
#define PMIC_ACCDET_DEBOUNCE0_SHIFT   0
#define PMIC_ACCDET_DEBOUNCE1_ADDR MT6358_ACCDET_CON7
#define PMIC_ACCDET_DEBOUNCE1_MASK 0xFFFF
#define PMIC_ACCDET_DEBOUNCE1_SHIFT   0
#define PMIC_ACCDET_DEBOUNCE2_ADDR MT6358_ACCDET_CON8
#define PMIC_ACCDET_DEBOUNCE2_MASK 0xFFFF
#define PMIC_ACCDET_DEBOUNCE2_SHIFT   0
#define PMIC_ACCDET_DEBOUNCE3_ADDR MT6358_ACCDET_CON9
#define PMIC_ACCDET_DEBOUNCE3_MASK 0xFFFF
#define PMIC_ACCDET_DEBOUNCE3_SHIFT   0
#define PMIC_ACCDET_DEBOUNCE4_ADDR MT6358_ACCDET_CON10
#define PMIC_ACCDET_DEBOUNCE4_MASK 0xFFFF
#define PMIC_ACCDET_DEBOUNCE4_SHIFT   0
#define PMIC_ACCDET_IVAL_CUR_IN_ADDR  MT6358_ACCDET_CON11
#define PMIC_ACCDET_IVAL_CUR_IN_MASK  0x3
#define PMIC_ACCDET_IVAL_CUR_IN_SHIFT 0
#define PMIC_ACCDET_EINT0_IVAL_CUR_IN_ADDR  MT6358_ACCDET_CON11
#define PMIC_ACCDET_EINT0_IVAL_CUR_IN_MASK  0x1
#define PMIC_ACCDET_EINT0_IVAL_CUR_IN_SHIFT 2
#define PMIC_ACCDET_EINT1_IVAL_CUR_IN_ADDR  MT6358_ACCDET_CON11
#define PMIC_ACCDET_EINT1_IVAL_CUR_IN_MASK  0x1
#define PMIC_ACCDET_EINT1_IVAL_CUR_IN_SHIFT 3
#define PMIC_ACCDET_IVAL_SAM_IN_ADDR  MT6358_ACCDET_CON11
#define PMIC_ACCDET_IVAL_SAM_IN_MASK  0x3
#define PMIC_ACCDET_IVAL_SAM_IN_SHIFT 4
#define PMIC_ACCDET_EINT0_IVAL_SAM_IN_ADDR  MT6358_ACCDET_CON11
#define PMIC_ACCDET_EINT0_IVAL_SAM_IN_MASK  0x1
#define PMIC_ACCDET_EINT0_IVAL_SAM_IN_SHIFT 6
#define PMIC_ACCDET_EINT1_IVAL_SAM_IN_ADDR  MT6358_ACCDET_CON11
#define PMIC_ACCDET_EINT1_IVAL_SAM_IN_MASK  0x1
#define PMIC_ACCDET_EINT1_IVAL_SAM_IN_SHIFT 7
#define PMIC_ACCDET_IVAL_MEM_IN_ADDR  MT6358_ACCDET_CON11
#define PMIC_ACCDET_IVAL_MEM_IN_MASK  0x3
#define PMIC_ACCDET_IVAL_MEM_IN_SHIFT 8
#define PMIC_ACCDET_EINT0_IVAL_MEM_IN_ADDR  MT6358_ACCDET_CON11
#define PMIC_ACCDET_EINT0_IVAL_MEM_IN_MASK  0x1
#define PMIC_ACCDET_EINT0_IVAL_MEM_IN_SHIFT 10
#define PMIC_ACCDET_EINT1_IVAL_MEM_IN_ADDR  MT6358_ACCDET_CON11
#define PMIC_ACCDET_EINT1_IVAL_MEM_IN_MASK  0x1
#define PMIC_ACCDET_EINT1_IVAL_MEM_IN_SHIFT 11
#define PMIC_ACCDET_IVAL_SEL_ADDR MT6358_ACCDET_CON11
#define PMIC_ACCDET_IVAL_SEL_MASK 0x1
#define PMIC_ACCDET_IVAL_SEL_SHIFT 13
#define PMIC_ACCDET_EINT0_IVAL_SEL_ADDR MT6358_ACCDET_CON11
#define PMIC_ACCDET_EINT0_IVAL_SEL_MASK 0x1
#define PMIC_ACCDET_EINT0_IVAL_SEL_SHIFT   14
#define PMIC_ACCDET_EINT1_IVAL_SEL_ADDR MT6358_ACCDET_CON11
#define PMIC_ACCDET_EINT1_IVAL_SEL_MASK 0x1
#define PMIC_ACCDET_EINT1_IVAL_SEL_SHIFT   15
#define PMIC_ACCDET_IRQ_ADDR MT6358_ACCDET_CON12
#define PMIC_ACCDET_IRQ_MASK 0x1
#define PMIC_ACCDET_IRQ_SHIFT   0
#define PMIC_ACCDET_EINT0_IRQ_ADDR MT6358_ACCDET_CON12
#define PMIC_ACCDET_EINT0_IRQ_MASK 0x1
#define PMIC_ACCDET_EINT0_IRQ_SHIFT   2
#define PMIC_ACCDET_EINT1_IRQ_ADDR MT6358_ACCDET_CON12
#define PMIC_ACCDET_EINT1_IRQ_MASK 0x1
#define PMIC_ACCDET_EINT1_IRQ_SHIFT   3
#define PMIC_ACCDET_IRQ_CLR_ADDR  MT6358_ACCDET_CON12
#define PMIC_ACCDET_IRQ_CLR_MASK  0x1
#define PMIC_ACCDET_IRQ_CLR_SHIFT 8
#define PMIC_ACCDET_EINT0_IRQ_CLR_ADDR  MT6358_ACCDET_CON12
#define PMIC_ACCDET_EINT0_IRQ_CLR_MASK  0x1
#define PMIC_ACCDET_EINT0_IRQ_CLR_SHIFT 10
#define PMIC_ACCDET_EINT1_IRQ_CLR_ADDR  MT6358_ACCDET_CON12
#define PMIC_ACCDET_EINT1_IRQ_CLR_MASK  0x1
#define PMIC_ACCDET_EINT1_IRQ_CLR_SHIFT 11
#define PMIC_ACCDET_EINT0_IRQ_POLARITY_ADDR MT6358_ACCDET_CON12
#define PMIC_ACCDET_EINT0_IRQ_POLARITY_MASK 0x1
#define PMIC_ACCDET_EINT0_IRQ_POLARITY_SHIFT  14
#define PMIC_ACCDET_EINT1_IRQ_POLARITY_ADDR MT6358_ACCDET_CON12
#define PMIC_ACCDET_EINT1_IRQ_POLARITY_MASK 0x1
#define PMIC_ACCDET_EINT1_IRQ_POLARITY_SHIFT  15
#define PMIC_ACCDET_TEST_MODE0_ADDR   MT6358_ACCDET_CON13
#define PMIC_ACCDET_TEST_MODE0_MASK   0x1
#define PMIC_ACCDET_TEST_MODE0_SHIFT  0
#define PMIC_ACCDET_CMP_SWSEL_ADDR MT6358_ACCDET_CON13
#define PMIC_ACCDET_CMP_SWSEL_MASK 0x1
#define PMIC_ACCDET_CMP_SWSEL_SHIFT   1
#define PMIC_ACCDET_VTH_SWSEL_ADDR MT6358_ACCDET_CON13
#define PMIC_ACCDET_VTH_SWSEL_MASK 0x1
#define PMIC_ACCDET_VTH_SWSEL_SHIFT   2
#define PMIC_ACCDET_MBIAS_SWSEL_ADDR  MT6358_ACCDET_CON13
#define PMIC_ACCDET_MBIAS_SWSEL_MASK  0x1
#define PMIC_ACCDET_MBIAS_SWSEL_SHIFT 3
#define PMIC_ACCDET_TEST_MODE4_ADDR   MT6358_ACCDET_CON13
#define PMIC_ACCDET_TEST_MODE4_MASK   0x1
#define PMIC_ACCDET_TEST_MODE4_SHIFT  4
#define PMIC_ACCDET_TEST_MODE5_ADDR   MT6358_ACCDET_CON13
#define PMIC_ACCDET_TEST_MODE5_MASK   0x1
#define PMIC_ACCDET_TEST_MODE5_SHIFT  5
#define PMIC_ACCDET_PWM_SEL_ADDR  MT6358_ACCDET_CON13
#define PMIC_ACCDET_PWM_SEL_MASK  0x3
#define PMIC_ACCDET_PWM_SEL_SHIFT 6
#define PMIC_ACCDET_IN_SW_ADDR  MT6358_ACCDET_CON13
#define PMIC_ACCDET_IN_SW_MASK  0x3
#define PMIC_ACCDET_IN_SW_SHIFT 8
#define PMIC_ACCDET_CMP_EN_SW_ADDR MT6358_ACCDET_CON13
#define PMIC_ACCDET_CMP_EN_SW_MASK 0x1
#define PMIC_ACCDET_CMP_EN_SW_SHIFT   12
#define PMIC_ACCDET_VTH_EN_SW_ADDR MT6358_ACCDET_CON13
#define PMIC_ACCDET_VTH_EN_SW_MASK 0x1
#define PMIC_ACCDET_VTH_EN_SW_SHIFT   13
#define PMIC_ACCDET_MBIAS_EN_SW_ADDR  MT6358_ACCDET_CON13
#define PMIC_ACCDET_MBIAS_EN_SW_MASK  0x1
#define PMIC_ACCDET_MBIAS_EN_SW_SHIFT 14
#define PMIC_ACCDET_PWM_EN_SW_ADDR MT6358_ACCDET_CON13
#define PMIC_ACCDET_PWM_EN_SW_MASK 0x1
#define PMIC_ACCDET_PWM_EN_SW_SHIFT   15
#define PMIC_ACCDET_IN_ADDR  MT6358_ACCDET_CON14
#define PMIC_ACCDET_IN_MASK  0x3
#define PMIC_ACCDET_IN_SHIFT 0
#define PMIC_ACCDET_CUR_IN_ADDR MT6358_ACCDET_CON14
#define PMIC_ACCDET_CUR_IN_MASK 0x3
#define PMIC_ACCDET_CUR_IN_SHIFT  2
#define PMIC_ACCDET_SAM_IN_ADDR MT6358_ACCDET_CON14
#define PMIC_ACCDET_SAM_IN_MASK 0x3
#define PMIC_ACCDET_SAM_IN_SHIFT  4
#define PMIC_ACCDET_MEM_IN_ADDR MT6358_ACCDET_CON14
#define PMIC_ACCDET_MEM_IN_MASK 0x3
#define PMIC_ACCDET_MEM_IN_SHIFT  6
#define PMIC_ACCDET_STATE_ADDR  MT6358_ACCDET_CON14
#define PMIC_ACCDET_STATE_MASK  0x7
#define PMIC_ACCDET_STATE_SHIFT 8
#define PMIC_ACCDET_MBIAS_CLK_ADDR MT6358_ACCDET_CON14
#define PMIC_ACCDET_MBIAS_CLK_MASK 0x1
#define PMIC_ACCDET_MBIAS_CLK_SHIFT   12
#define PMIC_ACCDET_VTH_CLK_ADDR  MT6358_ACCDET_CON14
#define PMIC_ACCDET_VTH_CLK_MASK  0x1
#define PMIC_ACCDET_VTH_CLK_SHIFT 13
#define PMIC_ACCDET_CMP_CLK_ADDR  MT6358_ACCDET_CON14
#define PMIC_ACCDET_CMP_CLK_MASK  0x1
#define PMIC_ACCDET_CMP_CLK_SHIFT 14
#define PMIC_DA_AUDACCDETAUXADCSWCTRL_ADDR  MT6358_ACCDET_CON14
#define PMIC_DA_AUDACCDETAUXADCSWCTRL_MASK  0x1
#define PMIC_DA_AUDACCDETAUXADCSWCTRL_SHIFT 15
#define PMIC_ACCDET_EINT0_DEB_SEL_ADDR  MT6358_ACCDET_CON15
#define PMIC_ACCDET_EINT0_DEB_SEL_MASK  0x1
#define PMIC_ACCDET_EINT0_DEB_SEL_SHIFT 0
#define PMIC_ACCDET_EINT0_DEBOUNCE_ADDR MT6358_ACCDET_CON15
#define PMIC_ACCDET_EINT0_DEBOUNCE_MASK 0xF
#define PMIC_ACCDET_EINT0_DEBOUNCE_SHIFT   3
#define PMIC_ACCDET_EINT0_PWM_THRESH_ADDR   MT6358_ACCDET_CON15
#define PMIC_ACCDET_EINT0_PWM_THRESH_MASK   0x7
#define PMIC_ACCDET_EINT0_PWM_THRESH_SHIFT  8
#define PMIC_ACCDET_EINT0_PWM_WIDTH_ADDR   MT6358_ACCDET_CON15
#define PMIC_ACCDET_EINT0_PWM_WIDTH_MASK   0x3
#define PMIC_ACCDET_EINT0_PWM_WIDTH_SHIFT   12
#define PMIC_ACCDET_EINT0_PWM_FALL_DELAY_ADDR MT6358_ACCDET_CON16
#define PMIC_ACCDET_EINT0_PWM_FALL_DELAY_MASK 0x1
#define PMIC_ACCDET_EINT0_PWM_FALL_DELAY_SHIFT   5
#define PMIC_ACCDET_EINT0_PWM_RISE_DELAY_ADDR MT6358_ACCDET_CON16
#define PMIC_ACCDET_EINT0_PWM_RISE_DELAY_MASK 0x3FF
#define PMIC_ACCDET_EINT0_PWM_RISE_DELAY_SHIFT   6
#define PMIC_ACCDET_TEST_MODE11_ADDR  MT6358_ACCDET_CON17
#define PMIC_ACCDET_TEST_MODE11_MASK  0x1
#define PMIC_ACCDET_TEST_MODE11_SHIFT 5
#define PMIC_ACCDET_TEST_MODE10_ADDR  MT6358_ACCDET_CON17
#define PMIC_ACCDET_TEST_MODE10_MASK  0x1
#define PMIC_ACCDET_TEST_MODE10_SHIFT 6
#define PMIC_ACCDET_EINT0_CMPOUT_SW_ADDR   MT6358_ACCDET_CON17
#define PMIC_ACCDET_EINT0_CMPOUT_SW_MASK   0x1
#define PMIC_ACCDET_EINT0_CMPOUT_SW_SHIFT   7
#define PMIC_ACCDET_EINT1_CMPOUT_SW_ADDR   MT6358_ACCDET_CON17
#define PMIC_ACCDET_EINT1_CMPOUT_SW_MASK   0x1
#define PMIC_ACCDET_EINT1_CMPOUT_SW_SHIFT   8
#define PMIC_ACCDET_TEST_MODE9_ADDR   MT6358_ACCDET_CON17
#define PMIC_ACCDET_TEST_MODE9_MASK   0x1
#define PMIC_ACCDET_TEST_MODE9_SHIFT  9
#define PMIC_ACCDET_TEST_MODE8_ADDR   MT6358_ACCDET_CON17
#define PMIC_ACCDET_TEST_MODE8_MASK   0x1
#define PMIC_ACCDET_TEST_MODE8_SHIFT  10
#define PMIC_ACCDET_AUXADC_CTRL_SW_ADDR MT6358_ACCDET_CON17
#define PMIC_ACCDET_AUXADC_CTRL_SW_MASK 0x1
#define PMIC_ACCDET_AUXADC_CTRL_SW_SHIFT   11
#define PMIC_ACCDET_TEST_MODE7_ADDR   MT6358_ACCDET_CON17
#define PMIC_ACCDET_TEST_MODE7_MASK   0x1
#define PMIC_ACCDET_TEST_MODE7_SHIFT  12
#define PMIC_ACCDET_TEST_MODE6_ADDR   MT6358_ACCDET_CON17
#define PMIC_ACCDET_TEST_MODE6_MASK   0x1
#define PMIC_ACCDET_TEST_MODE6_SHIFT  13
#define PMIC_ACCDET_EINT0_CMP_EN_SW_ADDR   MT6358_ACCDET_CON17
#define PMIC_ACCDET_EINT0_CMP_EN_SW_MASK   0x1
#define PMIC_ACCDET_EINT0_CMP_EN_SW_SHIFT   14
#define PMIC_ACCDET_EINT1_CMP_EN_SW_ADDR   MT6358_ACCDET_CON17
#define PMIC_ACCDET_EINT1_CMP_EN_SW_MASK   0x1
#define PMIC_ACCDET_EINT1_CMP_EN_SW_SHIFT   15
#define PMIC_ACCDET_EINT0_STATE_ADDR  MT6358_ACCDET_CON18
#define PMIC_ACCDET_EINT0_STATE_MASK  0x7
#define PMIC_ACCDET_EINT0_STATE_SHIFT 0
#define PMIC_ACCDET_AUXADC_DEBOUNCE_END_ADDR  MT6358_ACCDET_CON18
#define PMIC_ACCDET_AUXADC_DEBOUNCE_END_MASK  0x1
#define PMIC_ACCDET_AUXADC_DEBOUNCE_END_SHIFT 3
#define PMIC_ACCDET_AUXADC_CONNECT_PRE_ADDR MT6358_ACCDET_CON18
#define PMIC_ACCDET_AUXADC_CONNECT_PRE_MASK 0x1
#define PMIC_ACCDET_AUXADC_CONNECT_PRE_SHIFT  4
#define PMIC_ACCDET_EINT0_CUR_IN_ADDR MT6358_ACCDET_CON18
#define PMIC_ACCDET_EINT0_CUR_IN_MASK 0x1
#define PMIC_ACCDET_EINT0_CUR_IN_SHIFT  8
#define PMIC_ACCDET_EINT0_SAM_IN_ADDR MT6358_ACCDET_CON18
#define PMIC_ACCDET_EINT0_SAM_IN_MASK 0x1
#define PMIC_ACCDET_EINT0_SAM_IN_SHIFT  9
#define PMIC_ACCDET_EINT0_MEM_IN_ADDR MT6358_ACCDET_CON18
#define PMIC_ACCDET_EINT0_MEM_IN_MASK 0x1
#define PMIC_ACCDET_EINT0_MEM_IN_SHIFT  10
#define PMIC_AD_EINT0CMPOUT_ADDR  MT6358_ACCDET_CON18
#define PMIC_AD_EINT0CMPOUT_MASK  0x1
#define PMIC_AD_EINT0CMPOUT_SHIFT 14
#define PMIC_DA_NI_EINT0CMPEN_ADDR MT6358_ACCDET_CON18
#define PMIC_DA_NI_EINT0CMPEN_MASK 0x1
#define PMIC_DA_NI_EINT0CMPEN_SHIFT   15
#define PMIC_ACCDET_CUR_DEB_ADDR  MT6358_ACCDET_CON19
#define PMIC_ACCDET_CUR_DEB_MASK  0xFFFF
#define PMIC_ACCDET_CUR_DEB_SHIFT 0
#define PMIC_ACCDET_EINT0_CUR_DEB_ADDR  MT6358_ACCDET_CON20
#define PMIC_ACCDET_EINT0_CUR_DEB_MASK  0x7FFF
#define PMIC_ACCDET_EINT0_CUR_DEB_SHIFT 0
#define PMIC_ACCDET_MON_FLAG_EN_ADDR  MT6358_ACCDET_CON21
#define PMIC_ACCDET_MON_FLAG_EN_MASK  0x1
#define PMIC_ACCDET_MON_FLAG_EN_SHIFT 0
#define PMIC_ACCDET_MON_FLAG_SEL_ADDR MT6358_ACCDET_CON21
#define PMIC_ACCDET_MON_FLAG_SEL_MASK 0xFF
#define PMIC_ACCDET_MON_FLAG_SEL_SHIFT  4
#define PMIC_ACCDET_RSV_CON1_ADDR MT6358_ACCDET_CON22
#define PMIC_ACCDET_RSV_CON1_MASK 0xFFFF
#define PMIC_ACCDET_RSV_CON1_SHIFT 0
#define PMIC_ACCDET_AUXADC_CONNECT_TIME_ADDR  MT6358_ACCDET_CON23
#define PMIC_ACCDET_AUXADC_CONNECT_TIME_MASK  0xFFFF
#define PMIC_ACCDET_AUXADC_CONNECT_TIME_SHIFT 0
#define PMIC_ACCDET_HWEN_SEL_ADDR MT6358_ACCDET_CON24
#define PMIC_ACCDET_HWEN_SEL_MASK 0x3
#define PMIC_ACCDET_HWEN_SEL_SHIFT 0
#define PMIC_ACCDET_HWMODE_SEL_ADDR   MT6358_ACCDET_CON24
#define PMIC_ACCDET_HWMODE_SEL_MASK   0x1
#define PMIC_ACCDET_HWMODE_SEL_SHIFT  2
#define PMIC_ACCDET_EINT_DEB_OUT_DFF_ADDR   MT6358_ACCDET_CON24
#define PMIC_ACCDET_EINT_DEB_OUT_DFF_MASK   0x1
#define PMIC_ACCDET_EINT_DEB_OUT_DFF_SHIFT  3
#define PMIC_ACCDET_FAST_DISCHARGE_ADDR MT6358_ACCDET_CON24
#define PMIC_ACCDET_FAST_DISCHARGE_MASK 0x1
#define PMIC_ACCDET_FAST_DISCHARGE_SHIFT   4
#define PMIC_ACCDET_EINT0_REVERSE_ADDR  MT6358_ACCDET_CON24
#define PMIC_ACCDET_EINT0_REVERSE_MASK  0x1
#define PMIC_ACCDET_EINT0_REVERSE_SHIFT 14
#define PMIC_ACCDET_EINT1_REVERSE_ADDR  MT6358_ACCDET_CON24
#define PMIC_ACCDET_EINT1_REVERSE_MASK  0x1
#define PMIC_ACCDET_EINT1_REVERSE_SHIFT 15
#define PMIC_ACCDET_EINT1_DEB_SEL_ADDR  MT6358_ACCDET_CON25
#define PMIC_ACCDET_EINT1_DEB_SEL_MASK  0x1
#define PMIC_ACCDET_EINT1_DEB_SEL_SHIFT 0
#define PMIC_ACCDET_EINT1_DEBOUNCE_ADDR MT6358_ACCDET_CON25
#define PMIC_ACCDET_EINT1_DEBOUNCE_MASK 0xF
#define PMIC_ACCDET_EINT1_DEBOUNCE_SHIFT   3
#define PMIC_ACCDET_EINT1_PWM_THRESH_ADDR   MT6358_ACCDET_CON25
#define PMIC_ACCDET_EINT1_PWM_THRESH_MASK   0x7
#define PMIC_ACCDET_EINT1_PWM_THRESH_SHIFT  8
#define PMIC_ACCDET_EINT1_PWM_WIDTH_ADDR   MT6358_ACCDET_CON25
#define PMIC_ACCDET_EINT1_PWM_WIDTH_MASK   0x3
#define PMIC_ACCDET_EINT1_PWM_WIDTH_SHIFT   12
#define PMIC_ACCDET_EINT1_PWM_FALL_DELAY_ADDR MT6358_ACCDET_CON26
#define PMIC_ACCDET_EINT1_PWM_FALL_DELAY_MASK 0x1
#define PMIC_ACCDET_EINT1_PWM_FALL_DELAY_SHIFT   5
#define PMIC_ACCDET_EINT1_PWM_RISE_DELAY_ADDR MT6358_ACCDET_CON26
#define PMIC_ACCDET_EINT1_PWM_RISE_DELAY_MASK 0x3FF
#define PMIC_ACCDET_EINT1_PWM_RISE_DELAY_SHIFT   6
#define PMIC_ACCDET_EINT1_STATE_ADDR  MT6358_ACCDET_CON27
#define PMIC_ACCDET_EINT1_STATE_MASK  0x7
#define PMIC_ACCDET_EINT1_STATE_SHIFT 0
#define PMIC_ACCDET_EINT1_CUR_IN_ADDR MT6358_ACCDET_CON27
#define PMIC_ACCDET_EINT1_CUR_IN_MASK 0x1
#define PMIC_ACCDET_EINT1_CUR_IN_SHIFT  8
#define PMIC_ACCDET_EINT1_SAM_IN_ADDR MT6358_ACCDET_CON27
#define PMIC_ACCDET_EINT1_SAM_IN_MASK 0x1
#define PMIC_ACCDET_EINT1_SAM_IN_SHIFT  9
#define PMIC_ACCDET_EINT1_MEM_IN_ADDR MT6358_ACCDET_CON27
#define PMIC_ACCDET_EINT1_MEM_IN_MASK 0x1
#define PMIC_ACCDET_EINT1_MEM_IN_SHIFT  10
#define PMIC_AD_EINT1CMPOUT_ADDR  MT6358_ACCDET_CON27
#define PMIC_AD_EINT1CMPOUT_MASK  0x1
#define PMIC_AD_EINT1CMPOUT_SHIFT 14
#define PMIC_DA_NI_EINT1CMPEN_ADDR MT6358_ACCDET_CON27
#define PMIC_DA_NI_EINT1CMPEN_MASK 0x1
#define PMIC_DA_NI_EINT1CMPEN_SHIFT   15
#define PMIC_ACCDET_EINT1_CUR_DEB_ADDR  MT6358_ACCDET_CON28
#define PMIC_ACCDET_EINT1_CUR_DEB_MASK  0x7FFF
#define PMIC_ACCDET_EINT1_CUR_DEB_SHIFT 0

enum PMU_FLAGS_LIST {
	PMIC_TOP0_ANA_ID,
	PMIC_TOP0_DIG_ID,
	PMIC_TOP0_ANA_MINOR_REV,
	PMIC_TOP0_ANA_MAJOR_REV,
	PMIC_TOP0_DIG_MINOR_REV,
	PMIC_TOP0_DIG_MAJOR_REV,
	PMIC_TOP0_DSN_CBS,
	PMIC_TOP0_DSN_BIX,
	PMIC_TOP0_DSN_ESP,
	PMIC_TOP0_DSN_FPI,
	PMIC_HWCID,
	PMIC_SWCID,
	PMIC_STS_PWRKEY,
	PMIC_STS_RTCA,
	PMIC_STS_CHRIN,
	PMIC_STS_SPAR,
	PMIC_STS_RBOOT,
	PMIC_STS_UVLO,
	PMIC_STS_PGFAIL,
	PMIC_STS_PSOC,
	PMIC_STS_THRDN,
	PMIC_STS_WRST,
	PMIC_STS_CRST,
	PMIC_STS_PKEYLP,
	PMIC_STS_NORMOFF,
	PMIC_STS_BWDT,
	PMIC_STS_DDLO,
	PMIC_STS_WDT,
	PMIC_STS_PUPSRC,
	PMIC_STS_KEYPWR,
	PMIC_STS_PKSP,
	PMIC_RG_POFFSTS_CLR,
	PMIC_RG_PONSTS_CLR,
	PMIC_VIO18_PG_DEB,
	PMIC_VSRAM_PROC12_PG_DEB,
	PMIC_VSRAM_PROC11_PG_DEB,
	PMIC_VA12_PG_DEB,
	PMIC_VSRAM_GPU_PG_DEB,
	PMIC_VSRAM_OTHERS_PG_DEB,
	PMIC_VAUX18_PG_DEB,
	PMIC_VXO22_PG_DEB,
	PMIC_VDRAM1_PG_DEB,
	PMIC_VPROC12_PG_DEB,
	PMIC_VPROC11_PG_DEB,
	PMIC_VS1_PG_DEB,
	PMIC_VGPU_PG_DEB,
	PMIC_VMODEM_PG_DEB,
	PMIC_VCORE_PG_DEB,
	PMIC_VS2_PG_DEB,
	PMIC_RSV_PG_DEB,
	PMIC_VAUD28_PG_DEB,
	PMIC_VUSB_PG_DEB,
	PMIC_VDRAM2_PG_DEB,
	PMIC_VIO28_PG_DEB,
	PMIC_VEMC_PG_DEB,
	PMIC_STRUP_VIO18_PG_STATUS,
	PMIC_STRUP_VSRAM_PROC12_PG_STATUS,
	PMIC_STRUP_VSRAM_PROC11_PG_STATUS,
	PMIC_STRUP_VA12_PG_STATUS,
	PMIC_STRUP_VSRAM_GPU_PG_STATUS,
	PMIC_STRUP_VSRAM_OTHERS_PG_STATUS,
	PMIC_STRUP_VAUX18_PG_STATUS,
	PMIC_STRUP_VXO22_PG_STATUS,
	PMIC_STRUP_VDRAM1_PG_STATUS,
	PMIC_STRUP_VPROC12_PG_STATUS,
	PMIC_STRUP_VPROC11_PG_STATUS,
	PMIC_STRUP_VS1_PG_STATUS,
	PMIC_STRUP_VGPU_PG_STATUS,
	PMIC_STRUP_VMODEM_PG_STATUS,
	PMIC_STRUP_VCORE_PG_STATUS,
	PMIC_STRUP_VS2_PG_STATUS,
	PMIC_STRUP_RSV_PG_STATUS,
	PMIC_STRUP_VAUD28_PG_STATUS,
	PMIC_STRUP_VUSB_PG_STATUS,
	PMIC_STRUP_VDRAM2_PG_STATUS,
	PMIC_STRUP_VIO28_PG_STATUS,
	PMIC_STRUP_VEMC_PG_STATUS,
	PMIC_STRUP_VDRAM1_OC_STATUS,
	PMIC_STRUP_VPROC12_OC_STATUS,
	PMIC_STRUP_VPROC11_OC_STATUS,
	PMIC_STRUP_VS1_OC_STATUS,
	PMIC_STRUP_VGPU_OC_STATUS,
	PMIC_STRUP_VMODEM_OC_STATUS,
	PMIC_STRUP_VCORE_OC_STATUS,
	PMIC_STRUP_VS2_OC_STATUS,
	PMIC_PMU_THERMAL_DEB,
	PMIC_STRUP_THERMAL_STATUS,
	PMIC_RG_SRCLKEN_IN0_EN,
	PMIC_RG_SRCLKEN_IN0_HW_MODE,
	PMIC_RG_SRCLKEN_IN1_EN,
	PMIC_RG_SRCLKEN_IN1_HW_MODE,
	PMIC_RG_SRCLKEN_IN_SYNC_EN,
	PMIC_RG_OSC_EN_AUTO_OFF,
	PMIC_TEST_OUT,
	PMIC_RG_MON_FLAG_SEL,
	PMIC_RG_MON_GRP_SEL,
	PMIC_RG_NANDTREE_MODE,
	PMIC_RG_TEST_AUXADC,
	PMIC_RG_EFUSE_MODE,
	PMIC_RG_TEST_STRUP,
	PMIC_TESTMODE_SW,
	PMIC_PMU_TEST_MODE_SCAN,
	PMIC_PWRKEY_DEB,
	PMIC_CHRDET_DEB,
	PMIC_HOMEKEY_DEB,
	PMIC_RG_PMU_TDSEL,
	PMIC_RG_SPI_TDSEL,
	PMIC_RG_AUD_TDSEL,
	PMIC_RG_E32CAL_TDSEL,
	PMIC_RG_PMU_RDSEL,
	PMIC_RG_SPI_RDSEL,
	PMIC_RG_AUD_RDSEL,
	PMIC_RG_E32CAL_RDSEL,
	PMIC_RG_SMT_WDTRSTB_IN,
	PMIC_RG_SMT_SRCLKEN_IN0,
	PMIC_RG_SMT_SRCLKEN_IN1,
	PMIC_RG_SMT_RTC_32K1V8_0,
	PMIC_RG_SMT_RTC_32K1V8_1,
	PMIC_RG_SMT_HOMEKEY,
	PMIC_RG_SMT_SCP_VREQ_VAO,
	PMIC_RG_SMT_SD_CARD_DET_N,
	PMIC_RG_SMT_SPI_CLK,
	PMIC_RG_SMT_SPI_CSN,
	PMIC_RG_SMT_SPI_MOSI,
	PMIC_RG_SMT_SPI_MISO,
	PMIC_RG_SMT_AUD_CLK_MOSI,
	PMIC_RG_SMT_AUD_DAT_MOSI0,
	PMIC_RG_SMT_AUD_DAT_MOSI1,
	PMIC_RG_SMT_AUD_SYNC_MOSI,
	PMIC_RG_SMT_AUD_CLK_MISO,
	PMIC_RG_SMT_AUD_DAT_MISO0,
	PMIC_RG_SMT_AUD_DAT_MISO1,
	PMIC_RG_SMT_AUD_SYNC_MISO,
	PMIC_RG_TOP_RSV0,
	PMIC_RG_TOP_RSV1,
	PMIC_RG_OCTL_SRCLKEN_IN0,
	PMIC_RG_OCTL_SRCLKEN_IN1,
	PMIC_RG_OCTL_RTC_32K1V8_0,
	PMIC_RG_OCTL_RTC_32K1V8_1,
	PMIC_RG_OCTL_SPI_CLK,
	PMIC_RG_OCTL_SPI_CSN,
	PMIC_RG_OCTL_SPI_MOSI,
	PMIC_RG_OCTL_SPI_MISO,
	PMIC_RG_OCTL_AUD_CLK_MOSI,
	PMIC_RG_OCTL_AUD_DAT_MOSI0,
	PMIC_RG_OCTL_AUD_DAT_MOSI1,
	PMIC_RG_OCTL_AUD_SYNC_MOSI,
	PMIC_RG_OCTL_AUD_CLK_MISO,
	PMIC_RG_OCTL_AUD_DAT_MISO0,
	PMIC_RG_OCTL_AUD_DAT_MISO1,
	PMIC_RG_OCTL_AUD_SYNC_MISO,
	PMIC_RG_OCTL_HOMEKEY,
	PMIC_RG_OCTL_SCP_VREQ_VAO,
	PMIC_RG_OCTL_SD_CARD_DET_N,
	PMIC_RG_SRCLKEN_IN0_FILTER_EN,
	PMIC_RG_SRCLKEN_IN1_FILTER_EN,
	PMIC_RG_RTC32K_1V8_0_FILTER_EN,
	PMIC_RG_RTC32K_1V8_1_FILTER_EN,
	PMIC_RG_SPI_CLK_FILTER_EN,
	PMIC_RG_SPI_CSN_FILTER_EN,
	PMIC_RG_SPI_MOSI_FILTER_EN,
	PMIC_RG_SPI_MISO_FILTER_EN,
	PMIC_RG_AUD_CLK_MOSI_FILTER_EN,
	PMIC_RG_AUD_DAT_MOSI0_FILTER_EN,
	PMIC_RG_AUD_DAT_MOSI1_FILTER_EN,
	PMIC_RG_AUD_SYNC_MOSI_FILTER_EN,
	PMIC_RG_AUD_CLK_MISO_FILTER_EN,
	PMIC_RG_AUD_DAT_MISO0_FILTER_EN,
	PMIC_RG_AUD_DAT_MISO1_FILTER_EN,
	PMIC_RG_AUD_SYNC_MISO_FILTER_EN,
	PMIC_RG_WDTRSTB_IN_FILTER_EN,
	PMIC_RG_HOMEKEY_FILTER_EN,
	PMIC_RG_SCP_VREQ_VAO_FILTER_EN,
	PMIC_RG_SD_CARD_DET_N_FILTER_EN,
	PMIC_RG_SRCLKEN_IN0_RCSEL,
	PMIC_RG_SRCLKEN_IN1_RCSEL,
	PMIC_RG_RTC32K_1V8_0_RCSEL,
	PMIC_RG_RTC32K_1V8_1_RCSEL,
	PMIC_RG_SPI_CLK_RCSEL,
	PMIC_RG_SPI_CSN_RCSEL,
	PMIC_RG_SPI_MOSI_RCSEL,
	PMIC_RG_SPI_MISO_RCSEL,
	PMIC_RG_AUD_CLK_MOSI_RCSEL,
	PMIC_RG_AUD_DAT_MOSI0_RCSEL,
	PMIC_RG_AUD_DAT_MOSI1_RCSEL,
	PMIC_RG_AUD_SYNC_MOSI_RCSEL,
	PMIC_RG_AUD_CLK_MISO_RCSEL,
	PMIC_RG_AUD_DAT_MISO0_RCSEL,
	PMIC_RG_AUD_DAT_MISO1_RCSEL,
	PMIC_RG_AUD_SYNC_MISO_RCSEL,
	PMIC_RG_WDTRSTB_IN_RCSEL,
	PMIC_RG_HOMEKEY_RCSEL,
	PMIC_RG_SCP_VREQ_VAO_RCSEL,
	PMIC_RG_SD_CARD_DET_N_RCSEL,
	PMIC_TOP_STATUS,
	PMIC_TOP_STATUS_SET,
	PMIC_TOP_STATUS_CLR,
	PMIC_VM_MODE,
	PMIC_TOP1_ANA_ID,
	PMIC_TOP1_DIG_ID,
	PMIC_TOP1_ANA_MINOR_REV,
	PMIC_TOP1_ANA_MAJOR_REV,
	PMIC_TOP1_DIG_MINOR_REV,
	PMIC_TOP1_DIG_MAJOR_REV,
	PMIC_TOP1_DSN_CBS,
	PMIC_TOP1_DSN_BIX,
	PMIC_TOP1_DSN_ESP,
	PMIC_TOP1_DSN_FPI,
	PMIC_GPIO_DIR0,
	PMIC_GPIO_DIR0_SET,
	PMIC_GPIO_DIR0_CLR,
	PMIC_GPIO_DIR1,
	PMIC_GPIO_DIR1_SET,
	PMIC_GPIO_DIR1_CLR,
	PMIC_GPIO_PULLEN0,
	PMIC_GPIO_PULLEN0_SET,
	PMIC_GPIO_PULLEN0_CLR,
	PMIC_GPIO_PULLEN1,
	PMIC_GPIO_PULLEN1_SET,
	PMIC_GPIO_PULLEN1_CLR,
	PMIC_GPIO_PULLSEL0,
	PMIC_GPIO_PULLSEL0_SET,
	PMIC_GPIO_PULLSEL0_CLR,
	PMIC_GPIO_PULLSEL1,
	PMIC_GPIO_PULLSEL1_SET,
	PMIC_GPIO_PULLSEL1_CLR,
	PMIC_GPIO_DINV0,
	PMIC_GPIO_DINV0_SET,
	PMIC_GPIO_DINV0_CLR,
	PMIC_GPIO_DINV1,
	PMIC_GPIO_DINV1_SET,
	PMIC_GPIO_DINV1_CLR,
	PMIC_GPIO_DOUT0,
	PMIC_GPIO_DOUT0_SET,
	PMIC_GPIO_DOUT0_CLR,
	PMIC_GPIO_DOUT1,
	PMIC_GPIO_DOUT1_SET,
	PMIC_GPIO_DOUT1_CLR,
	PMIC_GPIO_PI0,
	PMIC_GPIO_PI1,
	PMIC_GPIO_POE0,
	PMIC_GPIO_POE1,
	PMIC_GPIO0_MODE,
	PMIC_GPIO1_MODE,
	PMIC_GPIO2_MODE,
	PMIC_GPIO3_MODE,
	PMIC_GPIO_MODE0_SET,
	PMIC_GPIO_MODE0_CLR,
	PMIC_GPIO4_MODE,
	PMIC_GPIO5_MODE,
	PMIC_GPIO6_MODE,
	PMIC_GPIO7_MODE,
	PMIC_GPIO_MODE1_SET,
	PMIC_GPIO_MODE1_CLR,
	PMIC_GPIO8_MODE,
	PMIC_GPIO9_MODE,
	PMIC_GPIO10_MODE,
	PMIC_GPIO11_MODE,
	PMIC_GPIO_MODE2_SET,
	PMIC_GPIO_MODE2_CLR,
	PMIC_GPIO12_MODE,
	PMIC_GPIO13_MODE,
	PMIC_GPIO14_MODE,
	PMIC_GPIO15_MODE,
	PMIC_GPIO_MODE3_SET,
	PMIC_GPIO_MODE3_CLR,
	PMIC_GPIO16_MODE,
	PMIC_GPIO17_MODE,
	PMIC_GPIO18_MODE,
	PMIC_GPIO_MODE4_SET,
	PMIC_GPIO_MODE4_CLR,
	PMIC_GPIO_RSV,
	PMIC_TOP2_ANA_ID,
	PMIC_TOP2_DIG_ID,
	PMIC_TOP2_ANA_MINOR_REV,
	PMIC_TOP2_ANA_MAJOR_REV,
	PMIC_TOP2_DIG_MINOR_REV,
	PMIC_TOP2_DIG_MAJOR_REV,
	PMIC_TOP2_DSN_CBS,
	PMIC_TOP2_DSN_BIX,
	PMIC_TOP2_DSN_ESP,
	PMIC_TOP2_DSN_FPI,
	PMIC_TOP_CLK_OFFSET,
	PMIC_TOP_RST_OFFSET,
	PMIC_TOP_INT_OFFSET,
	PMIC_TOP_INT_LEN,
	PMIC_RG_G_SMPS_CK_PDN,
	PMIC_RG_G_SMPS_TEST_CK_PDN,
	PMIC_RG_INTRP_CK_PDN,
	PMIC_RG_INTRP_PRE_OC_CK_PDN,
	PMIC_RG_EFUSE_CK_PDN,
	PMIC_RG_EINT_32K_CK_PDN,
	PMIC_RG_PMU1M_CK_PDN,
	PMIC_RG_SPI_CK_PDN,
	PMIC_RG_REG_CK_PDN,
	PMIC_RG_PMU32K_CK_PDN,
	PMIC_RG_FQMTR_32K_CK_PDN,
	PMIC_RG_FQMTR_CK_PDN,
	PMIC_RG_PMU26M_CK_PDN,
	PMIC_RG_PMU128K_CK_PDN,
	PMIC_RG_RTC26M_CK_PDN,
	PMIC_RG_RTC32K_CK_PDN,
	PMIC_TOP_CKPDN_CON0_SET,
	PMIC_TOP_CKPDN_CON0_CLR,
	PMIC_RG_RTC32K_1V8_0_PDN,
	PMIC_RG_RTC32K_1V8_1_PDN,
	PMIC_RG_TRIM_128K_CK_PDN,
	PMIC_RG_BGR_TEST_CK_PDN,
	PMIC_RG_PCHR_TEST_CK_PDN,
	PMIC_TOP_CKPDN_CON1_SET,
	PMIC_TOP_CKPDN_CON1_CLR,
	PMIC_RG_FQMTR_CK_CKSEL,
	PMIC_RG_RTC_32K1V8_SEL,
	PMIC_RG_BGR_TEST_CK_CKSEL,
	PMIC_RG_PCHR_TEST_CK_CKSEL,
	PMIC_RG_26M_CK_SEL_HWEN,
	PMIC_RG_26M_CK_SEL,
	PMIC_RG_PMU_1M_CK_SEL_HWEN,
	PMIC_RG_PMU_1M_CK_SEL,
	PMIC_RG_PMU32K_CK_CKSEL,
	PMIC_RG_TOP_CKSEL_CON0_RSV,
	PMIC_TOP_CKSEL_CON0_SET,
	PMIC_TOP_CKSEL_CON0_CLR,
	PMIC_RG_SRCVOLTEN_SW,
	PMIC_RG_VOWEN_SW,
	PMIC_RG_VOW_LDO_VSRAM_CORE_DVS_DONE,
	PMIC_RG_VOW_BUCK_VCORE_DVS_DONE,
	PMIC_RG_SRCVOLTEN_MODE,
	PMIC_RG_VOWEN_MODE,
	PMIC_RG_VOW_LDO_VSRAM_CORE_DVS_SW_MODE,
	PMIC_RG_VOW_BUCK_VCORE_DVS_SW_MODE,
	PMIC_RG_TOP_CKSEL_CON2_RSV,
	PMIC_TOP_CKSEL_CON1_SET,
	PMIC_TOP_CKSEL_CON1_CLR,
	PMIC_RG_REG_CK_DIVSEL,
	PMIC_TOP_CKDIVSEL_CON0_RSV,
	PMIC_TOP_CKDIVSEL_CON0_SET,
	PMIC_TOP_CKDIVSEL_CON0_CLR,
	PMIC_RG_G_SMPS_CK_PDN_HWEN,
	PMIC_RG_REG_CK_PDN_HWEN,
	PMIC_RG_EFUSE_CK_PDN_HWEN,
	PMIC_RG_EINT_32K_CK_PDN_HWEN,
	PMIC_RG_RTC26M_CK_PDN_HWEN,
	PMIC_RG_PMU26M_CK_PDN_HWEN,
	PMIC_RG_PMU_VXO22_ON,
	PMIC_RG_PMU_VXO22_ON_SW_EN,
	PMIC_TOP_CKHWEN_CON0_RSV,
	PMIC_TOP_CKHWEN_CON0_SET,
	PMIC_TOP_CKHWEN_CON0_CLR,
	PMIC_RG_PMU128K_CK_TST_DIS,
	PMIC_RG_SMPS_CK_TST_DIS,
	PMIC_RG_XO_CLK_26M_PMU_TST_DIS,
	PMIC_RG_XO_CLK_26M_DIG_TST_DIS,
	PMIC_RG_RTC_26M_CK_TST_DIS,
	PMIC_RG_RTC_32K_CK_TST_DIS,
	PMIC_RG_PMU_M_CK_TST_DIS,
	PMIC_TOP_CKTST_CON0_RSV,
	PMIC_RG_PMU128K_CK_TSTSEL,
	PMIC_RG_SMPS_CK_TSTSEL,
	PMIC_RG_XO_CLK_26M_PMU_TSTSEL,
	PMIC_RG_XO_CLK_26M_DIG_TSTSEL,
	PMIC_RG_RTC_26M_CK_TSTSEL,
	PMIC_RG_RTC_32K_CK_TSTSEL,
	PMIC_RG_PMU_M_CK_TSTSEL,
	PMIC_RG_EFUSE_CK_TSTSEL,
	PMIC_RG_BGR_TEST_CK_TSTSEL,
	PMIC_RG_PCHR_TEST_CK_TSTSEL,
	PMIC_RG_FQMTR_CK_TSTSEL,
	PMIC_RG_OSC_SEL_SW_EN,
	PMIC_RG_OSC_SEL,
	PMIC_RG_OSC_EN_SW_EN,
	PMIC_RG_OSC_EN,
	PMIC_RG_SRCVOLTEN_LP_EN,
	PMIC_RG_SRCLKEN0_LP_EN,
	PMIC_RG_SRCLKEN1_LP_EN,
	PMIC_RG_SRCLKEN2_LP_EN,
	PMIC_RG_BUCK_LP_EN,
	PMIC_RG_LDO_LP_EN,
	PMIC_RG_BUCK_PFM_FLAG,
	PMIC_RG_BUCK_PFM_FLAG_SW_EN,
	PMIC_RG_DCXO26M_RDY,
	PMIC_RG_DCXO26M_RDY_SW_EN,
	PMIC_RG_PMU_LP,
	PMIC_RG_PMU_LP_SW_EN,
	PMIC_TOP_CLK_CON0_SET,
	PMIC_TOP_CLK_CON0_CLR,
	PMIC_RG_PMU_MDB_DCM_SW_EN,
	PMIC_RG_PMU_MDB_DCM_SW_MODE,
	PMIC_RO_HANDOVER_DEBUG,
	PMIC_RG_EFUSE_MAN_RST,
	PMIC_RG_DRIVER_RST,
	PMIC_RG_FQMTR_RST,
	PMIC_RG_RTC_RST,
	PMIC_RG_TYPE_C_CC_RST,
	PMIC_RG_CLK_TRIM_RST,
	PMIC_RG_BUCK_SRCLKEN_RST,
	PMIC_TOP_RST_CON0_SET,
	PMIC_TOP_RST_CON0_CLR,
	PMIC_RG_BUCK_PROT_PMPP_RST,
	PMIC_RG_SPK_RST,
	PMIC_RG_FT_VR_SYSRSTB,
	PMIC_RG_LDO_CALI_RST,
	PMIC_TOP_RST_CON1_RSV,
	PMIC_TOP_RST_CON1_SET,
	PMIC_TOP_RST_CON1_CLR,
	PMIC_RG_CHR_LDO_DET_MODE,
	PMIC_RG_CHR_LDO_DET_SW,
	PMIC_RG_CHRWDT_FLAG_MODE,
	PMIC_RG_CHRWDT_FLAG_SW,
	PMIC_TOP_RST_CON2_RSV,
	PMIC_RG_WDTRSTB_EN,
	PMIC_RG_WDTRSTB_MODE,
	PMIC_WDTRSTB_STATUS,
	PMIC_WDTRSTB_STATUS_CLR,
	PMIC_RG_WDTRSTB_FB_EN,
	PMIC_RG_WDTRSTB_DEB,
	PMIC_RG_HOMEKEY_RST_EN,
	PMIC_RG_PWRKEY_RST_EN,
	PMIC_RG_PWRRST_TMR_DIS,
	PMIC_RG_PWRKEY_RST_TD,
	PMIC_TOP_RST_MISC_RSV,
	PMIC_TOP_RST_MISC_SET,
	PMIC_TOP_RST_MISC_CLR,
	PMIC_VPWRIN_RSTB_STATUS,
	PMIC_DDLO_RSTB_STATUS,
	PMIC_UVLO_RSTB_STATUS,
	PMIC_RTC_DDLO_RSTB_STATUS,
	PMIC_CHRWDT_REG_RSTB_STATUS,
	PMIC_CHRDET_REG_RSTB_STATUS,
	PMIC_BWDT_DDLO_RSTB_STATUS,
	PMIC_TOP_RST_STATUS_RSV,
	PMIC_TOP_RST_STATUS_SET,
	PMIC_TOP_RST_STATUS_CLR,
	PMIC_TOP2_ELR_LEN,
	PMIC_RG_TOP2_RSV0,
	PMIC_RG_TOP2_RSV1,
	PMIC_TOP3_ANA_ID,
	PMIC_TOP3_DIG_ID,
	PMIC_TOP3_ANA_MINOR_REV,
	PMIC_TOP3_ANA_MAJOR_REV,
	PMIC_TOP3_DIG_MINOR_REV,
	PMIC_TOP3_DIG_MAJOR_REV,
	PMIC_TOP3_DSN_CBS,
	PMIC_TOP3_DSN_BIX,
	PMIC_TOP3_DSN_ESP,
	PMIC_TOP3_DSN_FPI,
	PMIC_RG_INT_EN_SPI_CMD_ALERT,
	PMIC_MISC_TOP_INT_CON0_SET,
	PMIC_MISC_TOP_INT_CON0_CLR,
	PMIC_RG_INT_MASK_SPI_CMD_ALERT,
	PMIC_MISC_TOP_INT_MASK_CON0_SET,
	PMIC_MISC_TOP_INT_MASK_CON0_CLR,
	PMIC_RG_INT_STATUS_SPI_CMD_ALERT,
	PMIC_RG_INT_RAW_STATUS_SPI_CMD_ALERT,
	PMIC_RG_INT_MASK_BUCK_TOP,
	PMIC_RG_INT_MASK_LDO_TOP,
	PMIC_RG_INT_MASK_PSC_TOP,
	PMIC_RG_INT_MASK_SCK_TOP,
	PMIC_RG_INT_MASK_BM_TOP,
	PMIC_RG_INT_MASK_HK_TOP,
	PMIC_RG_INT_MASK_XPP_TOP,
	PMIC_RG_INT_MASK_AUD_TOP,
	PMIC_RG_INT_MASK_MISC_TOP,
	PMIC_TOP_INT_MASK_CON0_SET,
	PMIC_TOP_INT_MASK_CON0_CLR,
	PMIC_INT_STATUS_BUCK_TOP,
	PMIC_INT_STATUS_LDO_TOP,
	PMIC_INT_STATUS_PSC_TOP,
	PMIC_INT_STATUS_SCK_TOP,
	PMIC_INT_STATUS_BM_TOP,
	PMIC_INT_STATUS_HK_TOP,
	PMIC_INT_STATUS_XPP_TOP,
	PMIC_INT_STATUS_AUD_TOP,
	PMIC_INT_STATUS_MISC_TOP,
	PMIC_INT_STATUS_TOP_RSV,
	PMIC_INT_RAW_STATUS_BUCK_TOP,
	PMIC_INT_RAW_STATUS_LDO_TOP,
	PMIC_INT_RAW_STATUS_PSC_TOP,
	PMIC_INT_RAW_STATUS_SCK_TOP,
	PMIC_INT_RAW_STATUS_BM_TOP,
	PMIC_INT_RAW_STATUS_HK_TOP,
	PMIC_INT_RAW_STATUS_XPP_TOP,
	PMIC_INT_RAW_STATUS_AUD_TOP,
	PMIC_INT_RAW_STATUS_MISC_TOP,
	PMIC_INT_RAW_STATUS_TOP_RSV,
	PMIC_RG_INT_POLARITY,
	PMIC_PLT0_ANA_ID,
	PMIC_PLT0_DIG_ID,
	PMIC_PLT0_ANA_MINOR_REV,
	PMIC_PLT0_ANA_MAJOR_REV,
	PMIC_PLT0_DIG_MINOR_REV,
	PMIC_PLT0_DIG_MAJOR_REV,
	PMIC_PLT0_DSN_CBS,
	PMIC_PLT0_DSN_BIX,
	PMIC_PLT0_DSN_ESP,
	PMIC_PLT0_DSN_FPI,
	PMIC_RG_OSC_128K_TRIM_EN,
	PMIC_RG_OSC_128K_TRIM_RATE,
	PMIC_DA_OSC_128K_TRIM,
	PMIC_RG_OTP_PA,
	PMIC_RG_OTP_PDIN,
	PMIC_RG_OTP_PTM,
	PMIC_RG_OTP_PWE,
	PMIC_RG_OTP_PPROG,
	PMIC_RG_OTP_PWE_SRC,
	PMIC_RG_OTP_PROG_PKEY,
	PMIC_RG_OTP_RD_PKEY,
	PMIC_RG_OTP_RD_TRIG,
	PMIC_RG_RD_RDY_BYPASS,
	PMIC_RG_SKIP_OTP_OUT,
	PMIC_RG_OTP_RD_SW,
	PMIC_RG_OTP_DOUT_SW,
	PMIC_RG_OTP_RD_BUSY,
	PMIC_RG_OTP_RD_ACK,
	PMIC_RG_OTP_PA_SW,
	PMIC_TMA_KEY,
	PMIC_TOP_MDB_RSV0,
	PMIC_RG_MDB_DM1_DS_EN,
	PMIC_TOP_MDB_RSV1,
	PMIC_RG_PMU_MDB_BRIDGE_BYPASS_EN,
	PMIC_PLT0_ELR_LEN,
	PMIC_RG_OSC_128K_TRIM,
	PMIC_EFUSE_OSC_MODE,
	PMIC_SPISLV_ANA_ID,
	PMIC_SPISLV_DIG_ID,
	PMIC_SPISLV_ANA_MINOR_REV,
	PMIC_SPISLV_ANA_MAJOR_REV,
	PMIC_SPISLV_DIG_MINOR_REV,
	PMIC_SPISLV_DIG_MAJOR_REV,
	PMIC_SPISLV_DSN_CBS,
	PMIC_SPISLV_DSN_BIX,
	PMIC_SPISLV_DSN_ESP,
	PMIC_SPISLV_DSN_FPI,
	PMIC_RG_SLP_RW_EN,
	PMIC_RG_EN_RECORD,
	PMIC_RG_SPI_RSV,
	PMIC_DEW_DIO_EN,
	PMIC_DEW_READ_TEST,
	PMIC_DEW_WRITE_TEST,
	PMIC_DEW_CRC_SWRST,
	PMIC_DEW_CRC_EN,
	PMIC_DEW_CRC_VAL,
	PMIC_DEW_DBG_MON_SEL,
	PMIC_DEW_CIPHER_KEY_SEL,
	PMIC_DEW_CIPHER_IV_SEL,
	PMIC_DEW_CIPHER_EN,
	PMIC_DEW_CIPHER_RDY,
	PMIC_DEW_CIPHER_MODE,
	PMIC_DEW_CIPHER_SWRST,
	PMIC_DEW_RDDMY_NO,
	PMIC_INT_TYPE_CON0,
	PMIC_INT_TYPE_CON0_SET,
	PMIC_INT_TYPE_CON0_CLR,
	PMIC_CPU_INT_STA,
	PMIC_MD32_INT_STA,
	PMIC_RG_SRCLKEN_IN3_SMPS_CLK_MODE,
	PMIC_RG_SRCLKEN_IN3_EN_SMPS_TEST,
	PMIC_RG_SRCLKEN_IN2_SMPS_CLK_MODE,
	PMIC_RG_SRCLKEN_IN2_EN_SMPS_TEST,
	PMIC_RG_SPI_DLY_SEL,
	PMIC_RECORD_CMD0,
	PMIC_RECORD_CMD1,
	PMIC_RECORD_CMD2,
	PMIC_RECORD_WDATA0,
	PMIC_RECORD_WDATA1,
	PMIC_RECORD_WDATA2,
	PMIC_RG_ADDR_TARGET,
	PMIC_RG_ADDR_MASK,
	PMIC_RG_WDATA_TARGET,
	PMIC_RG_WDATA_MASK,
	PMIC_RG_SPI_RECORD_CLR,
	PMIC_RG_CMD_ALERT_CLR,
	PMIC_SPISLV_KEY,
	PMIC_RG_SRCLKEN_IN2_EN,
	PMIC_RG_SRCLKEN_IN3_EN,
	PMIC_SCK_TOP_ANA_ID,
	PMIC_SCK_TOP_DIG_ID,
	PMIC_SCK_TOP_ANA_MINOR_REV,
	PMIC_SCK_TOP_ANA_MAJOR_REV,
	PMIC_SCK_TOP_DIG_MINOR_REV,
	PMIC_SCK_TOP_DIG_MAJOR_REV,
	PMIC_SCK_TOP_CBS,
	PMIC_SCK_TOP_BIX,
	PMIC_SCK_TOP_ESP,
	PMIC_SCK_TOP_FPI,
	PMIC_SCK_TOP_CLK_OFFSET,
	PMIC_SCK_TOP_RST_OFFSET,
	PMIC_SCK_TOP_INT_OFFSET,
	PMIC_SCK_TOP_INT_LEN,
	PMIC_SCK_TOP_XTAL_SEL,
	PMIC_SCK_TOP_RESERVED,
	PMIC_XOSC32_ENB_DET,
	PMIC_SCK_TOP_TEST_OUT,
	PMIC_SCK_TOP_MON_FLAG_SEL,
	PMIC_SCK_TOP_MON_GRP_SEL,
	PMIC_FQMTR_TCKSEL,
	PMIC_FQMTR_BUSY,
	PMIC_FQMTR_DCXO26M_EN,
	PMIC_FQMTR_EN,
	PMIC_FQMTR_WINSET,
	PMIC_FQMTR_DATA,
	PMIC_RG_RTC_SEC_MCLK_PDN,
	PMIC_RG_EOSC_CALI_TEST_CK_PDN,
	PMIC_RG_RTC_EOSC32_CK_PDN,
	PMIC_RG_RTC_SEC_32K_CK_PDN,
	PMIC_RG_RTC_MCLK_PDN,
	PMIC_RG_RTC_32K_CK_PDN,
	PMIC_RG_RTC_26M_CK_PDN,
	PMIC_RG_RTC_2SEC_OFF_DET_PDN,
	PMIC_RG_RTC_INTRP_CK_PDN,
	PMIC_SCK_TOP_CKPDN_CON0_SET,
	PMIC_SCK_TOP_CKPDN_CON0_CLR,
	PMIC_RG_RTC_26M_CK_PDN_HWEN,
	PMIC_RG_RTC_MCLK_PDN_HWEN,
	PMIC_RG_RTC_SEC_32K_CK_PDN_HWEN,
	PMIC_RG_RTC_SEC_MCLK_PDN_HWEN,
	PMIC_RG_RTC_INTRP_CK_PDN_HWEN,
	PMIC_RG_RTC_CLK_PDN_HWEN_RSV_1,
	PMIC_RG_RTC_CLK_PDN_HWEN_RSV_0,
	PMIC_SCK_TOP_CKHWEN_CON_SET,
	PMIC_SCK_TOP_CKHWEN_CON_CLR,
	PMIC_RG_RTC_CK_TSTSEL_RSV,
	PMIC_RG_RTCDET_CK_TSTSEL,
	PMIC_RG_EOSC_CALI_TEST_CK_TSTSEL,
	PMIC_RG_RTC_EOSC32_CK_TSTSEL,
	PMIC_RG_RTC_SWRST,
	PMIC_RG_RTC_SEC_SWRST,
	PMIC_RG_BANK_RTC_SWRST,
	PMIC_RG_BANK_RTC_SEC_SWRST,
	PMIC_RG_BANK_EOSC_CALI_SWRST,
	PMIC_RG_BANK_SCK_TOP_SWRST,
	PMIC_SCK_TOP_RST_CON0_SET,
	PMIC_SCK_TOP_RST_CON0_CLR,
	PMIC_RG_INT_EN_RTC,
	PMIC_SCK_TOP_INT_CON0_SET,
	PMIC_SCK_TOP_INT_CON0_CLR,
	PMIC_RG_INT_MASK_RTC,
	PMIC_SCK_TOP_INT_MASK_CON0_SET,
	PMIC_SCK_TOP_INT_MASK_CON0_CLR,
	PMIC_RG_INT_STATUS_RTC,
	PMIC_RG_INT_RAW_STATUS_RTC,
	PMIC_SCK_TOP_POLARITY,
	PMIC_EOSC_CALI_START,
	PMIC_EOSC_CALI_TD,
	PMIC_EOSC_CALI_TEST,
	PMIC_EOSC_CALI_DCXO_RDY_TD,
	PMIC_FRC_VTCXO0_ON,
	PMIC_EOSC_CALI_RSV,
	PMIC_MIX_EOSC32_STP_LPDTB,
	PMIC_MIX_EOSC32_STP_LPDEN,
	PMIC_MIX_XOSC32_STP_PWDB,
	PMIC_MIX_XOSC32_STP_LPDTB,
	PMIC_MIX_XOSC32_STP_LPDEN,
	PMIC_MIX_XOSC32_STP_LPDRST,
	PMIC_MIX_XOSC32_STP_CALI,
	PMIC_STMP_MODE,
	PMIC_MIX_EOSC32_STP_CHOP_EN,
	PMIC_MIX_DCXO_STP_LVSH_EN,
	PMIC_MIX_PMU_STP_DDLO_VRTC,
	PMIC_MIX_PMU_STP_DDLO_VRTC_EN,
	PMIC_MIX_RTC_STP_XOSC32_ENB,
	PMIC_MIX_DCXO_STP_TEST_DEGLITCH_MODE,
	PMIC_MIX_EOSC32_STP_RSV,
	PMIC_MIX_EOSC32_VCT_EN,
	PMIC_MIX_EOSC32_OPT,
	PMIC_MIX_DCXO_STP_LVSH_EN_INT,
	PMIC_MIX_RTC_GPIO_COREDETB,
	PMIC_MIX_RTC_GPIO_F32KOB,
	PMIC_MIX_RTC_GPIO_GPO,
	PMIC_MIX_RTC_GPIO_OE,
	PMIC_MIX_RTC_STP_DEBUG_OUT,
	PMIC_MIX_RTC_STP_DEBUG_SEL,
	PMIC_MIX_RTC_STP_K_EOSC32_EN,
	PMIC_MIX_RTC_STP_EMBCK_SEL,
	PMIC_MIX_STP_BBWAKEUP,
	PMIC_MIX_STP_RTC_DDLO,
	PMIC_MIX_RTC_XOSC32_ENB,
	PMIC_MIX_EFUSE_XOSC32_ENB_OPT,
	PMIC_RTC_ANA_ID,
	PMIC_RTC_DIG_ID,
	PMIC_RTC_ANA_MINOR_REV,
	PMIC_RTC_ANA_MAJOR_REV,
	PMIC_RTC_DIG_MINOR_REV,
	PMIC_RTC_DIG_MAJOR_REV,
	PMIC_RTC_DSN_CBS,
	PMIC_RTC_DSN_BIX,
	PMIC_RTC_DSN_ESP,
	PMIC_RTC_DSN_FPI,
	PMIC_PWREN,
	PMIC_BBPU_CLR,
	PMIC_BBPU_INIT,
	PMIC_AUTO,
	PMIC_CLRPKY,
	PMIC_RELOAD,
	PMIC_CBUSY,
	PMIC_KEY_BBPU,
	PMIC_ALSTA,
	PMIC_TCSTA,
	PMIC_LPSTA,
	PMIC_AL_EN,
	PMIC_TC_EN,
	PMIC_ONESHOT,
	PMIC_LP_EN,
	PMIC_SECCII,
	PMIC_MINCII,
	PMIC_HOUCII,
	PMIC_DOMCII,
	PMIC_DOWCII,
	PMIC_MTHCII,
	PMIC_YEACII,
	PMIC_SECCII_1_2,
	PMIC_SECCII_1_4,
	PMIC_SECCII_1_8,
	PMIC_SEC_MSK,
	PMIC_MIN_MSK,
	PMIC_HOU_MSK,
	PMIC_DOM_MSK,
	PMIC_DOW_MSK,
	PMIC_MTH_MSK,
	PMIC_YEA_MSK,
	PMIC_TC_SECOND,
	PMIC_TC_MINUTE,
	PMIC_TC_HOUR,
	PMIC_TC_DOM,
	PMIC_TC_DOW,
	PMIC_TC_MONTH,
	PMIC_TC_YEAR,
	PMIC_AL_SECOND,
	PMIC_BBPU_AUTO_PDN_SEL,
	PMIC_BBPU_2SEC_CK_SEL,
	PMIC_BBPU_2SEC_EN,
	PMIC_BBPU_2SEC_MODE,
	PMIC_BBPU_2SEC_STAT_CLEAR,
	PMIC_BBPU_2SEC_STAT_STA,
	PMIC_RTC_LPD_OPT,
	PMIC_K_EOSC32_VTCXO_ON_SEL,
	PMIC_AL_MINUTE,
	PMIC_AL_HOUR,
	PMIC_NEW_SPARE0,
	PMIC_AL_DOM,
	PMIC_NEW_SPARE1,
	PMIC_AL_DOW,
	PMIC_NEW_SPARE2,
	PMIC_AL_MONTH,
	PMIC_NEW_SPARE3,
	PMIC_AL_YEAR,
	PMIC_RTC_K_EOSC_RSV,
	PMIC_XOSCCALI,
	PMIC_RTC_XOSC32_ENB,
	PMIC_RTC_EMBCK_SEL_MODE,
	PMIC_RTC_EMBCK_SRC_SEL,
	PMIC_RTC_EMBCK_SEL_OPTION,
	PMIC_RTC_GPS_CKOUT_EN,
	PMIC_RTC_EOSC32_VCT_EN,
	PMIC_RTC_EOSC32_CHOP_EN,
	PMIC_RTC_GP_OSC32_CON,
	PMIC_RTC_REG_XOSC32_ENB,
	PMIC_RTC_POWERKEY1,
	PMIC_RTC_POWERKEY2,
	PMIC_RTC_PDN1,
	PMIC_RTC_PDN2,
	PMIC_RTC_SPAR0,
	PMIC_RTC_SPAR1,
	PMIC_RTC_PROT,
	PMIC_RTC_DIFF,
	PMIC_POWER_DETECTED,
	PMIC_K_EOSC32_RSV,
	PMIC_CALI_RD_SEL,
	PMIC_RTC_CALI,
	PMIC_CALI_WR_SEL,
	PMIC_K_EOSC32_OVERFLOW,
	PMIC_WRTGR,
	PMIC_VBAT_LPSTA_RAW,
	PMIC_EOSC32_LPEN,
	PMIC_XOSC32_LPEN,
	PMIC_LPRST,
	PMIC_CDBO,
	PMIC_F32KOB,
	PMIC_GPO,
	PMIC_GOE,
	PMIC_GSR,
	PMIC_GSMT,
	PMIC_GPEN,
	PMIC_GPU,
	PMIC_GE4,
	PMIC_GE8,
	PMIC_GPI,
	PMIC_LPSTA_RAW,
	PMIC_DAT0_LOCK,
	PMIC_DAT1_LOCK,
	PMIC_DAT2_LOCK,
	PMIC_RTC_INT_CNT,
	PMIC_RTC_SEC_DAT0,
	PMIC_RTC_SEC_DAT1,
	PMIC_RTC_SEC_DAT2,
	PMIC_RTC_SEC_ANA_ID,
	PMIC_RTC_SEC_DIG_ID,
	PMIC_RTC_SEC_ANA_MINOR_REV,
	PMIC_RTC_SEC_ANA_MAJOR_REV,
	PMIC_RTC_SEC_DIG_MINOR_REV,
	PMIC_RTC_SEC_DIG_MAJOR_REV,
	PMIC_RTC_SEC_DSN_CBS,
	PMIC_RTC_SEC_DSN_BIX,
	PMIC_RTC_SEC_DSN_ESP,
	PMIC_RTC_SEC_DSN_FPI,
	PMIC_TC_SECOND_SEC,
	PMIC_TC_MINUTE_SEC,
	PMIC_TC_HOUR_SEC,
	PMIC_TC_DOM_SEC,
	PMIC_TC_DOW_SEC,
	PMIC_TC_MONTH_SEC,
	PMIC_TC_YEAR_SEC,
	PMIC_RTC_SEC_CK_PDN,
	PMIC_RTC_SEC_WRTGR,
	PMIC_DCXO_ANA_ID,
	PMIC_DCXO_DIG_ID,
	PMIC_DCXO_ANA_MINOR_REV,
	PMIC_DCXO_ANA_MAJOR_REV,
	PMIC_DCXO_DIG_MINOR_REV,
	PMIC_DCXO_DIG_MAJOR_REV,
	PMIC_DCXO_DSN_CBS,
	PMIC_DCXO_DSN_BIX,
	PMIC_DCXO_DSN_ESP,
	PMIC_DCXO_DSN_FPI,
	PMIC_XO_EXTBUF1_MODE,
	PMIC_XO_EXTBUF1_EN_M,
	PMIC_XO_EXTBUF2_MODE,
	PMIC_XO_EXTBUF2_EN_M,
	PMIC_XO_EXTBUF3_MODE,
	PMIC_XO_EXTBUF3_EN_M,
	PMIC_XO_EXTBUF4_MODE,
	PMIC_XO_EXTBUF4_EN_M,
	PMIC_XO_BB_LPM_EN,
	PMIC_XO_ENBB_MAN,
	PMIC_XO_ENBB_EN_M,
	PMIC_XO_CLKSEL_MAN,
	PMIC_DCXO_CW00_SET,
	PMIC_DCXO_CW00_CLR,
	PMIC_XO_CLKSEL_EN_M,
	PMIC_XO_EXTBUF1_CKG_MAN,
	PMIC_XO_EXTBUF1_CKG_EN_M,
	PMIC_XO_EXTBUF2_CKG_MAN,
	PMIC_XO_EXTBUF2_CKG_EN_M,
	PMIC_XO_EXTBUF3_CKG_MAN,
	PMIC_XO_EXTBUF3_CKG_EN_M,
	PMIC_XO_EXTBUF4_CKG_MAN,
	PMIC_XO_EXTBUF4_CKG_EN_M,
	PMIC_XO_INTBUF_MAN,
	PMIC_XO_PBUF_EN_M,
	PMIC_XO_IBUF_EN_M,
	PMIC_XO_LPMBUF_MAN,
	PMIC_XO_LPM_PREBUF_EN_M,
	PMIC_XO_LPBUF_EN_M,
	PMIC_XO_BBLPM_CKSEL_M,
	PMIC_XO_EN32K_MAN,
	PMIC_XO_EN32K_M,
	PMIC_XO_XMODE_MAN,
	PMIC_XO_XMODE_M,
	PMIC_XO_STRUP_MODE,
	PMIC_XO_AAC_FPM_TIME,
	PMIC_XO_AAC_MODE_LPM,
	PMIC_XO_AAC_MODE_FPM,
	PMIC_XO_EN26M_OFFSQ_EN,
	PMIC_XO_LDOCAL_EN,
	PMIC_XO_CBANK_SYNC_DYN,
	PMIC_XO_26MLP_MAN_EN,
	PMIC_XO_BUFLDOK_EN,
	PMIC_XO_PMU_CKEN_M,
	PMIC_XO_PMU_CKEN_MAN,
	PMIC_XO_EXTBUF6_CKG_MAN,
	PMIC_XO_EXTBUF6_CKG_EN_M,
	PMIC_XO_EXTBUF7_CKG_MAN,
	PMIC_XO_EXTBUF7_CKG_EN_M,
	PMIC_XO_LPM_ISEL_MAN,
	PMIC_XO_FPM_ISEL_MAN,
	PMIC_XO_CDAC_FPM,
	PMIC_XO_CDAC_LPM,
	PMIC_XO_32KDIV_NFRAC_FPM,
	PMIC_XO_COFST_FPM,
	PMIC_XO_32KDIV_NFRAC_LPM,
	PMIC_XO_COFST_LPM,
	PMIC_XO_CORE_MAN,
	PMIC_XO_CORE_EN_M,
	PMIC_XO_CORE_TURBO_EN_M,
	PMIC_XO_CORE_AAC_EN_M,
	PMIC_XO_STARTUP_EN_M,
	PMIC_XO_CORE_VBFPM_EN_M,
	PMIC_XO_CORE_VBLPM_EN_M,
	PMIC_XO_LPMBIAS_EN_M,
	PMIC_XO_VTCGEN_EN_M,
	PMIC_XO_IAAC_COMP_EN_M,
	PMIC_XO_IFPM_COMP_EN_M,
	PMIC_XO_ILPM_COMP_EN_M,
	PMIC_XO_CORE_BYPCAS_FPM,
	PMIC_XO_CORE_GMX2_FPM,
	PMIC_XO_CORE_IDAC_FPM,
	PMIC_XO_AAC_COMP_MAN,
	PMIC_XO_AAC_EN_M,
	PMIC_XO_AAC_MONEN_M,
	PMIC_XO_COMP_EN_M,
	PMIC_XO_COMP_TSTEN_M,
	PMIC_XO_AAC_HV_FPM,
	PMIC_XO_AAC_IBIAS_FPM,
	PMIC_XO_AAC_VOFST_FPM,
	PMIC_XO_AAC_COMP_HV_FPM,
	PMIC_XO_AAC_VSEL_FPM,
	PMIC_XO_AAC_COMP_POL,
	PMIC_XO_CORE_BYPCAS_LPM,
	PMIC_XO_CORE_GMX2_LPM,
	PMIC_XO_CORE_IDAC_LPM,
	PMIC_XO_AAC_COMP_HV_LPM,
	PMIC_XO_AAC_VSEL_LPM,
	PMIC_XO_AAC_HV_LPM,
	PMIC_XO_AAC_IBIAS_LPM,
	PMIC_XO_AAC_VOFST_LPM,
	PMIC_XO_AAC_FPM_SWEN,
	PMIC_XO_SWRST,
	PMIC_XO_32KDIV_SWRST,
	PMIC_XO_32KDIV_RATIO_MAN,
	PMIC_XO_32KDIV_TEST_EN,
	PMIC_XO_CBANK_SYNC_MAN,
	PMIC_XO_CBANK_SYNC_EN_M,
	PMIC_XO_CTL_SYNC_MAN,
	PMIC_XO_CTL_SYNC_EN_M,
	PMIC_XO_LDO_MAN,
	PMIC_XO_LDOPBUF_EN_M,
	PMIC_XO_LDOPBUF_VSET_M,
	PMIC_XO_LDOVTST_EN_M,
	PMIC_XO_TEST_VCAL_EN_M,
	PMIC_XO_VBIST_EN_M,
	PMIC_XO_VTEST_SEL_MUX,
	PMIC_XO_RESERVED3,
	PMIC_XO_EXTBUF6_MODE,
	PMIC_XO_EXTBUF6_EN_M,
	PMIC_XO_EXTBUF7_MODE,
	PMIC_XO_EXTBUF7_EN_M,
	PMIC_XO_BUFLDOK_MAN,
	PMIC_XO_BUF1LDO_CAL_M,
	PMIC_DCXO_CW11_SET,
	PMIC_DCXO_CW11_CLR,
	PMIC_XO_BUFLDO_CAL_M,
	PMIC_XO_EXTBUF4_CLKSEL_MAN,
	PMIC_XO_VIO18PG_BUFEN,
	PMIC_XO_CAL_EN_MAN,
	PMIC_XO_CAL_EN_M,
	PMIC_RG_XO_CORE_OSCTD,
	PMIC_XO_THADC_EN,
	PMIC_RG_XO_SYNC_CKPOL,
	PMIC_RG_XO_CBANK_POL,
	PMIC_RG_XO_CBANK_SYNC_BYP,
	PMIC_RG_XO_CTL_POL,
	PMIC_RG_XO_CTL_SYNC_BYP,
	PMIC_RG_XO_LPBUF_INV,
	PMIC_RG_XO_LDOPBUF_BYP,
	PMIC_RG_XO_LDOPBUF_ENCL,
	PMIC_RG_XO_VGBIAS_VSET,
	PMIC_RG_XO_PBUF_ISET,
	PMIC_RG_XO_IBUF_ISET,
	PMIC_RG_XO_RESERVED4,
	PMIC_RG_XO_VOW_EN,
	PMIC_RG_XO_VOW_DIV,
	PMIC_RG_XO_BUFLDO24_ENCL,
	PMIC_RG_XO_BUFLDO24_IBX2,
	PMIC_RG_XO_RESERVED5,
	PMIC_RG_XO_BUFLDO13_ENCL,
	PMIC_RG_XO_BUFLDO13_IBX2,
	PMIC_RG_XO_BUFLDO13_IX2,
	PMIC_RG_XO_LVLDO_I_CTRL,
	PMIC_RG_XO_BUFLDO67_ENCL,
	PMIC_RG_XO_BUFLDO67_IBX2,
	PMIC_RG_XO_BUFLDO67_IX2,
	PMIC_RG_XO_LVLDO_RFB,
	PMIC_RG_XO_EXTBUF_INV,
	PMIC_RG_XO_RESERVED0,
	PMIC_XO_EXTBUF2_CLKSEL_MAN,
	PMIC_XO_AUDIO_EN_M,
	PMIC_RG_XO_AUDIO_ATTEN,
	PMIC_RG_XO_AUDIO_ISET,
	PMIC_RG_XO_EXTBUF1_HD,
	PMIC_RG_XO_EXTBUF2_HD,
	PMIC_RG_XO_EXTBUF3_HD,
	PMIC_RG_XO_EXTBUF4_HD,
	PMIC_RG_XO_RESERVED8,
	PMIC_RG_XO_EXTBUF6_HD,
	PMIC_RG_XO_EXTBUF7_HD,
	PMIC_XO_EXTBUF1_ISET_M,
	PMIC_XO_EXTBUF2_ISET_M,
	PMIC_XO_EXTBUF3_ISET_M,
	PMIC_XO_EXTBUF4_ISET_M,
	PMIC_XO_RESERVED9,
	PMIC_XO_EXTBUF6_ISET_M,
	PMIC_XO_EXTBUF7_ISET_M,
	PMIC_RG_XO_LPM_PREBUF_ISET,
	PMIC_RG_XO_RESERVED1,
	PMIC_XO_THADC_EN_MAN,
	PMIC_RG_XO_TSOURCE_EN,
	PMIC_XO_BUFLDO13_VSET_M,
	PMIC_XO_BUFLDO24_VSET_M,
	PMIC_XO_BUFLDO67_VSET_M,
	PMIC_XO_STATIC_AUXOUT_SEL,
	PMIC_XO_AUXOUT_SEL,
	PMIC_XO_STATIC_AUXOUT,
	PMIC_RG_XO_PCTAT_COMP_EN,
	PMIC_RG_XO_HEATER_SEL,
	PMIC_RG_XO_CORNER_DETECT_EN,
	PMIC_RG_XO_CORNER_DETECT_EN_MAN,
	PMIC_RG_XO_RESRVED10,
	PMIC_RG_XO_CORNER_SETTING_TUNE,
	PMIC_RG_XO_RESRVED11,
	PMIC_RGS_AD_XO_CORNER_CAL_DONE,
	PMIC_RGS_AD_XO_CORNER_SEL,
	PMIC_XO_MDB_TBO_EN_SEL,
	PMIC_XO_PTATCTAT_EN_MAN,
	PMIC_XO_PTATCTAT_EN_M,
	PMIC_XO_PTATCTAT_EN_LPM,
	PMIC_XO_PTATCTAT_EN_FPM,
	PMIC_XO_BB_LPM_CEL,
	PMIC_XO_BUF1_BBLPM_EN_MASK,
	PMIC_XO_BUF2_BBLPM_EN_MASK,
	PMIC_XO_BUF3_BBLPM_EN_MASK,
	PMIC_XO_BUF4_BBLPM_EN_MASK,
	PMIC_XO_BUF6_BBLPM_EN_MASK,
	PMIC_XO_BUF7_BBLPM_EN_MASK,
	PMIC_XO_PMU_CKEN_MODE,
	PMIC_XO_RESERVED2,
	PMIC_RG_XO_RESRVED12,
	PMIC_DCXO_ELR_LEN,
	PMIC_RG_XO_PCTAT_RDEG_SEL,
	PMIC_RG_XO_GS_VTEMP,
	PMIC_XO_PWRKEY_RSTB_SEL,
	PMIC_PSC_TOP_ANA_ID,
	PMIC_PSC_TOP_DIG_ID,
	PMIC_PSC_TOP_ANA_MINOR_REV,
	PMIC_PSC_TOP_ANA_MAJOR_REV,
	PMIC_PSC_TOP_DIG_MINOR_REV,
	PMIC_PSC_TOP_DIG_MAJOR_REV,
	PMIC_PSC_TOP_CBS,
	PMIC_PSC_TOP_BIX,
	PMIC_PSC_TOP_ESP,
	PMIC_PSC_TOP_FPI,
	PMIC_PSC_TOP_CLK_OFFSET,
	PMIC_PSC_TOP_RST_OFFSET,
	PMIC_PSC_TOP_INT_OFFSET,
	PMIC_PSC_TOP_INT_LEN,
	PMIC_RG_PSC_INTRP_CK_PDN_HWEN,
	PMIC_RG_PSC_INTRP_CK_PDN,
	PMIC_RG_CHRDET_32K_CK_PDN,
	PMIC_RG_STRUP_LONG_PRESS_RST,
	PMIC_RG_PSEQ_PWRMSK_RST_SEL,
	PMIC_BANK_STRUP_SWRST,
	PMIC_BANK_PSEQ_SWRST,
	PMIC_BANK_CHRDET_SWRST,
	PMIC_RG_CHRDET_RST,
	PMIC_RG_INT_EN_PWRKEY,
	PMIC_RG_INT_EN_HOMEKEY,
	PMIC_RG_INT_EN_PWRKEY_R,
	PMIC_RG_INT_EN_HOMEKEY_R,
	PMIC_RG_INT_EN_NI_LBAT_INT,
	PMIC_RG_INT_EN_CHRDET,
	PMIC_RG_INT_EN_CHRDET_EDGE,
	PMIC_RG_INT_EN_VCDT_HV_DET,
	PMIC_PSC_INT_CON0_SET,
	PMIC_PSC_INT_CON0_CLR,
	PMIC_RG_INT_MASK_PWRKEY,
	PMIC_RG_INT_MASK_HOMEKEY,
	PMIC_RG_INT_MASK_PWRKEY_R,
	PMIC_RG_INT_MASK_HOMEKEY_R,
	PMIC_RG_INT_MASK_NI_LBAT_INT,
	PMIC_RG_INT_MASK_CHRDET,
	PMIC_RG_INT_MASK_CHRDET_EDGE,
	PMIC_RG_INT_MASK_VCDT_HV_DET,
	PMIC_PSC_INT_MASK_CON0_SET,
	PMIC_PSC_INT_MASK_CON0_CLR,
	PMIC_RG_INT_STATUS_PWRKEY,
	PMIC_RG_INT_STATUS_HOMEKEY,
	PMIC_RG_INT_STATUS_PWRKEY_R,
	PMIC_RG_INT_STATUS_HOMEKEY_R,
	PMIC_RG_INT_STATUS_NI_LBAT_INT,
	PMIC_RG_INT_STATUS_CHRDET,
	PMIC_RG_INT_STATUS_CHRDET_EDGE,
	PMIC_RG_INT_STATUS_VCDT_HV_DET,
	PMIC_RG_INT_RAW_STATUS_PWRKEY,
	PMIC_RG_INT_RAW_STATUS_HOMEKEY,
	PMIC_RG_INT_RAW_STATUS_PWRKEY_R,
	PMIC_RG_INT_RAW_STATUS_HOMEKEY_R,
	PMIC_RG_INT_RAW_STATUS_NI_LBAT_INT,
	PMIC_RG_INT_RAW_STATUS_CHRDET,
	PMIC_RG_INT_RAW_STATUS_CHRDET_EDGE,
	PMIC_RG_INT_RAW_STATUS_VCDT_HV_DET,
	PMIC_RG_PSC_INT_POLARITY,
	PMIC_RG_HOMEKEY_INT_SEL,
	PMIC_RG_PWRKEY_INT_SEL,
	PMIC_INT_MISC_CON_SET,
	PMIC_INT_MISC_CON_CLR,
	PMIC_RG_PSC_MON_GRP_SEL,
	PMIC_STRUP_ANA_ID,
	PMIC_STRUP_DIG_ID,
	PMIC_STRUP_ANA_MINOR_REV,
	PMIC_STRUP_ANA_MAJOR_REV,
	PMIC_STRUP_DIG_MINOR_REV,
	PMIC_STRUP_DIG_MAJOR_REV,
	PMIC_STRUP_CBS,
	PMIC_STRUP_BIX,
	PMIC_STRUP_DSN_ESP,
	PMIC_STRUP_DSN_FPI,
	PMIC_RG_TM_OUT,
	PMIC_RG_THRDET_SEL,
	PMIC_RG_STRUP_THR_SEL,
	PMIC_RG_THR_TMODE,
	PMIC_RG_VREF_BG,
	PMIC_RG_RST_DRVSEL,
	PMIC_RG_EN1_DRVSEL,
	PMIC_RG_EN2_DRVSEL,
	PMIC_RG_PMU_RSV,
	PMIC_RGS_ANA_CHIP_ID,
	PMIC_STRUP_ELR_LEN,
	PMIC_RG_STRUP_IREF_TRIM,
	PMIC_RG_THR_LOC_SEL,
	PMIC_PSEQ_ANA_ID,
	PMIC_PSEQ_DIG_ID,
	PMIC_PSEQ_ANA_MINOR_REV,
	PMIC_PSEQ_ANA_MAJOR_REV,
	PMIC_PSEQ_DIG_MINOR_REV,
	PMIC_PSEQ_DIG_MAJOR_REV,
	PMIC_PSEQ_CBS,
	PMIC_PSEQ_BIX,
	PMIC_PSEQ_ESP,
	PMIC_PSEQ_FPI,
	PMIC_RG_PWRHOLD,
	PMIC_RG_USBDL_MODE,
	PMIC_RG_CRST,
	PMIC_RG_WRST,
	PMIC_RG_CRST_INTV,
	PMIC_RG_WRST_INTV,
	PMIC_RG_PSEQ_PG_CK_SEL,
	PMIC_RG_PSEQ_SPAR_XCPT_MASK,
	PMIC_RG_PSEQ_RTCA_XCPT_MASK,
	PMIC_RG_THM_SHDN_EN,
	PMIC_RG_WDTRST_EN,
	PMIC_RG_WDTRST_ACT,
	PMIC_RG_KEYPWR_VCORE_OPT,
	PMIC_RG_PSEQ_FORCE_ON,
	PMIC_RG_PSEQ_FORCE_ALL_DOFF,
	PMIC_RG_POR_FLAG,
	PMIC_USBDL,
	PMIC_RG_THR_TEST,
	PMIC_RG_STRUP_THER_DEB_RTD,
	PMIC_RG_STRUP_THER_DEB_FTD,
	PMIC_DDUVLO_DEB_EN,
	PMIC_RG_STRUP_PG_DEB_MODE,
	PMIC_RG_STRUP_OSC_EN,
	PMIC_RG_STRUP_OSC_EN_SEL,
	PMIC_RG_STRUP_FT_CTRL,
	PMIC_RG_STRUP_PWRON_FORCE,
	PMIC_RG_BIASGEN_FORCE,
	PMIC_RG_STRUP_PWRON,
	PMIC_RG_STRUP_PWRON_SEL,
	PMIC_RG_BIASGEN,
	PMIC_RG_BIASGEN_SEL,
	PMIC_RG_RTC_XOSC32_ENB,
	PMIC_RG_RTC_XOSC32_ENB_SEL,
	PMIC_STRUP_DIG_IO_PG_FORCE,
	PMIC_RG_CLR_JUST_SMART_RST,
	PMIC_CLR_JUST_RST,
	PMIC_JUST_SMART_RST,
	PMIC_JUST_PWRKEY_RST,
	PMIC_DA_QI_OSC_EN,
	PMIC_RG_STRUP_EXT_PMIC_EN,
	PMIC_RG_STRUP_EXT_PMIC_SEL,
	PMIC_DA_EXT_PMIC_EN1,
	PMIC_DA_EXT_PMIC_EN2,
	PMIC_RG_STRUP_AUXADC_START_SW,
	PMIC_RG_STRUP_AUXADC_RSTB_SW,
	PMIC_RG_STRUP_AUXADC_START_SEL,
	PMIC_RG_STRUP_AUXADC_RSTB_SEL,
	PMIC_RG_STRUP_AUXADC_RPCNT_MAX,
	PMIC_STRUP_PWROFF_SEQ_EN,
	PMIC_STRUP_PWROFF_PREOFF_EN,
	PMIC_RG_SLOT_INTV_DOWN,
	PMIC_RG_DSEQ_LEN,
	PMIC_RG_VXO22_DSA,
	PMIC_RG_VAUX18_DSA,
	PMIC_RG_VS2_DSA,
	PMIC_RG_VCORE_DSA,
	PMIC_RG_VMODEM_DSA,
	PMIC_RG_VGPU_DSA,
	PMIC_RG_VSRAM_OTHERS_DSA,
	PMIC_RG_VSRAM_GPU_DSA,
	PMIC_RG_EXT_PMIC_2_DSA,
	PMIC_RG_VS1_DSA,
	PMIC_RG_VA12_DSA,
	PMIC_RG_VPROC11_DSA,
	PMIC_RG_VPROC12_DSA,
	PMIC_RG_VSRAM_PROC11_DSA,
	PMIC_RG_VSRAM_PROC12_DSA,
	PMIC_RG_VIO18_DSA,
	PMIC_RG_VEMC_DSA,
	PMIC_RG_EXT_PMIC_1_DSA,
	PMIC_RG_VIO28_DSA,
	PMIC_RG_VDRAM1_DSA,
	PMIC_RG_VDRAM2_DSA,
	PMIC_RG_VUSB_DSA,
	PMIC_RG_VAUD28_DSA,
	PMIC_RG_RSV_DSA,
	PMIC_RG_RSV_SWREG,
	PMIC_RG_STRUP_UVLO_U1U2_SEL,
	PMIC_RG_STRUP_UVLO_U1U2_SEL_SWCTRL,
	PMIC_RG_UVLO_DEC_EN,
	PMIC_RG_STRUP_THR_CLR,
	PMIC_RG_STRUP_LONG_PRESS_EXT_SEL,
	PMIC_RG_STRUP_LONG_PRESS_EXT_TD,
	PMIC_RG_STRUP_LONG_PRESS_EXT_EN,
	PMIC_RG_STRUP_LONG_PRESS_EXT_CHR_CTRL,
	PMIC_RG_STRUP_LONG_PRESS_EXT_PWRKEY_CTRL,
	PMIC_RG_STRUP_LONG_PRESS_EXT_SPAR_CTRL,
	PMIC_RG_STRUP_LONG_PRESS_EXT_RTCA_CTRL,
	PMIC_RG_SMART_RST_SDN_EN,
	PMIC_RG_SMART_RST_MODE,
	PMIC_RG_STRUP_ENVTEM,
	PMIC_RG_STRUP_ENVTEM_CTRL,
	PMIC_RG_STRUP_PWRKEY_COUNT_RESET,
	PMIC_PUP_PKEY_RELEASE,
	PMIC_PWRKEY_LONG_PRESS_COUNT,
	PMIC_RG_RTC_SPAR_DEB_EN,
	PMIC_RG_RTC_ALARM_DEB_EN,
	PMIC_RG_STRUP_VDRAM2_PG_H2L_EN,
	PMIC_RG_STRUP_VEMC_PG_H2L_EN,
	PMIC_RG_STRUP_VSRAM_PROC12_PG_H2L_EN,
	PMIC_RG_STRUP_VSRAM_PROC11_PG_H2L_EN,
	PMIC_RG_STRUP_VA12_PG_H2L_EN,
	PMIC_RG_STRUP_VSRAM_GPU_PG_H2L_EN,
	PMIC_RG_STRUP_VSRAM_OTHERS_PG_H2L_EN,
	PMIC_RG_STRUP_VAUX18_PG_H2L_EN,
	PMIC_RG_STRUP_VDRAM1_PG_H2L_EN,
	PMIC_RG_STRUP_VPROC12_PG_H2L_EN,
	PMIC_RG_STRUP_VPROC11_PG_H2L_EN,
	PMIC_RG_STRUP_VS1_PG_H2L_EN,
	PMIC_RG_STRUP_VGPU_PG_H2L_EN,
	PMIC_RG_STRUP_VMODEM_PG_H2L_EN,
	PMIC_RG_STRUP_VCORE_PG_H2L_EN,
	PMIC_RG_STRUP_VS2_PG_H2L_EN,
	PMIC_RG_STRUP_RSV_PG_H2L_EN,
	PMIC_RG_STRUP_VAUD28_PG_H2L_EN,
	PMIC_RG_STRUP_VUSB_PG_H2L_EN,
	PMIC_RG_STRUP_VIO18_PG_ENB,
	PMIC_RG_STRUP_VSRAM_PROC12_PG_ENB,
	PMIC_RG_STRUP_VSRAM_PROC11_PG_ENB,
	PMIC_RG_STRUP_VA12_PG_ENB,
	PMIC_RG_STRUP_VSRAM_GPU_PG_ENB,
	PMIC_RG_STRUP_VSRAM_OTHERS_PG_ENB,
	PMIC_RG_STRUP_VAUX18_PG_ENB,
	PMIC_RG_STRUP_VXO22_PG_ENB,
	PMIC_RG_STRUP_VDRAM1_PG_ENB,
	PMIC_RG_STRUP_VPROC12_PG_ENB,
	PMIC_RG_STRUP_VPROC11_PG_ENB,
	PMIC_RG_STRUP_VS1_PG_ENB,
	PMIC_RG_STRUP_VGPU_PG_ENB,
	PMIC_RG_STRUP_VMODEM_PG_ENB,
	PMIC_RG_STRUP_VCORE_PG_ENB,
	PMIC_RG_STRUP_VS2_PG_ENB,
	PMIC_RG_STRUP_RSV_PG_ENB,
	PMIC_RG_STRUP_VAUD28_PG_ENB,
	PMIC_RG_STRUP_VUSB_PG_ENB,
	PMIC_RG_STRUP_VDRAM2_PG_ENB,
	PMIC_RG_STRUP_VIO28_PG_ENB,
	PMIC_RG_STRUP_VEMC_PG_ENB,
	PMIC_RG_STRUP_VDRAM1_OC_ENB,
	PMIC_RG_STRUP_VPROC12_OC_ENB,
	PMIC_RG_STRUP_VPROC11_OC_ENB,
	PMIC_RG_STRUP_VS1_OC_ENB,
	PMIC_RG_STRUP_VGPU_OC_ENB,
	PMIC_RG_STRUP_VMODEM_OC_ENB,
	PMIC_RG_STRUP_VCORE_OC_ENB,
	PMIC_RG_STRUP_VS2_OC_ENB,
	PMIC_PSEQ_ELR_LEN,
	PMIC_RG_VXO22_USA,
	PMIC_RG_VAUX18_USA,
	PMIC_RG_VS2_USA,
	PMIC_RG_VCORE_USA,
	PMIC_RG_VMODEM_USA,
	PMIC_RG_VGPU_USA,
	PMIC_RG_VSRAM_OTHERS_USA,
	PMIC_RG_VSRAM_GPU_USA,
	PMIC_RG_EXT_PMIC_2_USA,
	PMIC_RG_VS1_USA,
	PMIC_RG_VA12_USA,
	PMIC_RG_VPROC11_USA,
	PMIC_RG_VPROC12_USA,
	PMIC_RG_VSRAM_PROC11_USA,
	PMIC_RG_VSRAM_PROC12_USA,
	PMIC_RG_VIO18_USA,
	PMIC_RG_VEMC_USA,
	PMIC_RG_EXT_PMIC_1_USA,
	PMIC_RG_VIO28_USA,
	PMIC_RG_VDRAM1_USA,
	PMIC_RG_VDRAM2_USA,
	PMIC_RG_VUSB_USA,
	PMIC_RG_VAUD28_USA,
	PMIC_RG_RSV_USA,
	PMIC_RG_BWDT_EN,
	PMIC_RG_BWDT_TSEL,
	PMIC_RG_BWDT_CSEL,
	PMIC_RG_BWDT_TD,
	PMIC_RG_BWDT_CHRTD,
	PMIC_RG_BWDT_DDLO_TD,
	PMIC_RG_BWDT_SRCSEL,
	PMIC_RG_SLOT_INTV_UP,
	PMIC_RG_SEQ_LEN,
	PMIC_RG_PSPG_SHDN_EN,
	PMIC_RG_RSTB_ONINTV,
	PMIC_RG_PSEQ_F75K_FORCE,
	PMIC_RG_PSEQ_1MS_TK_EXT,
	PMIC_RG_SMPS_IVGEN_SEL,
	PMIC_RG_STRUP_LONG_PRESS_RESET_EXTEND,
	PMIC_RG_CPS_S0EXT_ENB,
	PMIC_RG_CPS_S0EXT_TD,
	PMIC_RG_SDN_DLY_ENB,
	PMIC_RG_CHRDET_DEB_TD,
	PMIC_EFUSE_IVGEN_ENB_SEL,
	PMIC_RG_PWRKEY_EVENT_MODE,
	PMIC_RG_PWRKEY_EVENT_MODE_HW,
	PMIC_RG_LDO_PG_STB_MODE,
	PMIC_CHRDET_ANA_ID,
	PMIC_CHRDET_DIG_ID,
	PMIC_CHRDET_ANA_MINOR_REV,
	PMIC_CHRDET_ANA_MAJOR_REV,
	PMIC_CHRDET_DIG_MINOR_REV,
	PMIC_CHRDET_DIG_MAJOR_REV,
	PMIC_CHRDET_CBS,
	PMIC_CHRDET_BIX,
	PMIC_CHRDET_ESP,
	PMIC_CHRDET_FPI,
	PMIC_RG_VCDT_RST_SEL,
	PMIC_RG_VCDT_HV_EN,
	PMIC_RG_VCDT_DEB_SEL,
	PMIC_RG_PCHR_FT_CTRL,
	PMIC_RGS_CHRDET,
	PMIC_RGS_VCDT_LV_DET,
	PMIC_RGS_VCDT_HV_DET,
	PMIC_RG_VCDT_LV_VTH,
	PMIC_RG_VCDT_HV_VTH,
	PMIC_RGS_PCHR_FLAG_OUT,
	PMIC_RG_PCHR_FLAG_EN,
	PMIC_RG_PCHR_FLAG_SEL,
	PMIC_RG_ENVTEM_D,
	PMIC_RG_ENVTEM_EN,
	PMIC_DA_QI_BGR_EXT_BUF_EN,
	PMIC_RG_BGR_TEST_RSTB,
	PMIC_RG_BGR_TEST_EN,
	PMIC_RG_BGR_UNCHOP,
	PMIC_RG_BGR_UNCHOP_PH,
	PMIC_RG_OTG_BVALID_EN,
	PMIC_RG_UVLO_VTHL,
	PMIC_RG_LBAT_INT_VTH,
	PMIC_RG_PCHR_RV,
	PMIC_RGS_OTG_BVALID_DET,
	PMIC_RGS_CHR_LDO_DET,
	PMIC_RG_VCDT_UVLO_VTH,
	PMIC_CHRDET_ELR_LEN,
	PMIC_RG_VCDT_TRIM,
	PMIC_RG_BGR_TRIM,
	PMIC_RG_BGR_RSEL,
	PMIC_RG_BGR_TRIM_EN,
	PMIC_BM_TOP_ANA_ID,
	PMIC_BM_TOP_DIG_ID,
	PMIC_BM_TOP_ANA_MINOR_REV,
	PMIC_BM_TOP_ANA_MAJOR_REV,
	PMIC_BM_TOP_DIG_MINOR_REV,
	PMIC_BM_TOP_DIG_MAJOR_REV,
	PMIC_BM_TOP_CBS,
	PMIC_BM_TOP_BIX,
	PMIC_BM_TOP_ESP,
	PMIC_BM_TOP_FPI,
	PMIC_BM_TOP_CLK_OFFSET,
	PMIC_BM_TOP_RST_OFFSET,
	PMIC_BM_TOP_INT_OFFSET,
	PMIC_BM_TOP_INT_LEN,
	PMIC_RG_BATON_32K_CK_PDN,
	PMIC_RG_BATON_1K_CK_PDN,
	PMIC_RG_FGADC_FT_CK_PDN,
	PMIC_RG_FGADC_DIG_CK_PDN,
	PMIC_RG_FGADC_ANA_CK_PDN,
	PMIC_RG_G_BIF_1M_CK_PDN,
	PMIC_RG_BIF_X1_CK_PDN,
	PMIC_RG_BIF_X4_CK_PDN,
	PMIC_RG_BIF_X104_CK_PDN,
	PMIC_RG_BM_INTRP_CK_PDN,
	PMIC_RG_BM_TOP_CKPDN_CON0_RSV,
	PMIC_BM_TOP_CKPDN_CON0_SET,
	PMIC_BM_TOP_CKPDN_CON0_CLR,
	PMIC_RG_FGADC_ANA_CK_CKSEL,
	PMIC_BM_TOP_CKSEL_CON0_SET,
	PMIC_BM_TOP_CKSEL_CON0_CLR,
	PMIC_RG_BIF_X4_CK_DIVSEL,
	PMIC_BM_TOP_CKDIVSEL_CON0_RSV,
	PMIC_BM_TOP_CKDIVSEL_CON0_SET,
	PMIC_BM_TOP_CKDIVSEL_CON0_CLR,
	PMIC_RG_BIF_X4_CK_PDN_HWEN,
	PMIC_RG_BIF_X104_CK_PDN_HWEN,
	PMIC_RG_BM_INTRP_CK_PDN_HWEN,
	PMIC_BM_TOP_CKHWEN_CON0_RSV,
	PMIC_BM_TOP_CKHWEN_CON0_SET,
	PMIC_BM_TOP_CKHWEN_CON0_CLR,
	PMIC_RG_FG_CK_TSTSEL,
	PMIC_RG_FGADC_ANA_CK_TSTSEL,
	PMIC_RG_FG_CK_TST_DIS,
	PMIC_RG_FGADC_SWRST,
	PMIC_RG_BATON_SWRST,
	PMIC_RG_BIF_SWRST,
	PMIC_RG_BANK_FGADC_ANA_SWRST,
	PMIC_RG_BANK_FGADC0_SWRST,
	PMIC_RG_BANK_FGADC1_SWRST,
	PMIC_RG_BANK_BATON_ANA_SWRST,
	PMIC_RG_BANK_BATON_SWRST,
	PMIC_RG_BANK_BIF_SWRST,
	PMIC_BM_TOP_RST_CON0_SET,
	PMIC_BM_TOP_RST_CON0_CLR,
	PMIC_RG_FGADC_RST_SRC_SEL,
	PMIC_BM_TOP_RST_CON1_RSV,
	PMIC_BM_TOP_RST_CON1_SET,
	PMIC_BM_TOP_RST_CON1_CLR,
	PMIC_RG_INT_EN_FG_BAT0_H,
	PMIC_RG_INT_EN_FG_BAT0_L,
	PMIC_RG_INT_EN_FG_CUR_H,
	PMIC_RG_INT_EN_FG_CUR_L,
	PMIC_RG_INT_EN_FG_ZCV,
	PMIC_RG_INT_EN_FG_BAT1_H,
	PMIC_RG_INT_EN_FG_BAT1_L,
	PMIC_RG_INT_EN_FG_N_CHARGE_L,
	PMIC_RG_INT_EN_FG_IAVG_H,
	PMIC_RG_INT_EN_FG_IAVG_L,
	PMIC_RG_INT_EN_FG_TIME_H,
	PMIC_RG_INT_EN_FG_DISCHARGE,
	PMIC_RG_INT_EN_FG_CHARGE,
	PMIC_RG_BM_INT_EN_CON0_RSV,
	PMIC_BM_TOP_INT_CON0_SET,
	PMIC_BM_TOP_INT_CON0_CLR,
	PMIC_RG_INT_EN_BATON_LV,
	PMIC_RG_INT_EN_BATON_HT,
	PMIC_RG_INT_EN_BATON_BAT_IN,
	PMIC_RG_INT_EN_BATON_BAT_OUT,
	PMIC_RG_INT_EN_BIF,
	PMIC_BM_TOP_INT_CON1_SET,
	PMIC_BM_TOP_INT_CON1_CLR,
	PMIC_RG_INT_MASK_FG_BAT0_H,
	PMIC_RG_INT_MASK_FG_BAT0_L,
	PMIC_RG_INT_MASK_FG_CUR_H,
	PMIC_RG_INT_MASK_FG_CUR_L,
	PMIC_RG_INT_MASK_FG_ZCV,
	PMIC_RG_INT_MASK_FG_BAT1_H,
	PMIC_RG_INT_MASK_FG_BAT1_L,
	PMIC_RG_INT_MASK_FG_N_CHARGE_L,
	PMIC_RG_INT_MASK_FG_IAVG_H,
	PMIC_RG_INT_MASK_FG_IAVG_L,
	PMIC_RG_INT_MASK_FG_TIME_H,
	PMIC_RG_INT_MASK_FG_DISCHARGE,
	PMIC_RG_INT_MASK_FG_CHARGE,
	PMIC_RG_BM_INT_MASK_CON0_RSV,
	PMIC_BM_TOP_INT_MASK_CON0_SET,
	PMIC_BM_TOP_INT_MASK_CON0_CLR,
	PMIC_RG_INT_MASK_BATON_LV,
	PMIC_RG_INT_MASK_BATON_HT,
	PMIC_RG_INT_MASK_BATON_BAT_IN,
	PMIC_RG_INT_MASK_BATON_BAT_OUT,
	PMIC_RG_INT_MASK_BIF,
	PMIC_BM_TOP_INT_MASK_CON1_SET,
	PMIC_BM_TOP_INT_MASK_CON1_CLR,
	PMIC_RG_INT_STATUS_FG_BAT0_H,
	PMIC_RG_INT_STATUS_FG_BAT0_L,
	PMIC_RG_INT_STATUS_FG_CUR_H,
	PMIC_RG_INT_STATUS_FG_CUR_L,
	PMIC_RG_INT_STATUS_FG_ZCV,
	PMIC_RG_INT_STATUS_FG_BAT1_H,
	PMIC_RG_INT_STATUS_FG_BAT1_L,
	PMIC_RG_INT_STATUS_FG_N_CHARGE_L,
	PMIC_RG_INT_STATUS_FG_IAVG_H,
	PMIC_RG_INT_STATUS_FG_IAVG_L,
	PMIC_RG_INT_STATUS_FG_TIME_H,
	PMIC_RG_INT_STATUS_FG_DISCHARGE,
	PMIC_RG_INT_STATUS_FG_CHARGE,
	PMIC_RG_BM_INT_STATUS0_RSV,
	PMIC_RG_INT_STATUS_BATON_LV,
	PMIC_RG_INT_STATUS_BATON_HT,
	PMIC_RG_INT_STATUS_BATON_BAT_IN,
	PMIC_RG_INT_STATUS_BATON_BAT_OUT,
	PMIC_RG_INT_STATUS_BIF,
	PMIC_RG_INT_RAW_STATUS_FG_BAT0_H,
	PMIC_RG_INT_RAW_STATUS_FG_BAT0_L,
	PMIC_RG_INT_RAW_STATUS_FG_CUR_H,
	PMIC_RG_INT_RAW_STATUS_FG_CUR_L,
	PMIC_RG_INT_RAW_STATUS_FG_ZCV,
	PMIC_RG_INT_RAW_STATUS_FG_BAT1_H,
	PMIC_RG_INT_RAW_STATUS_FG_BAT1_L,
	PMIC_RG_INT_RAW_STATUS_FG_N_CHARGE_L,
	PMIC_RG_INT_RAW_STATUS_FG_IAVG_H,
	PMIC_RG_INT_RAW_STATUS_FG_IAVG_L,
	PMIC_RG_INT_RAW_STATUS_FG_TIME_H,
	PMIC_RG_INT_RAW_STATUS_FG_DISCHARGE,
	PMIC_RG_INT_RAW_STATUS_FG_CHARGE,
	PMIC_RG_BM_INT_RAW_STATUS_RSV,
	PMIC_RG_INT_RAW_STATUS_BATON_LV,
	PMIC_RG_INT_RAW_STATUS_BATON_HT,
	PMIC_RG_INT_RAW_STATUS_BATON_BAT_IN,
	PMIC_RG_INT_RAW_STATUS_BATON_BAT_OUT,
	PMIC_RG_INT_RAW_STATUS_BIF,
	PMIC_POLARITY,
	PMIC_RG_BM_MON_FLAG_SEL,
	PMIC_RG_BM_MON_GRP_SEL,
	PMIC_RG_BM_TOP_RSV0,
	PMIC_FGADC_ANA_ANA_ID,
	PMIC_FGADC_ANA_DIG_ID,
	PMIC_FGADC_ANA_ANA_MINOR_REV,
	PMIC_FGADC_ANA_ANA_MAJOR_REV,
	PMIC_FGADC_ANA_DIG_MINOR_REV,
	PMIC_FGADC_ANA_DIG_MAJOR_REV,
	PMIC_FGADC_ANA_DSN_CBS,
	PMIC_FGADC_ANA_DSN_BIX,
	PMIC_FGADC_ANA_DSN_ESP,
	PMIC_FGADC_ANA_DSN_FPI,
	PMIC_RG_FGANALOGTEST,
	PMIC_RG_FGINTMODE,
	PMIC_RG_SPARE,
	PMIC_FG_RNG_BIT_MODE,
	PMIC_FG_RNG_BIT_SW,
	PMIC_FG_RNG_EN_MODE,
	PMIC_FG_RNG_EN_SW,
	PMIC_DA_FG_RNG_EN,
	PMIC_DA_FG_RNG_BIT,
	PMIC_FG_DWA_T0,
	PMIC_FG_DWA_T1,
	PMIC_FG_DWA_RST_MODE,
	PMIC_FG_DWA_RST_SW,
	PMIC_DA_DWA_RST,
	PMIC_FGADC_ANA_ELR_LEN,
	PMIC_RG_FGADC_GAINERROR_CAL,
	PMIC_RG_FG_OFFSET_SWAP,
	PMIC_FGADC0_ANA_ID,
	PMIC_FGADC0_DIG_ID,
	PMIC_FGADC0_ANA_MINOR_REV,
	PMIC_FGADC0_ANA_MAJOR_REV,
	PMIC_FGADC0_DIG_MINOR_REV,
	PMIC_FGADC0_DIG_MAJOR_REV,
	PMIC_FGADC0_DSN_CBS,
	PMIC_FGADC0_DSN_BIX,
	PMIC_FGADC0_DSN_ESP,
	PMIC_FGADC0_DSN_FPI,
	PMIC_FG_ON,
	PMIC_FG_CAL,
	PMIC_FG_AUTOCALRATE,
	PMIC_FG_SON_SLP_EN,
	PMIC_FG_SOFF_SLP_EN,
	PMIC_FG_ZCV_DET_EN,
	PMIC_FG_AUXADC_R,
	PMIC_FG_IAVG_MODE,
	PMIC_FG_SW_READ_PRE,
	PMIC_FG_SW_RSTCLR,
	PMIC_FG_SW_CR,
	PMIC_FG_SW_CLEAR,
	PMIC_FG_OFFSET_RST,
	PMIC_FG_TIME_RST,
	PMIC_FG_CHARGE_RST,
	PMIC_FG_N_CHARGE_RST,
	PMIC_FG_SOFF_RST,
	PMIC_FG_LATCHDATA_ST,
	PMIC_EVENT_FG_BAT0_H,
	PMIC_EVENT_FG_BAT0_L,
	PMIC_EVENT_FG_CUR_H,
	PMIC_EVENT_FG_CUR_L,
	PMIC_EVENT_FG_ZCV,
	PMIC_EVENT_FG_BAT1_H,
	PMIC_EVENT_FG_BAT1_L,
	PMIC_EVENT_FG_N_CHARGE_L,
	PMIC_EVENT_FG_IAVG_H,
	PMIC_EVENT_FG_IAVG_L,
	PMIC_EVENT_FG_TIME_H,
	PMIC_EVENT_FG_DISCHARGE,
	PMIC_EVENT_FG_CHARGE,
	PMIC_FG_OSR1,
	PMIC_FG_OSR2,
	PMIC_FG_ADJ_OFFSET_EN,
	PMIC_FG_ADC_AUTORST,
	PMIC_FG_ADC_RSTDETECT,
	PMIC_FG_VA_AON,
	PMIC_FG_VA_AOFF,
	PMIC_FG_SON_SW,
	PMIC_FG_SON_SW_MODE,
	PMIC_FGADC_CON4_RSV,
	PMIC_FG_RSTB_STATUS,
	PMIC_FG_CAR_15_00,
	PMIC_FG_CAR_31_16,
	PMIC_FG_BAT0_LTH_15_00,
	PMIC_FG_BAT0_LTH_31_16,
	PMIC_FG_BAT0_HTH_15_00,
	PMIC_FG_BAT0_HTH_31_16,
	PMIC_FG_BAT1_LTH_15_00,
	PMIC_FG_BAT1_LTH_31_16,
	PMIC_FG_BAT1_HTH_15_00,
	PMIC_FG_BAT1_HTH_31_16,
	PMIC_FG_NCAR_15_00,
	PMIC_FG_NCAR_31_16,
	PMIC_FG_N_CHARGE_LTH_15_00,
	PMIC_FG_N_CHARGE_LTH_31_16,
	PMIC_FG_IAVG_15_00,
	PMIC_FG_IAVG_27_16,
	PMIC_FG_IAVG_VLD,
	PMIC_FG_IAVG_LTH_15_00,
	PMIC_FG_IAVG_LTH_28_16,
	PMIC_FG_IAVG_HTH_15_00,
	PMIC_FG_IAVG_HTH_28_16,
	PMIC_FG_NTER_15_00,
	PMIC_FG_NTER_29_16,
	PMIC_FG_TIME_HTH_15_00,
	PMIC_FG_TIME_HTH_29_16,
	PMIC_FG_SON_SLP_CUR_TH,
	PMIC_FG_SON_SLP_TIME,
	PMIC_FG_SON_DET_TIME,
	PMIC_FG_FP_FTIME,
	PMIC_FG_SOFF_SLP_CUR_TH,
	PMIC_FG_SOFF_SLP_TIME,
	PMIC_FG_SOFF_DET_TIME,
	PMIC_FG_SOFF_TIME_15_00,
	PMIC_FG_SOFF_TIME_29_16,
	PMIC_FG_SOFF,
	PMIC_FG_PWR_TIME0,
	PMIC_FG_PWR_TIME1,
	PMIC_FG_PWR_TIME2,
	PMIC_FG_ZCV_DET_IV,
	PMIC_FG_ZCV_CURR,
	PMIC_FG_ZCV_CAR_15_00,
	PMIC_FG_ZCV_CAR_31_16,
	PMIC_FG_ZCV_CAR_TH_15_00,
	PMIC_FG_ZCV_CAR_TH_30_16,
	PMIC_FGADC1_ANA_ID,
	PMIC_FGADC1_DIG_ID,
	PMIC_FGADC1_ANA_MINOR_REV,
	PMIC_FGADC1_ANA_MAJOR_REV,
	PMIC_FGADC1_DIG_MINOR_REV,
	PMIC_FGADC1_DIG_MAJOR_REV,
	PMIC_FGADC1_DSN_CBS,
	PMIC_FGADC1_DSN_BIX,
	PMIC_FGADC1_DSN_ESP,
	PMIC_FGADC1_DSN_FPI,
	PMIC_FG_R_CURR,
	PMIC_FG_CURRENT_OUT,
	PMIC_FG_CUR_LTH,
	PMIC_FG_CUR_HTH,
	PMIC_FG_CIC2,
	PMIC_FG_OFFSET,
	PMIC_FG_ADJUST_OFFSET_VALUE,
	PMIC_FG_GAIN,
	PMIC_FG_MODE,
	PMIC_FG_RST_SW,
	PMIC_FG_FGCAL_EN_SW,
	PMIC_FG_FGADC_EN_SW,
	PMIC_RG_SYSTEM_INFO_CON0,
	PMIC_BATON_ANA_ANA_ID,
	PMIC_BATON_ANA_DIG_ID,
	PMIC_BATON_ANA_ANA_MINOR_REV,
	PMIC_BATON_ANA_ANA_MAJOR_REV,
	PMIC_BATON_ANA_DIG_MINOR_REV,
	PMIC_BATON_ANA_DIG_MAJOR_REV,
	PMIC_BATON_ANA_DSN_CBS,
	PMIC_BATON_ANA_DSN_BIX,
	PMIC_BATON_ANA_DSN_ESP,
	PMIC_BATON_ANA_DSN_FPI,
	PMIC_RG_BATON_EN,
	PMIC_RG_BIF_BATID_SW_EN,
	PMIC_RG_QI_BATON_LT_EN,
	PMIC_RG_BATON_HT_EN,
	PMIC_RG_BATON_HT_VTH,
	PMIC_RG_HW_VTH1,
	PMIC_RG_HW_VTH2,
	PMIC_RG_HW_VTH_CTRL,
	PMIC_DA_BATON_HT_EN,
	PMIC_AD_BATON_UNDET,
	PMIC_AD_BATON_UNDET_RAW,
	PMIC_AD_BATON_HV,
	PMIC_DA_BIF_TX_EN,
	PMIC_DA_BIF_TX_DATA,
	PMIC_DA_BIF_RX_EN,
	PMIC_AD_BIF_RX_DATA,
	PMIC_BATON_ANA_ELR_LEN,
	PMIC_RG_BATON_HT_TRIM,
	PMIC_BATON_ANA_ID,
	PMIC_BATON_DIG_ID,
	PMIC_BATON_ANA_MINOR_REV,
	PMIC_BATON_ANA_MAJOR_REV,
	PMIC_BATON_DIG_MINOR_REV,
	PMIC_BATON_DIG_MAJOR_REV,
	PMIC_BATON_DSN_CBS,
	PMIC_BATON_DSN_BIX,
	PMIC_BATON_DSN_ESP,
	PMIC_BATON_DSN_FPI,
	PMIC_RG_BATON_DEBOUNCE_WND,
	PMIC_RG_BATON_DEBOUNCE_THD,
	PMIC_RG_BATON_CHRDET_TEST_MODE,
	PMIC_RG_BATON_UNDET_TEST_MODE,
	PMIC_RG_BATON_AUXADC_TEST_MODE,
	PMIC_RG_BATON_FGADC_TEST_MODE,
	PMIC_RG_BATON_RTC_TEST_MODE,
	PMIC_RG_BATON_BIF_TEST_MODE,
	PMIC_RG_BATON_RSV,
	PMIC_RG_BATON_CHRDET_SW,
	PMIC_RG_BATON_UNDET_SW,
	PMIC_RG_BATON_AUXADC_SW,
	PMIC_RG_BATON_FGADC_SW,
	PMIC_RG_BATON_RTC_SW,
	PMIC_RG_BATON_BIF_SW,
	PMIC_RG_BATON_RSV_SW,
	PMIC_BATON_STATUS,
	PMIC_BATON_AUXADC_SET,
	PMIC_BATON_DEB_VALID,
	PMIC_BATON_BIF_STATUS,
	PMIC_BATON_RTC_STATUS,
	PMIC_BATON_FGADC_STATUS,
	PMIC_BATON_AUXADC_TRIG,
	PMIC_BATON_CHRDET_DEB,
	PMIC_BATON_IVGEN_ENB,
	PMIC_BATON_VBIF28_STB,
	PMIC_BATON_VBIF28_EN,
	PMIC_BATON_RSV_0,
	PMIC_RG_BATON_PWR_TIME0,
	PMIC_RG_BATON_PWR_TIME1,
	PMIC_BATON_ELR_LEN,
	PMIC_RG_BATON_CHRDET_DEB_TD,
	PMIC_BIF_ANA_ID,
	PMIC_BIF_DIG_ID,
	PMIC_BIF_ANA_MINOR_REV,
	PMIC_BIF_ANA_MAJOR_REV,
	PMIC_BIF_DIG_MINOR_REV,
	PMIC_BIF_DIG_MAJOR_REV,
	PMIC_BIF_DSN_CBS,
	PMIC_BIF_DSN_BIX,
	PMIC_BIF_ESP,
	PMIC_BIF_DSN_FPI,
	PMIC_BIF_COMMAND_0,
	PMIC_BIF_COMMAND_1,
	PMIC_BIF_COMMAND_2,
	PMIC_BIF_COMMAND_3,
	PMIC_BIF_COMMAND_4,
	PMIC_BIF_COMMAND_5,
	PMIC_BIF_COMMAND_6,
	PMIC_BIF_COMMAND_7,
	PMIC_BIF_COMMAND_8,
	PMIC_BIF_COMMAND_9,
	PMIC_BIF_COMMAND_10,
	PMIC_BIF_COMMAND_11,
	PMIC_BIF_COMMAND_12,
	PMIC_BIF_COMMAND_13,
	PMIC_BIF_COMMAND_14,
	PMIC_BIF_RSV,
	PMIC_BIF_COMMAND_TYPE,
	PMIC_BIF_TRASFER_NUM,
	PMIC_BIF_LOGIC_0_SET,
	PMIC_BIF_LOGIC_1_SET,
	PMIC_BIF_STOP_SET,
	PMIC_BIF_DEBOUNCE_EN,
	PMIC_BIF_READ_EXPECT_NUM,
	PMIC_BIF_TRASACT_TRIGGER,
	PMIC_BIF_DATA_NUM,
	PMIC_BIF_RESPONSE,
	PMIC_BIF_DATA_0,
	PMIC_BIF_ACK_0,
	PMIC_BIF_ERROR_0,
	PMIC_BIF_DATA_1,
	PMIC_BIF_ACK_1,
	PMIC_BIF_ERROR_1,
	PMIC_BIF_DATA_2,
	PMIC_BIF_ACK_2,
	PMIC_BIF_ERROR_2,
	PMIC_BIF_DATA_3,
	PMIC_BIF_ACK_3,
	PMIC_BIF_ERROR_3,
	PMIC_BIF_DATA_4,
	PMIC_BIF_ACK_4,
	PMIC_BIF_ERROR_4,
	PMIC_BIF_DATA_5,
	PMIC_BIF_ACK_5,
	PMIC_BIF_ERROR_5,
	PMIC_BIF_DATA_6,
	PMIC_BIF_ACK_6,
	PMIC_BIF_ERROR_6,
	PMIC_BIF_DATA_7,
	PMIC_BIF_ACK_7,
	PMIC_BIF_ERROR_7,
	PMIC_BIF_DATA_8,
	PMIC_BIF_ACK_8,
	PMIC_BIF_ERROR_8,
	PMIC_BIF_DATA_9,
	PMIC_BIF_ACK_9,
	PMIC_BIF_ERROR_9,
	PMIC_BIF_TEST_MODE0,
	PMIC_BIF_TEST_MODE1,
	PMIC_BIF_TEST_MODE2,
	PMIC_BIF_TEST_MODE3,
	PMIC_BIF_TEST_MODE4,
	PMIC_BIF_TEST_MODE5,
	PMIC_BIF_TEST_MODE6,
	PMIC_BIF_TEST_MODE7,
	PMIC_BIF_TEST_MODE8,
	PMIC_BIF_BAT_LOST_SW,
	PMIC_BIF_RX_DATA_SW,
	PMIC_BIF_TX_DATA_SW,
	PMIC_BIF_RX_EN_SW,
	PMIC_BIF_TX_EN_SW,
	PMIC_BIF_BACK_NORMAL,
	PMIC_BIF_IRQ_CLR,
	PMIC_BIF_IRQ,
	PMIC_BIF_TIMEOUT,
	PMIC_BIF_BAT_UNDET,
	PMIC_BIF_TOTAL_VALID,
	PMIC_BIF_BUS_STATUS,
	PMIC_BIF_POWER_UP_COUNT,
	PMIC_BIF_POWER_UP,
	PMIC_BIF_RX_ERROR_UNKNOWN,
	PMIC_BIF_RX_ERROR_INSUFF,
	PMIC_BIF_RX_ERROR_LOWPHASE,
	PMIC_BIF_RX_STATE,
	PMIC_BIF_FLOW_CTL_STATE,
	PMIC_BIF_TX_STATE,
	PMIC_BIF_TX_DATA_FIANL,
	PMIC_BIF_RX_DATA_SAMPLING,
	PMIC_BIF_RX_DATA_RECOVERY,
	PMIC_RG_BATON_HT_EN_PRE,
	PMIC_RG_BATON_HT_EN_DLY_TIME,
	PMIC_BIF_TIMEOUT_SET,
	PMIC_BIF_RX_DEG_WND,
	PMIC_BIF_RX_DEG_EN,
	PMIC_BIF_RSV1,
	PMIC_BIF_RSV0,
	PMIC_HK_TOP_ANA_ID,
	PMIC_HK_TOP_DIG_ID,
	PMIC_HK_TOP_ANA_MINOR_REV,
	PMIC_HK_TOP_ANA_MAJOR_REV,
	PMIC_HK_TOP_DIG_MINOR_REV,
	PMIC_HK_TOP_DIG_MAJOR_REV,
	PMIC_HK_TOP_CBS,
	PMIC_HK_TOP_BIX,
	PMIC_HK_TOP_ESP,
	PMIC_HK_TOP_FPI,
	PMIC_HK_CLK_OFFSET,
	PMIC_HK_RST_OFFSET,
	PMIC_HK_INT_OFFSET,
	PMIC_HK_INT_LEN,
	PMIC_RG_AUXADC_AO_1M_CK_PDN,
	PMIC_RG_AUXADC_1M_CK_PDN_HWEN,
	PMIC_RG_AUXADC_1M_CK_PDN,
	PMIC_RG_AUXADC_CK_PDN_HWEN,
	PMIC_RG_AUXADC_CK_PDN,
	PMIC_RG_AUXADC_RNG_CK_PDN_HWEN,
	PMIC_RG_AUXADC_RNG_CK_PDN,
	PMIC_RG_AUXADC_32K_CK_PDN_HWEN,
	PMIC_RG_AUXADC_32K_CK_PDN,
	PMIC_RG_AUXADC_1K_CK_PDN_HWEN,
	PMIC_RG_AUXADC_1K_CK_PDN,
	PMIC_RG_HK_INTRP_CK_PDN_HWEN,
	PMIC_RG_HK_INTRP_CK_PDN,
	PMIC_RG_AUXADC_CK_DIVSEL,
	PMIC_RG_AUXADC_CK_TSTSEL,
	PMIC_RG_AUXADC_RST,
	PMIC_RG_AUXADC_REG_RST,
	PMIC_BANK_HK_TOP_SWRST,
	PMIC_BANK_AUXADC_SWRST,
	PMIC_BANK_AUXADC_DIG_1_SWRST,
	PMIC_BANK_AUXADC_DIG_2_SWRST,
	PMIC_BANK_AUXADC_DIG_3_SWRST,
	PMIC_BANK_AUXADC_DIG_4_SWRST,
	PMIC_RG_INT_EN_BAT_H,
	PMIC_RG_INT_EN_BAT_L,
	PMIC_RG_INT_EN_BAT2_H,
	PMIC_RG_INT_EN_BAT2_L,
	PMIC_RG_INT_EN_BAT_TEMP_H,
	PMIC_RG_INT_EN_BAT_TEMP_L,
	PMIC_RG_INT_EN_AUXADC_IMP,
	PMIC_RG_INT_EN_NAG_C_DLTV,
	PMIC_HK_INT_CON0_SET,
	PMIC_HK_INT_CON0_CLR,
	PMIC_RG_INT_MASK_BAT_H,
	PMIC_RG_INT_MASK_BAT_L,
	PMIC_RG_INT_MASK_BAT2_H,
	PMIC_RG_INT_MASK_BAT2_L,
	PMIC_RG_INT_MASK_BAT_TEMP_H,
	PMIC_RG_INT_MASK_BAT_TEMP_L,
	PMIC_RG_INT_MASK_AUXADC_IMP,
	PMIC_RG_INT_MASK_NAG_C_DLTV,
	PMIC_HK_INT_MASK_CON0_SET,
	PMIC_HK_INT_MASK_CON0_CLR,
	PMIC_RG_INT_STATUS_BAT_H,
	PMIC_RG_INT_STATUS_BAT_L,
	PMIC_RG_INT_STATUS_BAT2_H,
	PMIC_RG_INT_STATUS_BAT2_L,
	PMIC_RG_INT_STATUS_BAT_TEMP_H,
	PMIC_RG_INT_STATUS_BAT_TEMP_L,
	PMIC_RG_INT_STATUS_AUXADC_IMP,
	PMIC_RG_INT_STATUS_NAG_C_DLTV,
	PMIC_RG_INT_RAW_STATUS_BAT_H,
	PMIC_RG_INT_RAW_STATUS_BAT_L,
	PMIC_RG_INT_RAW_STATUS_BAT2_H,
	PMIC_RG_INT_RAW_STATUS_BAT2_L,
	PMIC_RG_INT_RAW_STATUS_BAT_TEMP_H,
	PMIC_RG_INT_RAW_STATUS_BAT_TEMP_L,
	PMIC_RG_INT_RAW_STATUS_AUXADC_IMP,
	PMIC_RG_INT_RAW_STATUS_NAG_C_DLTV,
	PMIC_RG_CLK_MON_FLAG_EN,
	PMIC_RG_CLK_MON_FLAG_SEL,
	PMIC_RG_INT_MON_FLAG_EN,
	PMIC_RG_INT_MON_FLAG_SEL,
	PMIC_RG_HK_MON_FLAG_SEL,
	PMIC_RG_MON_FLAG_SEL_AUXADC,
	PMIC_RG_ADCIN_VSEN_MUX_EN,
	PMIC_RG_BATON_TDET_EN,
	PMIC_RG_ADCIN_VSEN_EXT_BATON_EN,
	PMIC_RG_ADCIN_VBAT_EN,
	PMIC_RG_ADCIN_VSEN_EN,
	PMIC_RG_ADCIN_CHR_EN,
	PMIC_DA_ADCIN_VBAT_EN,
	PMIC_DA_AUXADC_VBAT_EN,
	PMIC_DA_ADCIN_VSEN_MUX_EN,
	PMIC_DA_ADCIN_VSEN_EN,
	PMIC_DA_ADCIN_CHR_EN,
	PMIC_DA_BATON_TDET_EN,
	PMIC_DA_ADCIN_BATID_SW_EN,
	PMIC_AUXADC_ANA_ID,
	PMIC_AUXADC_DIG_ID,
	PMIC_AUXADC_ANA_MINOR_REV,
	PMIC_AUXADC_ANA_MAJOR_REV,
	PMIC_AUXADC_DIG_MINOR_REV,
	PMIC_AUXADC_DIG_MAJOR_REV,
	PMIC_AUXADC_DSN_CBS,
	PMIC_AUXADC_DSN_BIX,
	PMIC_AUXADC_DSN_ESP,
	PMIC_AUXADC_DSN_FPI,
	PMIC_RG_AUXADC_CALI,
	PMIC_RG_AUX_RSV,
	PMIC_RG_VBUF_BYP,
	PMIC_RG_VBUF_CALEN,
	PMIC_RG_VBUF_EXTEN,
	PMIC_AUXADC_DIG_1_ANA_ID,
	PMIC_AUXADC_DIG_1_DIG_ID,
	PMIC_AUXADC_DIG_1_ANA_MINOR_REV,
	PMIC_AUXADC_DIG_1_ANA_MAJOR_REV,
	PMIC_AUXADC_DIG_1_DIG_MINOR_REV,
	PMIC_AUXADC_DIG_1_DIG_MAJOR_REV,
	PMIC_AUXADC_DIG_1_DSN_CBS,
	PMIC_AUXADC_DIG_1_DSN_BIX,
	PMIC_AUXADC_DIG_1_DSN_ESP,
	PMIC_AUXADC_DIG_1_DSN_FPI,
	PMIC_AUXADC_ADC_OUT_CH0,
	PMIC_AUXADC_ADC_RDY_CH0,
	PMIC_AUXADC_ADC_OUT_CH1,
	PMIC_AUXADC_ADC_RDY_CH1,
	PMIC_AUXADC_ADC_OUT_CH2,
	PMIC_AUXADC_ADC_RDY_CH2,
	PMIC_AUXADC_ADC_OUT_CH3,
	PMIC_AUXADC_ADC_RDY_CH3,
	PMIC_AUXADC_ADC_OUT_CH4,
	PMIC_AUXADC_ADC_RDY_CH4,
	PMIC_AUXADC_ADC_OUT_CH5,
	PMIC_AUXADC_ADC_RDY_CH5,
	PMIC_AUXADC_ADC_OUT_CH6,
	PMIC_AUXADC_ADC_RDY_CH6,
	PMIC_AUXADC_ADC_OUT_CH7,
	PMIC_AUXADC_ADC_RDY_CH7,
	PMIC_AUXADC_ADC_OUT_CH8,
	PMIC_AUXADC_ADC_RDY_CH8,
	PMIC_AUXADC_ADC_OUT_CH9,
	PMIC_AUXADC_ADC_RDY_CH9,
	PMIC_AUXADC_ADC_OUT_CH10,
	PMIC_AUXADC_ADC_RDY_CH10,
	PMIC_AUXADC_ADC_OUT_CH11,
	PMIC_AUXADC_ADC_RDY_CH11,
	PMIC_AUXADC_ADC_OUT_CH12_15,
	PMIC_AUXADC_ADC_RDY_CH12_15,
	PMIC_AUXADC_ADC_OUT_LBAT,
	PMIC_AUXADC_ADC_RDY_LBAT,
	PMIC_AUXADC_ADC_OUT_LBAT2,
	PMIC_AUXADC_ADC_RDY_LBAT2,
	PMIC_AUXADC_ADC_OUT_CH7_BY_GPS,
	PMIC_AUXADC_ADC_RDY_CH7_BY_GPS,
	PMIC_AUXADC_ADC_OUT_CH7_BY_MD,
	PMIC_AUXADC_ADC_RDY_CH7_BY_MD,
	PMIC_AUXADC_ADC_OUT_CH7_BY_AP,
	PMIC_AUXADC_ADC_RDY_CH7_BY_AP,
	PMIC_AUXADC_ADC_OUT_CH4_BY_MD,
	PMIC_AUXADC_ADC_RDY_CH4_BY_MD,
	PMIC_AUXADC_ADC_OUT_PWRON_PCHR,
	PMIC_AUXADC_ADC_RDY_PWRON_PCHR,
	PMIC_AUXADC_ADC_OUT_WAKEUP_PCHR,
	PMIC_AUXADC_ADC_RDY_WAKEUP_PCHR,
	PMIC_AUXADC_ADC_OUT_CH0_BY_MD,
	PMIC_AUXADC_ADC_RDY_CH0_BY_MD,
	PMIC_AUXADC_ADC_OUT_CH0_BY_AP,
	PMIC_AUXADC_ADC_RDY_CH0_BY_AP,
	PMIC_AUXADC_ADC_OUT_CH1_BY_MD,
	PMIC_AUXADC_ADC_RDY_CH1_BY_MD,
	PMIC_AUXADC_ADC_OUT_CH1_BY_AP,
	PMIC_AUXADC_ADC_RDY_CH1_BY_AP,
	PMIC_AUXADC_ADC_OUT_BAT_TEMP,
	PMIC_AUXADC_ADC_RDY_BAT_TEMP,
	PMIC_AUXADC_ADC_OUT_FGADC_PCHR,
	PMIC_AUXADC_ADC_RDY_FGADC_PCHR,
	PMIC_AUXADC_ADC_OUT_BAT_PLUGIN_PCHR,
	PMIC_AUXADC_ADC_RDY_BAT_PLUGIN_PCHR,
	PMIC_AUXADC_ADC_OUT_IMP,
	PMIC_AUXADC_ADC_RDY_IMP,
	PMIC_AUXADC_ADC_OUT_IMP_AVG,
	PMIC_AUXADC_ADC_RDY_IMP_AVG,
	PMIC_AUXADC_ADC_OUT_RAW,
	PMIC_AUXADC_ADC_OUT_MDRT,
	PMIC_AUXADC_ADC_RDY_MDRT,
	PMIC_AUXADC_ADC_OUT_DCXO_BY_GPS,
	PMIC_AUXADC_ADC_RDY_DCXO_BY_GPS,
	PMIC_AUXADC_ADC_OUT_DCXO_BY_MD,
	PMIC_AUXADC_ADC_RDY_DCXO_BY_MD,
	PMIC_AUXADC_ADC_OUT_DCXO_BY_AP,
	PMIC_AUXADC_ADC_RDY_DCXO_BY_AP,
	PMIC_AUXADC_ADC_OUT_DCXO_MDRT,
	PMIC_AUXADC_ADC_RDY_DCXO_MDRT,
	PMIC_AUXADC_ADC_OUT_NAG,
	PMIC_AUXADC_ADC_RDY_NAG,
	PMIC_AUXADC_ADC_OUT_BATID,
	PMIC_AUXADC_ADC_RDY_BATID,
	PMIC_AUXADC_ADC_OUT_CH4_BY_THR1,
	PMIC_AUXADC_ADC_RDY_CH4_BY_THR1,
	PMIC_AUXADC_ADC_OUT_CH4_BY_THR2,
	PMIC_AUXADC_ADC_RDY_CH4_BY_THR2,
	PMIC_AUXADC_ADC_OUT_CH4_BY_THR3,
	PMIC_AUXADC_ADC_RDY_CH4_BY_THR3,
	PMIC_AUXADC_ADC_BUSY_IN,
	PMIC_AUXADC_ADC_BUSY_IN_LBAT,
	PMIC_AUXADC_ADC_BUSY_IN_LBAT2,
	PMIC_AUXADC_ADC_BUSY_IN_BAT_TEMP,
	PMIC_AUXADC_ADC_BUSY_IN_WAKEUP,
	PMIC_AUXADC_ADC_BUSY_IN_DCXO_MDRT,
	PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_AP,
	PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS_MD,
	PMIC_AUXADC_ADC_BUSY_IN_DCXO_GPS,
	PMIC_AUXADC_ADC_BUSY_IN_MDRT,
	PMIC_AUXADC_ADC_BUSY_IN_SHARE,
	PMIC_AUXADC_ADC_BUSY_IN_IMP,
	PMIC_AUXADC_ADC_BUSY_IN_FGADC_PCHR,
	PMIC_AUXADC_ADC_BUSY_IN_GPS_AP,
	PMIC_AUXADC_ADC_BUSY_IN_GPS_MD,
	PMIC_AUXADC_ADC_BUSY_IN_GPS,
	PMIC_AUXADC_ADC_BUSY_IN_THR_MD,
	PMIC_AUXADC_ADC_BUSY_IN_BAT_PLUGIN_PCHR,
	PMIC_AUXADC_ADC_BUSY_IN_BATID,
	PMIC_AUXADC_ADC_BUSY_IN_PWRON,
	PMIC_AUXADC_ADC_BUSY_IN_THR1,
	PMIC_AUXADC_ADC_BUSY_IN_THR2,
	PMIC_AUXADC_ADC_BUSY_IN_THR3,
	PMIC_AUXADC_ADC_BUSY_IN_NAG,
	PMIC_AUXADC_DIG_2_ANA_ID,
	PMIC_AUXADC_DIG_2_DIG_ID,
	PMIC_AUXADC_DIG_2_ANA_MINOR_REV,
	PMIC_AUXADC_DIG_2_ANA_MAJOR_REV,
	PMIC_AUXADC_DIG_2_DIG_MINOR_REV,
	PMIC_AUXADC_DIG_2_DIG_MAJOR_REV,
	PMIC_AUXADC_DIG_2_DSN_CBS,
	PMIC_AUXADC_DIG_2_DSN_BIX,
	PMIC_AUXADC_DIG_2_DSN_ESP,
	PMIC_AUXADC_DIG_2_DSN_FPI,
	PMIC_AUXADC_RQST_CH0,
	PMIC_AUXADC_RQST_CH1,
	PMIC_AUXADC_RQST_CH2,
	PMIC_AUXADC_RQST_CH3,
	PMIC_AUXADC_RQST_CH4,
	PMIC_AUXADC_RQST_CH5,
	PMIC_AUXADC_RQST_CH6,
	PMIC_AUXADC_RQST_CH7,
	PMIC_AUXADC_RQST_CH8,
	PMIC_AUXADC_RQST_CH9,
	PMIC_AUXADC_RQST_CH10,
	PMIC_AUXADC_RQST_CH11,
	PMIC_AUXADC_RQST_CH12,
	PMIC_AUXADC_RQST_CH13,
	PMIC_AUXADC_RQST_CH14,
	PMIC_AUXADC_RQST_CH15,
	PMIC_AUXADC_RQST_CH0_BY_MD,
	PMIC_AUXADC_RQST_CH1_BY_MD,
	PMIC_AUXADC_RQST_CH4_BY_MD,
	PMIC_AUXADC_RQST_CH7_BY_MD,
	PMIC_AUXADC_RQST_CH7_BY_GPS,
	PMIC_AUXADC_RQST_DCXO_BY_MD,
	PMIC_AUXADC_RQST_DCXO_BY_GPS,
	PMIC_AUXADC_RQST_BATID,
	PMIC_AUXADC_RQST_CH4_BY_THR1,
	PMIC_AUXADC_RQST_CH4_BY_THR2,
	PMIC_AUXADC_RQST_CH4_BY_THR3,
	PMIC_AUXADC_RQST_RSV1,
	PMIC_AUXADC_DIG_3_ANA_ID,
	PMIC_AUXADC_DIG_3_DIG_ID,
	PMIC_AUXADC_DIG_3_ANA_MINOR_REV,
	PMIC_AUXADC_DIG_3_ANA_MAJOR_REV,
	PMIC_AUXADC_DIG_3_DIG_MINOR_REV,
	PMIC_AUXADC_DIG_3_DIG_MAJOR_REV,
	PMIC_AUXADC_DIG_3_DSN_CBS,
	PMIC_AUXADC_DIG_3_DSN_BIX,
	PMIC_AUXADC_DIG_3_DSN_ESP,
	PMIC_AUXADC_DIG_3_DSN_FPI,
	PMIC_AUXADC_CK_ON_EXTD,
	PMIC_AUXADC_SRCLKEN_SRC_SEL,
	PMIC_AUXADC_ADC_PWDB,
	PMIC_AUXADC_ADC_PWDB_SWCTRL,
	PMIC_AUXADC_STRUP_CK_ON_ENB,
	PMIC_AUXADC_SRCLKEN_CK_EN,
	PMIC_AUXADC_CK_AON_GPS,
	PMIC_AUXADC_CK_AON_MD,
	PMIC_AUXADC_CK_AON,
	PMIC_AUXADC_CON0_SET,
	PMIC_AUXADC_CON0_CLR,
	PMIC_AUXADC_AVG_NUM_SMALL,
	PMIC_AUXADC_AVG_NUM_LARGE,
	PMIC_AUXADC_SPL_NUM,
	PMIC_AUXADC_AVG_NUM_SEL,
	PMIC_AUXADC_AVG_NUM_SEL_SHARE,
	PMIC_AUXADC_AVG_NUM_SEL_LBAT,
	PMIC_AUXADC_AVG_NUM_SEL_BAT_TEMP,
	PMIC_AUXADC_AVG_NUM_SEL_WAKEUP,
	PMIC_AUXADC_SPL_NUM_LARGE,
	PMIC_AUXADC_SPL_NUM_SLEEP,
	PMIC_AUXADC_SPL_NUM_SLEEP_SEL,
	PMIC_AUXADC_SPL_NUM_SEL,
	PMIC_AUXADC_SPL_NUM_SEL_SHARE,
	PMIC_AUXADC_SPL_NUM_SEL_LBAT,
	PMIC_AUXADC_SPL_NUM_SEL_BAT_TEMP,
	PMIC_AUXADC_SPL_NUM_SEL_WAKEUP,
	PMIC_AUXADC_SPL_NUM_CH0,
	PMIC_AUXADC_SPL_NUM_CH3,
	PMIC_AUXADC_SPL_NUM_CH7,
	PMIC_AUXADC_AVG_NUM_LBAT,
	PMIC_AUXADC_AVG_NUM_CH7,
	PMIC_AUXADC_AVG_NUM_CH3,
	PMIC_AUXADC_AVG_NUM_CH0,
	PMIC_AUXADC_AVG_NUM_HPC,
	PMIC_AUXADC_AVG_NUM_DCXO,
	PMIC_AUXADC_TRIM_CH0_SEL,
	PMIC_AUXADC_TRIM_CH1_SEL,
	PMIC_AUXADC_TRIM_CH2_SEL,
	PMIC_AUXADC_TRIM_CH3_SEL,
	PMIC_AUXADC_TRIM_CH4_SEL,
	PMIC_AUXADC_TRIM_CH5_SEL,
	PMIC_AUXADC_TRIM_CH6_SEL,
	PMIC_AUXADC_TRIM_CH7_SEL,
	PMIC_AUXADC_TRIM_CH8_SEL,
	PMIC_AUXADC_TRIM_CH9_SEL,
	PMIC_AUXADC_TRIM_CH10_SEL,
	PMIC_AUXADC_TRIM_CH11_SEL,
	PMIC_AUXADC_ADC_2S_COMP_ENB,
	PMIC_AUXADC_ADC_TRIM_COMP,
	PMIC_AUXADC_RNG_EN,
	PMIC_AUXADC_TEST_MODE,
	PMIC_AUXADC_BIT_SEL,
	PMIC_AUXADC_START_SW,
	PMIC_AUXADC_START_SWCTRL,
	PMIC_AUXADC_TS_VBE_SEL,
	PMIC_AUXADC_TS_VBE_SEL_SWCTRL,
	PMIC_AUXADC_VBUF_EN,
	PMIC_AUXADC_VBUF_EN_SWCTRL,
	PMIC_AUXADC_OUT_SEL,
	PMIC_AUXADC_DA_DAC,
	PMIC_AUXADC_DA_DAC_SWCTRL,
	PMIC_AD_AUXADC_COMP,
	PMIC_AUXADC_ADCIN_VSEN_EN,
	PMIC_AUXADC_ADCIN_VBAT_EN,
	PMIC_AUXADC_ADCIN_VSEN_MUX_EN,
	PMIC_AUXADC_ADCIN_VSEN_EXT_BATON_EN,
	PMIC_AUXADC_ADCIN_CHR_EN,
	PMIC_AUXADC_ADCIN_BATON_TDET_EN,
	PMIC_AUXADC_ACCDET_ANASWCTRL_EN,
	PMIC_AUXADC_XO_THADC_EN,
	PMIC_AUXADC_ADCIN_BATID_SW_EN,
	PMIC_AUXADC_DIG0_RSV0,
	PMIC_AUXADC_CHSEL,
	PMIC_AUXADC_SWCTRL_EN,
	PMIC_AUXADC_SOURCE_LBAT_SEL,
	PMIC_AUXADC_SOURCE_LBAT2_SEL,
	PMIC_AUXADC_START_EXTD,
	PMIC_AUXADC_DAC_EXTD,
	PMIC_AUXADC_DAC_EXTD_EN,
	PMIC_AUXADC_DIG0_RSV1,
	PMIC_AUXADC_START_SHADE_NUM,
	PMIC_AUXADC_START_SHADE_EN,
	PMIC_AUXADC_START_SHADE_SEL,
	PMIC_AUXADC_ADC_RDY_WAKEUP_CLR,
	PMIC_AUXADC_ADC_RDY_FGADC_CLR,
	PMIC_AUXADC_ADC_RDY_BAT_PLUGIN_CLR,
	PMIC_AUXADC_ADC_RDY_PWRON_CLR,
	PMIC_AUXADC_DATA_REUSE_SEL,
	PMIC_AUXADC_CH0_DATA_REUSE_SEL,
	PMIC_AUXADC_CH1_DATA_REUSE_SEL,
	PMIC_AUXADC_DCXO_DATA_REUSE_SEL,
	PMIC_AUXADC_DATA_REUSE_EN,
	PMIC_AUXADC_CH0_DATA_REUSE_EN,
	PMIC_AUXADC_CH1_DATA_REUSE_EN,
	PMIC_AUXADC_DCXO_DATA_REUSE_EN,
	PMIC_AUXADC_AUTORPT_PRD,
	PMIC_AUXADC_AUTORPT_EN,
	PMIC_AUXADC_ACCDET_AUTO_SPL,
	PMIC_AUXADC_ACCDET_AUTO_RQST_CLR,
	PMIC_AUXADC_ACCDET_DIG1_RSV0,
	PMIC_AUXADC_ACCDET_DIG0_RSV0,
	PMIC_AUXADC_FGADC_START_SW,
	PMIC_AUXADC_FGADC_START_SEL,
	PMIC_AUXADC_FGADC_R_SW,
	PMIC_AUXADC_FGADC_R_SEL,
	PMIC_AUXADC_BAT_PLUGIN_START_SW,
	PMIC_AUXADC_BAT_PLUGIN_START_SEL,
	PMIC_AUXADC_DBG_DIG0_RSV2,
	PMIC_AUXADC_DBG_DIG1_RSV2,
	PMIC_AUXADC_DIG_3_ELR_LEN,
	PMIC_EFUSE_GAIN_CH7_TRIM,
	PMIC_EFUSE_OFFSET_CH7_TRIM,
	PMIC_EFUSE_GAIN_CH4_TRIM,
	PMIC_EFUSE_OFFSET_CH4_TRIM,
	PMIC_EFUSE_GAIN_CH0_TRIM,
	PMIC_EFUSE_OFFSET_CH0_TRIM,
	PMIC_AUXADC_SW_GAIN_TRIM,
	PMIC_AUXADC_SW_OFFSET_TRIM,
	PMIC_AUXADC_EFUSE_DEGC_CALI,
	PMIC_AUXADC_EFUSE_ADC_CALI_EN,
	PMIC_AUXADC_EFUSE_1RSV0,
	PMIC_AUXADC_EFUSE_O_VTS,
	PMIC_AUXADC_EFUSE_2RSV0,
	PMIC_AUXADC_EFUSE_O_SLOPE,
	PMIC_AUXADC_EFUSE_O_SLOPE_SIGN,
	PMIC_AUXADC_EFUSE_3RSV0,
	PMIC_AUXADC_EFUSE_AUXADC_RSV,
	PMIC_AUXADC_EFUSE_ID,
	PMIC_AUXADC_EFUSE_4RSV0,
	PMIC_AUXADC_EFUSE_O_VTS_2,
	PMIC_AUXADC_EFUSE_2RSV0_2,
	PMIC_AUXADC_EFUSE_O_VTS_3,
	PMIC_AUXADC_EFUSE_2RSV0_3,
	PMIC_AUXADC_DIG_4_ANA_ID,
	PMIC_AUXADC_DIG_4_DIG_ID,
	PMIC_AUXADC_DIG_4_ANA_MINOR_REV,
	PMIC_AUXADC_DIG_4_ANA_MAJOR_REV,
	PMIC_AUXADC_DIG_4_DIG_MINOR_REV,
	PMIC_AUXADC_DIG_4_DIG_MAJOR_REV,
	PMIC_AUXADC_DIG_4_DSN_CBS,
	PMIC_AUXADC_DIG_4_DSN_BIX,
	PMIC_AUXADC_DIG_4_DSN_ESP,
	PMIC_AUXADC_DIG_4_DSN_FPI,
	PMIC_AUXADC_IMPEDANCE_CNT,
	PMIC_AUXADC_IMPEDANCE_CHSEL,
	PMIC_AUXADC_IMPEDANCE_IRQ_CLR,
	PMIC_AUXADC_IMPEDANCE_IRQ_STATUS,
	PMIC_AUXADC_CLR_IMP_CNT_STOP,
	PMIC_AUXADC_IMPEDANCE_MODE,
	PMIC_AUXADC_IMP_AUTORPT_PRD,
	PMIC_AUXADC_IMP_AUTORPT_EN,
	PMIC_AUXADC_IMP_CNT,
	PMIC_AUXADC_IMP_CNT_STOP_STATE,
	PMIC_AUXADC_LBAT_DEBT_MAX,
	PMIC_AUXADC_LBAT_DEBT_MIN,
	PMIC_AUXADC_LBAT_DET_PRD_15_0,
	PMIC_AUXADC_LBAT_DET_PRD_19_16,
	PMIC_AUXADC_LBAT_VOLT_MAX,
	PMIC_AUXADC_LBAT_IRQ_EN_MAX,
	PMIC_AUXADC_LBAT_EN_MAX,
	PMIC_AUXADC_LBAT_MAX_IRQ_B,
	PMIC_AUXADC_LBAT_VOLT_MIN,
	PMIC_AUXADC_LBAT_IRQ_EN_MIN,
	PMIC_AUXADC_LBAT_EN_MIN,
	PMIC_AUXADC_LBAT_MIN_IRQ_B,
	PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MAX,
	PMIC_AUXADC_LBAT_DEBOUNCE_COUNT_MIN,
	PMIC_AUXADC_BAT_TEMP_FROZE_EN,
	PMIC_AUXADC_BAT_TEMP_DEBT_MAX,
	PMIC_AUXADC_BAT_TEMP_DEBT_MIN,
	PMIC_AUXADC_BAT_TEMP_DET_PRD_15_0,
	PMIC_AUXADC_BAT_TEMP_DET_PRD_19_16,
	PMIC_AUXADC_BAT_TEMP_VOLT_MAX,
	PMIC_AUXADC_BAT_TEMP_IRQ_EN_MAX,
	PMIC_AUXADC_BAT_TEMP_EN_MAX,
	PMIC_AUXADC_BAT_TEMP_MAX_IRQ_B,
	PMIC_AUXADC_BAT_TEMP_VOLT_MIN,
	PMIC_AUXADC_BAT_TEMP_IRQ_EN_MIN,
	PMIC_AUXADC_BAT_TEMP_EN_MIN,
	PMIC_AUXADC_BAT_TEMP_MIN_IRQ_B,
	PMIC_AUXADC_BAT_TEMP_DEBOUNCE_COUNT_MAX,
	PMIC_AUXADC_BAT_TEMP_DEBOUNCE_COUNT_MIN,
	PMIC_AUXADC_LBAT2_DEBT_MAX,
	PMIC_AUXADC_LBAT2_DEBT_MIN,
	PMIC_AUXADC_LBAT2_DET_PRD_15_0,
	PMIC_AUXADC_LBAT2_DET_PRD_19_16,
	PMIC_AUXADC_LBAT2_VOLT_MAX,
	PMIC_AUXADC_LBAT2_IRQ_EN_MAX,
	PMIC_AUXADC_LBAT2_EN_MAX,
	PMIC_AUXADC_LBAT2_MAX_IRQ_B,
	PMIC_AUXADC_LBAT2_VOLT_MIN,
	PMIC_AUXADC_LBAT2_IRQ_EN_MIN,
	PMIC_AUXADC_LBAT2_EN_MIN,
	PMIC_AUXADC_LBAT2_MIN_IRQ_B,
	PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MAX,
	PMIC_AUXADC_LBAT2_DEBOUNCE_COUNT_MIN,
	PMIC_AUXADC_MDRT_DET_PRD,
	PMIC_AUXADC_MDRT_DET_EN,
	PMIC_AUXADC_MDRT_DET_WKUP_START_CNT,
	PMIC_AUXADC_MDRT_DET_WKUP_START_CLR,
	PMIC_AUXADC_MDRT_DET_WKUP_START,
	PMIC_AUXADC_MDRT_DET_WKUP_START_SEL,
	PMIC_AUXADC_MDRT_DET_WKUP_EN,
	PMIC_AUXADC_MDRT_DET_SRCLKEN_IND,
	PMIC_AUXADC_MDRT_DET_RDY_ST_PRD,
	PMIC_AUXADC_MDRT_DET_RDY_ST_EN,
	PMIC_AUXADC_MDRT_DET_START_SEL,
	PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CNT,
	PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_CLR,
	PMIC_AUXADC_DCXO_MDRT_DET_WKUP_EN,
	PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START_SEL,
	PMIC_AUXADC_DCXO_MDRT_DET_WKUP_START,
	PMIC_AUXADC_NAG_EN,
	PMIC_AUXADC_NAG_CLR,
	PMIC_AUXADC_NAG_VBAT1_SEL,
	PMIC_AUXADC_NAG_PRD,
	PMIC_AUXADC_NAG_IRQ_EN,
	PMIC_AUXADC_NAG_C_DLTV_IRQ,
	PMIC_AUXADC_NAG_ZCV,
	PMIC_AUXADC_NAG_C_DLTV_TH_15_0,
	PMIC_AUXADC_NAG_C_DLTV_TH_26_16,
	PMIC_AUXADC_NAG_CNT_15_0,
	PMIC_AUXADC_NAG_CNT_25_16,
	PMIC_AUXADC_NAG_DLTV,
	PMIC_AUXADC_NAG_C_DLTV_15_0,
	PMIC_AUXADC_NAG_C_DLTV_26_16,
	PMIC_AUXADC_NAG_START,
	PMIC_AUXADC_NAG_CK_ON,
	PMIC_AUXADC_RSV_1RSV0,
	PMIC_AUXADC_NEW_PRIORITY_LIST_SEL,
	PMIC_AUXADC_IMP_CK_SW_MODE,
	PMIC_AUXADC_IMP_CK_SW_EN,
	PMIC_AUXADC_LBAT_CK_SW_MODE,
	PMIC_AUXADC_LBAT_CK_SW_EN,
	PMIC_AUXADC_BAT_TEMP_CK_SW_MODE,
	PMIC_AUXADC_BAT_TEMP_CK_SW_EN,
	PMIC_AUXADC_LBAT2_CK_SW_MODE,
	PMIC_AUXADC_LBAT2_CK_SW_EN,
	PMIC_AUXADC_NAG_CK_SW_MODE,
	PMIC_AUXADC_NAG_CK_SW_EN,
	PMIC_AUXADC_SAMPLE_LIST_15_0,
	PMIC_AUXADC_SAMPLE_LIST_31_16,
	PMIC_AUXADC_SAMPLE_LIST_33_32,
	PMIC_BUCK_TOP_ANA_ID,
	PMIC_BUCK_TOP_DIG_ID,
	PMIC_BUCK_TOP_ANA_MINOR_REV,
	PMIC_BUCK_TOP_ANA_MAJOR_REV,
	PMIC_BUCK_TOP_DIG_MINOR_REV,
	PMIC_BUCK_TOP_DIG_MAJOR_REV,
	PMIC_BUCK_TOP_CBS,
	PMIC_BUCK_TOP_BIX,
	PMIC_BUCK_TOP_ESP,
	PMIC_BUCK_TOP_FPI,
	PMIC_BUCK_TOP_CLK_OFFSET,
	PMIC_BUCK_TOP_RST_OFFSET,
	PMIC_BUCK_TOP_INT_OFFSET,
	PMIC_BUCK_TOP_INT_LEN,
	PMIC_RG_BUCK32K_CK_PDN,
	PMIC_RG_BUCK1M_CK_PDN,
	PMIC_RG_BUCK26M_CK_PDN,
	PMIC_RG_BUCK_ANA_AUTO_OFF_DIS,
	PMIC_RG_BUCK_ANA_CK_PDN,
	PMIC_RG_BUCK_TOP_CLK_CON0_SET,
	PMIC_RG_BUCK_TOP_CLK_CON0_CLR,
	PMIC_RG_BUCK32K_CK_PDN_HWEN,
	PMIC_RG_BUCK1M_CK_PDN_HWEN,
	PMIC_RG_BUCK26M_CK_PDN_HWEN,
	PMIC_RG_BUCK_DCM_MODE,
	PMIC_RG_BUCK_TOP_CLK_HWEN_CON0_SET,
	PMIC_RG_BUCK_TOP_CLK_HWEN_CON0_CLR,
	PMIC_RG_INT_EN_VPROC11_OC,
	PMIC_RG_INT_EN_VPROC12_OC,
	PMIC_RG_INT_EN_VCORE_OC,
	PMIC_RG_INT_EN_VGPU_OC,
	PMIC_RG_INT_EN_VMODEM_OC,
	PMIC_RG_INT_EN_VDRAM1_OC,
	PMIC_RG_INT_EN_VS1_OC,
	PMIC_RG_INT_EN_VS2_OC,
	PMIC_RG_INT_EN_VPA_OC,
	PMIC_RG_INT_EN_VCORE_PREOC,
	PMIC_RG_BUCK_TOP_INT_EN_CON0_SET,
	PMIC_RG_BUCK_TOP_INT_EN_CON0_CLR,
	PMIC_RG_INT_MASK_VPROC11_OC,
	PMIC_RG_INT_MASK_VPROC12_OC,
	PMIC_RG_INT_MASK_VCORE_OC,
	PMIC_RG_INT_MASK_VGPU_OC,
	PMIC_RG_INT_MASK_VMODEM_OC,
	PMIC_RG_INT_MASK_VDRAM1_OC,
	PMIC_RG_INT_MASK_VS1_OC,
	PMIC_RG_INT_MASK_VS2_OC,
	PMIC_RG_INT_MASK_VPA_OC,
	PMIC_RG_INT_MASK_VCORE_PREOC,
	PMIC_RG_BUCK_TOP_INT_MASK_CON0_SET,
	PMIC_RG_BUCK_TOP_INT_MASK_CON0_CLR,
	PMIC_RG_INT_STATUS_VPROC11_OC,
	PMIC_RG_INT_STATUS_VPROC12_OC,
	PMIC_RG_INT_STATUS_VCORE_OC,
	PMIC_RG_INT_STATUS_VGPU_OC,
	PMIC_RG_INT_STATUS_VMODEM_OC,
	PMIC_RG_INT_STATUS_VDRAM1_OC,
	PMIC_RG_INT_STATUS_VS1_OC,
	PMIC_RG_INT_STATUS_VS2_OC,
	PMIC_RG_INT_STATUS_VPA_OC,
	PMIC_RG_INT_STATUS_VCORE_PREOC,
	PMIC_RG_INT_RAW_STATUS_VPROC11_OC,
	PMIC_RG_INT_RAW_STATUS_VPROC12_OC,
	PMIC_RG_INT_RAW_STATUS_VCORE_OC,
	PMIC_RG_INT_RAW_STATUS_VGPU_OC,
	PMIC_RG_INT_RAW_STATUS_VMODEM_OC,
	PMIC_RG_INT_RAW_STATUS_VDRAM1_OC,
	PMIC_RG_INT_RAW_STATUS_VS1_OC,
	PMIC_RG_INT_RAW_STATUS_VS2_OC,
	PMIC_RG_INT_RAW_STATUS_VPA_OC,
	PMIC_RG_INT_RAW_STATUS_VCORE_PREOC,
	PMIC_RG_BUCK_STB_MAX,
	PMIC_RG_BUCK_LP_PROT_DISABLE,
	PMIC_RG_BUCK_VSLEEP_SRC0,
	PMIC_RG_BUCK_VSLEEP_SRC1,
	PMIC_RG_BUCK_R2R_SRC0,
	PMIC_RG_BUCK_R2R_SRC1,
	PMIC_RG_BUCK_LP_SEQ_COUNT,
	PMIC_RG_BUCK_ON_SEQ_COUNT,
	PMIC_RG_BUCK_MINFREQ_LATENCY_MAX,
	PMIC_RG_BUCK_MINFREQ_DURATION_MAX,
	PMIC_RG_BUCK_VPROC11_OC_SDN_STATUS,
	PMIC_RG_BUCK_VPROC12_OC_SDN_STATUS,
	PMIC_RG_BUCK_VCORE_OC_SDN_STATUS,
	PMIC_RG_BUCK_VGPU_OC_SDN_STATUS,
	PMIC_RG_BUCK_VMODEM_OC_SDN_STATUS,
	PMIC_RG_BUCK_VDRAM1_OC_SDN_STATUS,
	PMIC_RG_BUCK_VS1_OC_SDN_STATUS,
	PMIC_RG_BUCK_VS2_OC_SDN_STATUS,
	PMIC_RG_BUCK_VPA_OC_SDN_STATUS,
	PMIC_RG_BUCK_K_RST_DONE,
	PMIC_RG_BUCK_K_MAP_SEL,
	PMIC_RG_BUCK_K_ONCE_EN,
	PMIC_RG_BUCK_K_ONCE,
	PMIC_RG_BUCK_K_START_MANUAL,
	PMIC_RG_BUCK_K_SRC_SEL,
	PMIC_RG_BUCK_K_AUTO_EN,
	PMIC_RG_BUCK_K_INV,
	PMIC_RG_BUCK_K_CK_EN,
	PMIC_BUCK_K_RESULT,
	PMIC_BUCK_K_DONE,
	PMIC_BUCK_K_CONTROL,
	PMIC_DA_SMPS_OSC_CAL,
	PMIC_RG_BUCK_K_BUCK_CK_CNT,
	PMIC_BUCK_VPROC11_WDTDBG_VOSEL,
	PMIC_BUCK_VPROC12_WDTDBG_VOSEL,
	PMIC_BUCK_VCORE_WDTDBG_VOSEL,
	PMIC_BUCK_VGPU_WDTDBG_VOSEL,
	PMIC_BUCK_VMODEM_WDTDBG_VOSEL,
	PMIC_BUCK_VDRAM1_WDTDBG_VOSEL,
	PMIC_BUCK_VS1_WDTDBG_VOSEL,
	PMIC_BUCK_VS2_WDTDBG_VOSEL,
	PMIC_BUCK_VPA_WDTDBG_VOSEL,
	PMIC_BUCK_TOP_ELR_LEN,
	PMIC_RG_BUCK_VPROC11_OC_SDN_EN,
	PMIC_RG_BUCK_VPROC12_OC_SDN_EN,
	PMIC_RG_BUCK_VCORE_OC_SDN_EN,
	PMIC_RG_BUCK_VGPU_OC_SDN_EN,
	PMIC_RG_BUCK_VMODEM_OC_SDN_EN,
	PMIC_RG_BUCK_VDRAM1_OC_SDN_EN,
	PMIC_RG_BUCK_VS1_OC_SDN_EN,
	PMIC_RG_BUCK_VS2_OC_SDN_EN,
	PMIC_RG_BUCK_VPA_OC_SDN_EN,
	PMIC_RG_BUCK_OC_SDN_EN_SEL,
	PMIC_RG_BUCK_K_CONTROL_SMPS,
	PMIC_RG_BUCK_VPROC11_VOSEL_LIMIT_SEL,
	PMIC_RG_BUCK_VPROC12_VOSEL_LIMIT_SEL,
	PMIC_RG_BUCK_VCORE_VOSEL_LIMIT_SEL,
	PMIC_RG_BUCK_VGPU_VOSEL_LIMIT_SEL,
	PMIC_RG_BUCK_VMODEM_VOSEL_LIMIT_SEL,
	PMIC_RG_BUCK_VDRAM1_VOSEL_LIMIT_SEL,
	PMIC_RG_BUCK_VS1_VOSEL_LIMIT_SEL,
	PMIC_RG_BUCK_VS2_VOSEL_LIMIT_SEL,
	PMIC_RG_BUCK_VPA_VOSEL_LIMIT_SEL,
	PMIC_RG_BUCK_VDRAM1_VOSEL_LP3,
	PMIC_BUCK_VPROC11_ANA_ID,
	PMIC_BUCK_VPROC11_DIG_ID,
	PMIC_BUCK_VPROC11_ANA_MINOR_REV,
	PMIC_BUCK_VPROC11_ANA_MAJOR_REV,
	PMIC_BUCK_VPROC11_DIG_MINOR_REV,
	PMIC_BUCK_VPROC11_DIG_MAJOR_REV,
	PMIC_BUCK_VPROC11_DSN_CBS,
	PMIC_BUCK_VPROC11_DSN_BIX,
	PMIC_BUCK_VPROC11_DSN_ESP,
	PMIC_BUCK_VPROC11_DSN_FPI_SSHUB,
	PMIC_BUCK_VPROC11_DSN_FPI_TRACKING,
	PMIC_BUCK_VPROC11_DSN_FPI_PREOC,
	PMIC_BUCK_VPROC11_DSN_FPI_VOTER,
	PMIC_BUCK_VPROC11_DSN_FPI_ULTRASONIC,
	PMIC_BUCK_VPROC11_DSN_FPI_DLC,
	PMIC_BUCK_VPROC11_DSN_FPI_TRAP,
	PMIC_RG_BUCK_VPROC11_EN,
	PMIC_RG_BUCK_VPROC11_LP,
	PMIC_RG_BUCK_VPROC11_VOSEL_SLEEP,
	PMIC_RG_BUCK_VPROC11_SFCHG_FRATE,
	PMIC_RG_BUCK_VPROC11_SFCHG_FEN,
	PMIC_RG_BUCK_VPROC11_SFCHG_RRATE,
	PMIC_RG_BUCK_VPROC11_SFCHG_REN,
	PMIC_RG_BUCK_VPROC11_DVS_EN_TD,
	PMIC_RG_BUCK_VPROC11_DVS_EN_CTRL,
	PMIC_RG_BUCK_VPROC11_DVS_EN_ONCE,
	PMIC_RG_BUCK_VPROC11_DVS_DOWN_TD,
	PMIC_RG_BUCK_VPROC11_DVS_DOWN_CTRL,
	PMIC_RG_BUCK_VPROC11_DVS_DOWN_ONCE,
	PMIC_RG_BUCK_VPROC11_SW_OP_EN,
	PMIC_RG_BUCK_VPROC11_HW0_OP_EN,
	PMIC_RG_BUCK_VPROC11_HW1_OP_EN,
	PMIC_RG_BUCK_VPROC11_HW2_OP_EN,
	PMIC_RG_BUCK_VPROC11_OP_EN_SET,
	PMIC_RG_BUCK_VPROC11_OP_EN_CLR,
	PMIC_RG_BUCK_VPROC11_HW0_OP_CFG,
	PMIC_RG_BUCK_VPROC11_HW1_OP_CFG,
	PMIC_RG_BUCK_VPROC11_HW2_OP_CFG,
	PMIC_RG_BUCK_VPROC11_ON_OP,
	PMIC_RG_BUCK_VPROC11_LP_OP,
	PMIC_RG_BUCK_VPROC11_OP_CFG_SET,
	PMIC_RG_BUCK_VPROC11_OP_CFG_CLR,
	PMIC_RG_BUCK_VPROC11_OC_DEG_EN,
	PMIC_RG_BUCK_VPROC11_OC_WND,
	PMIC_RG_BUCK_VPROC11_OC_THD,
	PMIC_DA_VPROC11_VOSEL,
	PMIC_DA_VPROC11_VOSEL_GRAY,
	PMIC_DA_VPROC11_EN,
	PMIC_DA_VPROC11_STB,
	PMIC_DA_VPROC11_LOOP_SEL,
	PMIC_DA_VPROC11_R2R_PDN,
	PMIC_DA_VPROC11_DVS_EN,
	PMIC_DA_VPROC11_DVS_DOWN,
	PMIC_DA_VPROC11_SSH,
	PMIC_DA_VPROC11_MINFREQ_DISCHARGE,
	PMIC_RG_BUCK_VPROC11_OC_FLAG_CLR_SEL,
	PMIC_RG_BUCK_VPROC11_OSC_SEL_DIS,
	PMIC_RG_BUCK_VPROC11_CK_SW_MODE,
	PMIC_RG_BUCK_VPROC11_CK_SW_EN,
	PMIC_BUCK_VPROC11_ELR_LEN,
	PMIC_RG_BUCK_VPROC11_VOSEL,
	PMIC_BUCK_VPROC12_ANA_ID,
	PMIC_BUCK_VPROC12_DIG_ID,
	PMIC_BUCK_VPROC12_ANA_MINOR_REV,
	PMIC_BUCK_VPROC12_ANA_MAJOR_REV,
	PMIC_BUCK_VPROC12_DIG_MINOR_REV,
	PMIC_BUCK_VPROC12_DIG_MAJOR_REV,
	PMIC_BUCK_VPROC12_DSN_CBS,
	PMIC_BUCK_VPROC12_DSN_BIX,
	PMIC_BUCK_VPROC12_DSN_ESP,
	PMIC_BUCK_VPROC12_DSN_FPI_SSHUB,
	PMIC_BUCK_VPROC12_DSN_FPI_TRACKING,
	PMIC_BUCK_VPROC12_DSN_FPI_PREOC,
	PMIC_BUCK_VPROC12_DSN_FPI_VOTER,
	PMIC_BUCK_VPROC12_DSN_FPI_ULTRASONIC,
	PMIC_BUCK_VPROC12_DSN_FPI_DLC,
	PMIC_BUCK_VPROC12_DSN_FPI_TRAP,
	PMIC_RG_BUCK_VPROC12_EN,
	PMIC_RG_BUCK_VPROC12_LP,
	PMIC_RG_BUCK_VPROC12_VOSEL_SLEEP,
	PMIC_RG_BUCK_VPROC12_SFCHG_FRATE,
	PMIC_RG_BUCK_VPROC12_SFCHG_FEN,
	PMIC_RG_BUCK_VPROC12_SFCHG_RRATE,
	PMIC_RG_BUCK_VPROC12_SFCHG_REN,
	PMIC_RG_BUCK_VPROC12_DVS_EN_TD,
	PMIC_RG_BUCK_VPROC12_DVS_EN_CTRL,
	PMIC_RG_BUCK_VPROC12_DVS_EN_ONCE,
	PMIC_RG_BUCK_VPROC12_DVS_DOWN_TD,
	PMIC_RG_BUCK_VPROC12_DVS_DOWN_CTRL,
	PMIC_RG_BUCK_VPROC12_DVS_DOWN_ONCE,
	PMIC_RG_BUCK_VPROC12_SW_OP_EN,
	PMIC_RG_BUCK_VPROC12_HW0_OP_EN,
	PMIC_RG_BUCK_VPROC12_HW1_OP_EN,
	PMIC_RG_BUCK_VPROC12_HW2_OP_EN,
	PMIC_RG_BUCK_VPROC12_OP_EN_SET,
	PMIC_RG_BUCK_VPROC12_OP_EN_CLR,
	PMIC_RG_BUCK_VPROC12_HW0_OP_CFG,
	PMIC_RG_BUCK_VPROC12_HW1_OP_CFG,
	PMIC_RG_BUCK_VPROC12_HW2_OP_CFG,
	PMIC_RG_BUCK_VPROC12_ON_OP,
	PMIC_RG_BUCK_VPROC12_LP_OP,
	PMIC_RG_BUCK_VPROC12_OP_CFG_SET,
	PMIC_RG_BUCK_VPROC12_OP_CFG_CLR,
	PMIC_RG_BUCK_VPROC12_OC_DEG_EN,
	PMIC_RG_BUCK_VPROC12_OC_WND,
	PMIC_RG_BUCK_VPROC12_OC_THD,
	PMIC_DA_VPROC12_VOSEL,
	PMIC_DA_VPROC12_VOSEL_GRAY,
	PMIC_DA_VPROC12_EN,
	PMIC_DA_VPROC12_STB,
	PMIC_DA_VPROC12_LOOP_SEL,
	PMIC_DA_VPROC12_R2R_PDN,
	PMIC_DA_VPROC12_DVS_EN,
	PMIC_DA_VPROC12_DVS_DOWN,
	PMIC_DA_VPROC12_SSH,
	PMIC_DA_VPROC12_MINFREQ_DISCHARGE,
	PMIC_RG_BUCK_VPROC12_OC_FLAG_CLR_SEL,
	PMIC_RG_BUCK_VPROC12_OSC_SEL_DIS,
	PMIC_RG_BUCK_VPROC12_CK_SW_MODE,
	PMIC_RG_BUCK_VPROC12_CK_SW_EN,
	PMIC_BUCK_VPROC12_ELR_LEN,
	PMIC_RG_BUCK_VPROC12_VOSEL,
	PMIC_BUCK_VCORE_ANA_ID,
	PMIC_BUCK_VCORE_DIG_ID,
	PMIC_BUCK_VCORE_ANA_MINOR_REV,
	PMIC_BUCK_VCORE_ANA_MAJOR_REV,
	PMIC_BUCK_VCORE_DIG_MINOR_REV,
	PMIC_BUCK_VCORE_DIG_MAJOR_REV,
	PMIC_BUCK_VCORE_DSN_CBS,
	PMIC_BUCK_VCORE_DSN_BIX,
	PMIC_BUCK_VCORE_DSN_ESP,
	PMIC_BUCK_VCORE_DSN_FPI_SSHUB,
	PMIC_BUCK_VCORE_DSN_FPI_TRACKING,
	PMIC_BUCK_VCORE_DSN_FPI_PREOC,
	PMIC_BUCK_VCORE_DSN_FPI_VOTER,
	PMIC_BUCK_VCORE_DSN_FPI_ULTRASONIC,
	PMIC_BUCK_VCORE_DSN_FPI_DLC,
	PMIC_BUCK_VCORE_DSN_FPI_TRAP,
	PMIC_RG_BUCK_VCORE_EN,
	PMIC_RG_BUCK_VCORE_LP,
	PMIC_RG_BUCK_VCORE_VOSEL_SLEEP,
	PMIC_RG_BUCK_VCORE_SFCHG_FRATE,
	PMIC_RG_BUCK_VCORE_SFCHG_FEN,
	PMIC_RG_BUCK_VCORE_SFCHG_RRATE,
	PMIC_RG_BUCK_VCORE_SFCHG_REN,
	PMIC_RG_BUCK_VCORE_DVS_EN_TD,
	PMIC_RG_BUCK_VCORE_DVS_EN_CTRL,
	PMIC_RG_BUCK_VCORE_DVS_EN_ONCE,
	PMIC_RG_BUCK_VCORE_DVS_DOWN_TD,
	PMIC_RG_BUCK_VCORE_DVS_DOWN_CTRL,
	PMIC_RG_BUCK_VCORE_DVS_DOWN_ONCE,
	PMIC_RG_BUCK_VCORE_SW_OP_EN,
	PMIC_RG_BUCK_VCORE_HW0_OP_EN,
	PMIC_RG_BUCK_VCORE_HW1_OP_EN,
	PMIC_RG_BUCK_VCORE_HW2_OP_EN,
	PMIC_RG_BUCK_VCORE_OP_EN_SET,
	PMIC_RG_BUCK_VCORE_OP_EN_CLR,
	PMIC_RG_BUCK_VCORE_HW0_OP_CFG,
	PMIC_RG_BUCK_VCORE_HW1_OP_CFG,
	PMIC_RG_BUCK_VCORE_HW2_OP_CFG,
	PMIC_RG_BUCK_VCORE_ON_OP,
	PMIC_RG_BUCK_VCORE_LP_OP,
	PMIC_RG_BUCK_VCORE_OP_CFG_SET,
	PMIC_RG_BUCK_VCORE_OP_CFG_CLR,
	PMIC_RG_BUCK_VCORE_OC_DEG_EN,
	PMIC_RG_BUCK_VCORE_OC_WND,
	PMIC_RG_BUCK_VCORE_OC_THD,
	PMIC_DA_VCORE_VOSEL,
	PMIC_DA_VCORE_VOSEL_GRAY,
	PMIC_DA_VCORE_EN,
	PMIC_DA_VCORE_STB,
	PMIC_DA_VCORE_LOOP_SEL,
	PMIC_DA_VCORE_R2R_PDN,
	PMIC_DA_VCORE_DVS_EN,
	PMIC_DA_VCORE_DVS_DOWN,
	PMIC_DA_VCORE_SSH,
	PMIC_DA_VCORE_MINFREQ_DISCHARGE,
	PMIC_RG_BUCK_VCORE_OC_FLAG_CLR_SEL,
	PMIC_RG_BUCK_VCORE_OSC_SEL_DIS,
	PMIC_RG_BUCK_VCORE_CK_SW_MODE,
	PMIC_RG_BUCK_VCORE_CK_SW_EN,
	PMIC_RG_BUCK_VCORE_SSHUB_EN,
	PMIC_RG_BUCK_VCORE_SSHUB_SLEEP_VOSEL_EN,
	PMIC_RG_BUCK_VCORE_SSHUB_VOSEL,
	PMIC_RG_BUCK_VCORE_SSHUB_VOSEL_SLEEP,
	PMIC_BUCK_VCORE_ELR_LEN,
	PMIC_RG_BUCK_VCORE_VOSEL,
	PMIC_BUCK_VGPU_ANA_ID,
	PMIC_BUCK_VGPU_DIG_ID,
	PMIC_BUCK_VGPU_ANA_MINOR_REV,
	PMIC_BUCK_VGPU_ANA_MAJOR_REV,
	PMIC_BUCK_VGPU_DIG_MINOR_REV,
	PMIC_BUCK_VGPU_DIG_MAJOR_REV,
	PMIC_BUCK_VGPU_DSN_CBS,
	PMIC_BUCK_VGPU_DSN_BIX,
	PMIC_BUCK_VGPU_DSN_ESP,
	PMIC_BUCK_VGPU_DSN_FPI_SSHUB,
	PMIC_BUCK_VGPU_DSN_FPI_TRACKING,
	PMIC_BUCK_VGPU_DSN_FPI_PREOC,
	PMIC_BUCK_VGPU_DSN_FPI_VOTER,
	PMIC_BUCK_VGPU_DSN_FPI_ULTRASONIC,
	PMIC_BUCK_VGPU_DSN_FPI_DLC,
	PMIC_BUCK_VGPU_DSN_FPI_TRAP,
	PMIC_RG_BUCK_VGPU_EN,
	PMIC_RG_BUCK_VGPU_LP,
	PMIC_RG_BUCK_VGPU_VOSEL_SLEEP,
	PMIC_RG_BUCK_VGPU_SFCHG_FRATE,
	PMIC_RG_BUCK_VGPU_SFCHG_FEN,
	PMIC_RG_BUCK_VGPU_SFCHG_RRATE,
	PMIC_RG_BUCK_VGPU_SFCHG_REN,
	PMIC_RG_BUCK_VGPU_DVS_EN_TD,
	PMIC_RG_BUCK_VGPU_DVS_EN_CTRL,
	PMIC_RG_BUCK_VGPU_DVS_EN_ONCE,
	PMIC_RG_BUCK_VGPU_DVS_DOWN_TD,
	PMIC_RG_BUCK_VGPU_DVS_DOWN_CTRL,
	PMIC_RG_BUCK_VGPU_DVS_DOWN_ONCE,
	PMIC_RG_BUCK_VGPU_SW_OP_EN,
	PMIC_RG_BUCK_VGPU_HW0_OP_EN,
	PMIC_RG_BUCK_VGPU_HW1_OP_EN,
	PMIC_RG_BUCK_VGPU_HW2_OP_EN,
	PMIC_RG_BUCK_VGPU_OP_EN_SET,
	PMIC_RG_BUCK_VGPU_OP_EN_CLR,
	PMIC_RG_BUCK_VGPU_HW0_OP_CFG,
	PMIC_RG_BUCK_VGPU_HW1_OP_CFG,
	PMIC_RG_BUCK_VGPU_HW2_OP_CFG,
	PMIC_RG_BUCK_VGPU_ON_OP,
	PMIC_RG_BUCK_VGPU_LP_OP,
	PMIC_RG_BUCK_VGPU_OP_CFG_SET,
	PMIC_RG_BUCK_VGPU_OP_CFG_CLR,
	PMIC_RG_BUCK_VGPU_OC_DEG_EN,
	PMIC_RG_BUCK_VGPU_OC_WND,
	PMIC_RG_BUCK_VGPU_OC_THD,
	PMIC_DA_VGPU_VOSEL,
	PMIC_DA_VGPU_VOSEL_GRAY,
	PMIC_DA_VGPU_EN,
	PMIC_DA_VGPU_STB,
	PMIC_DA_VGPU_LOOP_SEL,
	PMIC_DA_VGPU_R2R_PDN,
	PMIC_DA_VGPU_DVS_EN,
	PMIC_DA_VGPU_DVS_DOWN,
	PMIC_DA_VGPU_SSH,
	PMIC_DA_VGPU_MINFREQ_DISCHARGE,
	PMIC_RG_BUCK_VGPU_OC_FLAG_CLR_SEL,
	PMIC_RG_BUCK_VGPU_OSC_SEL_DIS,
	PMIC_RG_BUCK_VGPU_CK_SW_MODE,
	PMIC_RG_BUCK_VGPU_CK_SW_EN,
	PMIC_BUCK_VGPU_ELR_LEN,
	PMIC_RG_BUCK_VGPU_VOSEL,
	PMIC_BUCK_VMODEM_ANA_ID,
	PMIC_BUCK_VMODEM_DIG_ID,
	PMIC_BUCK_VMODEM_ANA_MINOR_REV,
	PMIC_BUCK_VMODEM_ANA_MAJOR_REV,
	PMIC_BUCK_VMODEM_DIG_MINOR_REV,
	PMIC_BUCK_VMODEM_DIG_MAJOR_REV,
	PMIC_BUCK_VMODEM_DSN_CBS,
	PMIC_BUCK_VMODEM_DSN_BIX,
	PMIC_BUCK_VMODEM_DSN_ESP,
	PMIC_BUCK_VMODEM_DSN_FPI_SSHUB,
	PMIC_BUCK_VMODEM_DSN_FPI_TRACKING,
	PMIC_BUCK_VMODEM_DSN_FPI_PREOC,
	PMIC_BUCK_VMODEM_DSN_FPI_VOTER,
	PMIC_BUCK_VMODEM_DSN_FPI_ULTRASONIC,
	PMIC_BUCK_VMODEM_DSN_FPI_DLC,
	PMIC_BUCK_VMODEM_DSN_FPI_TRAP,
	PMIC_RG_BUCK_VMODEM_EN,
	PMIC_RG_BUCK_VMODEM_LP,
	PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP,
	PMIC_RG_BUCK_VMODEM_SFCHG_FRATE,
	PMIC_RG_BUCK_VMODEM_SFCHG_FEN,
	PMIC_RG_BUCK_VMODEM_SFCHG_RRATE,
	PMIC_RG_BUCK_VMODEM_SFCHG_REN,
	PMIC_RG_BUCK_VMODEM_DVS_EN_TD,
	PMIC_RG_BUCK_VMODEM_DVS_EN_CTRL,
	PMIC_RG_BUCK_VMODEM_DVS_EN_ONCE,
	PMIC_RG_BUCK_VMODEM_DVS_DOWN_TD,
	PMIC_RG_BUCK_VMODEM_DVS_DOWN_CTRL,
	PMIC_RG_BUCK_VMODEM_DVS_DOWN_ONCE,
	PMIC_RG_BUCK_VMODEM_SW_OP_EN,
	PMIC_RG_BUCK_VMODEM_HW0_OP_EN,
	PMIC_RG_BUCK_VMODEM_HW1_OP_EN,
	PMIC_RG_BUCK_VMODEM_HW2_OP_EN,
	PMIC_RG_BUCK_VMODEM_OP_EN_SET,
	PMIC_RG_BUCK_VMODEM_OP_EN_CLR,
	PMIC_RG_BUCK_VMODEM_HW0_OP_CFG,
	PMIC_RG_BUCK_VMODEM_HW1_OP_CFG,
	PMIC_RG_BUCK_VMODEM_HW2_OP_CFG,
	PMIC_RG_BUCK_VMODEM_ON_OP,
	PMIC_RG_BUCK_VMODEM_LP_OP,
	PMIC_RG_BUCK_VMODEM_OP_CFG_SET,
	PMIC_RG_BUCK_VMODEM_OP_CFG_CLR,
	PMIC_RG_BUCK_VMODEM_OC_DEG_EN,
	PMIC_RG_BUCK_VMODEM_OC_WND,
	PMIC_RG_BUCK_VMODEM_OC_THD,
	PMIC_DA_VMODEM_VOSEL,
	PMIC_DA_VMODEM_VOSEL_GRAY,
	PMIC_DA_VMODEM_EN,
	PMIC_DA_VMODEM_STB,
	PMIC_DA_VMODEM_LOOP_SEL,
	PMIC_DA_VMODEM_R2R_PDN,
	PMIC_DA_VMODEM_DVS_EN,
	PMIC_DA_VMODEM_DVS_DOWN,
	PMIC_DA_VMODEM_SSH,
	PMIC_DA_VMODEM_MINFREQ_DISCHARGE,
	PMIC_RG_BUCK_VMODEM_OC_FLAG_CLR_SEL,
	PMIC_RG_BUCK_VMODEM_OSC_SEL_DIS,
	PMIC_RG_BUCK_VMODEM_CK_SW_MODE,
	PMIC_RG_BUCK_VMODEM_CK_SW_EN,
	PMIC_BUCK_VMODEM_ELR_LEN,
	PMIC_RG_BUCK_VMODEM_VOSEL,
	PMIC_BUCK_VDRAM1_ANA_ID,
	PMIC_BUCK_VDRAM1_DIG_ID,
	PMIC_BUCK_VDRAM1_ANA_MINOR_REV,
	PMIC_BUCK_VDRAM1_ANA_MAJOR_REV,
	PMIC_BUCK_VDRAM1_DIG_MINOR_REV,
	PMIC_BUCK_VDRAM1_DIG_MAJOR_REV,
	PMIC_BUCK_VDRAM1_DSN_CBS,
	PMIC_BUCK_VDRAM1_DSN_BIX,
	PMIC_BUCK_VDRAM1_DSN_ESP,
	PMIC_BUCK_VDRAM1_DSN_FPI_SSHUB,
	PMIC_BUCK_VDRAM1_DSN_FPI_TRACKING,
	PMIC_BUCK_VDRAM1_DSN_FPI_PREOC,
	PMIC_BUCK_VDRAM1_DSN_FPI_VOTER,
	PMIC_BUCK_VDRAM1_DSN_FPI_ULTRASONIC,
	PMIC_BUCK_VDRAM1_DSN_FPI_DLC,
	PMIC_BUCK_VDRAM1_DSN_FPI_TRAP,
	PMIC_RG_BUCK_VDRAM1_EN,
	PMIC_RG_BUCK_VDRAM1_LP,
	PMIC_RG_BUCK_VDRAM1_VOSEL_SLEEP,
	PMIC_RG_BUCK_VDRAM1_SFCHG_FRATE,
	PMIC_RG_BUCK_VDRAM1_SFCHG_FEN,
	PMIC_RG_BUCK_VDRAM1_SFCHG_RRATE,
	PMIC_RG_BUCK_VDRAM1_SFCHG_REN,
	PMIC_RG_BUCK_VDRAM1_DVS_EN_TD,
	PMIC_RG_BUCK_VDRAM1_DVS_EN_CTRL,
	PMIC_RG_BUCK_VDRAM1_DVS_EN_ONCE,
	PMIC_RG_BUCK_VDRAM1_DVS_DOWN_TD,
	PMIC_RG_BUCK_VDRAM1_DVS_DOWN_CTRL,
	PMIC_RG_BUCK_VDRAM1_DVS_DOWN_ONCE,
	PMIC_RG_BUCK_VDRAM1_SW_OP_EN,
	PMIC_RG_BUCK_VDRAM1_HW0_OP_EN,
	PMIC_RG_BUCK_VDRAM1_HW1_OP_EN,
	PMIC_RG_BUCK_VDRAM1_HW2_OP_EN,
	PMIC_RG_BUCK_VDRAM1_OP_EN_SET,
	PMIC_RG_BUCK_VDRAM1_OP_EN_CLR,
	PMIC_RG_BUCK_VDRAM1_HW0_OP_CFG,
	PMIC_RG_BUCK_VDRAM1_HW1_OP_CFG,
	PMIC_RG_BUCK_VDRAM1_HW2_OP_CFG,
	PMIC_RG_BUCK_VDRAM1_ON_OP,
	PMIC_RG_BUCK_VDRAM1_LP_OP,
	PMIC_RG_BUCK_VDRAM1_OP_CFG_SET,
	PMIC_RG_BUCK_VDRAM1_OP_CFG_CLR,
	PMIC_RG_BUCK_VDRAM1_OC_DEG_EN,
	PMIC_RG_BUCK_VDRAM1_OC_WND,
	PMIC_RG_BUCK_VDRAM1_OC_THD,
	PMIC_DA_VDRAM1_VOSEL,
	PMIC_DA_VDRAM1_VOSEL_GRAY,
	PMIC_DA_VDRAM1_EN,
	PMIC_DA_VDRAM1_STB,
	PMIC_DA_VDRAM1_LOOP_SEL,
	PMIC_DA_VDRAM1_R2R_PDN,
	PMIC_DA_VDRAM1_DVS_EN,
	PMIC_DA_VDRAM1_DVS_DOWN,
	PMIC_DA_VDRAM1_SSH,
	PMIC_DA_VDRAM1_MINFREQ_DISCHARGE,
	PMIC_RG_BUCK_VDRAM1_OC_FLAG_CLR_SEL,
	PMIC_RG_BUCK_VDRAM1_OSC_SEL_DIS,
	PMIC_RG_BUCK_VDRAM1_CK_SW_MODE,
	PMIC_RG_BUCK_VDRAM1_CK_SW_EN,
	PMIC_BUCK_VDRAM1_ELR_LEN,
	PMIC_RG_BUCK_VDRAM1_VOSEL,
	PMIC_BUCK_VS1_ANA_ID,
	PMIC_BUCK_VS1_DIG_ID,
	PMIC_BUCK_VS1_ANA_MINOR_REV,
	PMIC_BUCK_VS1_ANA_MAJOR_REV,
	PMIC_BUCK_VS1_DIG_MINOR_REV,
	PMIC_BUCK_VS1_DIG_MAJOR_REV,
	PMIC_BUCK_VS1_DSN_CBS,
	PMIC_BUCK_VS1_DSN_BIX,
	PMIC_BUCK_VS1_DSN_ESP,
	PMIC_BUCK_VS1_DSN_FPI_SSHUB,
	PMIC_BUCK_VS1_DSN_FPI_TRACKING,
	PMIC_BUCK_VS1_DSN_FPI_PREOC,
	PMIC_BUCK_VS1_DSN_FPI_VOTER,
	PMIC_BUCK_VS1_DSN_FPI_ULTRASONIC,
	PMIC_BUCK_VS1_DSN_FPI_DLC,
	PMIC_BUCK_VS1_DSN_FPI_TRAP,
	PMIC_RG_BUCK_VS1_EN,
	PMIC_RG_BUCK_VS1_LP,
	PMIC_RG_BUCK_VS1_VOSEL_SLEEP,
	PMIC_RG_BUCK_VS1_SFCHG_FRATE,
	PMIC_RG_BUCK_VS1_SFCHG_FEN,
	PMIC_RG_BUCK_VS1_SFCHG_RRATE,
	PMIC_RG_BUCK_VS1_SFCHG_REN,
	PMIC_RG_BUCK_VS1_DVS_EN_TD,
	PMIC_RG_BUCK_VS1_DVS_EN_CTRL,
	PMIC_RG_BUCK_VS1_DVS_EN_ONCE,
	PMIC_RG_BUCK_VS1_DVS_DOWN_TD,
	PMIC_RG_BUCK_VS1_DVS_DOWN_CTRL,
	PMIC_RG_BUCK_VS1_DVS_DOWN_ONCE,
	PMIC_RG_BUCK_VS1_SW_OP_EN,
	PMIC_RG_BUCK_VS1_HW0_OP_EN,
	PMIC_RG_BUCK_VS1_HW1_OP_EN,
	PMIC_RG_BUCK_VS1_HW2_OP_EN,
	PMIC_RG_BUCK_VS1_OP_EN_SET,
	PMIC_RG_BUCK_VS1_OP_EN_CLR,
	PMIC_RG_BUCK_VS1_HW0_OP_CFG,
	PMIC_RG_BUCK_VS1_HW1_OP_CFG,
	PMIC_RG_BUCK_VS1_HW2_OP_CFG,
	PMIC_RG_BUCK_VS1_ON_OP,
	PMIC_RG_BUCK_VS1_LP_OP,
	PMIC_RG_BUCK_VS1_OP_CFG_SET,
	PMIC_RG_BUCK_VS1_OP_CFG_CLR,
	PMIC_RG_BUCK_VS1_OC_DEG_EN,
	PMIC_RG_BUCK_VS1_OC_WND,
	PMIC_RG_BUCK_VS1_OC_THD,
	PMIC_DA_VS1_VOSEL,
	PMIC_DA_VS1_VOSEL_GRAY,
	PMIC_DA_VS1_EN,
	PMIC_DA_VS1_STB,
	PMIC_DA_VS1_LOOP_SEL,
	PMIC_DA_VS1_R2R_PDN,
	PMIC_DA_VS1_DVS_EN,
	PMIC_DA_VS1_DVS_DOWN,
	PMIC_DA_VS1_SSH,
	PMIC_DA_VS1_MINFREQ_DISCHARGE,
	PMIC_RG_BUCK_VS1_OC_FLAG_CLR_SEL,
	PMIC_RG_BUCK_VS1_OSC_SEL_DIS,
	PMIC_RG_BUCK_VS1_CK_SW_MODE,
	PMIC_RG_BUCK_VS1_CK_SW_EN,
	PMIC_RG_BUCK_VS1_VOTER_EN,
	PMIC_RG_BUCK_VS1_VOTER_EN_SET,
	PMIC_RG_BUCK_VS1_VOTER_EN_CLR,
	PMIC_RG_BUCK_VS1_VOTER_VOSEL,
	PMIC_BUCK_VS1_ELR_LEN,
	PMIC_RG_BUCK_VS1_VOSEL,
	PMIC_BUCK_VS2_ANA_ID,
	PMIC_BUCK_VS2_DIG_ID,
	PMIC_BUCK_VS2_ANA_MINOR_REV,
	PMIC_BUCK_VS2_ANA_MAJOR_REV,
	PMIC_BUCK_VS2_DIG_MINOR_REV,
	PMIC_BUCK_VS2_DIG_MAJOR_REV,
	PMIC_BUCK_VS2_DSN_CBS,
	PMIC_BUCK_VS2_DSN_BIX,
	PMIC_BUCK_VS2_DSN_ESP,
	PMIC_BUCK_VS2_DSN_FPI_SSHUB,
	PMIC_BUCK_VS2_DSN_FPI_TRACKING,
	PMIC_BUCK_VS2_DSN_FPI_PREOC,
	PMIC_BUCK_VS2_DSN_FPI_VOTER,
	PMIC_BUCK_VS2_DSN_FPI_ULTRASONIC,
	PMIC_BUCK_VS2_DSN_FPI_DLC,
	PMIC_BUCK_VS2_DSN_FPI_TRAP,
	PMIC_RG_BUCK_VS2_EN,
	PMIC_RG_BUCK_VS2_LP,
	PMIC_RG_BUCK_VS2_VOSEL_SLEEP,
	PMIC_RG_BUCK_VS2_SFCHG_FRATE,
	PMIC_RG_BUCK_VS2_SFCHG_FEN,
	PMIC_RG_BUCK_VS2_SFCHG_RRATE,
	PMIC_RG_BUCK_VS2_SFCHG_REN,
	PMIC_RG_BUCK_VS2_DVS_EN_TD,
	PMIC_RG_BUCK_VS2_DVS_EN_CTRL,
	PMIC_RG_BUCK_VS2_DVS_EN_ONCE,
	PMIC_RG_BUCK_VS2_DVS_DOWN_TD,
	PMIC_RG_BUCK_VS2_DVS_DOWN_CTRL,
	PMIC_RG_BUCK_VS2_DVS_DOWN_ONCE,
	PMIC_RG_BUCK_VS2_SW_OP_EN,
	PMIC_RG_BUCK_VS2_HW0_OP_EN,
	PMIC_RG_BUCK_VS2_HW1_OP_EN,
	PMIC_RG_BUCK_VS2_HW2_OP_EN,
	PMIC_RG_BUCK_VS2_OP_EN_SET,
	PMIC_RG_BUCK_VS2_OP_EN_CLR,
	PMIC_RG_BUCK_VS2_HW0_OP_CFG,
	PMIC_RG_BUCK_VS2_HW1_OP_CFG,
	PMIC_RG_BUCK_VS2_HW2_OP_CFG,
	PMIC_RG_BUCK_VS2_ON_OP,
	PMIC_RG_BUCK_VS2_LP_OP,
	PMIC_RG_BUCK_VS2_OP_CFG_SET,
	PMIC_RG_BUCK_VS2_OP_CFG_CLR,
	PMIC_RG_BUCK_VS2_OC_DEG_EN,
	PMIC_RG_BUCK_VS2_OC_WND,
	PMIC_RG_BUCK_VS2_OC_THD,
	PMIC_DA_VS2_VOSEL,
	PMIC_DA_VS2_VOSEL_GRAY,
	PMIC_DA_VS2_EN,
	PMIC_DA_VS2_STB,
	PMIC_DA_VS2_LOOP_SEL,
	PMIC_DA_VS2_R2R_PDN,
	PMIC_DA_VS2_DVS_EN,
	PMIC_DA_VS2_DVS_DOWN,
	PMIC_DA_VS2_SSH,
	PMIC_DA_VS2_MINFREQ_DISCHARGE,
	PMIC_RG_BUCK_VS2_OC_FLAG_CLR_SEL,
	PMIC_RG_BUCK_VS2_OSC_SEL_DIS,
	PMIC_RG_BUCK_VS2_CK_SW_MODE,
	PMIC_RG_BUCK_VS2_CK_SW_EN,
	PMIC_RG_BUCK_VS2_VOTER_EN,
	PMIC_RG_BUCK_VS2_VOTER_EN_SET,
	PMIC_RG_BUCK_VS2_VOTER_EN_CLR,
	PMIC_RG_BUCK_VS2_VOTER_VOSEL,
	PMIC_BUCK_VS2_ELR_LEN,
	PMIC_RG_BUCK_VS2_VOSEL,
	PMIC_BUCK_VPA_ANA_ID,
	PMIC_BUCK_VPA_DIG_ID,
	PMIC_BUCK_VPA_ANA_MINOR_REV,
	PMIC_BUCK_VPA_ANA_MAJOR_REV,
	PMIC_BUCK_VPA_DIG_MINOR_REV,
	PMIC_BUCK_VPA_DIG_MAJOR_REV,
	PMIC_BUCK_VPA_DSN_CBS,
	PMIC_BUCK_VPA_DSN_BIX,
	PMIC_BUCK_VPA_DSN_ESP,
	PMIC_BUCK_VPA_DSN_FPI_SSHUB,
	PMIC_BUCK_VPA_DSN_FPI_TRACKING,
	PMIC_BUCK_VPA_DSN_FPI_PREOC,
	PMIC_BUCK_VPA_DSN_FPI_VOTER,
	PMIC_BUCK_VPA_DSN_FPI_ULTRASONIC,
	PMIC_BUCK_VPA_DSN_FPI_DLC,
	PMIC_BUCK_VPA_DSN_FPI_TRAP,
	PMIC_RG_BUCK_VPA_EN,
	PMIC_RG_BUCK_VPA_VOSEL,
	PMIC_RG_BUCK_VPA_SFCHG_FRATE,
	PMIC_RG_BUCK_VPA_SFCHG_FEN,
	PMIC_RG_BUCK_VPA_SFCHG_RRATE,
	PMIC_RG_BUCK_VPA_SFCHG_REN,
	PMIC_RG_BUCK_VPA_DVS_TRANST_TD,
	PMIC_RG_BUCK_VPA_DVS_TRANST_CTRL,
	PMIC_RG_BUCK_VPA_DVS_TRANST_ONCE,
	PMIC_RG_BUCK_VPA_DVS_BW_TD,
	PMIC_RG_BUCK_VPA_DVS_BW_CTRL,
	PMIC_RG_BUCK_VPA_DVS_BW_ONCE,
	PMIC_RG_BUCK_VPA_OC_DEG_EN,
	PMIC_RG_BUCK_VPA_OC_WND,
	PMIC_RG_BUCK_VPA_OC_THD,
	PMIC_DA_VPA_VOSEL,
	PMIC_DA_VPA_VOSEL_GRAY,
	PMIC_DA_VPA_EN,
	PMIC_DA_VPA_STB,
	PMIC_DA_VPA_DVS_TRANST,
	PMIC_DA_VPA_DVS_BW,
	PMIC_RG_BUCK_VPA_OC_FLAG_CLR_SEL,
	PMIC_RG_BUCK_VPA_OSC_SEL_DIS,
	PMIC_RG_BUCK_VPA_CK_SW_MODE,
	PMIC_RG_BUCK_VPA_CK_SW_EN,
	PMIC_RG_BUCK_VPA_VOSEL_DLC011,
	PMIC_RG_BUCK_VPA_VOSEL_DLC111,
	PMIC_RG_BUCK_VPA_VOSEL_DLC001,
	PMIC_RG_BUCK_VPA_DLC_MAP_EN,
	PMIC_RG_BUCK_VPA_DLC,
	PMIC_DA_VPA_DLC,
	PMIC_RG_BUCK_VPA_MSFG_EN,
	PMIC_RG_BUCK_VPA_MSFG_RDELTA2GO,
	PMIC_RG_BUCK_VPA_MSFG_FDELTA2GO,
	PMIC_RG_BUCK_VPA_MSFG_RRATE0,
	PMIC_RG_BUCK_VPA_MSFG_RRATE1,
	PMIC_RG_BUCK_VPA_MSFG_RRATE2,
	PMIC_RG_BUCK_VPA_MSFG_RRATE3,
	PMIC_RG_BUCK_VPA_MSFG_RRATE4,
	PMIC_RG_BUCK_VPA_MSFG_RRATE5,
	PMIC_RG_BUCK_VPA_MSFG_RTHD0,
	PMIC_RG_BUCK_VPA_MSFG_RTHD1,
	PMIC_RG_BUCK_VPA_MSFG_RTHD2,
	PMIC_RG_BUCK_VPA_MSFG_RTHD3,
	PMIC_RG_BUCK_VPA_MSFG_RTHD4,
	PMIC_RG_BUCK_VPA_MSFG_FRATE0,
	PMIC_RG_BUCK_VPA_MSFG_FRATE1,
	PMIC_RG_BUCK_VPA_MSFG_FRATE2,
	PMIC_RG_BUCK_VPA_MSFG_FRATE3,
	PMIC_RG_BUCK_VPA_MSFG_FRATE4,
	PMIC_RG_BUCK_VPA_MSFG_FRATE5,
	PMIC_RG_BUCK_VPA_MSFG_FTHD0,
	PMIC_RG_BUCK_VPA_MSFG_FTHD1,
	PMIC_RG_BUCK_VPA_MSFG_FTHD2,
	PMIC_RG_BUCK_VPA_MSFG_FTHD3,
	PMIC_RG_BUCK_VPA_MSFG_FTHD4,
	PMIC_BUCK_ANA0_ANA_ID,
	PMIC_BUCK_ANA0_DIG_ID,
	PMIC_BUCK_ANA0_ANA_MINOR_REV,
	PMIC_BUCK_ANA0_ANA_MAJOR_REV,
	PMIC_BUCK_ANA0_DIG_MINOR_REV,
	PMIC_BUCK_ANA0_DIG_MAJOR_REV,
	PMIC_BUCK_ANA0_DSN_CBS,
	PMIC_BUCK_ANA0_DSN_BIX,
	PMIC_BUCK_ANA0_DSN_ESP,
	PMIC_BUCK_ANA0_DSN_FPI,
	PMIC_RG_SMPS_TESTMODE_B,
	PMIC_RG_VPA_BURSTH,
	PMIC_RG_VPA_BURSTL,
	PMIC_RG_SMPS_IVGD_DET,
	PMIC_RG_AUTOK_RST,
	PMIC_RG_VMODEM_SLEEP_VOLTAGE,
	PMIC_RG_VPROC11_FPWM,
	PMIC_RG_VPROC12_FPWM,
	PMIC_RG_VPROC11_NDIS_EN,
	PMIC_RG_VPROC12_NDIS_EN,
	PMIC_RG_VPROC11_FCOT,
	PMIC_RG_VPROC12_FCOT,
	PMIC_RG_VPROC11VPROC12_TMDL,
	PMIC_RG_VPROC11_TBDIS,
	PMIC_RG_VPROC12_TBDIS,
	PMIC_RG_VPROC11_VDIFFOFF,
	PMIC_RG_VPROC12_VDIFFOFF,
	PMIC_RG_VPROC11_RCOMP0,
	PMIC_RG_VPROC11_RCOMP1,
	PMIC_RG_VPROC11_CCOMP0,
	PMIC_RG_VPROC11_CCOMP1,
	PMIC_RG_VPROC11_RAMP_SLP,
	PMIC_RG_VPROC12_RCOMP0,
	PMIC_RG_VPROC12_RCOMP1,
	PMIC_RG_VPROC12_CCOMP0,
	PMIC_RG_VPROC12_CCOMP1,
	PMIC_RG_VPROC12_RAMP_SLP,
	PMIC_RG_VPROC11_RCS,
	PMIC_RG_VPROC12_RCS,
	PMIC_RG_VPROC11_RCB,
	PMIC_RG_VPROC12_RCB,
	PMIC_RG_VPROC11_TB_WIDTH,
	PMIC_RG_VPROC12_TB_WIDTH,
	PMIC_RG_VPROC11_UG_SR,
	PMIC_RG_VPROC11_LG_SR,
	PMIC_RG_VPROC12_UG_SR,
	PMIC_RG_VPROC12_LG_SR,
	PMIC_RG_VPROC11_PFM_TON,
	PMIC_RG_VPROC12_PFM_TON,
	PMIC_RGS_VPROC11_OC_STATUS,
	PMIC_RGS_VPROC12_OC_STATUS,
	PMIC_RGS_VPROC11_PREOC_STATUS,
	PMIC_RGS_VPROC11_DIG_MON,
	PMIC_RGS_VPROC11_ENPWM_STATUS,
	PMIC_RGS_VPROC12_ENPWM_STATUS,
	PMIC_RGS_VPROC12_DIG_MON,
	PMIC_RG_VPROC11_TRAN_BST,
	PMIC_RG_VPROC12_TRAN_BST,
	PMIC_RG_VPROC11_COTRAMP_SLP,
	PMIC_RG_VPROC12_COTRAMP_SLP,
	PMIC_RG_VPROC11_SLEEP_TIME,
	PMIC_RG_VPROC12_SLEEP_TIME,
	PMIC_RG_VPROC11_VREFTB,
	PMIC_RG_VPROC12_VREFTB,
	PMIC_RG_VPROC11_FUGON,
	PMIC_RG_VPROC12_FUGON,
	PMIC_RG_VPROC11_FLGON,
	PMIC_RG_VPROC12_FLGON,
	PMIC_RG_VPROC11_RSV,
	PMIC_RG_VPROC12_RSV,
	PMIC_RG_VPROC11VPROC12_DISAUTOK,
	PMIC_RGS_VPROC11_PFM_FLAG,
	PMIC_RGS_VPROC12_PFM_FLAG,
	PMIC_RG_VPROC12_NONAUDIBLE_EN,
	PMIC_RG_VPROC11_NONAUDIBLE_EN,
	PMIC_RG_VPROC11_CSP,
	PMIC_RG_VPROC11_CSN,
	PMIC_RG_VPROC12_CSP,
	PMIC_RG_VPROC12_CSN,
	PMIC_RG_VPROC11_SONIC_PFM_TON,
	PMIC_RG_VPROC12_SONIC_PFM_TON,
	PMIC_RG_VPROC11_RETENTION_EN,
	PMIC_RG_VPROC12_RETENTION_EN,
	PMIC_RGS_VPROC11VPROC12_TRIMOK_STATUS,
	PMIC_RG_VCORE_FPWM,
	PMIC_RG_VGPU_FPWM,
	PMIC_RG_VCORE_NDIS_EN,
	PMIC_RG_VGPU_NDIS_EN,
	PMIC_RG_VCORE_FCOT,
	PMIC_RG_VGPU_FCOT,
	PMIC_RG_VCOREVGPU_TMDL,
	PMIC_RG_VCORE_TBDIS,
	PMIC_RG_VGPU_TBDIS,
	PMIC_RG_VCORE_VDIFFOFF,
	PMIC_RG_VGPU_VDIFFOFF,
	PMIC_RG_VCORE_RCOMP0,
	PMIC_RG_VCORE_RCOMP1,
	PMIC_RG_VCORE_CCOMP0,
	PMIC_RG_VCORE_CCOMP1,
	PMIC_RG_VCORE_RAMP_SLP,
	PMIC_RG_VGPU_RCOMP0,
	PMIC_RG_VGPU_RCOMP1,
	PMIC_RG_VGPU_CCOMP0,
	PMIC_RG_VGPU_CCOMP1,
	PMIC_RG_VGPU_RAMP_SLP,
	PMIC_RG_VCORE_RCS,
	PMIC_RG_VGPU_RCS,
	PMIC_RG_VCORE_RCB,
	PMIC_RG_VGPU_RCB,
	PMIC_RG_VCORE_TB_WIDTH,
	PMIC_RG_VGPU_TB_WIDTH,
	PMIC_RG_VCORE_UG_SR,
	PMIC_RG_VCORE_LG_SR,
	PMIC_RG_VGPU_UG_SR,
	PMIC_RG_VGPU_LG_SR,
	PMIC_RG_VCORE_PFM_TON,
	PMIC_RG_VGPU_PFM_TON,
	PMIC_RGS_VCORE_OC_STATUS,
	PMIC_RGS_VGPU_OC_STATUS,
	PMIC_RGS_VCORE_PREOC_STATUS,
	PMIC_RGS_VCORE_DIG_MON,
	PMIC_RGS_VCORE_ENPWM_STATUS,
	PMIC_RGS_VGPU_ENPWM_STATUS,
	PMIC_RGS_VGPU_DIG_MON,
	PMIC_RG_VCORE_TRAN_BST,
	PMIC_RG_VGPU_TRAN_BST,
	PMIC_RG_VCORE_COTRAMP_SLP,
	PMIC_RG_VGPU_COTRAMP_SLP,
	PMIC_RG_VCORE_SLEEP_TIME,
	PMIC_RG_VGPU_SLEEP_TIME,
	PMIC_RG_VCORE_VREFTB,
	PMIC_RG_VGPU_VREFTB,
	PMIC_RG_VCORE_FUGON,
	PMIC_RG_VGPU_FUGON,
	PMIC_RG_VCORE_FLGON,
	PMIC_RG_VGPU_FLGON,
	PMIC_RG_VCORE_RSV,
	PMIC_RG_VGPU_RSV,
	PMIC_RG_VCOREVGPU_DISAUTOK,
	PMIC_RGS_VCORE_PFM_FLAG,
	PMIC_RGS_VGPU_PFM_FLAG,
	PMIC_RG_VGPU_NONAUDIBLE_EN,
	PMIC_RG_VCORE_NONAUDIBLE_EN,
	PMIC_RG_VCORE_CSP,
	PMIC_RG_VCORE_CSN,
	PMIC_RG_VGPU_CSP,
	PMIC_RG_VGPU_CSN,
	PMIC_RG_VCORE_SONIC_PFM_TON,
	PMIC_RG_VGPU_SONIC_PFM_TON,
	PMIC_RG_VCORE_RETENTION_EN,
	PMIC_RG_VGPU_RETENTION_EN,
	PMIC_RGS_VCOREVGPU_TRIMOK_STATUS,
	PMIC_BUCK_ANA0_ELR_LEN,
	PMIC_RG_VS1_TRIMH,
	PMIC_RG_VS2_TRIMH,
	PMIC_RG_VMODEM_TRIMH,
	PMIC_RG_VMODEM_VSLEEP_TRIM,
	PMIC_RG_VGPU_TRIMH,
	PMIC_RG_VCORE_TRIMH,
	PMIC_RG_VPROC11_TRIMH,
	PMIC_RG_VPROC12_TRIMH,
	PMIC_RG_VPA_TRIMH,
	PMIC_RG_VPA_TRIML,
	PMIC_RG_VPA_TRIM_REF,
	PMIC_RG_VDRAM1_TRIMH,
	PMIC_RG_VSRAM_PROC11_TRIMH,
	PMIC_RG_VSRAM_GPU_TRIMH,
	PMIC_RG_VSRAM_OTHERS_TRIMH,
	PMIC_RG_VOUTDET_EN,
	PMIC_RG_VSRAM_PROC12_TRIMH,
	PMIC_RG_VPROC11_ZC_TRIM,
	PMIC_RG_VPROC11_NLIM_TRIM,
	PMIC_RG_VPROC11_TON_TRIM,
	PMIC_RG_VPROC11_RPSI1_TRIM,
	PMIC_RG_VPROC11_PREOC_TRIM,
	PMIC_RG_VPROC11_CSPSLP_TRIM,
	PMIC_RG_VPROC11_CSNSLP_TRIM,
	PMIC_RG_VPROC12_ZC_TRIM,
	PMIC_RG_VPROC12_NLIM_TRIM,
	PMIC_RG_VPROC12_TON_TRIM,
	PMIC_RG_VPROC12_RPSI1_TRIM,
	PMIC_RG_VPROC12_CSPSLP_TRIM,
	PMIC_RG_VPROC12_CSNSLP_TRIM,
	PMIC_RG_VPROC11VPROC12_DISCONFIG20,
	PMIC_RG_VPROC11_LDO_AUTO_TRACK,
	PMIC_RG_VPROC12_LDO_AUTO_TRACK,
	PMIC_RG_VCORE_ZC_TRIM,
	PMIC_RG_VCORE_NLIM_TRIM,
	PMIC_RG_VCORE_TON_TRIM,
	PMIC_RG_VCORE_RPSI1_TRIM,
	PMIC_RG_VCORE_PREOC_TRIM,
	PMIC_RG_VCORE_CSPSLP_TRIM,
	PMIC_RG_VCORE_CSNSLP_TRIM,
	PMIC_RG_VGPU_ZC_TRIM,
	PMIC_RG_VGPU_NLIM_TRIM,
	PMIC_RG_VGPU_TON_TRIM,
	PMIC_RG_VGPU_RPSI1_TRIM,
	PMIC_RG_VGPU_CSPSLP_TRIM,
	PMIC_RG_VGPU_CSNSLP_TRIM,
	PMIC_RG_VCOREVGPU_DISCONFIG20,
	PMIC_RG_VCORE_LDO_AUTO_TRACK,
	PMIC_RG_VGPU_LDO_AUTO_TRACK,
	PMIC_BUCK_ANA1_ANA_ID,
	PMIC_BUCK_ANA1_DIG_ID,
	PMIC_BUCK_ANA1_ANA_MINOR_REV,
	PMIC_BUCK_ANA1_ANA_MAJOR_REV,
	PMIC_BUCK_ANA1_DIG_MINOR_REV,
	PMIC_BUCK_ANA1_DIG_MAJOR_REV,
	PMIC_BUCK_ANA1_DSN_CBS,
	PMIC_BUCK_ANA1_DSN_BIX,
	PMIC_BUCK_ANA1_DSN_ESP,
	PMIC_BUCK_ANA1_DSN_FPI,
	PMIC_RG_VMODEM_FCOT,
	PMIC_RG_VMODEM_RCOMP,
	PMIC_RG_VMODEM_TB_DIS,
	PMIC_RG_VMODEM_DISPG,
	PMIC_RG_VMODEM_FPWM,
	PMIC_RG_VMODEM_PFM_TON,
	PMIC_RG_VMODEM_PWMRAMP_SLP,
	PMIC_RG_VMODEM_COTRAMP_SLP,
	PMIC_RG_VMODEM_RCS,
	PMIC_RG_VMODEM_SLEEP_TIME,
	PMIC_RG_VMODEM_NLIM_GATING,
	PMIC_RG_VMODEM_VDIFF_OFF,
	PMIC_RG_VMODEM_VREFUP,
	PMIC_RG_VMODEM_TB_WIDTH,
	PMIC_RG_VMODEM_UG_SR,
	PMIC_RG_VMODEM_LG_SR,
	PMIC_RG_VMODEM_CCOMP,
	PMIC_RG_VMODEM_NDIS_EN,
	PMIC_RG_VMODEM_TMDL,
	PMIC_RG_VMODEM_RSV,
	PMIC_RG_VMODEM_FUGON,
	PMIC_RG_VMODEM_FLGON,
	PMIC_RG_VMODEM_VDIFFPFM_OFF,
	PMIC_RGS_VMODEM_OC_STATUS,
	PMIC_RGS_VMODEM_ENPWM_STATUS,
	PMIC_RG_VMODEM_DISAUTOK,
	PMIC_RGS_VMODEM_TRIMOK_STATUS,
	PMIC_RGS_VMODEM_DIG_MON,
	PMIC_RG_VMODEM_NONAUDIBLE_EN,
	PMIC_RGS_VMODEM_PFM_FLAG,
	PMIC_RG_VMODEM_CSP,
	PMIC_RG_VMODEM_CSN,
	PMIC_RG_VMODEM_SONIC_PFM_TON,
	PMIC_RG_VMODEM_RETENTION_EN,
	PMIC_RG_VDRAM1_FCOT,
	PMIC_RG_VDRAM1_RCOMP,
	PMIC_RG_VDRAM1_TB_DIS,
	PMIC_RG_VDRAM1_DISPG,
	PMIC_RG_VDRAM1_FPWM,
	PMIC_RG_VDRAM1_PFM_TON,
	PMIC_RG_VDRAM1_PWMRAMP_SLP,
	PMIC_RG_VDRAM1_COTRAMP_SLP,
	PMIC_RG_VDRAM1_RCS,
	PMIC_RG_VDRAM1_SLEEP_TIME,
	PMIC_RG_VDRAM1_NLIM_GATING,
	PMIC_RG_VDRAM1_VDIFF_OFF,
	PMIC_RG_VDRAM1_VREFUP,
	PMIC_RG_VDRAM1_TB_WIDTH,
	PMIC_RG_VDRAM1_UG_SR,
	PMIC_RG_VDRAM1_LG_SR,
	PMIC_RG_VDRAM1_CCOMP,
	PMIC_RG_VDRAM1_NDIS_EN,
	PMIC_RG_VDRAM1_TMDL,
	PMIC_RG_VDRAM1_RSV,
	PMIC_RG_VDRAM1_FUGON,
	PMIC_RG_VDRAM1_FLGON,
	PMIC_RG_VDRAM1_VDIFFPFM_OFF,
	PMIC_RGS_VDRAM1_OC_STATUS,
	PMIC_RGS_VDRAM1_ENPWM_STATUS,
	PMIC_RG_VDRAM1_DISAUTOK,
	PMIC_RGS_VDRAM1_TRIMOK_STATUS,
	PMIC_RGS_VDRAM1_DIG_MON,
	PMIC_RG_VDRAM1_NONAUDIBLE_EN,
	PMIC_RG_VDRAM1_CSP,
	PMIC_RG_VDRAM1_CSN,
	PMIC_RGS_VDRAM1_PFM_FLAG,
	PMIC_RG_VDRAM1_SONIC_PFM_TON,
	PMIC_RG_VDRAM1_RETENTION_EN,
	PMIC_RG_VS1_FCOT,
	PMIC_RG_VS1_RCOMP,
	PMIC_RG_VS1_TB_DIS,
	PMIC_RG_VS1_DISPG,
	PMIC_RG_VS1_FPWM,
	PMIC_RG_VS1_PFM_TON,
	PMIC_RG_VS1_PWMRAMP_SLP,
	PMIC_RG_VS1_COTRAMP_SLP,
	PMIC_RG_VS1_RCS,
	PMIC_RG_VS1_SLEEP_TIME,
	PMIC_RG_VS1_NLIM_GATING,
	PMIC_RG_VS1_VDIFF_OFF,
	PMIC_RG_VS1_VREFUP,
	PMIC_RG_VS1_TB_WIDTH,
	PMIC_RG_VS1_UG_SR,
	PMIC_RG_VS1_LG_SR,
	PMIC_RG_VS1_CCOMP,
	PMIC_RG_VS1_NDIS_EN,
	PMIC_RG_VS1_TMDL,
	PMIC_RG_VS1_RSV,
	PMIC_RG_VS1_FUGON,
	PMIC_RG_VS1_FLGON,
	PMIC_RG_VS1_VDIFFPFM_OFF,
	PMIC_RGS_VS1_OC_STATUS,
	PMIC_RGS_VS1_ENPWM_STATUS,
	PMIC_RG_VS1_DISAUTOK,
	PMIC_RGS_VS1_TRIMOK_STATUS,
	PMIC_RGS_VS1_DIG_MON,
	PMIC_RG_VS1_NONAUDIBLE_EN,
	PMIC_RG_VS1_CSP,
	PMIC_RG_VS1_CSN,
	PMIC_RGS_VS1_PFM_FLAG,
	PMIC_RG_VS1_SONIC_PFM_TON,
	PMIC_RG_VS1_RETENTION_EN,
	PMIC_RG_VS2_FCOT,
	PMIC_RG_VS2_RCOMP,
	PMIC_RG_VS2_TB_DIS,
	PMIC_RG_VS2_DISPG,
	PMIC_RG_VS2_FPWM,
	PMIC_RG_VS2_PFM_TON,
	PMIC_RG_VS2_PWMRAMP_SLP,
	PMIC_RG_VS2_COTRAMP_SLP,
	PMIC_RG_VS2_RCS,
	PMIC_RG_VS2_SLEEP_TIME,
	PMIC_RG_VS2_NLIM_GATING,
	PMIC_RG_VS2_VDIFF_OFF,
	PMIC_RG_VS2_VREFUP,
	PMIC_RG_VS2_TB_WIDTH,
	PMIC_RG_VS2_UG_SR,
	PMIC_RG_VS2_LG_SR,
	PMIC_RG_VS2_CCOMP,
	PMIC_RG_VS2_NDIS_EN,
	PMIC_RG_VS2_TMDL,
	PMIC_RG_VS2_RSV,
	PMIC_RG_VS2_FUGON,
	PMIC_RG_VS2_FLGON,
	PMIC_RG_VS2_VDIFFPFM_OFF,
	PMIC_RGS_VS2_OC_STATUS,
	PMIC_RGS_VS2_ENPWM_STATUS,
	PMIC_RG_VS2_DISAUTOK,
	PMIC_RGS_VS2_TRIMOK_STATUS,
	PMIC_RGS_VS2_DIG_MON,
	PMIC_RG_VS2_NONAUDIBLE_EN,
	PMIC_RG_VS2_CSP,
	PMIC_RG_VS2_CSN,
	PMIC_RGS_VS2_PFM_FLAG,
	PMIC_RG_VS2_SONIC_PFM_TON,
	PMIC_RG_VS2_RETENTION_EN,
	PMIC_RG_VPA_NDIS_EN,
	PMIC_RG_VPA_MODESET,
	PMIC_RG_VPA_CC,
	PMIC_RG_VPA_CSR,
	PMIC_RG_VPA_CSMIR,
	PMIC_RG_VPA_CSL,
	PMIC_RG_VPA_SLP,
	PMIC_RG_VPA_AZC_EN,
	PMIC_RG_VPA_CP_FWUPOFF,
	PMIC_RG_VPA_AZC_DELAY,
	PMIC_RG_VPA_RZSEL,
	PMIC_RG_VPA_HZP,
	PMIC_RG_VPA_BWEX_GAT,
	PMIC_RG_VPA_SLEW,
	PMIC_RG_VPA_SLEW_NMOS,
	PMIC_RG_VPA_MIN_ON,
	PMIC_RG_VPA_VBAT_DEL,
	PMIC_RGS_VPA_AZC_VOS_SEL,
	PMIC_RG_VPA_MIN_PK,
	PMIC_RG_VPA_RSV1,
	PMIC_RG_VPA_RSV2,
	PMIC_RGS_VPA_OC_STATUS,
	PMIC_RGS_VPA_AZC_ZX,
	PMIC_RGS_VPA_DIG_MON,
	PMIC_BUCK_ANA1_ELR_LEN,
	PMIC_RG_VMODEM_ZC_TRIM,
	PMIC_RG_VMODEM_NLIM_TRIM,
	PMIC_RG_VMODEM_TON_TRIM,
	PMIC_RG_VMODEM_RPSI_TRIM,
	PMIC_RG_VMODEM_CSNSLP_TRIM,
	PMIC_RG_VMODEM_CSPSLP_TRIM,
	PMIC_RG_VDRAM1_ZC_TRIM,
	PMIC_RG_VDRAM1_NLIM_TRIM,
	PMIC_RG_VDRAM1_TON_TRIM,
	PMIC_RG_VDRAM1_RPSI_TRIM,
	PMIC_RG_VDRAM1_CSNSLP_TRIM,
	PMIC_RG_VDRAM1_CSPSLP_TRIM,
	PMIC_RG_VS1_ZC_TRIM,
	PMIC_RG_VS1_NLIM_TRIM,
	PMIC_RG_VS1_TON_TRIM,
	PMIC_RG_VS1_RPSI_TRIM,
	PMIC_RG_VS1_CSNSLP_TRIM,
	PMIC_RG_VS1_CSPSLP_TRIM,
	PMIC_RG_VS2_ZC_TRIM,
	PMIC_RG_VS2_NLIM_TRIM,
	PMIC_RG_VS2_TON_TRIM,
	PMIC_RG_VS2_RPSI_TRIM,
	PMIC_RG_VS2_CSNSLP_TRIM,
	PMIC_RG_VS2_CSPSLP_TRIM,
	PMIC_RG_VPA_ZXREF,
	PMIC_RG_VPA_NLIM_SEL,
	PMIC_LDO_TOP_ANA_ID,
	PMIC_LDO_TOP_DIG_ID,
	PMIC_LDO_TOP_ANA_MINOR_REV,
	PMIC_LDO_TOP_ANA_MAJOR_REV,
	PMIC_LDO_TOP_DIG_MINOR_REV,
	PMIC_LDO_TOP_DIG_MAJOR_REV,
	PMIC_LDO_TOP_CBS,
	PMIC_LDO_TOP_BIX,
	PMIC_LDO_TOP_ESP,
	PMIC_LDO_TOP_FPI,
	PMIC_LDO_TOP_CLK_OFFSET,
	PMIC_LDO_TOP_RST_OFFSET,
	PMIC_LDO_TOP_INT_OFFSET,
	PMIC_LDO_TOP_INT_LEN,
	PMIC_RG_LDO_32K_CK_PDN,
	PMIC_RG_LDO_INTRP_CK_PDN,
	PMIC_RG_LDO_32K_CK_PDN_HWEN,
	PMIC_RG_LDO_INTRP_CK_PDN_HWEN,
	PMIC_RG_LDO_DCM_MODE,
	PMIC_RG_LDO_VFE28_CK_SW_MODE,
	PMIC_RG_LDO_VXO22_CK_SW_MODE,
	PMIC_RG_LDO_VRF18_CK_SW_MODE,
	PMIC_RG_LDO_VRF12_CK_SW_MODE,
	PMIC_RG_LDO_VEFUSE_CK_SW_MODE,
	PMIC_RG_LDO_VCN33_CK_SW_MODE,
	PMIC_RG_LDO_VCN28_CK_SW_MODE,
	PMIC_RG_LDO_VCN18_CK_SW_MODE,
	PMIC_RG_LDO_VCAMA1_CK_SW_MODE,
	PMIC_RG_LDO_VCAMA2_CK_SW_MODE,
	PMIC_RG_LDO_VCAMD_CK_SW_MODE,
	PMIC_RG_LDO_VCAMIO_CK_SW_MODE,
	PMIC_RG_LDO_VLDO28_CK_SW_MODE,
	PMIC_RG_LDO_VA12_CK_SW_MODE,
	PMIC_RG_LDO_VAUX18_CK_SW_MODE,
	PMIC_RG_LDO_VAUD28_CK_SW_MODE,
	PMIC_RG_LDO_VIO28_CK_SW_MODE,
	PMIC_RG_LDO_VIO18_CK_SW_MODE,
	PMIC_RG_LDO_VSRAM_PROC11_CK_SW_MODE,
	PMIC_RG_LDO_VSRAM_PROC11_OSC_SEL_DIS,
	PMIC_RG_LDO_VSRAM_PROC12_CK_SW_MODE,
	PMIC_RG_LDO_VSRAM_PROC12_OSC_SEL_DIS,
	PMIC_RG_LDO_VSRAM_OTHERS_CK_SW_MODE,
	PMIC_RG_LDO_VSRAM_OTHERS_OSC_SEL_DIS,
	PMIC_RG_LDO_VSRAM_GPU_CK_SW_MODE,
	PMIC_RG_LDO_VSRAM_GPU_OSC_SEL_DIS,
	PMIC_RG_LDO_VDRAM2_CK_SW_MODE,
	PMIC_RG_LDO_VMC_CK_SW_MODE,
	PMIC_RG_LDO_VMCH_CK_SW_MODE,
	PMIC_RG_LDO_VEMC_CK_SW_MODE,
	PMIC_RG_LDO_VSIM1_CK_SW_MODE,
	PMIC_RG_LDO_VSIM2_CK_SW_MODE,
	PMIC_RG_LDO_VIBR_CK_SW_MODE,
	PMIC_RG_LDO_VUSB_CK_SW_MODE,
	PMIC_RG_LDO_VBIF28_CK_SW_MODE,
	PMIC_RG_INT_EN_VFE28_OC,
	PMIC_RG_INT_EN_VXO22_OC,
	PMIC_RG_INT_EN_VRF18_OC,
	PMIC_RG_INT_EN_VRF12_OC,
	PMIC_RG_INT_EN_VEFUSE_OC,
	PMIC_RG_INT_EN_VCN33_OC,
	PMIC_RG_INT_EN_VCN28_OC,
	PMIC_RG_INT_EN_VCN18_OC,
	PMIC_RG_INT_EN_VCAMA1_OC,
	PMIC_RG_INT_EN_VCAMA2_OC,
	PMIC_RG_INT_EN_VCAMD_OC,
	PMIC_RG_INT_EN_VCAMIO_OC,
	PMIC_RG_INT_EN_VLDO28_OC,
	PMIC_RG_INT_EN_VA12_OC,
	PMIC_RG_INT_EN_VAUX18_OC,
	PMIC_RG_INT_EN_VAUD28_OC,
	PMIC_LDO_INT_CON0_SET,
	PMIC_LDO_INT_CON0_CLR,
	PMIC_RG_INT_EN_VIO28_OC,
	PMIC_RG_INT_EN_VIO18_OC,
	PMIC_RG_INT_EN_VSRAM_PROC11_OC,
	PMIC_RG_INT_EN_VSRAM_PROC12_OC,
	PMIC_RG_INT_EN_VSRAM_OTHERS_OC,
	PMIC_RG_INT_EN_VSRAM_GPU_OC,
	PMIC_RG_INT_EN_VDRAM2_OC,
	PMIC_RG_INT_EN_VMC_OC,
	PMIC_RG_INT_EN_VMCH_OC,
	PMIC_RG_INT_EN_VEMC_OC,
	PMIC_RG_INT_EN_VSIM1_OC,
	PMIC_RG_INT_EN_VSIM2_OC,
	PMIC_RG_INT_EN_VIBR_OC,
	PMIC_RG_INT_EN_VUSB_OC,
	PMIC_RG_INT_EN_VBIF28_OC,
	PMIC_LDO_INT_CON1_SET,
	PMIC_LDO_INT_CON1_CLR,
	PMIC_RG_INT_MASK_VFE28_OC,
	PMIC_RG_INT_MASK_VXO22_OC,
	PMIC_RG_INT_MASK_VRF18_OC,
	PMIC_RG_INT_MASK_VRF12_OC,
	PMIC_RG_INT_MASK_VEFUSE_OC,
	PMIC_RG_INT_MASK_VCN33_OC,
	PMIC_RG_INT_MASK_VCN28_OC,
	PMIC_RG_INT_MASK_VCN18_OC,
	PMIC_RG_INT_MASK_VCAMA1_OC,
	PMIC_RG_INT_MASK_VCAMA2_OC,
	PMIC_RG_INT_MASK_VCAMD_OC,
	PMIC_RG_INT_MASK_VCAMIO_OC,
	PMIC_RG_INT_MASK_VLDO28_OC,
	PMIC_RG_INT_MASK_VA12_OC,
	PMIC_RG_INT_MASK_VAUX18_OC,
	PMIC_RG_INT_MASK_VAUD28_OC,
	PMIC_LDO_INT_MASK_CON0_SET,
	PMIC_LDO_INT_MASK_CON0_CLR,
	PMIC_RG_INT_MASK_VIO28_OC,
	PMIC_RG_INT_MASK_VIO18_OC,
	PMIC_RG_INT_MASK_VSRAM_PROC11_OC,
	PMIC_RG_INT_MASK_VSRAM_PROC12_OC,
	PMIC_RG_INT_MASK_VSRAM_OTHERS_OC,
	PMIC_RG_INT_MASK_VSRAM_GPU_OC,
	PMIC_RG_INT_MASK_VDRAM2_OC,
	PMIC_RG_INT_MASK_VMC_OC,
	PMIC_RG_INT_MASK_VMCH_OC,
	PMIC_RG_INT_MASK_VEMC_OC,
	PMIC_RG_INT_MASK_VSIM1_OC,
	PMIC_RG_INT_MASK_VSIM2_OC,
	PMIC_RG_INT_MASK_VIBR_OC,
	PMIC_RG_INT_MASK_VUSB_OC,
	PMIC_RG_INT_MASK_VBIF28_OC,
	PMIC_LDO_INT_MASK_CON1_SET,
	PMIC_LDO_INT_MASK_CON1_CLR,
	PMIC_RG_INT_STATUS_VFE28_OC,
	PMIC_RG_INT_STATUS_VXO22_OC,
	PMIC_RG_INT_STATUS_VRF18_OC,
	PMIC_RG_INT_STATUS_VRF12_OC,
	PMIC_RG_INT_STATUS_VEFUSE_OC,
	PMIC_RG_INT_STATUS_VCN33_OC,
	PMIC_RG_INT_STATUS_VCN28_OC,
	PMIC_RG_INT_STATUS_VCN18_OC,
	PMIC_RG_INT_STATUS_VCAMA1_OC,
	PMIC_RG_INT_STATUS_VCAMA2_OC,
	PMIC_RG_INT_STATUS_VCAMD_OC,
	PMIC_RG_INT_STATUS_VCAMIO_OC,
	PMIC_RG_INT_STATUS_VLDO28_OC,
	PMIC_RG_INT_STATUS_VA12_OC,
	PMIC_RG_INT_STATUS_VAUX18_OC,
	PMIC_RG_INT_STATUS_VAUD28_OC,
	PMIC_RG_INT_STATUS_VIO28_OC,
	PMIC_RG_INT_STATUS_VIO18_OC,
	PMIC_RG_INT_STATUS_VSRAM_PROC11_OC,
	PMIC_RG_INT_STATUS_VSRAM_PROC12_OC,
	PMIC_RG_INT_STATUS_VSRAM_OTHERS_OC,
	PMIC_RG_INT_STATUS_VSRAM_GPU_OC,
	PMIC_RG_INT_STATUS_VDRAM2_OC,
	PMIC_RG_INT_STATUS_VMC_OC,
	PMIC_RG_INT_STATUS_VMCH_OC,
	PMIC_RG_INT_STATUS_VEMC_OC,
	PMIC_RG_INT_STATUS_VSIM1_OC,
	PMIC_RG_INT_STATUS_VSIM2_OC,
	PMIC_RG_INT_STATUS_VIBR_OC,
	PMIC_RG_INT_STATUS_VUSB_OC,
	PMIC_RG_INT_STATUS_VBIF28_OC,
	PMIC_RG_INT_RAW_STATUS_VFE28_OC,
	PMIC_RG_INT_RAW_STATUS_VXO22_OC,
	PMIC_RG_INT_RAW_STATUS_VRF18_OC,
	PMIC_RG_INT_RAW_STATUS_VRF12_OC,
	PMIC_RG_INT_RAW_STATUS_VEFUSE_OC,
	PMIC_RG_INT_RAW_STATUS_VCN33_OC,
	PMIC_RG_INT_RAW_STATUS_VCN28_OC,
	PMIC_RG_INT_RAW_STATUS_VCN18_OC,
	PMIC_RG_INT_RAW_STATUS_VCAMA1_OC,
	PMIC_RG_INT_RAW_STATUS_VCAMA2_OC,
	PMIC_RG_INT_RAW_STATUS_VCAMD_OC,
	PMIC_RG_INT_RAW_STATUS_VCAMIO_OC,
	PMIC_RG_INT_RAW_STATUS_VLDO28_OC,
	PMIC_RG_INT_RAW_STATUS_VA12_OC,
	PMIC_RG_INT_RAW_STATUS_VAUX18_OC,
	PMIC_RG_INT_RAW_STATUS_VAUD28_OC,
	PMIC_RG_INT_RAW_STATUS_VIO28_OC,
	PMIC_RG_INT_RAW_STATUS_VIO18_OC,
	PMIC_RG_INT_RAW_STATUS_VSRAM_PROC11_OC,
	PMIC_RG_INT_RAW_STATUS_VSRAM_PROC12_OC,
	PMIC_RG_INT_RAW_STATUS_VSRAM_OTHERS_OC,
	PMIC_RG_INT_RAW_STATUS_VSRAM_GPU_OC,
	PMIC_RG_INT_RAW_STATUS_VDRAM2_OC,
	PMIC_RG_INT_RAW_STATUS_VMC_OC,
	PMIC_RG_INT_RAW_STATUS_VMCH_OC,
	PMIC_RG_INT_RAW_STATUS_VEMC_OC,
	PMIC_RG_INT_RAW_STATUS_VSIM1_OC,
	PMIC_RG_INT_RAW_STATUS_VSIM2_OC,
	PMIC_RG_INT_RAW_STATUS_VIBR_OC,
	PMIC_RG_INT_RAW_STATUS_VUSB_OC,
	PMIC_RG_INT_RAW_STATUS_VBIF28_OC,
	PMIC_RG_LDO_MON_FLAG_SEL,
	PMIC_RG_LDO_INT_FLAG_EN,
	PMIC_RG_LDO_MON_GRP_SEL,
	PMIC_RG_LDO_WDT_MODE,
	PMIC_RG_LDO_TOP_RSV0,
	PMIC_RG_LDO_TOP_RSV1,
	PMIC_LDO_DEGTD_SEL,
	PMIC_RG_LDO_LP_PROT_DISABLE,
	PMIC_RG_LDO_DUMMY_LOAD_GATED_DIS,
	PMIC_LDO_GON0_ANA_ID,
	PMIC_LDO_GON0_DIG_ID,
	PMIC_LDO_GON0_ANA_MINOR_REV,
	PMIC_LDO_GON0_ANA_MAJOR_REV,
	PMIC_LDO_GON0_DIG_MINOR_REV,
	PMIC_LDO_GON0_DIG_MAJOR_REV,
	PMIC_LDO_GON0_DSN_CBS,
	PMIC_LDO_GON0_DSN_BIX,
	PMIC_LDO_GON0_DSN_ESP,
	PMIC_LDO_GON0_DSN_FPI,
	PMIC_RG_LDO_VXO22_EN,
	PMIC_RG_LDO_VXO22_LP,
	PMIC_RG_LDO_VXO22_SW_OP_EN,
	PMIC_RG_LDO_VXO22_HW0_OP_EN,
	PMIC_RG_LDO_VXO22_HW1_OP_EN,
	PMIC_RG_LDO_VXO22_HW2_OP_EN,
	PMIC_RG_LDO_VXO22_OP_EN_SET,
	PMIC_RG_LDO_VXO22_OP_EN_CLR,
	PMIC_RG_LDO_VXO22_HW0_OP_CFG,
	PMIC_RG_LDO_VXO22_HW1_OP_CFG,
	PMIC_RG_LDO_VXO22_HW2_OP_CFG,
	PMIC_RG_LDO_VXO22_OP_CFG_SET,
	PMIC_RG_LDO_VXO22_OP_CFG_CLR,
	PMIC_DA_VXO22_MODE,
	PMIC_RG_LDO_VXO22_STBTD,
	PMIC_DA_VXO22_STB,
	PMIC_DA_VXO22_EN,
	PMIC_RG_LDO_VXO22_OCFB_EN,
	PMIC_DA_VXO22_OCFB_EN,
	PMIC_RG_LDO_VXO22_DUMMY_LOAD,
	PMIC_DA_VXO22_DUMMY_LOAD,
	PMIC_RG_LDO_VA12_EN,
	PMIC_RG_LDO_VA12_LP,
	PMIC_RG_LDO_VA12_SW_OP_EN,
	PMIC_RG_LDO_VA12_HW0_OP_EN,
	PMIC_RG_LDO_VA12_HW1_OP_EN,
	PMIC_RG_LDO_VA12_HW2_OP_EN,
	PMIC_RG_LDO_VA12_OP_EN_SET,
	PMIC_RG_LDO_VA12_OP_EN_CLR,
	PMIC_RG_LDO_VA12_HW0_OP_CFG,
	PMIC_RG_LDO_VA12_HW1_OP_CFG,
	PMIC_RG_LDO_VA12_HW2_OP_CFG,
	PMIC_RG_LDO_VA12_OP_CFG_SET,
	PMIC_RG_LDO_VA12_OP_CFG_CLR,
	PMIC_DA_VA12_MODE,
	PMIC_RG_LDO_VA12_STBTD,
	PMIC_DA_VA12_STB,
	PMIC_DA_VA12_EN,
	PMIC_RG_LDO_VA12_AUXADC_PWDB_EN,
	PMIC_RG_LDO_VA12_OCFB_EN,
	PMIC_DA_VA12_OCFB_EN,
	PMIC_RG_LDO_VA12_DUMMY_LOAD,
	PMIC_DA_VA12_DUMMY_LOAD,
	PMIC_RG_LDO_VAUX18_EN,
	PMIC_RG_LDO_VAUX18_LP,
	PMIC_RG_LDO_VAUX18_SW_OP_EN,
	PMIC_RG_LDO_VAUX18_HW0_OP_EN,
	PMIC_RG_LDO_VAUX18_HW1_OP_EN,
	PMIC_RG_LDO_VAUX18_HW2_OP_EN,
	PMIC_RG_LDO_VAUX18_OP_EN_SET,
	PMIC_RG_LDO_VAUX18_OP_EN_CLR,
	PMIC_RG_LDO_VAUX18_HW0_OP_CFG,
	PMIC_RG_LDO_VAUX18_HW1_OP_CFG,
	PMIC_RG_LDO_VAUX18_HW2_OP_CFG,
	PMIC_RG_LDO_VAUX18_OP_CFG_SET,
	PMIC_RG_LDO_VAUX18_OP_CFG_CLR,
	PMIC_DA_VAUX18_MODE,
	PMIC_RG_LDO_VAUX18_STBTD,
	PMIC_DA_VAUX18_STB,
	PMIC_DA_VAUX18_EN,
	PMIC_RG_LDO_VAUX18_AUXADC_PWDB_EN,
	PMIC_RG_LDO_VAUX18_OCFB_EN,
	PMIC_DA_VAUX18_OCFB_EN,
	PMIC_RG_LDO_VAUX18_DUMMY_LOAD,
	PMIC_DA_VAUX18_DUMMY_LOAD,
	PMIC_RG_LDO_VAUD28_EN,
	PMIC_RG_LDO_VAUD28_LP,
	PMIC_RG_LDO_VAUD28_SW_OP_EN,
	PMIC_RG_LDO_VAUD28_HW0_OP_EN,
	PMIC_RG_LDO_VAUD28_HW1_OP_EN,
	PMIC_RG_LDO_VAUD28_HW2_OP_EN,
	PMIC_RG_LDO_VAUD28_OP_EN_SET,
	PMIC_RG_LDO_VAUD28_OP_EN_CLR,
	PMIC_RG_LDO_VAUD28_HW0_OP_CFG,
	PMIC_RG_LDO_VAUD28_HW1_OP_CFG,
	PMIC_RG_LDO_VAUD28_HW2_OP_CFG,
	PMIC_RG_LDO_VAUD28_OP_CFG_SET,
	PMIC_RG_LDO_VAUD28_OP_CFG_CLR,
	PMIC_DA_VAUD28_MODE,
	PMIC_RG_LDO_VAUD28_STBTD,
	PMIC_DA_VAUD28_STB,
	PMIC_DA_VAUD28_EN,
	PMIC_RG_LDO_VAUD28_AUXADC_PWDB_EN,
	PMIC_RG_LDO_VAUD28_OCFB_EN,
	PMIC_DA_VAUD28_OCFB_EN,
	PMIC_RG_LDO_VAUD28_DUMMY_LOAD,
	PMIC_DA_VAUD28_DUMMY_LOAD,
	PMIC_RG_LDO_VIO28_EN,
	PMIC_RG_LDO_VIO28_LP,
	PMIC_RG_LDO_VIO28_SW_OP_EN,
	PMIC_RG_LDO_VIO28_HW0_OP_EN,
	PMIC_RG_LDO_VIO28_HW1_OP_EN,
	PMIC_RG_LDO_VIO28_HW2_OP_EN,
	PMIC_RG_LDO_VIO28_OP_EN_SET,
	PMIC_RG_LDO_VIO28_OP_EN_CLR,
	PMIC_RG_LDO_VIO28_HW0_OP_CFG,
	PMIC_RG_LDO_VIO28_HW1_OP_CFG,
	PMIC_RG_LDO_VIO28_HW2_OP_CFG,
	PMIC_RG_LDO_VIO28_OP_CFG_SET,
	PMIC_RG_LDO_VIO28_OP_CFG_CLR,
	PMIC_DA_VIO28_MODE,
	PMIC_RG_LDO_VIO28_STBTD,
	PMIC_DA_VIO28_STB,
	PMIC_DA_VIO28_EN,
	PMIC_RG_LDO_VIO28_OCFB_EN,
	PMIC_DA_VIO28_OCFB_EN,
	PMIC_RG_LDO_VIO28_DUMMY_LOAD,
	PMIC_DA_VIO28_DUMMY_LOAD,
	PMIC_RG_LDO_VIO18_EN,
	PMIC_RG_LDO_VIO18_LP,
	PMIC_RG_LDO_VIO18_SW_OP_EN,
	PMIC_RG_LDO_VIO18_HW0_OP_EN,
	PMIC_RG_LDO_VIO18_HW1_OP_EN,
	PMIC_RG_LDO_VIO18_HW2_OP_EN,
	PMIC_RG_LDO_VIO18_OP_EN_SET,
	PMIC_RG_LDO_VIO18_OP_EN_CLR,
	PMIC_RG_LDO_VIO18_HW0_OP_CFG,
	PMIC_RG_LDO_VIO18_HW1_OP_CFG,
	PMIC_RG_LDO_VIO18_HW2_OP_CFG,
	PMIC_RG_LDO_VIO18_OP_CFG_SET,
	PMIC_RG_LDO_VIO18_OP_CFG_CLR,
	PMIC_DA_VIO18_MODE,
	PMIC_RG_LDO_VIO18_STBTD,
	PMIC_DA_VIO18_STB,
	PMIC_DA_VIO18_EN,
	PMIC_RG_LDO_VIO18_OCFB_EN,
	PMIC_DA_VIO18_OCFB_EN,
	PMIC_RG_LDO_VIO18_DUMMY_LOAD,
	PMIC_DA_VIO18_DUMMY_LOAD,
	PMIC_LDO_GON1_ANA_ID,
	PMIC_LDO_GON1_DIG_ID,
	PMIC_LDO_GON1_ANA_MINOR_REV,
	PMIC_LDO_GON1_ANA_MAJOR_REV,
	PMIC_LDO_GON1_DIG_MINOR_REV,
	PMIC_LDO_GON1_DIG_MAJOR_REV,
	PMIC_LDO_GON1_DSN_CBS,
	PMIC_LDO_GON1_DSN_BIX,
	PMIC_LDO_GON1_DSN_ESP,
	PMIC_LDO_GON1_DSN_FPI,
	PMIC_RG_LDO_VDRAM2_EN,
	PMIC_RG_LDO_VDRAM2_LP,
	PMIC_RG_LDO_VDRAM2_SW_OP_EN,
	PMIC_RG_LDO_VDRAM2_HW0_OP_EN,
	PMIC_RG_LDO_VDRAM2_HW1_OP_EN,
	PMIC_RG_LDO_VDRAM2_HW2_OP_EN,
	PMIC_RG_LDO_VDRAM2_OP_EN_SET,
	PMIC_RG_LDO_VDRAM2_OP_EN_CLR,
	PMIC_RG_LDO_VDRAM2_HW0_OP_CFG,
	PMIC_RG_LDO_VDRAM2_HW1_OP_CFG,
	PMIC_RG_LDO_VDRAM2_HW2_OP_CFG,
	PMIC_RG_LDO_VDRAM2_OP_CFG_SET,
	PMIC_RG_LDO_VDRAM2_OP_CFG_CLR,
	PMIC_DA_VDRAM2_MODE,
	PMIC_RG_LDO_VDRAM2_STBTD,
	PMIC_DA_VDRAM2_STB,
	PMIC_DA_VDRAM2_EN,
	PMIC_RG_LDO_VDRAM2_OCFB_EN,
	PMIC_DA_VDRAM2_OCFB_EN,
	PMIC_RG_LDO_VDRAM2_DUMMY_LOAD,
	PMIC_DA_VDRAM2_DUMMY_LOAD,
	PMIC_RG_LDO_VEMC_EN,
	PMIC_RG_LDO_VEMC_LP,
	PMIC_RG_LDO_VEMC_SW_OP_EN,
	PMIC_RG_LDO_VEMC_HW0_OP_EN,
	PMIC_RG_LDO_VEMC_HW1_OP_EN,
	PMIC_RG_LDO_VEMC_HW2_OP_EN,
	PMIC_RG_LDO_VEMC_OP_EN_SET,
	PMIC_RG_LDO_VEMC_OP_EN_CLR,
	PMIC_RG_LDO_VEMC_HW0_OP_CFG,
	PMIC_RG_LDO_VEMC_HW1_OP_CFG,
	PMIC_RG_LDO_VEMC_HW2_OP_CFG,
	PMIC_RG_LDO_VEMC_OP_CFG_SET,
	PMIC_RG_LDO_VEMC_OP_CFG_CLR,
	PMIC_DA_VEMC_MODE,
	PMIC_RG_LDO_VEMC_STBTD,
	PMIC_DA_VEMC_STB,
	PMIC_DA_VEMC_EN,
	PMIC_RG_LDO_VEMC_OCFB_EN,
	PMIC_DA_VEMC_OCFB_EN,
	PMIC_RG_LDO_VEMC_DUMMY_LOAD,
	PMIC_DA_VEMC_DUMMY_LOAD,
	PMIC_RG_LDO_VUSB_EN_0,
	PMIC_RG_LDO_VUSB_LP,
	PMIC_RG_LDO_VUSB_SW_OP_EN,
	PMIC_RG_LDO_VUSB_HW0_OP_EN,
	PMIC_RG_LDO_VUSB_HW1_OP_EN,
	PMIC_RG_LDO_VUSB_HW2_OP_EN,
	PMIC_RG_LDO_VUSB_OP_EN_SET,
	PMIC_RG_LDO_VUSB_OP_EN_CLR,
	PMIC_RG_LDO_VUSB_HW0_OP_CFG,
	PMIC_RG_LDO_VUSB_HW1_OP_CFG,
	PMIC_RG_LDO_VUSB_HW2_OP_CFG,
	PMIC_RG_LDO_VUSB_OP_CFG_SET,
	PMIC_RG_LDO_VUSB_OP_CFG_CLR,
	PMIC_RG_LDO_VUSB_EN_1,
	PMIC_DA_VUSB_MODE,
	PMIC_RG_LDO_VUSB_STBTD,
	PMIC_DA_VUSB_STB,
	PMIC_DA_VUSB_EN,
	PMIC_RG_LDO_VUSB_OCFB_EN,
	PMIC_DA_VUSB_OCFB_EN,
	PMIC_RG_LDO_VUSB_DUMMY_LOAD,
	PMIC_DA_VUSB_DUMMY_LOAD,
	PMIC_RG_LDO_VSRAM_PROC11_EN,
	PMIC_RG_LDO_VSRAM_PROC11_LP,
	PMIC_RG_LDO_VSRAM_PROC11_VOSEL_SLEEP,
	PMIC_RG_LDO_VSRAM_PROC11_SFCHG_FRATE,
	PMIC_RG_LDO_VSRAM_PROC11_SFCHG_FEN,
	PMIC_RG_LDO_VSRAM_PROC11_SFCHG_RRATE,
	PMIC_RG_LDO_VSRAM_PROC11_SFCHG_REN,
	PMIC_RG_LDO_VSRAM_PROC11_DVS_TRANS_TD,
	PMIC_RG_LDO_VSRAM_PROC11_DVS_TRANS_CTRL,
	PMIC_RG_LDO_VSRAM_PROC11_DVS_TRANS_ONCE,
	PMIC_RG_LDO_VSRAM_PROC11_SW_OP_EN,
	PMIC_RG_LDO_VSRAM_PROC11_HW0_OP_EN,
	PMIC_RG_LDO_VSRAM_PROC11_HW1_OP_EN,
	PMIC_RG_LDO_VSRAM_PROC11_HW2_OP_EN,
	PMIC_RG_LDO_VSRAM_PROC11_OP_EN_SET,
	PMIC_RG_LDO_VSRAM_PROC11_OP_EN_CLR,
	PMIC_RG_LDO_VSRAM_PROC11_HW0_OP_CFG,
	PMIC_RG_LDO_VSRAM_PROC11_HW1_OP_CFG,
	PMIC_RG_LDO_VSRAM_PROC11_HW2_OP_CFG,
	PMIC_RG_LDO_VSRAM_PROC11_OP_CFG_SET,
	PMIC_RG_LDO_VSRAM_PROC11_OP_CFG_CLR,
	PMIC_DA_VSRAM_PROC11_MODE,
	PMIC_RG_LDO_VSRAM_PROC11_STBTD,
	PMIC_RG_LDO_VSRAM_PROC11_OCFB_EN,
	PMIC_DA_VSRAM_PROC11_OCFB_EN,
	PMIC_RG_LDO_VSRAM_PROC11_DUMMY_LOAD,
	PMIC_DA_VSRAM_PROC11_DUMMY_LOAD,
	PMIC_DA_VSRAM_PROC11_VOSEL_GRAY,
	PMIC_DA_VSRAM_PROC11_VOSEL,
	PMIC_DA_VSRAM_PROC11_EN,
	PMIC_DA_VSRAM_PROC11_STB,
	PMIC_DA_VSRAM_PROC11_VSLEEP_SEL,
	PMIC_DA_VSRAM_PROC11_R2R_PDN,
	PMIC_DA_VSRAM_PROC11_TRACK_NDIS_EN,
	PMIC_RG_LDO_VSRAM_PROC11_TRACK_SLEEP_CTRL,
	PMIC_RG_LDO_VSRAM_PROC11_TRACK_ON_CTRL,
	PMIC_RG_LDO_VSRAM_PROC11_TRACK_VPROC11_ON_CTRL,
	PMIC_RG_LDO_VSRAM_PROC11_VOSEL_DELTA,
	PMIC_RG_LDO_VSRAM_PROC11_VOSEL_OFFSET,
	PMIC_RG_LDO_VSRAM_PROC11_VOSEL_ON_LB,
	PMIC_RG_LDO_VSRAM_PROC11_VOSEL_ON_HB,
	PMIC_RG_LDO_VSRAM_PROC11_VOSEL_SLEEP_LB,
	PMIC_RG_LDO_VSRAM_PROC12_TRACK_SLEEP_CTRL,
	PMIC_RG_LDO_VSRAM_PROC12_TRACK_ON_CTRL,
	PMIC_RG_LDO_VSRAM_PROC12_TRACK_VPROC12_ON_CTRL,
	PMIC_RG_LDO_VSRAM_PROC12_VOSEL_DELTA,
	PMIC_RG_LDO_VSRAM_PROC12_VOSEL_OFFSET,
	PMIC_RG_LDO_VSRAM_PROC12_VOSEL_ON_LB,
	PMIC_RG_LDO_VSRAM_PROC12_VOSEL_ON_HB,
	PMIC_RG_LDO_VSRAM_PROC12_VOSEL_SLEEP_LB,
	PMIC_RG_LDO_VSRAM_WAKEUP_TIME,
	PMIC_LDO_GON1_ELR_LEN,
	PMIC_RG_LDO_VDRAM2_VOSEL_0,
	PMIC_RG_LDO_VDRAM2_VOSEL_1,
	PMIC_RG_LDO_FROM_STRUP_EN,
	PMIC_LDO_GON2_ANA_ID,
	PMIC_LDO_GON2_DIG_ID,
	PMIC_LDO_GON2_ANA_MINOR_REV,
	PMIC_LDO_GON2_ANA_MAJOR_REV,
	PMIC_LDO_GON2_DIG_MINOR_REV,
	PMIC_LDO_GON2_DIG_MAJOR_REV,
	PMIC_LDO_GON2_DSN_CBS,
	PMIC_LDO_GON2_DSN_BIX,
	PMIC_LDO_GON2_DSN_ESP,
	PMIC_LDO_GON2_DSN_FPI,
	PMIC_RG_LDO_VSRAM_PROC12_EN,
	PMIC_RG_LDO_VSRAM_PROC12_LP,
	PMIC_RG_LDO_VSRAM_PROC12_VOSEL_SLEEP,
	PMIC_RG_LDO_VSRAM_PROC12_SFCHG_FRATE,
	PMIC_RG_LDO_VSRAM_PROC12_SFCHG_FEN,
	PMIC_RG_LDO_VSRAM_PROC12_SFCHG_RRATE,
	PMIC_RG_LDO_VSRAM_PROC12_SFCHG_REN,
	PMIC_RG_LDO_VSRAM_PROC12_DVS_TRANS_TD,
	PMIC_RG_LDO_VSRAM_PROC12_DVS_TRANS_CTRL,
	PMIC_RG_LDO_VSRAM_PROC12_DVS_TRANS_ONCE,
	PMIC_RG_LDO_VSRAM_PROC12_SW_OP_EN,
	PMIC_RG_LDO_VSRAM_PROC12_HW0_OP_EN,
	PMIC_RG_LDO_VSRAM_PROC12_HW1_OP_EN,
	PMIC_RG_LDO_VSRAM_PROC12_HW2_OP_EN,
	PMIC_RG_LDO_VSRAM_PROC12_OP_EN_SET,
	PMIC_RG_LDO_VSRAM_PROC12_OP_EN_CLR,
	PMIC_RG_LDO_VSRAM_PROC12_HW0_OP_CFG,
	PMIC_RG_LDO_VSRAM_PROC12_HW1_OP_CFG,
	PMIC_RG_LDO_VSRAM_PROC12_HW2_OP_CFG,
	PMIC_RG_LDO_VSRAM_PROC12_OP_CFG_SET,
	PMIC_RG_LDO_VSRAM_PROC12_OP_CFG_CLR,
	PMIC_DA_VSRAM_PROC12_MODE,
	PMIC_RG_LDO_VSRAM_PROC12_STBTD,
	PMIC_RG_LDO_VSRAM_PROC12_OCFB_EN,
	PMIC_DA_VSRAM_PROC12_OCFB_EN,
	PMIC_RG_LDO_VSRAM_PROC12_DUMMY_LOAD,
	PMIC_DA_VSRAM_PROC12_DUMMY_LOAD,
	PMIC_DA_VSRAM_PROC12_VOSEL_GRAY,
	PMIC_DA_VSRAM_PROC12_VOSEL,
	PMIC_DA_VSRAM_PROC12_EN,
	PMIC_DA_VSRAM_PROC12_STB,
	PMIC_DA_VSRAM_PROC12_VSLEEP_SEL,
	PMIC_DA_VSRAM_PROC12_R2R_PDN,
	PMIC_DA_VSRAM_PROC12_TRACK_NDIS_EN,
	PMIC_RG_LDO_VSRAM_OTHERS_EN,
	PMIC_RG_LDO_VSRAM_OTHERS_LP,
	PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_SLEEP,
	PMIC_RG_LDO_VSRAM_OTHERS_SFCHG_FRATE,
	PMIC_RG_LDO_VSRAM_OTHERS_SFCHG_FEN,
	PMIC_RG_LDO_VSRAM_OTHERS_SFCHG_RRATE,
	PMIC_RG_LDO_VSRAM_OTHERS_SFCHG_REN,
	PMIC_RG_LDO_VSRAM_OTHERS_DVS_TRANS_TD,
	PMIC_RG_LDO_VSRAM_OTHERS_DVS_TRANS_CTRL,
	PMIC_RG_LDO_VSRAM_OTHERS_DVS_TRANS_ONCE,
	PMIC_RG_LDO_VSRAM_OTHERS_SW_OP_EN,
	PMIC_RG_LDO_VSRAM_OTHERS_HW0_OP_EN,
	PMIC_RG_LDO_VSRAM_OTHERS_HW1_OP_EN,
	PMIC_RG_LDO_VSRAM_OTHERS_HW2_OP_EN,
	PMIC_RG_LDO_VSRAM_OTHERS_OP_EN_SET,
	PMIC_RG_LDO_VSRAM_OTHERS_OP_EN_CLR,
	PMIC_RG_LDO_VSRAM_OTHERS_HW0_OP_CFG,
	PMIC_RG_LDO_VSRAM_OTHERS_HW1_OP_CFG,
	PMIC_RG_LDO_VSRAM_OTHERS_HW2_OP_CFG,
	PMIC_RG_LDO_VSRAM_OTHERS_OP_CFG_SET,
	PMIC_RG_LDO_VSRAM_OTHERS_OP_CFG_CLR,
	PMIC_DA_VSRAM_OTHERS_MODE,
	PMIC_RG_LDO_VSRAM_OTHERS_STBTD,
	PMIC_RG_LDO_VSRAM_OTHERS_OCFB_EN,
	PMIC_DA_VSRAM_OTHERS_OCFB_EN,
	PMIC_RG_LDO_VSRAM_OTHERS_DUMMY_LOAD,
	PMIC_DA_VSRAM_OTHERS_DUMMY_LOAD,
	PMIC_DA_VSRAM_OTHERS_VOSEL_GRAY,
	PMIC_DA_VSRAM_OTHERS_VOSEL,
	PMIC_DA_VSRAM_OTHERS_EN,
	PMIC_DA_VSRAM_OTHERS_STB,
	PMIC_DA_VSRAM_OTHERS_VSLEEP_SEL,
	PMIC_DA_VSRAM_OTHERS_R2R_PDN,
	PMIC_DA_VSRAM_OTHERS_TRACK_NDIS_EN,
	PMIC_RG_LDO_VSRAM_OTHERS_SSHUB_EN,
	PMIC_RG_LDO_VSRAM_OTHERS_SSHUB_SLEEP_VOSEL_EN,
	PMIC_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL,
	PMIC_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SLEEP,
	PMIC_RG_LDO_VSRAM_GPU_EN,
	PMIC_RG_LDO_VSRAM_GPU_LP,
	PMIC_RG_LDO_VSRAM_GPU_VOSEL_SLEEP,
	PMIC_RG_LDO_VSRAM_GPU_SFCHG_FRATE,
	PMIC_RG_LDO_VSRAM_GPU_SFCHG_FEN,
	PMIC_RG_LDO_VSRAM_GPU_SFCHG_RRATE,
	PMIC_RG_LDO_VSRAM_GPU_SFCHG_REN,
	PMIC_RG_LDO_VSRAM_GPU_DVS_TRANS_TD,
	PMIC_RG_LDO_VSRAM_GPU_DVS_TRANS_CTRL,
	PMIC_RG_LDO_VSRAM_GPU_DVS_TRANS_ONCE,
	PMIC_RG_LDO_VSRAM_GPU_SW_OP_EN,
	PMIC_RG_LDO_VSRAM_GPU_HW0_OP_EN,
	PMIC_RG_LDO_VSRAM_GPU_HW1_OP_EN,
	PMIC_RG_LDO_VSRAM_GPU_HW2_OP_EN,
	PMIC_RG_LDO_VSRAM_GPU_OP_EN_SET,
	PMIC_RG_LDO_VSRAM_GPU_OP_EN_CLR,
	PMIC_RG_LDO_VSRAM_GPU_HW0_OP_CFG,
	PMIC_RG_LDO_VSRAM_GPU_HW1_OP_CFG,
	PMIC_RG_LDO_VSRAM_GPU_HW2_OP_CFG,
	PMIC_RG_LDO_VSRAM_GPU_OP_CFG_SET,
	PMIC_RG_LDO_VSRAM_GPU_OP_CFG_CLR,
	PMIC_DA_VSRAM_GPU_MODE,
	PMIC_RG_LDO_VSRAM_GPU_STBTD,
	PMIC_RG_LDO_VSRAM_GPU_OCFB_EN,
	PMIC_DA_VSRAM_GPU_OCFB_EN,
	PMIC_RG_LDO_VSRAM_GPU_DUMMY_LOAD,
	PMIC_DA_VSRAM_GPU_DUMMY_LOAD,
	PMIC_DA_VSRAM_GPU_VOSEL_GRAY,
	PMIC_DA_VSRAM_GPU_VOSEL,
	PMIC_DA_VSRAM_GPU_EN,
	PMIC_DA_VSRAM_GPU_STB,
	PMIC_DA_VSRAM_GPU_VSLEEP_SEL,
	PMIC_DA_VSRAM_GPU_R2R_PDN,
	PMIC_DA_VSRAM_GPU_TRACK_NDIS_EN,
	PMIC_RG_LDO_VSRAM_PROC11_R2R_PDN_DIS,
	PMIC_RG_LDO_VSRAM_PROC12_R2R_PDN_DIS,
	PMIC_RG_LDO_VSRAM_OTHERS_R2R_PDN_DIS,
	PMIC_RG_LDO_VSRAM_GPU_R2R_PDN_DIS,
	PMIC_LDO_VSRAM_PROC11_WDTDBG_VOSEL,
	PMIC_LDO_VSRAM_PROC12_WDTDBG_VOSEL,
	PMIC_LDO_VSRAM_OTHERS_WDTDBG_VOSEL,
	PMIC_LDO_VSRAM_GPU_WDTDBG_VOSEL,
	PMIC_LDO_GON2_ELR_LEN,
	PMIC_RG_LDO_VSRAM_PROC11_VOSEL,
	PMIC_RG_LDO_VSRAM_PROC12_VOSEL,
	PMIC_RG_LDO_VSRAM_OTHERS_VOSEL,
	PMIC_RG_LDO_VSRAM_GPU_VOSEL,
	PMIC_RG_LDO_VSRAM_PROC11_VOSEL_LIMIT_SEL,
	PMIC_RG_LDO_VSRAM_PROC12_VOSEL_LIMIT_SEL,
	PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_LIMIT_SEL,
	PMIC_RG_LDO_VSRAM_GPU_VOSEL_LIMIT_SEL,
	PMIC_LDO_GOFF0_ANA_ID,
	PMIC_LDO_GOFF0_DIG_ID,
	PMIC_LDO_GOFF0_ANA_MINOR_REV,
	PMIC_LDO_GOFF0_ANA_MAJOR_REV,
	PMIC_LDO_GOFF0_DIG_MINOR_REV,
	PMIC_LDO_GOFF0_DIG_MAJOR_REV,
	PMIC_LDO_GOFF0_DSN_CBS,
	PMIC_LDO_GOFF0_DSN_BIX,
	PMIC_LDO_GOFF0_DSN_ESP,
	PMIC_LDO_GOFF0_DSN_FPI,
	PMIC_RG_LDO_VFE28_EN,
	PMIC_RG_LDO_VFE28_LP,
	PMIC_RG_LDO_VFE28_SW_OP_EN,
	PMIC_RG_LDO_VFE28_HW0_OP_EN,
	PMIC_RG_LDO_VFE28_HW1_OP_EN,
	PMIC_RG_LDO_VFE28_HW2_OP_EN,
	PMIC_RG_LDO_VFE28_OP_EN_SET,
	PMIC_RG_LDO_VFE28_OP_EN_CLR,
	PMIC_RG_LDO_VFE28_HW0_OP_CFG,
	PMIC_RG_LDO_VFE28_HW1_OP_CFG,
	PMIC_RG_LDO_VFE28_HW2_OP_CFG,
	PMIC_RG_LDO_VFE28_ON_OP,
	PMIC_RG_LDO_VFE28_LP_OP,
	PMIC_RG_LDO_VFE28_OP_CFG_SET,
	PMIC_RG_LDO_VFE28_OP_CFG_CLR,
	PMIC_DA_VFE28_MODE,
	PMIC_RG_LDO_VFE28_STBTD,
	PMIC_DA_VFE28_STB,
	PMIC_DA_VFE28_EN,
	PMIC_RG_LDO_VFE28_OCFB_EN,
	PMIC_DA_VFE28_OCFB_EN,
	PMIC_RG_LDO_VFE28_DUMMY_LOAD,
	PMIC_DA_VFE28_DUMMY_LOAD,
	PMIC_RG_LDO_VRF18_EN,
	PMIC_RG_LDO_VRF18_LP,
	PMIC_RG_LDO_VRF18_SW_OP_EN,
	PMIC_RG_LDO_VRF18_HW0_OP_EN,
	PMIC_RG_LDO_VRF18_HW1_OP_EN,
	PMIC_RG_LDO_VRF18_HW2_OP_EN,
	PMIC_RG_LDO_VRF18_OP_EN_SET,
	PMIC_RG_LDO_VRF18_OP_EN_CLR,
	PMIC_RG_LDO_VRF18_HW0_OP_CFG,
	PMIC_RG_LDO_VRF18_HW1_OP_CFG,
	PMIC_RG_LDO_VRF18_HW2_OP_CFG,
	PMIC_RG_LDO_VRF18_OP_CFG_SET,
	PMIC_RG_LDO_VRF18_OP_CFG_CLR,
	PMIC_DA_VRF18_MODE,
	PMIC_RG_LDO_VRF18_STBTD,
	PMIC_DA_VRF18_STB,
	PMIC_DA_VRF18_EN,
	PMIC_RG_LDO_VRF18_OCFB_EN,
	PMIC_DA_VRF18_OCFB_EN,
	PMIC_RG_LDO_VRF18_DUMMY_LOAD,
	PMIC_DA_VRF18_DUMMY_LOAD,
	PMIC_RG_LDO_VRF12_EN,
	PMIC_RG_LDO_VRF12_LP,
	PMIC_RG_LDO_VRF12_SW_OP_EN,
	PMIC_RG_LDO_VRF12_HW0_OP_EN,
	PMIC_RG_LDO_VRF12_HW1_OP_EN,
	PMIC_RG_LDO_VRF12_HW2_OP_EN,
	PMIC_RG_LDO_VRF12_OP_EN_SET,
	PMIC_RG_LDO_VRF12_OP_EN_CLR,
	PMIC_RG_LDO_VRF12_HW0_OP_CFG,
	PMIC_RG_LDO_VRF12_HW1_OP_CFG,
	PMIC_RG_LDO_VRF12_HW2_OP_CFG,
	PMIC_RG_LDO_VRF12_OP_CFG_SET,
	PMIC_RG_LDO_VRF12_OP_CFG_CLR,
	PMIC_DA_VRF12_MODE,
	PMIC_RG_LDO_VRF12_STBTD,
	PMIC_DA_VRF12_STB,
	PMIC_DA_VRF12_EN,
	PMIC_RG_LDO_VRF12_OCFB_EN,
	PMIC_DA_VRF12_OCFB_EN,
	PMIC_RG_LDO_VRF12_DUMMY_LOAD,
	PMIC_DA_VRF12_DUMMY_LOAD,
	PMIC_RG_LDO_VEFUSE_EN,
	PMIC_RG_LDO_VEFUSE_LP,
	PMIC_RG_LDO_VEFUSE_SW_OP_EN,
	PMIC_RG_LDO_VEFUSE_HW0_OP_EN,
	PMIC_RG_LDO_VEFUSE_HW1_OP_EN,
	PMIC_RG_LDO_VEFUSE_HW2_OP_EN,
	PMIC_RG_LDO_VEFUSE_OP_EN_SET,
	PMIC_RG_LDO_VEFUSE_OP_EN_CLR,
	PMIC_RG_LDO_VEFUSE_HW0_OP_CFG,
	PMIC_RG_LDO_VEFUSE_HW1_OP_CFG,
	PMIC_RG_LDO_VEFUSE_HW2_OP_CFG,
	PMIC_RG_LDO_VEFUSE_OP_CFG_SET,
	PMIC_RG_LDO_VEFUSE_OP_CFG_CLR,
	PMIC_DA_VEFUSE_MODE,
	PMIC_RG_LDO_VEFUSE_STBTD,
	PMIC_DA_VEFUSE_STB,
	PMIC_DA_VEFUSE_EN,
	PMIC_RG_LDO_VEFUSE_OCFB_EN,
	PMIC_DA_VEFUSE_OCFB_EN,
	PMIC_RG_LDO_VEFUSE_DUMMY_LOAD,
	PMIC_DA_VEFUSE_DUMMY_LOAD,
	PMIC_RG_LDO_VCN18_EN,
	PMIC_RG_LDO_VCN18_LP,
	PMIC_RG_LDO_VCN18_SW_OP_EN,
	PMIC_RG_LDO_VCN18_HW0_OP_EN,
	PMIC_RG_LDO_VCN18_HW1_OP_EN,
	PMIC_RG_LDO_VCN18_HW2_OP_EN,
	PMIC_RG_LDO_VCN18_OP_EN_SET,
	PMIC_RG_LDO_VCN18_OP_EN_CLR,
	PMIC_RG_LDO_VCN18_HW0_OP_CFG,
	PMIC_RG_LDO_VCN18_HW1_OP_CFG,
	PMIC_RG_LDO_VCN18_HW2_OP_CFG,
	PMIC_RG_LDO_VCN18_OP_CFG_SET,
	PMIC_RG_LDO_VCN18_OP_CFG_CLR,
	PMIC_DA_VCN18_MODE,
	PMIC_RG_LDO_VCN18_STBTD,
	PMIC_DA_VCN18_STB,
	PMIC_DA_VCN18_EN,
	PMIC_RG_LDO_VCN18_OCFB_EN,
	PMIC_DA_VCN18_OCFB_EN,
	PMIC_RG_LDO_VCN18_DUMMY_LOAD,
	PMIC_DA_VCN18_DUMMY_LOAD,
	PMIC_RG_LDO_VCAMA1_EN,
	PMIC_RG_LDO_VCAMA1_LP,
	PMIC_RG_LDO_VCAMA1_SW_OP_EN,
	PMIC_RG_LDO_VCAMA1_HW0_OP_EN,
	PMIC_RG_LDO_VCAMA1_HW1_OP_EN,
	PMIC_RG_LDO_VCAMA1_HW2_OP_EN,
	PMIC_RG_LDO_VCAMA1_OP_EN_SET,
	PMIC_RG_LDO_VCAMA1_OP_EN_CLR,
	PMIC_RG_LDO_VCAMA1_HW0_OP_CFG,
	PMIC_RG_LDO_VCAMA1_HW1_OP_CFG,
	PMIC_RG_LDO_VCAMA1_HW2_OP_CFG,
	PMIC_RG_LDO_VCAMA1_OP_CFG_SET,
	PMIC_RG_LDO_VCAMA1_OP_CFG_CLR,
	PMIC_DA_VCAMA1_MODE,
	PMIC_RG_LDO_VCAMA1_STBTD,
	PMIC_DA_VCAMA1_STB,
	PMIC_DA_VCAMA1_EN,
	PMIC_RG_LDO_VCAMA1_OCFB_EN,
	PMIC_DA_VCAMA1_OCFB_EN,
	PMIC_RG_LDO_VCAMA1_DUMMY_LOAD,
	PMIC_DA_VCAMA1_DUMMY_LOAD,
	PMIC_LDO_GOFF1_ANA_ID,
	PMIC_LDO_GOFF1_DIG_ID,
	PMIC_LDO_GOFF1_ANA_MINOR_REV,
	PMIC_LDO_GOFF1_ANA_MAJOR_REV,
	PMIC_LDO_GOFF1_DIG_MINOR_REV,
	PMIC_LDO_GOFF1_DIG_MAJOR_REV,
	PMIC_LDO_GOFF1_DSN_CBS,
	PMIC_LDO_GOFF1_DSN_BIX,
	PMIC_LDO_GOFF1_DSN_ESP,
	PMIC_LDO_GOFF1_DSN_FPI,
	PMIC_RG_LDO_VCAMA2_EN,
	PMIC_RG_LDO_VCAMA2_LP,
	PMIC_RG_LDO_VCAMA2_SW_OP_EN,
	PMIC_RG_LDO_VCAMA2_HW0_OP_EN,
	PMIC_RG_LDO_VCAMA2_HW1_OP_EN,
	PMIC_RG_LDO_VCAMA2_HW2_OP_EN,
	PMIC_RG_LDO_VCAMA2_OP_EN_SET,
	PMIC_RG_LDO_VCAMA2_OP_EN_CLR,
	PMIC_RG_LDO_VCAMA2_HW0_OP_CFG,
	PMIC_RG_LDO_VCAMA2_HW1_OP_CFG,
	PMIC_RG_LDO_VCAMA2_HW2_OP_CFG,
	PMIC_RG_LDO_VCAMA2_OP_CFG_SET,
	PMIC_RG_LDO_VCAMA2_OP_CFG_CLR,
	PMIC_DA_VCAMA2_MODE,
	PMIC_RG_LDO_VCAMA2_STBTD,
	PMIC_DA_VCAMA2_STB,
	PMIC_DA_VCAMA2_EN,
	PMIC_RG_LDO_VCAMA2_OCFB_EN,
	PMIC_DA_VCAMA2_OCFB_EN,
	PMIC_RG_LDO_VCAMA2_DUMMY_LOAD,
	PMIC_DA_VCAMA2_DUMMY_LOAD,
	PMIC_RG_LDO_VCAMD_EN,
	PMIC_RG_LDO_VCAMD_LP,
	PMIC_RG_LDO_VCAMD_SW_OP_EN,
	PMIC_RG_LDO_VCAMD_HW0_OP_EN,
	PMIC_RG_LDO_VCAMD_HW1_OP_EN,
	PMIC_RG_LDO_VCAMD_HW2_OP_EN,
	PMIC_RG_LDO_VCAMD_OP_EN_SET,
	PMIC_RG_LDO_VCAMD_OP_EN_CLR,
	PMIC_RG_LDO_VCAMD_HW0_OP_CFG,
	PMIC_RG_LDO_VCAMD_HW1_OP_CFG,
	PMIC_RG_LDO_VCAMD_HW2_OP_CFG,
	PMIC_RG_LDO_VCAMD_OP_CFG_SET,
	PMIC_RG_LDO_VCAMD_OP_CFG_CLR,
	PMIC_DA_VCAMD_MODE,
	PMIC_RG_LDO_VCAMD_STBTD,
	PMIC_DA_VCAMD_STB,
	PMIC_DA_VCAMD_EN,
	PMIC_RG_LDO_VCAMD_OCFB_EN,
	PMIC_DA_VCAMD_OCFB_EN,
	PMIC_RG_LDO_VCAMD_DUMMY_LOAD,
	PMIC_DA_VCAMD_DUMMY_LOAD,
	PMIC_RG_LDO_VCAMIO_EN,
	PMIC_RG_LDO_VCAMIO_LP,
	PMIC_RG_LDO_VCAMIO_SW_OP_EN,
	PMIC_RG_LDO_VCAMIO_HW0_OP_EN,
	PMIC_RG_LDO_VCAMIO_HW1_OP_EN,
	PMIC_RG_LDO_VCAMIO_HW2_OP_EN,
	PMIC_RG_LDO_VCAMIO_OP_EN_SET,
	PMIC_RG_LDO_VCAMIO_OP_EN_CLR,
	PMIC_RG_LDO_VCAMIO_HW0_OP_CFG,
	PMIC_RG_LDO_VCAMIO_HW1_OP_CFG,
	PMIC_RG_LDO_VCAMIO_HW2_OP_CFG,
	PMIC_RG_LDO_VCAMIO_OP_CFG_SET,
	PMIC_RG_LDO_VCAMIO_OP_CFG_CLR,
	PMIC_DA_VCAMIO_MODE,
	PMIC_RG_LDO_VCAMIO_STBTD,
	PMIC_DA_VCAMIO_STB,
	PMIC_DA_VCAMIO_EN,
	PMIC_RG_LDO_VCAMIO_OCFB_EN,
	PMIC_DA_VCAMIO_OCFB_EN,
	PMIC_RG_LDO_VCAMIO_DUMMY_LOAD,
	PMIC_DA_VCAMIO_DUMMY_LOAD,
	PMIC_RG_LDO_VMC_EN,
	PMIC_RG_LDO_VMC_LP,
	PMIC_RG_LDO_VMC_SW_OP_EN,
	PMIC_RG_LDO_VMC_HW0_OP_EN,
	PMIC_RG_LDO_VMC_HW1_OP_EN,
	PMIC_RG_LDO_VMC_HW2_OP_EN,
	PMIC_RG_LDO_VMC_OP_EN_SET,
	PMIC_RG_LDO_VMC_OP_EN_CLR,
	PMIC_RG_LDO_VMC_HW0_OP_CFG,
	PMIC_RG_LDO_VMC_HW1_OP_CFG,
	PMIC_RG_LDO_VMC_HW2_OP_CFG,
	PMIC_RG_LDO_VMC_OP_CFG_SET,
	PMIC_RG_LDO_VMC_OP_CFG_CLR,
	PMIC_DA_VMC_MODE,
	PMIC_RG_LDO_VMC_STBTD,
	PMIC_DA_VMC_STB,
	PMIC_DA_VMC_EN,
	PMIC_RG_LDO_VMC_OCFB_EN,
	PMIC_DA_VMC_OCFB_EN,
	PMIC_RG_LDO_VMC_DUMMY_LOAD,
	PMIC_DA_VMC_DUMMY_LOAD,
	PMIC_RG_LDO_VMCH_EN,
	PMIC_RG_LDO_VMCH_LP,
	PMIC_RG_LDO_VMCH_SW_OP_EN,
	PMIC_RG_LDO_VMCH_HW0_OP_EN,
	PMIC_RG_LDO_VMCH_HW1_OP_EN,
	PMIC_RG_LDO_VMCH_HW2_OP_EN,
	PMIC_RG_LDO_VMCH_OP_EN_SET,
	PMIC_RG_LDO_VMCH_OP_EN_CLR,
	PMIC_RG_LDO_VMCH_HW0_OP_CFG,
	PMIC_RG_LDO_VMCH_HW1_OP_CFG,
	PMIC_RG_LDO_VMCH_HW2_OP_CFG,
	PMIC_RG_LDO_VMCH_OP_CFG_SET,
	PMIC_RG_LDO_VMCH_OP_CFG_CLR,
	PMIC_DA_VMCH_MODE,
	PMIC_RG_LDO_VMCH_STBTD,
	PMIC_DA_VMCH_STB,
	PMIC_DA_VMCH_EN,
	PMIC_RG_LDO_VMCH_OCFB_EN,
	PMIC_DA_VMCH_OCFB_EN,
	PMIC_RG_LDO_VMCH_DUMMY_LOAD,
	PMIC_DA_VMCH_DUMMY_LOAD,
	PMIC_LDO_GOFF2_ANA_ID,
	PMIC_LDO_GOFF2_DIG_ID,
	PMIC_LDO_GOFF2_ANA_MINOR_REV,
	PMIC_LDO_GOFF2_ANA_MAJOR_REV,
	PMIC_LDO_GOFF2_DIG_MINOR_REV,
	PMIC_LDO_GOFF2_DIG_MAJOR_REV,
	PMIC_LDO_GOFF2_DSN_CBS,
	PMIC_LDO_GOFF2_DSN_BIX,
	PMIC_LDO_GOFF2_DSN_ESP,
	PMIC_LDO_GOFF2_DSN_FPI,
	PMIC_RG_LDO_VIBR_EN,
	PMIC_RG_LDO_VIBR_LP,
	PMIC_RG_LDO_VIBR_SW_OP_EN,
	PMIC_RG_LDO_VIBR_HW0_OP_EN,
	PMIC_RG_LDO_VIBR_HW1_OP_EN,
	PMIC_RG_LDO_VIBR_HW2_OP_EN,
	PMIC_RG_LDO_VIBR_OP_EN_SET,
	PMIC_RG_LDO_VIBR_OP_EN_CLR,
	PMIC_RG_LDO_VIBR_HW0_OP_CFG,
	PMIC_RG_LDO_VIBR_HW1_OP_CFG,
	PMIC_RG_LDO_VIBR_HW2_OP_CFG,
	PMIC_RG_LDO_VIBR_OP_CFG_SET,
	PMIC_RG_LDO_VIBR_OP_CFG_CLR,
	PMIC_DA_VIBR_MODE,
	PMIC_RG_LDO_VIBR_STBTD,
	PMIC_DA_VIBR_STB,
	PMIC_DA_VIBR_EN,
	PMIC_RG_LDO_VIBR_OCFB_EN,
	PMIC_DA_VIBR_OCFB_EN,
	PMIC_RG_LDO_VIBR_DUMMY_LOAD,
	PMIC_DA_VIBR_DUMMY_LOAD,
	PMIC_RG_LDO_VCN33_EN_0,
	PMIC_RG_LDO_VCN33_LP,
	PMIC_RG_LDO_VCN33_SW_OP_EN,
	PMIC_RG_LDO_VCN33_HW0_OP_EN,
	PMIC_RG_LDO_VCN33_HW1_OP_EN,
	PMIC_RG_LDO_VCN33_HW2_OP_EN,
	PMIC_RG_LDO_VCN33_OP_EN_SET,
	PMIC_RG_LDO_VCN33_OP_EN_CLR,
	PMIC_RG_LDO_VCN33_HW0_OP_CFG,
	PMIC_RG_LDO_VCN33_HW1_OP_CFG,
	PMIC_RG_LDO_VCN33_HW2_OP_CFG,
	PMIC_RG_LDO_VCN33_OP_CFG_SET,
	PMIC_RG_LDO_VCN33_OP_CFG_CLR,
	PMIC_RG_LDO_VCN33_EN_1,
	PMIC_DA_VCN33_MODE,
	PMIC_RG_LDO_VCN33_STBTD,
	PMIC_DA_VCN33_STB,
	PMIC_DA_VCN33_EN,
	PMIC_RG_LDO_VCN33_OCFB_EN,
	PMIC_DA_VCN33_OCFB_EN,
	PMIC_RG_LDO_VCN33_DUMMY_LOAD,
	PMIC_DA_VCN33_DUMMY_LOAD,
	PMIC_RG_LDO_VLDO28_EN_0,
	PMIC_RG_LDO_VLDO28_LP,
	PMIC_RG_LDO_VLDO28_SW_OP_EN,
	PMIC_RG_LDO_VLDO28_HW0_OP_EN,
	PMIC_RG_LDO_VLDO28_HW1_OP_EN,
	PMIC_RG_LDO_VLDO28_HW2_OP_EN,
	PMIC_RG_LDO_VLDO28_OP_EN_SET,
	PMIC_RG_LDO_VLDO28_OP_EN_CLR,
	PMIC_RG_LDO_VLDO28_HW0_OP_CFG,
	PMIC_RG_LDO_VLDO28_HW1_OP_CFG,
	PMIC_RG_LDO_VLDO28_HW2_OP_CFG,
	PMIC_RG_LDO_VLDO28_OP_CFG_SET,
	PMIC_RG_LDO_VLDO28_OP_CFG_CLR,
	PMIC_RG_LDO_VLDO28_EN_1,
	PMIC_DA_VLDO28_MODE,
	PMIC_RG_LDO_VLDO28_STBTD,
	PMIC_DA_VLDO28_STB,
	PMIC_DA_VLDO28_EN,
	PMIC_RG_LDO_VLDO28_OCFB_EN,
	PMIC_DA_VLDO28_OCFB_EN,
	PMIC_RG_LDO_VLDO28_DUMMY_LOAD,
	PMIC_DA_VLDO28_DUMMY_LOAD,
	PMIC_RG_LDO_VSIM1_EN,
	PMIC_RG_LDO_VSIM1_LP,
	PMIC_RG_LDO_VSIM1_SW_OP_EN,
	PMIC_RG_LDO_VSIM1_HW0_OP_EN,
	PMIC_RG_LDO_VSIM1_HW1_OP_EN,
	PMIC_RG_LDO_VSIM1_HW2_OP_EN,
	PMIC_RG_LDO_VSIM1_OP_EN_SET,
	PMIC_RG_LDO_VSIM1_OP_EN_CLR,
	PMIC_RG_LDO_VSIM1_HW0_OP_CFG,
	PMIC_RG_LDO_VSIM1_HW1_OP_CFG,
	PMIC_RG_LDO_VSIM1_HW2_OP_CFG,
	PMIC_RG_LDO_VSIM1_OP_CFG_SET,
	PMIC_RG_LDO_VSIM1_OP_CFG_CLR,
	PMIC_DA_VSIM1_MODE,
	PMIC_RG_LDO_VSIM1_STBTD,
	PMIC_DA_VSIM1_STB,
	PMIC_DA_VSIM1_EN,
	PMIC_RG_LDO_VSIM1_OCFB_EN,
	PMIC_DA_VSIM1_OCFB_EN,
	PMIC_RG_LDO_VSIM1_DUMMY_LOAD,
	PMIC_DA_VSIM1_DUMMY_LOAD,
	PMIC_RG_LDO_VSIM2_EN,
	PMIC_RG_LDO_VSIM2_LP,
	PMIC_RG_LDO_VSIM2_SW_OP_EN,
	PMIC_RG_LDO_VSIM2_HW0_OP_EN,
	PMIC_RG_LDO_VSIM2_HW1_OP_EN,
	PMIC_RG_LDO_VSIM2_HW2_OP_EN,
	PMIC_RG_LDO_VSIM2_OP_EN_SET,
	PMIC_RG_LDO_VSIM2_OP_EN_CLR,
	PMIC_RG_LDO_VSIM2_HW0_OP_CFG,
	PMIC_RG_LDO_VSIM2_HW1_OP_CFG,
	PMIC_RG_LDO_VSIM2_HW2_OP_CFG,
	PMIC_RG_LDO_VSIM2_OP_CFG_SET,
	PMIC_RG_LDO_VSIM2_OP_CFG_CLR,
	PMIC_DA_VSIM2_MODE,
	PMIC_RG_LDO_VSIM2_STBTD,
	PMIC_DA_VSIM2_STB,
	PMIC_DA_VSIM2_EN,
	PMIC_RG_LDO_VSIM2_OCFB_EN,
	PMIC_DA_VSIM2_OCFB_EN,
	PMIC_RG_LDO_VSIM2_DUMMY_LOAD,
	PMIC_DA_VSIM2_DUMMY_LOAD,
	PMIC_RG_LDO_VMCH_SD_EN,
	PMIC_RG_LDO_VMCH_SD_POL,
	PMIC_RG_LDO_VMCH_SD_DB_SEL,
	PMIC_RG_LDO_VSIM1_SD_EN,
	PMIC_RG_LDO_VSIM1_SD_POL,
	PMIC_RG_LDO_VSIM1_SD_DB_SEL,
	PMIC_RG_LDO_VSIM2_SD_EN,
	PMIC_RG_LDO_VSIM2_SD_POL,
	PMIC_RG_LDO_VSIM2_SD_DB_SEL,
	PMIC_RG_LDO_GOFF2_RSV0,
	PMIC_RG_LDO_GOFF2_RSV1,
	PMIC_LDO_GOFF3_ANA_ID,
	PMIC_LDO_GOFF3_DIG_ID,
	PMIC_LDO_GOFF3_ANA_MINOR_REV,
	PMIC_LDO_GOFF3_ANA_MAJOR_REV,
	PMIC_LDO_GOFF3_DIG_MINOR_REV,
	PMIC_LDO_GOFF3_DIG_MAJOR_REV,
	PMIC_LDO_GOFF3_DSN_CBS,
	PMIC_LDO_GOFF3_DSN_BIX,
	PMIC_LDO_GOFF3_DSN_ESP,
	PMIC_LDO_GOFF3_DSN_FPI,
	PMIC_RG_LDO_VCN28_EN,
	PMIC_RG_LDO_VCN28_LP,
	PMIC_RG_LDO_VCN28_SW_OP_EN,
	PMIC_RG_LDO_VCN28_HW0_OP_EN,
	PMIC_RG_LDO_VCN28_HW1_OP_EN,
	PMIC_RG_LDO_VCN28_HW2_OP_EN,
	PMIC_RG_LDO_VCN28_HW3_OP_EN,
	PMIC_RG_LDO_VCN28_OP_EN_SET,
	PMIC_RG_LDO_VCN28_OP_EN_CLR,
	PMIC_RG_LDO_VCN28_HW0_OP_CFG,
	PMIC_RG_LDO_VCN28_HW1_OP_CFG,
	PMIC_RG_LDO_VCN28_HW2_OP_CFG,
	PMIC_RG_LDO_VCN28_HW3_OP_CFG,
	PMIC_RG_LDO_VCN28_OP_CFG_SET,
	PMIC_RG_LDO_VCN28_OP_CFG_CLR,
	PMIC_DA_VCN28_MODE,
	PMIC_RG_LDO_VCN28_STBTD,
	PMIC_DA_VCN28_STB,
	PMIC_DA_VCN28_EN,
	PMIC_RG_LDO_VCN28_OCFB_EN,
	PMIC_DA_VCN28_OCFB_EN,
	PMIC_RG_LDO_VCN28_DUMMY_LOAD,
	PMIC_DA_VCN28_DUMMY_LOAD,
	PMIC_RG_VRTC28_EN,
	PMIC_DA_VRTC28_EN,
	PMIC_RG_LDO_VBIF28_EN,
	PMIC_RG_LDO_VBIF28_LP,
	PMIC_RG_LDO_VBIF28_SW_OP_EN,
	PMIC_RG_LDO_VBIF28_HW0_OP_EN,
	PMIC_RG_LDO_VBIF28_HW1_OP_EN,
	PMIC_RG_LDO_VBIF28_HW2_OP_EN,
	PMIC_RG_LDO_VBIF28_OP_EN_SET,
	PMIC_RG_LDO_VBIF28_OP_EN_CLR,
	PMIC_RG_LDO_VBIF28_HW0_OP_CFG,
	PMIC_RG_LDO_VBIF28_HW1_OP_CFG,
	PMIC_RG_LDO_VBIF28_HW2_OP_CFG,
	PMIC_RG_LDO_VBIF28_OP_CFG_SET,
	PMIC_RG_LDO_VBIF28_OP_CFG_CLR,
	PMIC_DA_VBIF28_MODE,
	PMIC_RG_LDO_VBIF28_STBTD,
	PMIC_DA_VBIF28_STB,
	PMIC_DA_VBIF28_EN,
	PMIC_RG_LDO_VBIF28_OCFB_EN,
	PMIC_DA_VBIF28_OCFB_EN,
	PMIC_RG_LDO_VBIF28_DUMMY_LOAD,
	PMIC_DA_VBIF28_DUMMY_LOAD,
	PMIC_RG_LDO_GOFF3_RSV0,
	PMIC_RG_LDO_GOFF3_RSV1,
	PMIC_LDO_ANA0_ANA_ID,
	PMIC_LDO_ANA0_DIG_ID,
	PMIC_LDO_ANA0_ANA_MINOR_REV,
	PMIC_LDO_ANA0_ANA_MAJOR_REV,
	PMIC_LDO_ANA0_DIG_MINOR_REV,
	PMIC_LDO_ANA0_DIG_MAJOR_REV,
	PMIC_LDO_ANA0_DSN_CBS,
	PMIC_LDO_ANA0_DSN_BIX,
	PMIC_LDO_ANA0_DSN_ESP,
	PMIC_LDO_ANA0_DSN_FPI,
	PMIC_RG_VCAMA1_VOCAL,
	PMIC_RG_VCAMA1_VOSEL,
	PMIC_RG_VCAMA1_NDIS_EN,
	PMIC_RG_VCAMA1_RSV,
	PMIC_RG_VCAMA2_VOCAL,
	PMIC_RG_VCAMA2_VOSEL,
	PMIC_RG_VCAMA2_NDIS_EN,
	PMIC_RG_VCAMA2_RSV,
	PMIC_RG_VFE28_VOCAL,
	PMIC_RG_VFE28_NDIS_EN,
	PMIC_RG_VFE28_RSV,
	PMIC_RG_VCN28_VOCAL,
	PMIC_RG_VCN28_NDIS_EN,
	PMIC_RG_VCN28_RSV,
	PMIC_RG_VBIF28_VOCAL,
	PMIC_RG_VBIF28_NDIS_EN,
	PMIC_RG_VBIF28_RSV,
	PMIC_RG_VAUD28_VOCAL,
	PMIC_RG_VAUD28_NDIS_EN,
	PMIC_RG_VAUD28_RSV,
	PMIC_RG_VAUX18_VOCAL,
	PMIC_RG_VAUX18_NDIS_EN,
	PMIC_RG_VAUX18_RSV,
	PMIC_RG_VXO22_VOCAL,
	PMIC_RG_VXO22_VOSEL,
	PMIC_RG_VXO22_NDIS_EN,
	PMIC_RG_VXO22_RSV,
	PMIC_RG_VCN33_VOCAL,
	PMIC_RG_VCN33_VOSEL,
	PMIC_RG_VCN33_NDIS_EN,
	PMIC_RG_VCN33_RSV,
	PMIC_RG_VSIM1_VOCAL,
	PMIC_RG_VSIM1_VOSEL,
	PMIC_RG_VSIM1_NDIS_EN,
	PMIC_RG_VSIM1_RSV,
	PMIC_RG_VSIM2_VOCAL,
	PMIC_RG_VSIM2_VOSEL,
	PMIC_RG_VSIM2_NDIS_EN,
	PMIC_RG_VSIM2_RSV,
	PMIC_RG_VUSB_VOCAL,
	PMIC_RG_VUSB_VOSEL,
	PMIC_RG_VUSB_NDIS_EN,
	PMIC_RG_VUSB_RSV,
	PMIC_RG_VEMC_VOCAL,
	PMIC_RG_VEMC_VOSEL,
	PMIC_RG_VEMC_NDIS_EN,
	PMIC_RG_VEMC_RSV,
	PMIC_RG_VLDO28_VOCAL,
	PMIC_RG_VLDO28_VOSEL,
	PMIC_RG_VLDO28_NDIS_EN,
	PMIC_RG_VLDO28_RSV,
	PMIC_RG_VIO28_VOCAL,
	PMIC_RG_VIO28_NDIS_EN,
	PMIC_RG_VIO28_RSV,
	PMIC_RG_VIBR_VOCAL,
	PMIC_RG_VIBR_VOSEL,
	PMIC_RG_VIBR_NDIS_EN,
	PMIC_RG_VIBR_RSV,
	PMIC_RG_VMCH_VOCAL,
	PMIC_RG_VMCH_VOSEL,
	PMIC_RG_VMCH_NDIS_EN,
	PMIC_RG_VMCH_STB_SEL,
	PMIC_RG_VMCH_RSV,
	PMIC_RG_VMC_VOCAL,
	PMIC_RG_VMC_VOSEL,
	PMIC_RG_VMC_NDIS_EN,
	PMIC_RG_VMC_STB_SEL,
	PMIC_RG_VMC_RSV,
	PMIC_LDO_ANA0_ELR_LEN,
	PMIC_RG_VCAMA1_VOTRIM,
	PMIC_RG_VCAMA2_VOTRIM,
	PMIC_RG_VFE28_VOTRIM,
	PMIC_RG_VCN28_VOTRIM,
	PMIC_RG_VBIF28_VOTRIM,
	PMIC_RG_VAUD28_VOTRIM,
	PMIC_RG_VAUX18_VOTRIM,
	PMIC_RG_VXO22_VOTRIM,
	PMIC_RG_VCN33_VOTRIM,
	PMIC_RG_VCN33_OC_TRIM,
	PMIC_RG_VSIM1_VOTRIM,
	PMIC_RG_VSIM2_VOTRIM,
	PMIC_RG_VUSB_VOTRIM,
	PMIC_RG_VEMC_VOTRIM,
	PMIC_RG_VEMC_OC_TRIM,
	PMIC_RG_VLDO28_VOTRIM,
	PMIC_RG_VIO28_VOTRIM,
	PMIC_RG_VIBR_VOTRIM,
	PMIC_RG_VMCH_VOTRIM,
	PMIC_RG_VMCH_OC_TRIM,
	PMIC_RG_VMC_VOTRIM,
	PMIC_LDO_ANA1_ANA_ID,
	PMIC_LDO_ANA1_DIG_ID,
	PMIC_LDO_ANA1_ANA_MINOR_REV,
	PMIC_LDO_ANA1_ANA_MAJOR_REV,
	PMIC_LDO_ANA1_DIG_MINOR_REV,
	PMIC_LDO_ANA1_DIG_MAJOR_REV,
	PMIC_LDO_ANA1_DSN_CBS,
	PMIC_LDO_ANA1_DSN_BIX,
	PMIC_LDO_ANA1_DSN_ESP,
	PMIC_LDO_ANA1_DSN_FPI,
	PMIC_RG_VRF18_VOCAL,
	PMIC_RG_VRF18_NDIS_EN,
	PMIC_RG_VRF18_RSV,
	PMIC_RG_VCN18_VOCAL,
	PMIC_RG_VCN18_NDIS_EN,
	PMIC_RG_VCN18_RSV,
	PMIC_RG_VCAMIO_VOCAL,
	PMIC_RG_VCAMIO_NDIS_EN,
	PMIC_RG_VCAMIO_RSV,
	PMIC_RG_VIO18_VOCAL,
	PMIC_RG_VIO18_NDIS_EN,
	PMIC_RG_VIO18_RSV,
	PMIC_RG_VEFUSE_VOCAL,
	PMIC_RG_VEFUSE_VOSEL,
	PMIC_RG_VEFUSE_NDIS_EN,
	PMIC_RG_VEFUSE_RSV,
	PMIC_RG_VRF12_VOCAL,
	PMIC_RG_VRF12_NDIS_EN,
	PMIC_RG_VRF12_RSV,
	PMIC_RG_VSRAM_PROC11_STB_SEL,
	PMIC_RG_VSRAM_PROC11_NDIS_EN,
	PMIC_RG_VSRAM_PROC11_NDIS_PLCUR,
	PMIC_RG_VSRAM_PROC11_PLCUR_EN,
	PMIC_RG_VSRAM_PROC11_LPOC_EN,
	PMIC_RG_VSRAM_PROC11_RSV_H,
	PMIC_RG_VSRAM_PROC11_RSV_L,
	PMIC_RG_VSRAM_PROC11_AUTO_TRACK,
	PMIC_RG_VSRAM_PROC12_STB_SEL,
	PMIC_RG_VSRAM_PROC12_NDIS_EN,
	PMIC_RG_VSRAM_PROC12_NDIS_PLCUR,
	PMIC_RG_VSRAM_PROC12_PLCUR_EN,
	PMIC_RG_VSRAM_PROC12_LPOC_EN,
	PMIC_RG_VSRAM_PROC12_RSV_H,
	PMIC_RG_VSRAM_PROC12_RSV_L,
	PMIC_RG_VSRAM_OTHERS_STB_SEL,
	PMIC_RG_VSRAM_OTHERS_NDIS_EN,
	PMIC_RG_VSRAM_OTHERS_NDIS_PLCUR,
	PMIC_RG_VSRAM_OTHERS_PLCUR_EN,
	PMIC_RG_VSRAM_OTHERS_LPOC_EN,
	PMIC_RG_VSRAM_OTHERS_RSV_H,
	PMIC_RG_VSRAM_OTHERS_RSV_L,
	PMIC_RG_VSRAM_GPU_STB_SEL,
	PMIC_RG_VSRAM_GPU_NDIS_EN,
	PMIC_RG_VSRAM_GPU_NDIS_PLCUR,
	PMIC_RG_VSRAM_GPU_PLCUR_EN,
	PMIC_RG_VSRAM_GPU_LPOC_EN,
	PMIC_RG_VSRAM_GPU_RSV_H,
	PMIC_RG_VSRAM_GPU_RSV_L,
	PMIC_RG_VDRAM2_VOCAL,
	PMIC_RG_VDRAM2_NDIS_EN,
	PMIC_RG_VDRAM2_RSV,
	PMIC_RG_VCAMD_VOCAL,
	PMIC_RG_VCAMD_VOSEL,
	PMIC_RG_VCAMD_NDIS_EN,
	PMIC_RG_VCAMD_RSV,
	PMIC_RG_VA12_VOCAL,
	PMIC_RG_VA12_NDIS_EN,
	PMIC_RG_VA12_RSV,
	PMIC_LDO_ANA1_ELR_LEN,
	PMIC_RG_VRF18_VOTRIM,
	PMIC_RG_VCN18_VOTRIM,
	PMIC_RG_VCAMIO_VOTRIM,
	PMIC_RG_VIO18_VOTRIM,
	PMIC_RG_VEFUSE_VOTRIM,
	PMIC_RG_VRF12_VOTRIM,
	PMIC_RG_VDRAM2_VOTRIM,
	PMIC_RG_VCAMD_VOTRIM,
	PMIC_RG_VA12_VOTRIM,
	PMIC_RG_VRTC28_BIAS_SEL,
	PMIC_DUMMYLOAD_ANA_ID,
	PMIC_DUMMYLOAD_DIG_ID,
	PMIC_DUMMYLOAD_ANA_MINOR_REV,
	PMIC_DUMMYLOAD_ANA_MAJOR_REV,
	PMIC_DUMMYLOAD_DIG_MINOR_REV,
	PMIC_DUMMYLOAD_DIG_MAJOR_REV,
	PMIC_DUMMYLOAD_DSN_CBS,
	PMIC_DUMMYLOAD_DSN_BIX,
	PMIC_DUMMYLOAD_DSN_ESP,
	PMIC_DUMMYLOAD_DSN_FPI,
	PMIC_RG_ISINK_TRIM_EN,
	PMIC_RG_ISINK_TRIM_SEL,
	PMIC_RG_ISINK_RSV,
	PMIC_RG_ISINK0_CHOP_EN,
	PMIC_RG_ISINK1_CHOP_EN,
	PMIC_RG_ISINK0_DOUBLE,
	PMIC_RG_ISINK1_DOUBLE,
	PMIC_ISINK0_RSV1,
	PMIC_ISINK0_RSV0,
	PMIC_ISINK_CH0_STEP,
	PMIC_ISINK1_RSV1,
	PMIC_ISINK1_RSV0,
	PMIC_ISINK_CH1_STEP,
	PMIC_AD_ISINK0_STATUS,
	PMIC_AD_ISINK1_STATUS,
	PMIC_ISINK_CH1_EN,
	PMIC_ISINK_CH0_EN,
	PMIC_ISINK_CHOP1_EN,
	PMIC_ISINK_CHOP0_EN,
	PMIC_ISINK_CH1_BIAS_EN,
	PMIC_ISINK_CH0_BIAS_EN,
	PMIC_DUMMYLOAD_ELR_LEN,
	PMIC_RG_ISINK_TRIM_BIAS,
	PMIC_AUD_TOP_ANA_ID,
	PMIC_AUD_TOP_DIG_ID,
	PMIC_AUD_TOP_ANA_MINOR_REV,
	PMIC_AUD_TOP_ANA_MAJOR_REV,
	PMIC_AUD_TOP_DIG_MINOR_REV,
	PMIC_AUD_TOP_DIG_MAJOR_REV,
	PMIC_AUD_TOP_CBS,
	PMIC_AUD_TOP_BIX,
	PMIC_AUD_TOP_ESP,
	PMIC_AUD_TOP_FPI,
	PMIC_AUD_TOP_CLK_OFFSET,
	PMIC_AUD_TOP_RST_OFFSET,
	PMIC_AUD_TOP_INT_OFFSET,
	PMIC_AUD_TOP_INT_LEN,
	PMIC_RG_ACCDET_CK_PDN,
	PMIC_RG_AUD_CK_PDN,
	PMIC_RG_AUDIF_CK_PDN,
	PMIC_RG_ZCD13M_CK_PDN,
	PMIC_RG_AUDNCP_CK_PDN,
	PMIC_RG_PAD_AUD_CLK_MISO_CK_PDN,
	PMIC_RG_AUD_INTRP_CK_PDN,
	PMIC_RG_VOW32K_CK_PDN,
	PMIC_RG_VOW13M_CK_PDN,
	PMIC_RG_AUD_TOP_CKPDN_CON0_SET,
	PMIC_RG_AUD_TOP_CKPDN_CON0_CLR,
	PMIC_RG_AUD_CK_CKSEL,
	PMIC_RG_AUDIF_CK_CKSEL,
	PMIC_RG_AUD_TOP_CKSEL_CON0_SET,
	PMIC_RG_AUD_TOP_CKSEL_CON0_CLR,
	PMIC_RG_AUD26M_CK_TST_DIS,
	PMIC_RG_AUD_CK_TSTSEL,
	PMIC_RG_AUDIF_CK_TSTSEL,
	PMIC_RG_AUD26M_CK_TSTSEL,
	PMIC_RG_VOW13M_CK_TST_DIS,
	PMIC_RG_VOW13M_CK_TSTSEL,
	PMIC_RG_AUD_INTRP_CK_PDN_HWEN,
	PMIC_RG_AUD_INTRP_CK_PND_HWEN_CON0_SET,
	PMIC_RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR,
	PMIC_RG_AUDIO_RST,
	PMIC_RG_ACCDET_RST,
	PMIC_RG_ZCD_RST,
	PMIC_RG_AUDNCP_RST,
	PMIC_RG_AUD_TOP_RST_CON0_SET,
	PMIC_RG_AUD_TOP_RST_CON0_CLR,
	PMIC_BANK_ACCDET_SWRST,
	PMIC_BANK_AUDIO_SWRST,
	PMIC_BANK_AUDZCD_SWRST,
	PMIC_RG_INT_EN_AUDIO,
	PMIC_RG_INT_EN_ACCDET,
	PMIC_RG_INT_EN_ACCDET_EINT0,
	PMIC_RG_INT_EN_ACCDET_EINT1,
	PMIC_RG_AUD_INT_CON0_SET,
	PMIC_RG_AUD_INT_CON0_CLR,
	PMIC_RG_INT_MASK_AUDIO,
	PMIC_RG_INT_MASK_ACCDET,
	PMIC_RG_INT_MASK_ACCDET_EINT0,
	PMIC_RG_INT_MASK_ACCDET_EINT1,
	PMIC_RG_AUD_INT_MASK_CON0_SET,
	PMIC_RG_AUD_INT_MASK_CON0_CLR,
	PMIC_RG_INT_STATUS_AUDIO,
	PMIC_RG_INT_STATUS_ACCDET,
	PMIC_RG_INT_STATUS_ACCDET_EINT0,
	PMIC_RG_INT_STATUS_ACCDET_EINT1,
	PMIC_RG_INT_RAW_STATUS_AUDIO,
	PMIC_RG_INT_RAW_STATUS_ACCDET,
	PMIC_RG_INT_RAW_STATUS_ACCDET_EINT0,
	PMIC_RG_INT_RAW_STATUS_ACCDET_EINT1,
	PMIC_RG_AUD_TOP_INT_POLARITY,
	PMIC_RG_DIVCKS_CHG,
	PMIC_RG_DIVCKS_ON,
	PMIC_RG_DIVCKS_PRG,
	PMIC_RG_DIVCKS_PWD_NCP,
	PMIC_RG_DIVCKS_PWD_NCP_ST_SEL,
	PMIC_RG_AUD_TOP_MON_SEL,
	PMIC_RG_AUD_CLK_INT_MON_FLAG_SEL,
	PMIC_RG_AUD_CLK_INT_MON_FLAG_EN,
	PMIC_AUDIO_DIG_ANA_ID,
	PMIC_AUDIO_DIG_DIG_ID,
	PMIC_AUDIO_DIG_ANA_MINOR_REV,
	PMIC_AUDIO_DIG_ANA_MAJOR_REV,
	PMIC_AUDIO_DIG_DIG_MINOR_REV,
	PMIC_AUDIO_DIG_DIG_MAJOR_REV,
	PMIC_AUDIO_DIG_DSN_CBS,
	PMIC_AUDIO_DIG_DSN_BIX,
	PMIC_AUDIO_DIG_ESP,
	PMIC_AUDIO_DIG_DSN_FPI,
	PMIC_AFE_ON,
	PMIC_AFE_DL_LR_SWAP,
	PMIC_AFE_UL_LR_SWAP,
	PMIC_DL_2_SRC_ON_TMP_CTL_PRE,
	PMIC_C_TWO_DIGITAL_MIC_CTL,
	PMIC_C_DIGMIC_PHASE_SEL_CH2_CTL,
	PMIC_C_DIGMIC_PHASE_SEL_CH1_CTL,
	PMIC_UL_SRC_ON_TMP_CTL,
	PMIC_UL_SDM_3_LEVEL_CTL,
	PMIC_UL_LOOP_BACK_MODE_CTL,
	PMIC_DIGMIC_3P25M_1P625M_SEL_CTL,
	PMIC_DMIC_LOW_POWER_MODE_CTL,
	PMIC_DL_SINE_ON,
	PMIC_UL_SINE_ON,
	PMIC_MTKAIF_SINE_ON,
	PMIC_PDN_RESERVED,
	PMIC_PDN_AFE_TESTMODEL_CTL,
	PMIC_PWR_CLK_DIS_CTL,
	PMIC_PDN_I2S_DL_CTL,
	PMIC_PDN_ADC_CTL,
	PMIC_PDN_DAC_CTL,
	PMIC_PDN_AFE_CTL,
	PMIC_AFE_MON_SEL,
	PMIC_AUDIO_SYS_TOP_MON_SEL,
	PMIC_AUDIO_SYS_TOP_MON_SWAP,
	PMIC_CCI_SCRAMBLER_EN,
	PMIC_CCI_AUD_SDM_7BIT_SEL,
	PMIC_CCI_AUD_SDM_MUTER,
	PMIC_CCI_AUD_SDM_MUTEL,
	PMIC_CCI_AUD_SPLIT_TEST_EN,
	PMIC_CCI_ZERO_PAD_DISABLE,
	PMIC_CCI_AUD_IDAC_TEST_EN,
	PMIC_CCI_SPLT_SCRMB_ON,
	PMIC_CCI_SPLT_SCRMB_CLK_ON,
	PMIC_CCI_RAND_EN,
	PMIC_CCI_LCH_INV,
	PMIC_CCI_SCRAMBLER_CG_EN,
	PMIC_CCI_AUDIO_FIFO_WPTR,
	PMIC_CCI_AUD_ANACK_SEL,
	PMIC_AUD_SDM_TEST_R,
	PMIC_AUD_SDM_TEST_L,
	PMIC_CCI_ACD_FUNC_RSTB,
	PMIC_CCI_AFIFO_CLK_PWDB,
	PMIC_CCI_ACD_MODE,
	PMIC_CCI_AUDIO_FIFO_ENABLE,
	PMIC_CCI_AUDIO_FIFO_CLKIN_INV,
	PMIC_CCI_AUD_DAC_ANA_RSTB_SEL,
	PMIC_CCI_AUD_DAC_ANA_MUTE,
	PMIC_DIGMIC_TESTCK_SEL,
	PMIC_DIGMIC_TESTCK_SRC_SEL,
	PMIC_SDM_TESTCK_SRC_SEL,
	PMIC_SDM_ANA13M_TESTCK_SRC_SEL,
	PMIC_SDM_ANA13M_TESTCK_SEL,
	PMIC_UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL,
	PMIC_UL_FIFO_WCLK_6P5M_TESTCK_SEL,
	PMIC_UL_FIFO_WDATA_TESTSRC_SEL,
	PMIC_UL_FIFO_WDATA_TESTEN,
	PMIC_UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL,
	PMIC_UL_FIFO_WCLK_INV,
	PMIC_R_AUD_DAC_NEG_LARGE_MONO,
	PMIC_R_AUD_DAC_POS_LARGE_MONO,
	PMIC_R_AUD_DAC_SW_RSTB,
	PMIC_R_AUD_DAC_MONO_SEL,
	PMIC_R_AUD_DAC_NEG_TINY_MONO,
	PMIC_R_AUD_DAC_POS_TINY_MONO,
	PMIC_R_AUD_DAC_NEG_SMALL_MONO,
	PMIC_R_AUD_DAC_POS_SMALL_MONO,
	PMIC_AUD_SCR_OUT_R,
	PMIC_AUD_SCR_OUT_L,
	PMIC_RGS_AUDRCTUNE0READ,
	PMIC_RGS_AUDRCTUNE1READ,
	PMIC_ASYNC_TEST_OUT_BCK,
	PMIC_RG_MTKAIF_RXIF_FIFO_INTEN,
	PMIC_AFE_RESERVED,
	PMIC_MTKAIF_RXIF_RD_EMPTY_STATUS,
	PMIC_MTKAIF_RXIF_WR_FULL_STATUS,
	PMIC_MTKAIF_RXIF_FIFO_STATUS,
	PMIC_MTKAIFTX_V3_SDATA_OUT1,
	PMIC_MTKAIFTX_V3_SDATA_OUT2,
	PMIC_MTKAIFTX_V3_SYNC_OUT,
	PMIC_MTKAIF_RXIF_INVALID_CYCLE,
	PMIC_MTKAIF_RXIF_INVALID_FLAG,
	PMIC_MTKAIF_RXIF_SEARCH_FAIL_FLAG,
	PMIC_MTKAIFRX_V3_SDATA_IN1,
	PMIC_MTKAIFRX_V3_SDATA_IN2,
	PMIC_MTKAIFRX_V3_SYNC_IN,
	PMIC_MTKAIF_TXIF_IN_CH1,
	PMIC_MTKAIF_TXIF_IN_CH2,
	PMIC_MTKAIF_RXIF_OUT_CH1,
	PMIC_MTKAIF_RXIF_OUT_CH2,
	PMIC_RG_MTKAIF_LOOPBACK_TEST1,
	PMIC_RG_MTKAIF_LOOPBACK_TEST2,
	PMIC_RG_MTKAIF_PMIC_TXIF_8TO5,
	PMIC_RG_MTKAIF_TXIF_PROTOCOL2,
	PMIC_RG_MTKAIF_BYPASS_SRC_TEST,
	PMIC_RG_MTKAIF_BYPASS_SRC_MODE,
	PMIC_RG_MTKAIF_RXIF_PROTOCOL2,
	PMIC_RG_MTKAIF_RXIF_CLKINV,
	PMIC_RG_MTKAIF_RXIF_DATA_MODE,
	PMIC_RG_MTKAIF_RXIF_DETECT_ON,
	PMIC_RG_MTKAIF_RXIF_FIFO_RSP,
	PMIC_RG_MTKAIF_RXIF_DATA_BIT,
	PMIC_RG_MTKAIF_RXIF_VOICE_MODE,
	PMIC_RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2,
	PMIC_RG_MTKAIF_RXIF_SYNC_CHECK_ROUND,
	PMIC_RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND,
	PMIC_RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE,
	PMIC_RG_MTKAIF_RXIF_SYNC_CNT_TABLE,
	PMIC_RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL,
	PMIC_RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2,
	PMIC_RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2,
	PMIC_RG_MTKAIF_RXIF_LOOPBACK_USE_NLE,
	PMIC_RG_MTKAIF_SYNC_WORD1,
	PMIC_RG_MTKAIF_SYNC_WORD2,
	PMIC_R_AUD_SDM_MUTE_R,
	PMIC_R_AUD_SDM_MUTE_L,
	PMIC_C_MUTE_SW_CTL,
	PMIC_C_DAC_EN_CTL,
	PMIC_C_AMP_DIV_CH1_CTL,
	PMIC_C_FREQ_DIV_CH1_CTL,
	PMIC_C_SGEN_RCH_INV_8BIT,
	PMIC_C_SGEN_RCH_INV_5BIT,
	PMIC_RG_AMIC_UL_ADC_CLK_SEL,
	PMIC_RG_UL_ASYNC_FIFO_SOFT_RST,
	PMIC_RG_UL_ASYNC_FIFO_SOFT_RST_EN,
	PMIC_DCCLK_GEN_ON,
	PMIC_DCCLK_PDN,
	PMIC_DCCLK_INV,
	PMIC_DCCLK_DIV,
	PMIC_DCCLK_PHASE_SEL,
	PMIC_DCCLK_RESYNC_BYPASS,
	PMIC_RESYNC_SRC_CK_INV,
	PMIC_RESYNC_SRC_SEL,
	PMIC_RG_AUD_PAD_TOP_PHASE_MODE,
	PMIC_RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK,
	PMIC_RG_AUD_PAD_TOP_PHASE_MODE2,
	PMIC_RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK,
	PMIC_RG_AUD_PAD_TOP_TX_FIFO_ON,
	PMIC_RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2,
	PMIC_RG_AUD_PAD_TOP_TX_FIFO_RSP,
	PMIC_ADDA_AUD_PAD_TOP_MON,
	PMIC_ADDA_AUD_PAD_TOP_MON1,
	PMIC_NLE_LCH_ON,
	PMIC_NLE_LCH_CH_SEL,
	PMIC_NLE_LCH_HPGAIN_SEL,
	PMIC_NLE_RCH_ON,
	PMIC_NLE_RCH_CH_SEL,
	PMIC_NLE_RCH_HPGAIN_SEL,
	PMIC_NLE_MONITOR,
	PMIC_CK_CG_EN_MON,
	PMIC_AUDIO_DIG_2ND_ANA_ID,
	PMIC_AUDIO_DIG_2ND_DIG_ID,
	PMIC_AUDIO_DIG_2ND_ANA_MINOR_REV,
	PMIC_AUDIO_DIG_2ND_ANA_MAJOR_REV,
	PMIC_AUDIO_DIG_2ND_DIG_MINOR_REV,
	PMIC_AUDIO_DIG_2ND_DIG_MAJOR_REV,
	PMIC_AUDIO_DIG_2ND_DSN_CBS,
	PMIC_AUDIO_DIG_2ND_DSN_BIX,
	PMIC_AUDIO_DIG_2ND_ESP,
	PMIC_AUDIO_DIG_2ND_DSN_FPI,
	PMIC_RG_UP8X_SYNC_WORD,
	PMIC_VOW_INTR_FLAG,
	PMIC_SAMPLE_BASE_MODE,
	PMIC_S_N_VALUE_RST,
	PMIC_VOW_INTR_CLR,
	PMIC_VOW_INTR_SOURCE_SEL,
	PMIC_VOW_LOOP_BACK_MODE,
	PMIC_VOW_SDM_3_LEVEL,
	PMIC_MAIN_DMIC_CK_VOW_SEL,
	PMIC_VOW_DIGMIC_CK_PHASE_SEL,
	PMIC_VOW_ON,
	PMIC_VOW_CK_DIV_RST,
	PMIC_VOW_DIGMIC_ON,
	PMIC_VOW_1P6M_800K_SEL,
	PMIC_PDN_VOW,
	PMIC_AMPREF,
	PMIC_TIMERINI,
	PMIC_A_INI,
	PMIC_B_INI,
	PMIC_A_DEFAULT,
	PMIC_B_DEFAULT,
	PMIC_K_ALPHA_FALL,
	PMIC_K_ALPHA_RISE,
	PMIC_K_BETA_FALL,
	PMIC_K_BETA_RISE,
	PMIC_K_GAMMA,
	PMIC_VOW_TXIF_SCK_DIV,
	PMIC_VOW_TXIF_MONO,
	PMIC_VOW_ADC_CLK_INV,
	PMIC_VOW_ADC_TESTCK_SEL,
	PMIC_VOW_ADC_TESTCK_SRC_SEL,
	PMIC_VOW_TXIF_SCK_INV,
	PMIC_N_MIN,
	PMIC_RG_BUCK_DVFS_HW_CNT_THR,
	PMIC_RG_BUCK_DVFS_DONE_HW_MODE,
	PMIC_RG_BUCK_DVFS_DONE_SW_CTL,
	PMIC_RG_FLR_RATIO,
	PMIC_RG_FLR_BYPASS,
	PMIC_RG_WINDOW_SIZE_SEL,
	PMIC_VOW_DOWNCNT,
	PMIC_SECOND_CNT_START,
	PMIC_VOW_A,
	PMIC_VOW_B,
	PMIC_SLT_COUNTER_MON,
	PMIC_K_TMP_MON,
	PMIC_VOW_S_L,
	PMIC_VOW_S_H,
	PMIC_VOW_N_L,
	PMIC_VOW_N_H,
	PMIC_VOW_SN_INI_CFG_VAL,
	PMIC_VOW_SN_INI_CFG_EN,
	PMIC_VOW_TGEN_FREQ_DIV,
	PMIC_VOW_TGEN_MUTE_SW,
	PMIC_VOW_TGEN_EN,
	PMIC_RG_VOW_POSDIV,
	PMIC_VOW_CIC_MODE_SEL,
	PMIC_VOW_INTR_SW_VAL,
	PMIC_VOW_INTR_SW_MODE,
	PMIC_VOW_CLK_SEL,
	PMIC_RG_A1P6M_EN_SEL,
	PMIC_RG_BUCK_CLK_DIV,
	PMIC_VOW_32K_MODE,
	PMIC_BUCK_DVFS_DONE,
	PMIC_RG_HPF_ON,
	PMIC_RG_SNRDET_HPF_BYPASS,
	PMIC_RG_MTKAIF_HPF_BYPASS,
	PMIC_RG_BASELINE_ALPHA_ORDER,
	PMIC_VOW_POSDIVCLK_PDN,
	PMIC_VOW_DMICCLK_PDN,
	PMIC_VOW_IRQ_LATCH_SNR_EN,
	PMIC_VOW_HPF_DC_TEST,
	PMIC_RG_PERIODIC_CNT_PERIOD,
	PMIC_RG_PERIODIC_CNT_CLR,
	PMIC_RG_PERIODIC_EN,
	PMIC_RG_PERIODIC_CNT_SET_VALUE,
	PMIC_RG_PERIODIC_CNT_PAUSE,
	PMIC_RG_PERIODIC_CNT_SET,
	PMIC_AUDPREAMPLON_PERIODIC_ON_CYCLE,
	PMIC_AUDPREAMPLON_PERIODIC_INVERSE,
	PMIC_AUDPREAMPLON_PERIODIC_MODE,
	PMIC_AUDPREAMPLDCPRECHARGE_PERIODIC_ON_CYCLE,
	PMIC_AUDPREAMPLDCPRECHARGE_PERIODIC_INVERSE,
	PMIC_AUDPREAMPLDCPRECHARGE_PERIODIC_MODE,
	PMIC_AUDADCLPWRUP_PERIODIC_ON_CYCLE,
	PMIC_AUDADCLPWRUP_PERIODIC_INVERSE,
	PMIC_AUDADCLPWRUP_PERIODIC_MODE,
	PMIC_AUDGLBVOWLPWEN_PERIODIC_ON_CYCLE,
	PMIC_AUDGLBVOWLPWEN_PERIODIC_INVERSE,
	PMIC_AUDGLBVOWLPWEN_PERIODIC_MODE,
	PMIC_AUDDIGMICEN_PERIODIC_ON_CYCLE,
	PMIC_AUDDIGMICEN_PERIODIC_INVERSE,
	PMIC_AUDDIGMICEN_PERIODIC_MODE,
	PMIC_AUDPWDBMICBIAS0_PERIODIC_ON_CYCLE,
	PMIC_AUDPWDBMICBIAS0_PERIODIC_INVERSE,
	PMIC_AUDPWDBMICBIAS0_PERIODIC_MODE,
	PMIC_AUDPWDBMICBIAS1_PERIODIC_ON_CYCLE,
	PMIC_AUDPWDBMICBIAS1_PERIODIC_INVERSE,
	PMIC_AUDPWDBMICBIAS1_PERIODIC_MODE,
	PMIC_XO_VOW_CK_EN_PERIODIC_ON_CYCLE,
	PMIC_XO_VOW_CK_EN_PERIODIC_INVERSE,
	PMIC_XO_VOW_CK_EN_PERIODIC_MODE,
	PMIC_AUDGLB_PWRDN_PERIODIC_ON_CYCLE,
	PMIC_AUDGLB_PWRDN_PERIODIC_INVERSE,
	PMIC_AUDGLB_PWRDN_PERIODIC_MODE,
	PMIC_VOW_ON_PERIODIC_ON_CYCLE,
	PMIC_VOW_ON_PERIODIC_INVERSE,
	PMIC_VOW_ON_PERIODIC_MODE,
	PMIC_DMIC_ON_PERIODIC_ON_CYCLE,
	PMIC_DMIC_ON_PERIODIC_INVERSE,
	PMIC_DMIC_ON_PERIODIC_MODE,
	PMIC_AUDPREAMPLON_PERIODIC_OFF_CYCLE,
	PMIC_PDN_VOW_F32K_CK,
	PMIC_AUDPREAMPLDCPRECHARGE_PERIODIC_OFF_CYCLE,
	PMIC_VOW_SNRDET_PERIODIC_CFG,
	PMIC_AUDADCLPWRUP_PERIODIC_OFF_CYCLE,
	PMIC_AUDGLBVOWLPWEN_PERIODIC_OFF_CYCLE,
	PMIC_AUDDIGMICEN_PERIODIC_OFF_CYCLE,
	PMIC_AUDPWDBMICBIAS0_PERIODIC_OFF_CYCLE,
	PMIC_AUDPWDBMICBIAS1_PERIODIC_OFF_CYCLE,
	PMIC_XO_VOW_CK_EN_PERIODIC_OFF_CYCLE,
	PMIC_CLKSQ_EN_VOW_PERIODIC_MODE,
	PMIC_AUDGLB_PWRDN_PERIODIC_OFF_CYCLE,
	PMIC_VOW_ON_PERIODIC_OFF_CYCLE,
	PMIC_DMIC_ON_PERIODIC_OFF_CYCLE,
	PMIC_VOW_PERIODIC_MON,
	PMIC_VOW_PERIODIC_COUNT_MON,
	PMIC_AUDENC_ANA_ID,
	PMIC_AUDENC_DIG_ID,
	PMIC_AUDENC_ANA_MINOR_REV,
	PMIC_AUDENC_ANA_MAJOR_REV,
	PMIC_AUDENC_DIG_MINOR_REV,
	PMIC_AUDENC_DIG_MAJOR_REV,
	PMIC_AUDENC_DSN_CBS,
	PMIC_AUDENC_DSN_BIX,
	PMIC_AUDENC_DSN_ESP,
	PMIC_AUDENC_DSN_FPI,
	PMIC_RG_AUDPREAMPLON,
	PMIC_RG_AUDPREAMPLDCCEN,
	PMIC_RG_AUDPREAMPLDCPRECHARGE,
	PMIC_RG_AUDPREAMPLPGATEST,
	PMIC_RG_AUDPREAMPLVSCALE,
	PMIC_RG_AUDPREAMPLINPUTSEL,
	PMIC_RG_AUDPREAMPLGAIN,
	PMIC_RG_AUDADCLPWRUP,
	PMIC_RG_AUDADCLINPUTSEL,
	PMIC_RG_AUDPREAMPRON,
	PMIC_RG_AUDPREAMPRDCCEN,
	PMIC_RG_AUDPREAMPRDCPRECHARGE,
	PMIC_RG_AUDPREAMPRPGATEST,
	PMIC_RG_AUDPREAMPRVSCALE,
	PMIC_RG_AUDPREAMPRINPUTSEL,
	PMIC_RG_AUDPREAMPRGAIN,
	PMIC_RG_AUDIO_VOW_EN,
	PMIC_RG_AUDADCRPWRUP,
	PMIC_RG_AUDADCRINPUTSEL,
	PMIC_RG_CLKSQ_EN_VOW,
	PMIC_RG_AUDULHALFBIAS,
	PMIC_RG_AUDGLBVOWLPWEN,
	PMIC_RG_AUDPREAMPLPEN,
	PMIC_RG_AUDADC1STSTAGELPEN,
	PMIC_RG_AUDADC2NDSTAGELPEN,
	PMIC_RG_AUDADCFLASHLPEN,
	PMIC_RG_AUDPREAMPIDDTEST,
	PMIC_RG_AUDADC1STSTAGEIDDTEST,
	PMIC_RG_AUDADC2NDSTAGEIDDTEST,
	PMIC_RG_AUDADCREFBUFIDDTEST,
	PMIC_RG_AUDADCFLASHIDDTEST,
	PMIC_RG_AUDADCDAC0P25FS,
	PMIC_RG_AUDADCCLKSEL,
	PMIC_RG_AUDADCCLKSOURCE,
	PMIC_RG_AUDPREAMPAAFEN,
	PMIC_RG_DCCVCMBUFLPMODSEL,
	PMIC_RG_DCCVCMBUFLPSWEN,
	PMIC_RG_CMSTBENH,
	PMIC_RG_PGABODYSW,
	PMIC_RG_AUDADC1STSTAGESDENB,
	PMIC_RG_AUDADC2NDSTAGERESET,
	PMIC_RG_AUDADC3RDSTAGERESET,
	PMIC_RG_AUDADCFSRESET,
	PMIC_RG_AUDADCWIDECM,
	PMIC_RG_AUDADCNOPATEST,
	PMIC_RG_AUDADCBYPASS,
	PMIC_RG_AUDADCFFBYPASS,
	PMIC_RG_AUDADCDACFBCURRENT,
	PMIC_RG_AUDADCDACIDDTEST,
	PMIC_RG_AUDADCDACNRZ,
	PMIC_RG_AUDADCNODEM,
	PMIC_RG_AUDADCDACTEST,
	PMIC_RG_AUDRCTUNEL,
	PMIC_RG_AUDRCTUNELSEL,
	PMIC_RG_AUDRCTUNER,
	PMIC_RG_AUDRCTUNERSEL,
	PMIC_RG_CLKSQ_EN,
	PMIC_RG_CLKSQ_IN_SEL_TEST,
	PMIC_RG_CM_REFGENSEL,
	PMIC_RG_AUDSPARE,
	PMIC_RG_AUDENCSPARE,
	PMIC_RG_AUDENCSPARE2,
	PMIC_RG_AUDDIGMICEN,
	PMIC_RG_AUDDIGMICBIAS,
	PMIC_RG_DMICHPCLKEN,
	PMIC_RG_AUDDIGMICPDUTY,
	PMIC_RG_AUDDIGMICNDUTY,
	PMIC_RG_DMICMONEN,
	PMIC_RG_DMICMONSEL,
	PMIC_RG_AUDSPAREVMIC,
	PMIC_RG_AUDPWDBMICBIAS0,
	PMIC_RG_AUDMICBIAS0BYPASSEN,
	PMIC_RG_AUDMICBIAS0LOWPEN,
	PMIC_RG_AUDMICBIAS0VREF,
	PMIC_RG_AUDMICBIAS0DCSW0P1EN,
	PMIC_RG_AUDMICBIAS0DCSW0P2EN,
	PMIC_RG_AUDMICBIAS0DCSW0NEN,
	PMIC_RG_AUDMICBIAS0DCSW2P1EN,
	PMIC_RG_AUDMICBIAS0DCSW2P2EN,
	PMIC_RG_AUDMICBIAS0DCSW2NEN,
	PMIC_RG_AUDPWDBMICBIAS1,
	PMIC_RG_AUDMICBIAS1BYPASSEN,
	PMIC_RG_AUDMICBIAS1LOWPEN,
	PMIC_RG_AUDMICBIAS1VREF,
	PMIC_RG_AUDMICBIAS1DCSW1PEN,
	PMIC_RG_AUDMICBIAS1DCSW1NEN,
	PMIC_RG_BANDGAPGEN,
	PMIC_RG_MTEST_EN,
	PMIC_RG_MTEST_SEL,
	PMIC_RG_MTEST_CURRENT,
	PMIC_RG_AUDACCDETMICBIAS0PULLLOW,
	PMIC_RG_AUDACCDETMICBIAS1PULLLOW,
	PMIC_RG_AUDACCDETVIN1PULLLOW,
	PMIC_RG_AUDACCDETVTHACAL,
	PMIC_RG_AUDACCDETVTHBCAL,
	PMIC_RG_AUDACCDETTVDET,
	PMIC_RG_ACCDETSEL,
	PMIC_RG_SWBUFMODSEL,
	PMIC_RG_SWBUFSWEN,
	PMIC_RG_EINTCOMPVTH,
	PMIC_RG_EINTCONFIGACCDET,
	PMIC_RG_EINTHIRENB,
	PMIC_RG_ACCDET2AUXRESBYPASS,
	PMIC_RG_ACCDET2AUXBUFFERBYPASS,
	PMIC_RG_ACCDET2AUXSWEN,
	PMIC_RGS_AUDRCTUNELREAD,
	PMIC_RGS_AUDRCTUNERREAD,
	PMIC_AUDDEC_ANA_ID,
	PMIC_AUDDEC_DIG_ID,
	PMIC_AUDDEC_ANA_MINOR_REV,
	PMIC_AUDDEC_ANA_MAJOR_REV,
	PMIC_AUDDEC_DIG_MINOR_REV,
	PMIC_AUDDEC_DIG_MAJOR_REV,
	PMIC_AUDDEC_DSN_CBS,
	PMIC_AUDDEC_DSN_BIX,
	PMIC_AUDDEC_DSN_ESP,
	PMIC_AUDDEC_DSN_FPI,
	PMIC_RG_AUDDACLPWRUP_VAUDP15,
	PMIC_RG_AUDDACRPWRUP_VAUDP15,
	PMIC_RG_AUD_DAC_PWR_UP_VA28,
	PMIC_RG_AUD_DAC_PWL_UP_VA28,
	PMIC_RG_AUDHPLPWRUP_VAUDP15,
	PMIC_RG_AUDHPRPWRUP_VAUDP15,
	PMIC_RG_AUDHPLPWRUP_IBIAS_VAUDP15,
	PMIC_RG_AUDHPRPWRUP_IBIAS_VAUDP15,
	PMIC_RG_AUDHPLMUXINPUTSEL_VAUDP15,
	PMIC_RG_AUDHPRMUXINPUTSEL_VAUDP15,
	PMIC_RG_AUDHPLSCDISABLE_VAUDP15,
	PMIC_RG_AUDHPRSCDISABLE_VAUDP15,
	PMIC_RG_AUDHPLBSCCURRENT_VAUDP15,
	PMIC_RG_AUDHPRBSCCURRENT_VAUDP15,
	PMIC_RG_AUDHPLOUTPWRUP_VAUDP15,
	PMIC_RG_AUDHPROUTPWRUP_VAUDP15,
	PMIC_RG_AUDHPLOUTAUXPWRUP_VAUDP15,
	PMIC_RG_AUDHPROUTAUXPWRUP_VAUDP15,
	PMIC_RG_HPLAUXFBRSW_EN_VAUDP15,
	PMIC_RG_HPRAUXFBRSW_EN_VAUDP15,
	PMIC_RG_HPLSHORT2HPLAUX_EN_VAUDP15,
	PMIC_RG_HPRSHORT2HPRAUX_EN_VAUDP15,
	PMIC_RG_HPLOUTSTGCTRL_VAUDP15,
	PMIC_RG_HPROUTSTGCTRL_VAUDP15,
	PMIC_RG_HPLOUTPUTSTBENH_VAUDP15,
	PMIC_RG_HPROUTPUTSTBENH_VAUDP15,
	PMIC_RG_AUDHPSTARTUP_VAUDP15,
	PMIC_RG_AUDREFN_DERES_EN_VAUDP15,
	PMIC_RG_HPPSHORT2VCM_VAUDP15,
	PMIC_RG_HPINPUTSTBENH_VAUDP15,
	PMIC_RG_HPINPUTRESET0_VAUDP15,
	PMIC_RG_HPOUTPUTRESET0_VAUDP15,
	PMIC_RG_ABIDEC_RSVD0_VAUDP28,
	PMIC_RG_AUDHPDECMGAINADJ_VAUDP15,
	PMIC_RG_AUDHPDEDMGAINADJ_VAUDP15,
	PMIC_RG_AUDHSPWRUP_VAUDP15,
	PMIC_RG_AUDHSPWRUP_IBIAS_VAUDP15,
	PMIC_RG_AUDHSMUXINPUTSEL_VAUDP15,
	PMIC_RG_AUDHSSCDISABLE_VAUDP15,
	PMIC_RG_AUDHSBSCCURRENT_VAUDP15,
	PMIC_RG_AUDHSSTARTUP_VAUDP15,
	PMIC_RG_HSOUTPUTSTBENH_VAUDP15,
	PMIC_RG_HSINPUTSTBENH_VAUDP15,
	PMIC_RG_HSINPUTRESET0_VAUDP15,
	PMIC_RG_HSOUTPUTRESET0_VAUDP15,
	PMIC_RG_HSOUT_SHORTVCM_VAUDP15,
	PMIC_RG_AUDLOLPWRUP_VAUDP15,
	PMIC_RG_AUDLOLPWRUP_IBIAS_VAUDP15,
	PMIC_RG_AUDLOLMUXINPUTSEL_VAUDP15,
	PMIC_RG_AUDLOLSCDISABLE_VAUDP15,
	PMIC_RG_AUDLOLBSCCURRENT_VAUDP15,
	PMIC_RG_AUDLOSTARTUP_VAUDP15,
	PMIC_RG_LOINPUTSTBENH_VAUDP15,
	PMIC_RG_LOOUTPUTSTBENH_VAUDP15,
	PMIC_RG_LOINPUTRESET0_VAUDP15,
	PMIC_RG_LOOUTPUTRESET0_VAUDP15,
	PMIC_RG_LOOUT_SHORTVCM_VAUDP15,
	PMIC_RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15,
	PMIC_RG_AUDTRIMBUF_GAINSEL_VAUDP15,
	PMIC_RG_AUDTRIMBUF_EN_VAUDP15,
	PMIC_RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15,
	PMIC_RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15,
	PMIC_RG_AUDHPSPKDET_EN_VAUDP15,
	PMIC_RG_ABIDEC_RSVD0_VA28,
	PMIC_RG_ABIDEC_RSVD0_VAUDP15,
	PMIC_RG_ABIDEC_RSVD1_VAUDP15,
	PMIC_RG_ABIDEC_RSVD2_VAUDP15,
	PMIC_RG_AUDZCDMUXSEL_VAUDP15,
	PMIC_RG_AUDZCDCLKSEL_VAUDP15,
	PMIC_RG_AUDBIASADJ_0_VAUDP15,
	PMIC_RG_AUDBIASADJ_1_VAUDP15,
	PMIC_RG_AUDIBIASPWRDN_VAUDP15,
	PMIC_RG_RSTB_DECODER_VA28,
	PMIC_RG_SEL_DECODER_96K_VA28,
	PMIC_RG_SEL_DELAY_VCORE,
	PMIC_RG_AUDGLB_PWRDN_VA28,
	PMIC_RG_RSTB_ENCODER_VA28,
	PMIC_RG_SEL_ENCODER_96K_VA28,
	PMIC_RG_HCLDO_EN_VA18,
	PMIC_RG_HCLDO_PDDIS_EN_VA18,
	PMIC_RG_HCLDO_REMOTE_SENSE_VA18,
	PMIC_RG_LCLDO_EN_VA18,
	PMIC_RG_LCLDO_PDDIS_EN_VA18,
	PMIC_RG_LCLDO_REMOTE_SENSE_VA18,
	PMIC_RG_LCLDO_ENC_EN_VA28,
	PMIC_RG_LCLDO_ENC_PDDIS_EN_VA28,
	PMIC_RG_LCLDO_ENC_REMOTE_SENSE_VA28,
	PMIC_RG_VA33REFGEN_EN_VA18,
	PMIC_RG_VA28REFGEN_EN_VA28,
	PMIC_RG_HCLDO_VOSEL_VA18,
	PMIC_RG_LCLDO_VOSEL_VA18,
	PMIC_RG_NVREG_EN_VAUDP15,
	PMIC_RG_NVREG_PULL0V_VAUDP15,
	PMIC_RG_AUDPMU_RSD0_VAUDP15,
	PMIC_RG_AUDPMU_RSD0_VA18,
	PMIC_RG_AUDPMU_RSD0_VA28,
	PMIC_AUDDEC_ELR_LEN,
	PMIC_RG_AUDHPLTRIM_VAUDP15,
	PMIC_RG_AUDHPRTRIM_VAUDP15,
	PMIC_RG_AUDHPLFINETRIM_VAUDP15,
	PMIC_RG_AUDHPRFINETRIM_VAUDP15,
	PMIC_RG_AUDHPTRIM_EN_VAUDP15,
	PMIC_AUDZCD_ANA_ID,
	PMIC_AUDZCD_DIG_ID,
	PMIC_AUDZCD_ANA_MINOR_REV,
	PMIC_AUDZCD_ANA_MAJOR_REV,
	PMIC_AUDZCD_DIG_MINOR_REV,
	PMIC_AUDZCD_DIG_MAJOR_REV,
	PMIC_AUDZCD_DSN_CBS,
	PMIC_AUDZCD_DSN_BIX,
	PMIC_AUDZCD_DSN_ESP,
	PMIC_AUDZCD_DSN_FPI,
	PMIC_RG_AUDZCDENABLE,
	PMIC_RG_AUDZCDGAINSTEPTIME,
	PMIC_RG_AUDZCDGAINSTEPSIZE,
	PMIC_RG_AUDZCDTIMEOUTMODESEL,
	PMIC_RG_AUDLOLGAIN,
	PMIC_RG_AUDLORGAIN,
	PMIC_RG_AUDHPLGAIN,
	PMIC_RG_AUDHPRGAIN,
	PMIC_RG_AUDHSGAIN,
	PMIC_RG_AUDIVLGAIN,
	PMIC_RG_AUDIVRGAIN,
	PMIC_RG_AUDINTGAIN1,
	PMIC_RG_AUDINTGAIN2,
	PMIC_ACCDET_ANA_ID,
	PMIC_ACCDET_DIG_ID,
	PMIC_ACCDET_ANA_MINOR_REV,
	PMIC_ACCDET_ANA_MAJOR_REV,
	PMIC_ACCDET_DIG_MINOR_REV,
	PMIC_ACCDET_DIG_MAJOR_REV,
	PMIC_ACCDET_DSN_CBS,
	PMIC_ACCDET_DSN_BIX,
	PMIC_ACCDET_ESP,
	PMIC_ACCDET_DSN_FPI,
	PMIC_AUDACCDETAUXADCSWCTRL,
	PMIC_AUDACCDETAUXADCSWCTRL_SEL,
	PMIC_RG_AUDACCDETRSV,
	PMIC_ACCDET_EN,
	PMIC_ACCDET_SEQ_INIT,
	PMIC_ACCDET_EINT0_EN,
	PMIC_ACCDET_EINT0_SEQ_INIT,
	PMIC_ACCDET_EINT1_EN,
	PMIC_ACCDET_EINT1_SEQ_INIT,
	PMIC_ACCDET_ANASWCTRL_SEL,
	PMIC_ACCDET_CMP_PWM_EN,
	PMIC_ACCDET_VTH_PWM_EN,
	PMIC_ACCDET_MBIAS_PWM_EN,
	PMIC_ACCDET_EINT0_PWM_EN,
	PMIC_ACCDET_EINT1_PWM_EN,
	PMIC_ACCDET_CMP_PWM_IDLE,
	PMIC_ACCDET_VTH_PWM_IDLE,
	PMIC_ACCDET_MBIAS_PWM_IDLE,
	PMIC_ACCDET_EINT0_PWM_IDLE,
	PMIC_ACCDET_EINT1_PWM_IDLE,
	PMIC_ACCDET_PWM_WIDTH,
	PMIC_ACCDET_PWM_THRESH,
	PMIC_ACCDET_RISE_DELAY,
	PMIC_ACCDET_FALL_DELAY,
	PMIC_ACCDET_DEBOUNCE0,
	PMIC_ACCDET_DEBOUNCE1,
	PMIC_ACCDET_DEBOUNCE2,
	PMIC_ACCDET_DEBOUNCE3,
	PMIC_ACCDET_DEBOUNCE4,
	PMIC_ACCDET_IVAL_CUR_IN,
	PMIC_ACCDET_EINT0_IVAL_CUR_IN,
	PMIC_ACCDET_EINT1_IVAL_CUR_IN,
	PMIC_ACCDET_IVAL_SAM_IN,
	PMIC_ACCDET_EINT0_IVAL_SAM_IN,
	PMIC_ACCDET_EINT1_IVAL_SAM_IN,
	PMIC_ACCDET_IVAL_MEM_IN,
	PMIC_ACCDET_EINT0_IVAL_MEM_IN,
	PMIC_ACCDET_EINT1_IVAL_MEM_IN,
	PMIC_ACCDET_IVAL_SEL,
	PMIC_ACCDET_EINT0_IVAL_SEL,
	PMIC_ACCDET_EINT1_IVAL_SEL,
	PMIC_ACCDET_IRQ,
	PMIC_ACCDET_EINT0_IRQ,
	PMIC_ACCDET_EINT1_IRQ,
	PMIC_ACCDET_IRQ_CLR,
	PMIC_ACCDET_EINT0_IRQ_CLR,
	PMIC_ACCDET_EINT1_IRQ_CLR,
	PMIC_ACCDET_EINT0_IRQ_POLARITY,
	PMIC_ACCDET_EINT1_IRQ_POLARITY,
	PMIC_ACCDET_TEST_MODE0,
	PMIC_ACCDET_CMP_SWSEL,
	PMIC_ACCDET_VTH_SWSEL,
	PMIC_ACCDET_MBIAS_SWSEL,
	PMIC_ACCDET_TEST_MODE4,
	PMIC_ACCDET_TEST_MODE5,
	PMIC_ACCDET_PWM_SEL,
	PMIC_ACCDET_IN_SW,
	PMIC_ACCDET_CMP_EN_SW,
	PMIC_ACCDET_VTH_EN_SW,
	PMIC_ACCDET_MBIAS_EN_SW,
	PMIC_ACCDET_PWM_EN_SW,
	PMIC_ACCDET_IN,
	PMIC_ACCDET_CUR_IN,
	PMIC_ACCDET_SAM_IN,
	PMIC_ACCDET_MEM_IN,
	PMIC_ACCDET_STATE,
	PMIC_ACCDET_MBIAS_CLK,
	PMIC_ACCDET_VTH_CLK,
	PMIC_ACCDET_CMP_CLK,
	PMIC_DA_AUDACCDETAUXADCSWCTRL,
	PMIC_ACCDET_EINT0_DEB_SEL,
	PMIC_ACCDET_EINT0_DEBOUNCE,
	PMIC_ACCDET_EINT0_PWM_THRESH,
	PMIC_ACCDET_EINT0_PWM_WIDTH,
	PMIC_ACCDET_EINT0_PWM_FALL_DELAY,
	PMIC_ACCDET_EINT0_PWM_RISE_DELAY,
	PMIC_ACCDET_TEST_MODE11,
	PMIC_ACCDET_TEST_MODE10,
	PMIC_ACCDET_EINT0_CMPOUT_SW,
	PMIC_ACCDET_EINT1_CMPOUT_SW,
	PMIC_ACCDET_TEST_MODE9,
	PMIC_ACCDET_TEST_MODE8,
	PMIC_ACCDET_AUXADC_CTRL_SW,
	PMIC_ACCDET_TEST_MODE7,
	PMIC_ACCDET_TEST_MODE6,
	PMIC_ACCDET_EINT0_CMP_EN_SW,
	PMIC_ACCDET_EINT1_CMP_EN_SW,
	PMIC_ACCDET_EINT0_STATE,
	PMIC_ACCDET_AUXADC_DEBOUNCE_END,
	PMIC_ACCDET_AUXADC_CONNECT_PRE,
	PMIC_ACCDET_EINT0_CUR_IN,
	PMIC_ACCDET_EINT0_SAM_IN,
	PMIC_ACCDET_EINT0_MEM_IN,
	PMIC_AD_EINT0CMPOUT,
	PMIC_DA_NI_EINT0CMPEN,
	PMIC_ACCDET_CUR_DEB,
	PMIC_ACCDET_EINT0_CUR_DEB,
	PMIC_ACCDET_MON_FLAG_EN,
	PMIC_ACCDET_MON_FLAG_SEL,
	PMIC_ACCDET_RSV_CON1,
	PMIC_ACCDET_AUXADC_CONNECT_TIME,
	PMIC_ACCDET_HWEN_SEL,
	PMIC_ACCDET_HWMODE_SEL,
	PMIC_ACCDET_EINT_DEB_OUT_DFF,
	PMIC_ACCDET_FAST_DISCHARGE,
	PMIC_ACCDET_EINT0_REVERSE,
	PMIC_ACCDET_EINT1_REVERSE,
	PMIC_ACCDET_EINT1_DEB_SEL,
	PMIC_ACCDET_EINT1_DEBOUNCE,
	PMIC_ACCDET_EINT1_PWM_THRESH,
	PMIC_ACCDET_EINT1_PWM_WIDTH,
	PMIC_ACCDET_EINT1_PWM_FALL_DELAY,
	PMIC_ACCDET_EINT1_PWM_RISE_DELAY,
	PMIC_ACCDET_EINT1_STATE,
	PMIC_ACCDET_EINT1_CUR_IN,
	PMIC_ACCDET_EINT1_SAM_IN,
	PMIC_ACCDET_EINT1_MEM_IN,
	PMIC_AD_EINT1CMPOUT,
	PMIC_DA_NI_EINT1CMPEN,
	PMIC_ACCDET_EINT1_CUR_DEB,
	PMU_COMMAND_MAX
};

struct pmu_flag_table_entry_t {
	enum PMU_FLAGS_LIST flagname;
	unsigned short offset;
	unsigned short mask;
	unsigned char shift;
};

#endif		/* _MT_PMIC_UPMU_HW_MT6358_H_ */
